1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Driver for Realtek PCI-Express card reader 3 * 4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 5 * 6 * Author: 7 * Wei WANG <wei_wang@realsil.com.cn> 8 */ 9 10 #include <linux/module.h> 11 #include <linux/delay.h> 12 #include <linux/rtsx_pci.h> 13 14 #include "rtsx_pcr.h" 15 16 static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr) 17 { 18 u8 val; 19 20 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val); 21 return val & 0x0F; 22 } 23 24 static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage) 25 { 26 u8 driving_3v3[4][3] = { 27 {0x11, 0x11, 0x18}, 28 {0x55, 0x55, 0x5C}, 29 {0xFF, 0xFF, 0xFF}, 30 {0x96, 0x96, 0x96}, 31 }; 32 u8 driving_1v8[4][3] = { 33 {0xC4, 0xC4, 0xC4}, 34 {0x3C, 0x3C, 0x3C}, 35 {0xFE, 0xFE, 0xFE}, 36 {0xB3, 0xB3, 0xB3}, 37 }; 38 u8 (*driving)[3], drive_sel; 39 40 if (voltage == OUTPUT_3V3) { 41 driving = driving_3v3; 42 drive_sel = pcr->sd30_drive_sel_3v3; 43 } else { 44 driving = driving_1v8; 45 drive_sel = pcr->sd30_drive_sel_1v8; 46 } 47 48 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL, 49 0xFF, driving[drive_sel][0]); 50 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL, 51 0xFF, driving[drive_sel][1]); 52 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL, 53 0xFF, driving[drive_sel][2]); 54 } 55 56 static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr) 57 { 58 struct pci_dev *pdev = pcr->pci; 59 u32 reg; 60 61 pci_read_config_dword(pdev, PCR_SETTING_REG1, ®); 62 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); 63 pci_write_config_dword(pdev, 0x718, 0x0007C000); 64 65 if (!rtsx_vendor_setting_valid(reg)) { 66 pcr_dbg(pcr, "skip fetch vendor setting\n"); 67 return; 68 } 69 70 pcr->aspm_en = rtsx_reg_to_aspm(reg); 71 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg); 72 pcr->card_drive_sel &= 0x3F; 73 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg); 74 75 pci_read_config_dword(pdev, PCR_SETTING_REG2, ®); 76 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg); 77 78 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) 79 pcr->rtd3_en = rtsx_reg_to_rtd3_uhsii(reg); 80 81 if (rtsx_check_mmc_support(reg)) 82 pcr->extra_caps |= EXTRA_CAPS_NO_MMC; 83 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg); 84 if (rtsx_reg_check_reverse_socket(reg)) 85 pcr->flags |= PCR_REVERSE_SOCKET; 86 if (rtsx_reg_check_cd_reverse(reg)) 87 pcr->option.sd_cd_reverse_en = 1; 88 if (rtsx_reg_check_wp_reverse(reg)) 89 pcr->option.sd_wp_reverse_en = 1; 90 } 91 92 static void rts5249_init_from_cfg(struct rtsx_pcr *pcr) 93 { 94 struct rtsx_cr_option *option = &(pcr->option); 95 96 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { 97 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN 98 | PM_L1_1_EN | PM_L1_2_EN)) 99 rtsx_pci_disable_oobs_polling(pcr); 100 else 101 rtsx_pci_enable_oobs_polling(pcr); 102 } 103 104 if (option->ltr_en) { 105 if (option->ltr_enabled) 106 rtsx_set_ltr_latency(pcr, option->ltr_active_latency); 107 } 108 } 109 110 static void rts52xa_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime) 111 { 112 /* Set relink_time to 0 */ 113 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0); 114 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0); 115 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 116 RELINK_TIME_MASK, 0); 117 118 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 119 D3_DELINK_MODE_EN, D3_DELINK_MODE_EN); 120 121 if (!runtime) { 122 rtsx_pci_write_register(pcr, RTS524A_AUTOLOAD_CFG1, 123 CD_RESUME_EN_MASK, 0); 124 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x00); 125 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x20); 126 } 127 128 rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN); 129 } 130 131 static void rts52xa_save_content_from_efuse(struct rtsx_pcr *pcr) 132 { 133 u8 cnt, sv; 134 u16 j = 0; 135 u8 tmp; 136 u8 val; 137 int i; 138 139 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 140 REG_EFUSE_BYPASS | REG_EFUSE_POR, REG_EFUSE_POR); 141 udelay(1); 142 143 pcr_dbg(pcr, "Enable efuse por!"); 144 pcr_dbg(pcr, "save efuse to autoload"); 145 146 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, REG_EFUSE_ADD_MASK, 0x00); 147 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL, 148 REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE); 149 /* Wait transfer end */ 150 for (j = 0; j < 1024; j++) { 151 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp); 152 if ((tmp & 0x80) == 0) 153 break; 154 } 155 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val); 156 cnt = val & 0x0F; 157 sv = val & 0x10; 158 159 if (sv) { 160 for (i = 0; i < 4; i++) { 161 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, 162 REG_EFUSE_ADD_MASK, 0x04 + i); 163 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL, 164 REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE); 165 /* Wait transfer end */ 166 for (j = 0; j < 1024; j++) { 167 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp); 168 if ((tmp & 0x80) == 0) 169 break; 170 } 171 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val); 172 rtsx_pci_write_register(pcr, 0xFF04 + i, 0xFF, val); 173 } 174 } else { 175 rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr)); 176 rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8)); 177 rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr)); 178 rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8)); 179 } 180 181 for (i = 0; i < cnt * 4; i++) { 182 if (sv) 183 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, 184 REG_EFUSE_ADD_MASK, 0x08 + i); 185 else 186 rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, 187 REG_EFUSE_ADD_MASK, 0x04 + i); 188 rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL, 189 REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE); 190 /* Wait transfer end */ 191 for (j = 0; j < 1024; j++) { 192 rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp); 193 if ((tmp & 0x80) == 0) 194 break; 195 } 196 rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val); 197 rtsx_pci_write_register(pcr, 0xFF08 + i, 0xFF, val); 198 } 199 rtsx_pci_write_register(pcr, 0xFF00, 0xFF, (cnt & 0x7F) | 0x80); 200 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 201 REG_EFUSE_BYPASS | REG_EFUSE_POR, REG_EFUSE_BYPASS); 202 pcr_dbg(pcr, "Disable efuse por!"); 203 } 204 205 static void rts52xa_save_content_to_autoload_space(struct rtsx_pcr *pcr) 206 { 207 u8 val; 208 209 rtsx_pci_read_register(pcr, RESET_LOAD_REG, &val); 210 if (val & 0x02) { 211 rtsx_pci_read_register(pcr, RTS525A_BIOS_CFG, &val); 212 if (val & RTS525A_LOAD_BIOS_FLAG) { 213 rtsx_pci_write_register(pcr, RTS525A_BIOS_CFG, 214 RTS525A_LOAD_BIOS_FLAG, RTS525A_CLEAR_BIOS_FLAG); 215 216 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 217 REG_EFUSE_POWER_MASK, REG_EFUSE_POWERON); 218 219 pcr_dbg(pcr, "Power ON efuse!"); 220 mdelay(1); 221 rts52xa_save_content_from_efuse(pcr); 222 } else { 223 rtsx_pci_read_register(pcr, RTS524A_PME_FORCE_CTL, &val); 224 if (!(val & 0x08)) 225 rts52xa_save_content_from_efuse(pcr); 226 } 227 } else { 228 pcr_dbg(pcr, "Load from autoload"); 229 rtsx_pci_write_register(pcr, 0xFF00, 0xFF, 0x80); 230 rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr)); 231 rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8)); 232 rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr)); 233 rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8)); 234 } 235 } 236 237 static int rts5249_extra_init_hw(struct rtsx_pcr *pcr) 238 { 239 struct rtsx_cr_option *option = &(pcr->option); 240 241 rts5249_init_from_cfg(pcr); 242 243 rtsx_pci_init_cmd(pcr); 244 245 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) 246 rts52xa_save_content_to_autoload_space(pcr); 247 248 /* Rest L1SUB Config */ 249 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00); 250 /* Configure GPIO as output */ 251 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02); 252 /* Reset ASPM state to default value */ 253 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0); 254 /* Switch LDO3318 source from DV33 to card_3v3 */ 255 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00); 256 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01); 257 /* LED shine disabled, set initial shine cycle period */ 258 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02); 259 /* Configure driving */ 260 rts5249_fill_driving(pcr, OUTPUT_3V3); 261 if (pcr->flags & PCR_REVERSE_SOCKET) 262 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x30); 263 else { 264 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x20, option->sd_cd_reverse_en << 5); 265 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x10, option->sd_wp_reverse_en << 4); 266 } 267 268 rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF); 269 270 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { 271 rtsx_pci_write_register(pcr, REG_VREF, PWD_SUSPND_EN, PWD_SUSPND_EN); 272 rtsx_pci_write_register(pcr, RTS524A_AUTOLOAD_CFG1, 273 CD_RESUME_EN_MASK, CD_RESUME_EN_MASK); 274 } 275 276 if (pcr->rtd3_en) { 277 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { 278 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x01); 279 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x30); 280 } else { 281 rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x01); 282 rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x33); 283 } 284 } else { 285 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { 286 rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x00); 287 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x20); 288 } else { 289 rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x30); 290 rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x00); 291 } 292 } 293 294 295 /* 296 * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced 297 * to drive low, and we forcibly request clock. 298 */ 299 if (option->force_clkreq_0) 300 rtsx_pci_write_register(pcr, PETXCFG, 301 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); 302 else 303 rtsx_pci_write_register(pcr, PETXCFG, 304 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); 305 306 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00); 307 if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { 308 rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 309 REG_EFUSE_POWER_MASK, REG_EFUSE_POWEROFF); 310 pcr_dbg(pcr, "Power OFF efuse!"); 311 } 312 313 return 0; 314 } 315 316 static int rts5249_optimize_phy(struct rtsx_pcr *pcr) 317 { 318 int err; 319 320 err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00); 321 if (err < 0) 322 return err; 323 324 err = rtsx_pci_write_phy_register(pcr, PHY_REV, 325 PHY_REV_RESV | PHY_REV_RXIDLE_LATCHED | 326 PHY_REV_P1_EN | PHY_REV_RXIDLE_EN | 327 PHY_REV_CLKREQ_TX_EN | PHY_REV_RX_PWST | 328 PHY_REV_CLKREQ_DT_1_0 | PHY_REV_STOP_CLKRD | 329 PHY_REV_STOP_CLKWR); 330 if (err < 0) 331 return err; 332 333 msleep(1); 334 335 err = rtsx_pci_write_phy_register(pcr, PHY_BPCR, 336 PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL | 337 PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN); 338 if (err < 0) 339 return err; 340 341 err = rtsx_pci_write_phy_register(pcr, PHY_PCR, 342 PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 | 343 PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | 344 PHY_PCR_RSSI_EN | PHY_PCR_RX10K); 345 if (err < 0) 346 return err; 347 348 err = rtsx_pci_write_phy_register(pcr, PHY_RCR2, 349 PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR | 350 PHY_RCR2_CDR_SR_2 | PHY_RCR2_FREQSEL_12 | 351 PHY_RCR2_CDR_SC_12P | PHY_RCR2_CALIB_LATE); 352 if (err < 0) 353 return err; 354 355 err = rtsx_pci_write_phy_register(pcr, PHY_FLD4, 356 PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF | 357 PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA | 358 PHY_FLD4_BER_COUNT | PHY_FLD4_BER_TIMER | 359 PHY_FLD4_BER_CHK_EN); 360 if (err < 0) 361 return err; 362 err = rtsx_pci_write_phy_register(pcr, PHY_RDR, 363 PHY_RDR_RXDSEL_1_9 | PHY_SSC_AUTO_PWD); 364 if (err < 0) 365 return err; 366 err = rtsx_pci_write_phy_register(pcr, PHY_RCR1, 367 PHY_RCR1_ADP_TIME_4 | PHY_RCR1_VCO_COARSE); 368 if (err < 0) 369 return err; 370 err = rtsx_pci_write_phy_register(pcr, PHY_FLD3, 371 PHY_FLD3_TIMER_4 | PHY_FLD3_TIMER_6 | 372 PHY_FLD3_RXDELINK); 373 if (err < 0) 374 return err; 375 376 return rtsx_pci_write_phy_register(pcr, PHY_TUNE, 377 PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 | 378 PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 | 379 PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12); 380 } 381 382 static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr) 383 { 384 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02); 385 } 386 387 static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr) 388 { 389 return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00); 390 } 391 392 static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr) 393 { 394 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08); 395 } 396 397 static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr) 398 { 399 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00); 400 } 401 402 static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card) 403 { 404 int err; 405 struct rtsx_cr_option *option = &pcr->option; 406 407 if (option->ocp_en) 408 rtsx_pci_enable_ocp(pcr); 409 410 rtsx_pci_init_cmd(pcr); 411 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, 412 SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON); 413 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, 414 LDO3318_PWR_MASK, 0x02); 415 err = rtsx_pci_send_cmd(pcr, 100); 416 if (err < 0) 417 return err; 418 419 msleep(5); 420 421 rtsx_pci_init_cmd(pcr); 422 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, 423 SD_POWER_MASK, SD_VCC_POWER_ON); 424 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, 425 LDO3318_PWR_MASK, 0x06); 426 return rtsx_pci_send_cmd(pcr, 100); 427 } 428 429 static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card) 430 { 431 struct rtsx_cr_option *option = &pcr->option; 432 433 if (option->ocp_en) 434 rtsx_pci_disable_ocp(pcr); 435 436 rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK, SD_POWER_OFF); 437 438 rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0x00); 439 return 0; 440 } 441 442 static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) 443 { 444 int err; 445 u16 append; 446 447 switch (voltage) { 448 case OUTPUT_3V3: 449 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK, 450 PHY_TUNE_VOLTAGE_3V3); 451 if (err < 0) 452 return err; 453 break; 454 case OUTPUT_1V8: 455 append = PHY_TUNE_D18_1V8; 456 if (CHK_PCI_PID(pcr, 0x5249)) { 457 err = rtsx_pci_update_phy(pcr, PHY_BACR, 458 PHY_BACR_BASIC_MASK, 0); 459 if (err < 0) 460 return err; 461 append = PHY_TUNE_D18_1V7; 462 } 463 464 err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK, 465 append); 466 if (err < 0) 467 return err; 468 break; 469 default: 470 pcr_dbg(pcr, "unknown output voltage %d\n", voltage); 471 return -EINVAL; 472 } 473 474 /* set pad drive */ 475 rtsx_pci_init_cmd(pcr); 476 rts5249_fill_driving(pcr, voltage); 477 return rtsx_pci_send_cmd(pcr, 100); 478 } 479 480 static const struct pcr_ops rts5249_pcr_ops = { 481 .fetch_vendor_settings = rtsx_base_fetch_vendor_settings, 482 .extra_init_hw = rts5249_extra_init_hw, 483 .optimize_phy = rts5249_optimize_phy, 484 .turn_on_led = rtsx_base_turn_on_led, 485 .turn_off_led = rtsx_base_turn_off_led, 486 .enable_auto_blink = rtsx_base_enable_auto_blink, 487 .disable_auto_blink = rtsx_base_disable_auto_blink, 488 .card_power_on = rtsx_base_card_power_on, 489 .card_power_off = rtsx_base_card_power_off, 490 .switch_output_voltage = rtsx_base_switch_output_voltage, 491 }; 492 493 /* SD Pull Control Enable: 494 * SD_DAT[3:0] ==> pull up 495 * SD_CD ==> pull up 496 * SD_WP ==> pull up 497 * SD_CMD ==> pull up 498 * SD_CLK ==> pull down 499 */ 500 static const u32 rts5249_sd_pull_ctl_enable_tbl[] = { 501 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66), 502 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA), 503 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9), 504 RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA), 505 0, 506 }; 507 508 /* SD Pull Control Disable: 509 * SD_DAT[3:0] ==> pull down 510 * SD_CD ==> pull up 511 * SD_WP ==> pull down 512 * SD_CMD ==> pull down 513 * SD_CLK ==> pull down 514 */ 515 static const u32 rts5249_sd_pull_ctl_disable_tbl[] = { 516 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66), 517 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 518 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5), 519 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55), 520 0, 521 }; 522 523 /* MS Pull Control Enable: 524 * MS CD ==> pull up 525 * others ==> pull down 526 */ 527 static const u32 rts5249_ms_pull_ctl_enable_tbl[] = { 528 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55), 529 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55), 530 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15), 531 0, 532 }; 533 534 /* MS Pull Control Disable: 535 * MS CD ==> pull up 536 * others ==> pull down 537 */ 538 static const u32 rts5249_ms_pull_ctl_disable_tbl[] = { 539 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55), 540 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55), 541 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15), 542 0, 543 }; 544 545 void rts5249_init_params(struct rtsx_pcr *pcr) 546 { 547 struct rtsx_cr_option *option = &(pcr->option); 548 549 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; 550 pcr->num_slots = 2; 551 pcr->ops = &rts5249_pcr_ops; 552 553 pcr->flags = 0; 554 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; 555 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; 556 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; 557 pcr->aspm_en = ASPM_L1_EN; 558 pcr->aspm_mode = ASPM_MODE_CFG; 559 pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16); 560 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); 561 562 pcr->ic_version = rts5249_get_ic_version(pcr); 563 pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl; 564 pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl; 565 pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl; 566 pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl; 567 568 pcr->reg_pm_ctrl3 = PM_CTRL3; 569 570 option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN 571 | LTR_L1SS_PWR_GATE_EN); 572 option->ltr_en = true; 573 574 /* Init latency of active, idle, L1OFF to 60us, 300us, 3ms */ 575 option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF; 576 option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF; 577 option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF; 578 option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF; 579 option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5249_DEF; 580 option->ltr_l1off_snooze_sspwrgate = 581 LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF; 582 583 option->sd_cd_reverse_en = 0; 584 option->sd_wp_reverse_en = 0; 585 } 586 587 static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val) 588 { 589 addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr; 590 591 return __rtsx_pci_write_phy_register(pcr, addr, val); 592 } 593 594 static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val) 595 { 596 addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr; 597 598 return __rtsx_pci_read_phy_register(pcr, addr, val); 599 } 600 601 static int rts524a_optimize_phy(struct rtsx_pcr *pcr) 602 { 603 int err; 604 605 err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 606 D3_DELINK_MODE_EN, 0x00); 607 if (err < 0) 608 return err; 609 610 rtsx_pci_write_phy_register(pcr, PHY_PCR, 611 PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 | 612 PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN); 613 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3, 614 PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY); 615 616 if (is_version(pcr, 0x524A, IC_VER_A)) { 617 rtsx_pci_write_phy_register(pcr, PHY_SSCCR3, 618 PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY); 619 rtsx_pci_write_phy_register(pcr, PHY_SSCCR2, 620 PHY_SSCCR2_PLL_NCODE | PHY_SSCCR2_TIME0 | 621 PHY_SSCCR2_TIME2_WIDTH); 622 rtsx_pci_write_phy_register(pcr, PHY_ANA1A, 623 PHY_ANA1A_TXR_LOOPBACK | PHY_ANA1A_RXT_BIST | 624 PHY_ANA1A_TXR_BIST | PHY_ANA1A_REV); 625 rtsx_pci_write_phy_register(pcr, PHY_ANA1D, 626 PHY_ANA1D_DEBUG_ADDR); 627 rtsx_pci_write_phy_register(pcr, PHY_DIG1E, 628 PHY_DIG1E_REV | PHY_DIG1E_D0_X_D1 | 629 PHY_DIG1E_RX_ON_HOST | PHY_DIG1E_RCLK_REF_HOST | 630 PHY_DIG1E_RCLK_TX_EN_KEEP | 631 PHY_DIG1E_RCLK_TX_TERM_KEEP | 632 PHY_DIG1E_RCLK_RX_EIDLE_ON | PHY_DIG1E_TX_TERM_KEEP | 633 PHY_DIG1E_RX_TERM_KEEP | PHY_DIG1E_TX_EN_KEEP | 634 PHY_DIG1E_RX_EN_KEEP); 635 } 636 637 rtsx_pci_write_phy_register(pcr, PHY_ANA08, 638 PHY_ANA08_RX_EQ_DCGAIN | PHY_ANA08_SEL_RX_EN | 639 PHY_ANA08_RX_EQ_VAL | PHY_ANA08_SCP | PHY_ANA08_SEL_IPI); 640 641 return 0; 642 } 643 644 static int rts524a_extra_init_hw(struct rtsx_pcr *pcr) 645 { 646 rts5249_extra_init_hw(pcr); 647 648 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, 649 FORCE_ASPM_L1_EN, FORCE_ASPM_L1_EN); 650 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0); 651 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN, 652 LDO_VCC_LMT_EN); 653 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL); 654 if (is_version(pcr, 0x524A, IC_VER_A)) { 655 rtsx_pci_write_register(pcr, LDO_DV18_CFG, 656 LDO_DV18_SR_MASK, LDO_DV18_SR_DF); 657 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, 658 LDO_VCC_REF_TUNE_MASK, LDO_VCC_REF_1V2); 659 rtsx_pci_write_register(pcr, LDO_VIO_CFG, 660 LDO_VIO_REF_TUNE_MASK, LDO_VIO_REF_1V2); 661 rtsx_pci_write_register(pcr, LDO_VIO_CFG, 662 LDO_VIO_SR_MASK, LDO_VIO_SR_DF); 663 rtsx_pci_write_register(pcr, LDO_DV12S_CFG, 664 LDO_REF12_TUNE_MASK, LDO_REF12_TUNE_DF); 665 rtsx_pci_write_register(pcr, SD40_LDO_CTL1, 666 SD40_VIO_TUNE_MASK, SD40_VIO_TUNE_1V7); 667 } 668 669 return 0; 670 } 671 672 static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active) 673 { 674 struct rtsx_cr_option *option = &(pcr->option); 675 676 u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR); 677 int card_exist = (interrupt & SD_EXIST) | (interrupt & MS_EXIST); 678 int aspm_L1_1, aspm_L1_2; 679 u8 val = 0; 680 681 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN); 682 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN); 683 684 if (active) { 685 /* Run, latency: 60us */ 686 if (aspm_L1_1) 687 val = option->ltr_l1off_snooze_sspwrgate; 688 } else { 689 /* L1off, latency: 300us */ 690 if (aspm_L1_2) 691 val = option->ltr_l1off_sspwrgate; 692 } 693 694 if (aspm_L1_1 || aspm_L1_2) { 695 if (rtsx_check_dev_flag(pcr, 696 LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) { 697 if (card_exist) 698 val &= ~L1OFF_MBIAS2_EN_5250; 699 else 700 val |= L1OFF_MBIAS2_EN_5250; 701 } 702 } 703 rtsx_set_l1off_sub(pcr, val); 704 } 705 706 static const struct pcr_ops rts524a_pcr_ops = { 707 .write_phy = rts524a_write_phy, 708 .read_phy = rts524a_read_phy, 709 .fetch_vendor_settings = rtsx_base_fetch_vendor_settings, 710 .extra_init_hw = rts524a_extra_init_hw, 711 .optimize_phy = rts524a_optimize_phy, 712 .turn_on_led = rtsx_base_turn_on_led, 713 .turn_off_led = rtsx_base_turn_off_led, 714 .enable_auto_blink = rtsx_base_enable_auto_blink, 715 .disable_auto_blink = rtsx_base_disable_auto_blink, 716 .card_power_on = rtsx_base_card_power_on, 717 .card_power_off = rtsx_base_card_power_off, 718 .switch_output_voltage = rtsx_base_switch_output_voltage, 719 .force_power_down = rts52xa_force_power_down, 720 .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0, 721 }; 722 723 void rts524a_init_params(struct rtsx_pcr *pcr) 724 { 725 rts5249_init_params(pcr); 726 pcr->aspm_mode = ASPM_MODE_REG; 727 pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11); 728 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; 729 pcr->option.ltr_l1off_snooze_sspwrgate = 730 LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF; 731 732 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3; 733 pcr->ops = &rts524a_pcr_ops; 734 735 pcr->option.ocp_en = 1; 736 if (pcr->option.ocp_en) 737 pcr->hw_param.interrupt_en |= SD_OC_INT_EN; 738 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M; 739 pcr->option.sd_800mA_ocp_thd = RTS524A_OCP_THD_800; 740 741 } 742 743 static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card) 744 { 745 rtsx_pci_write_register(pcr, LDO_VCC_CFG1, 746 LDO_VCC_TUNE_MASK, LDO_VCC_3V3); 747 return rtsx_base_card_power_on(pcr, card); 748 } 749 750 static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) 751 { 752 switch (voltage) { 753 case OUTPUT_3V3: 754 rtsx_pci_write_register(pcr, LDO_CONFIG2, 755 LDO_D3318_MASK, LDO_D3318_33V); 756 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0); 757 break; 758 case OUTPUT_1V8: 759 rtsx_pci_write_register(pcr, LDO_CONFIG2, 760 LDO_D3318_MASK, LDO_D3318_18V); 761 rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 762 SD_IO_USING_1V8); 763 break; 764 default: 765 return -EINVAL; 766 } 767 768 rtsx_pci_init_cmd(pcr); 769 rts5249_fill_driving(pcr, voltage); 770 return rtsx_pci_send_cmd(pcr, 100); 771 } 772 773 static int rts525a_optimize_phy(struct rtsx_pcr *pcr) 774 { 775 int err; 776 777 err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 778 D3_DELINK_MODE_EN, 0x00); 779 if (err < 0) 780 return err; 781 782 rtsx_pci_write_phy_register(pcr, _PHY_FLD0, 783 _PHY_FLD0_CLK_REQ_20C | _PHY_FLD0_RX_IDLE_EN | 784 _PHY_FLD0_BIT_ERR_RSTN | _PHY_FLD0_BER_COUNT | 785 _PHY_FLD0_BER_TIMER | _PHY_FLD0_CHECK_EN); 786 787 rtsx_pci_write_phy_register(pcr, _PHY_ANA03, 788 _PHY_ANA03_TIMER_MAX | _PHY_ANA03_OOBS_DEB_EN | 789 _PHY_CMU_DEBUG_EN); 790 791 if (is_version(pcr, 0x525A, IC_VER_A)) 792 rtsx_pci_write_phy_register(pcr, _PHY_REV0, 793 _PHY_REV0_FILTER_OUT | _PHY_REV0_CDR_BYPASS_PFD | 794 _PHY_REV0_CDR_RX_IDLE_BYPASS); 795 796 return 0; 797 } 798 799 static int rts525a_extra_init_hw(struct rtsx_pcr *pcr) 800 { 801 rts5249_extra_init_hw(pcr); 802 803 rtsx_pci_write_register(pcr, RTS5250_CLK_CFG3, RTS525A_CFG_MEM_PD, RTS525A_CFG_MEM_PD); 804 805 rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL); 806 if (is_version(pcr, 0x525A, IC_VER_A)) { 807 rtsx_pci_write_register(pcr, L1SUB_CONFIG2, 808 L1SUB_AUTO_CFG, L1SUB_AUTO_CFG); 809 rtsx_pci_write_register(pcr, RREF_CFG, 810 RREF_VBGSEL_MASK, RREF_VBGSEL_1V25); 811 rtsx_pci_write_register(pcr, LDO_VIO_CFG, 812 LDO_VIO_TUNE_MASK, LDO_VIO_1V7); 813 rtsx_pci_write_register(pcr, LDO_DV12S_CFG, 814 LDO_D12_TUNE_MASK, LDO_D12_TUNE_DF); 815 rtsx_pci_write_register(pcr, LDO_AV12S_CFG, 816 LDO_AV12S_TUNE_MASK, LDO_AV12S_TUNE_DF); 817 rtsx_pci_write_register(pcr, LDO_VCC_CFG0, 818 LDO_VCC_LMTVTH_MASK, LDO_VCC_LMTVTH_2A); 819 rtsx_pci_write_register(pcr, OOBS_CONFIG, 820 OOBS_AUTOK_DIS | OOBS_VAL_MASK, 0x89); 821 } 822 823 return 0; 824 } 825 826 static const struct pcr_ops rts525a_pcr_ops = { 827 .fetch_vendor_settings = rtsx_base_fetch_vendor_settings, 828 .extra_init_hw = rts525a_extra_init_hw, 829 .optimize_phy = rts525a_optimize_phy, 830 .turn_on_led = rtsx_base_turn_on_led, 831 .turn_off_led = rtsx_base_turn_off_led, 832 .enable_auto_blink = rtsx_base_enable_auto_blink, 833 .disable_auto_blink = rtsx_base_disable_auto_blink, 834 .card_power_on = rts525a_card_power_on, 835 .card_power_off = rtsx_base_card_power_off, 836 .switch_output_voltage = rts525a_switch_output_voltage, 837 .force_power_down = rts52xa_force_power_down, 838 .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0, 839 }; 840 841 void rts525a_init_params(struct rtsx_pcr *pcr) 842 { 843 rts5249_init_params(pcr); 844 pcr->aspm_mode = ASPM_MODE_REG; 845 pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11); 846 pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; 847 pcr->option.ltr_l1off_snooze_sspwrgate = 848 LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF; 849 850 pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3; 851 pcr->ops = &rts525a_pcr_ops; 852 853 pcr->option.ocp_en = 1; 854 if (pcr->option.ocp_en) 855 pcr->hw_param.interrupt_en |= SD_OC_INT_EN; 856 pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M; 857 pcr->option.sd_800mA_ocp_thd = RTS525A_OCP_THD_800; 858 } 859