1*e455b69dSRui Feng /* Driver for Realtek PCI-Express card reader 2*e455b69dSRui Feng * 3*e455b69dSRui Feng * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 4*e455b69dSRui Feng * 5*e455b69dSRui Feng * This program is free software; you can redistribute it and/or modify it 6*e455b69dSRui Feng * under the terms of the GNU General Public License as published by the 7*e455b69dSRui Feng * Free Software Foundation; either version 2, or (at your option) any 8*e455b69dSRui Feng * later version. 9*e455b69dSRui Feng * 10*e455b69dSRui Feng * This program is distributed in the hope that it will be useful, but 11*e455b69dSRui Feng * WITHOUT ANY WARRANTY; without even the implied warranty of 12*e455b69dSRui Feng * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13*e455b69dSRui Feng * General Public License for more details. 14*e455b69dSRui Feng * 15*e455b69dSRui Feng * You should have received a copy of the GNU General Public License along 16*e455b69dSRui Feng * with this program; if not, see <http://www.gnu.org/licenses/>. 17*e455b69dSRui Feng * 18*e455b69dSRui Feng * Author: 19*e455b69dSRui Feng * Wei WANG <wei_wang@realsil.com.cn> 20*e455b69dSRui Feng */ 21*e455b69dSRui Feng 22*e455b69dSRui Feng #include <linux/module.h> 23*e455b69dSRui Feng #include <linux/delay.h> 24*e455b69dSRui Feng #include <linux/rtsx_pci.h> 25*e455b69dSRui Feng 26*e455b69dSRui Feng #include "rtsx_pcr.h" 27*e455b69dSRui Feng 28*e455b69dSRui Feng static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr) 29*e455b69dSRui Feng { 30*e455b69dSRui Feng u8 val; 31*e455b69dSRui Feng 32*e455b69dSRui Feng rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val); 33*e455b69dSRui Feng return val & 0x0F; 34*e455b69dSRui Feng } 35*e455b69dSRui Feng 36*e455b69dSRui Feng static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage) 37*e455b69dSRui Feng { 38*e455b69dSRui Feng u8 driving_3v3[4][3] = { 39*e455b69dSRui Feng {0x11, 0x11, 0x18}, 40*e455b69dSRui Feng {0x55, 0x55, 0x5C}, 41*e455b69dSRui Feng {0xFF, 0xFF, 0xFF}, 42*e455b69dSRui Feng {0x96, 0x96, 0x96}, 43*e455b69dSRui Feng }; 44*e455b69dSRui Feng u8 driving_1v8[4][3] = { 45*e455b69dSRui Feng {0xC4, 0xC4, 0xC4}, 46*e455b69dSRui Feng {0x3C, 0x3C, 0x3C}, 47*e455b69dSRui Feng {0xFE, 0xFE, 0xFE}, 48*e455b69dSRui Feng {0xB3, 0xB3, 0xB3}, 49*e455b69dSRui Feng }; 50*e455b69dSRui Feng u8 (*driving)[3], drive_sel; 51*e455b69dSRui Feng 52*e455b69dSRui Feng if (voltage == OUTPUT_3V3) { 53*e455b69dSRui Feng driving = driving_3v3; 54*e455b69dSRui Feng drive_sel = pcr->sd30_drive_sel_3v3; 55*e455b69dSRui Feng } else { 56*e455b69dSRui Feng driving = driving_1v8; 57*e455b69dSRui Feng drive_sel = pcr->sd30_drive_sel_1v8; 58*e455b69dSRui Feng } 59*e455b69dSRui Feng 60*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL, 61*e455b69dSRui Feng 0xFF, driving[drive_sel][0]); 62*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL, 63*e455b69dSRui Feng 0xFF, driving[drive_sel][1]); 64*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL, 65*e455b69dSRui Feng 0xFF, driving[drive_sel][2]); 66*e455b69dSRui Feng } 67*e455b69dSRui Feng 68*e455b69dSRui Feng static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr) 69*e455b69dSRui Feng { 70*e455b69dSRui Feng u32 reg; 71*e455b69dSRui Feng 72*e455b69dSRui Feng rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®); 73*e455b69dSRui Feng pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); 74*e455b69dSRui Feng 75*e455b69dSRui Feng if (!rtsx_vendor_setting_valid(reg)) { 76*e455b69dSRui Feng pcr_dbg(pcr, "skip fetch vendor setting\n"); 77*e455b69dSRui Feng return; 78*e455b69dSRui Feng } 79*e455b69dSRui Feng 80*e455b69dSRui Feng pcr->aspm_en = rtsx_reg_to_aspm(reg); 81*e455b69dSRui Feng pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg); 82*e455b69dSRui Feng pcr->card_drive_sel &= 0x3F; 83*e455b69dSRui Feng pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg); 84*e455b69dSRui Feng 85*e455b69dSRui Feng rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, ®); 86*e455b69dSRui Feng pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg); 87*e455b69dSRui Feng pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg); 88*e455b69dSRui Feng if (rtsx_reg_check_reverse_socket(reg)) 89*e455b69dSRui Feng pcr->flags |= PCR_REVERSE_SOCKET; 90*e455b69dSRui Feng } 91*e455b69dSRui Feng 92*e455b69dSRui Feng static void rtsx_base_force_power_down(struct rtsx_pcr *pcr, u8 pm_state) 93*e455b69dSRui Feng { 94*e455b69dSRui Feng /* Set relink_time to 0 */ 95*e455b69dSRui Feng rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, 0xFF, 0); 96*e455b69dSRui Feng rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, 0xFF, 0); 97*e455b69dSRui Feng rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 0x01, 0); 98*e455b69dSRui Feng 99*e455b69dSRui Feng if (pm_state == HOST_ENTER_S3) 100*e455b69dSRui Feng rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 101*e455b69dSRui Feng D3_DELINK_MODE_EN, D3_DELINK_MODE_EN); 102*e455b69dSRui Feng 103*e455b69dSRui Feng rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03); 104*e455b69dSRui Feng } 105*e455b69dSRui Feng 106*e455b69dSRui Feng static void rts5249_init_from_cfg(struct rtsx_pcr *pcr) 107*e455b69dSRui Feng { 108*e455b69dSRui Feng struct rtsx_cr_option *option = &(pcr->option); 109*e455b69dSRui Feng u32 lval; 110*e455b69dSRui Feng 111*e455b69dSRui Feng if (CHK_PCI_PID(pcr, PID_524A)) 112*e455b69dSRui Feng rtsx_pci_read_config_dword(pcr, 113*e455b69dSRui Feng PCR_ASPM_SETTING_REG1, &lval); 114*e455b69dSRui Feng else 115*e455b69dSRui Feng rtsx_pci_read_config_dword(pcr, 116*e455b69dSRui Feng PCR_ASPM_SETTING_REG2, &lval); 117*e455b69dSRui Feng 118*e455b69dSRui Feng if (lval & ASPM_L1_1_EN_MASK) 119*e455b69dSRui Feng rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); 120*e455b69dSRui Feng 121*e455b69dSRui Feng if (lval & ASPM_L1_2_EN_MASK) 122*e455b69dSRui Feng rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); 123*e455b69dSRui Feng 124*e455b69dSRui Feng if (lval & PM_L1_1_EN_MASK) 125*e455b69dSRui Feng rtsx_set_dev_flag(pcr, PM_L1_1_EN); 126*e455b69dSRui Feng 127*e455b69dSRui Feng if (lval & PM_L1_2_EN_MASK) 128*e455b69dSRui Feng rtsx_set_dev_flag(pcr, PM_L1_2_EN); 129*e455b69dSRui Feng 130*e455b69dSRui Feng if (option->ltr_en) { 131*e455b69dSRui Feng u16 val; 132*e455b69dSRui Feng 133*e455b69dSRui Feng pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val); 134*e455b69dSRui Feng if (val & PCI_EXP_DEVCTL2_LTR_EN) { 135*e455b69dSRui Feng option->ltr_enabled = true; 136*e455b69dSRui Feng option->ltr_active = true; 137*e455b69dSRui Feng rtsx_set_ltr_latency(pcr, option->ltr_active_latency); 138*e455b69dSRui Feng } else { 139*e455b69dSRui Feng option->ltr_enabled = false; 140*e455b69dSRui Feng } 141*e455b69dSRui Feng } 142*e455b69dSRui Feng } 143*e455b69dSRui Feng 144*e455b69dSRui Feng static int rts5249_init_from_hw(struct rtsx_pcr *pcr) 145*e455b69dSRui Feng { 146*e455b69dSRui Feng struct rtsx_cr_option *option = &(pcr->option); 147*e455b69dSRui Feng 148*e455b69dSRui Feng if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN 149*e455b69dSRui Feng | PM_L1_1_EN | PM_L1_2_EN)) 150*e455b69dSRui Feng option->force_clkreq_0 = false; 151*e455b69dSRui Feng else 152*e455b69dSRui Feng option->force_clkreq_0 = true; 153*e455b69dSRui Feng 154*e455b69dSRui Feng return 0; 155*e455b69dSRui Feng } 156*e455b69dSRui Feng 157*e455b69dSRui Feng static int rts5249_extra_init_hw(struct rtsx_pcr *pcr) 158*e455b69dSRui Feng { 159*e455b69dSRui Feng struct rtsx_cr_option *option = &(pcr->option); 160*e455b69dSRui Feng 161*e455b69dSRui Feng rts5249_init_from_cfg(pcr); 162*e455b69dSRui Feng rts5249_init_from_hw(pcr); 163*e455b69dSRui Feng 164*e455b69dSRui Feng rtsx_pci_init_cmd(pcr); 165*e455b69dSRui Feng 166*e455b69dSRui Feng /* Rest L1SUB Config */ 167*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00); 168*e455b69dSRui Feng /* Configure GPIO as output */ 169*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02); 170*e455b69dSRui Feng /* Reset ASPM state to default value */ 171*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0); 172*e455b69dSRui Feng /* Switch LDO3318 source from DV33 to card_3v3 */ 173*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00); 174*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01); 175*e455b69dSRui Feng /* LED shine disabled, set initial shine cycle period */ 176*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02); 177*e455b69dSRui Feng /* Configure driving */ 178*e455b69dSRui Feng rts5249_fill_driving(pcr, OUTPUT_3V3); 179*e455b69dSRui Feng if (pcr->flags & PCR_REVERSE_SOCKET) 180*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0); 181*e455b69dSRui Feng else 182*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80); 183*e455b69dSRui Feng 184*e455b69dSRui Feng /* 185*e455b69dSRui Feng * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced 186*e455b69dSRui Feng * to drive low, and we forcibly request clock. 187*e455b69dSRui Feng */ 188*e455b69dSRui Feng if (option->force_clkreq_0) 189*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 190*e455b69dSRui Feng FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); 191*e455b69dSRui Feng else 192*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 193*e455b69dSRui Feng FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); 194*e455b69dSRui Feng 195*e455b69dSRui Feng return rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF); 196*e455b69dSRui Feng } 197*e455b69dSRui Feng 198*e455b69dSRui Feng static int rts5249_optimize_phy(struct rtsx_pcr *pcr) 199*e455b69dSRui Feng { 200*e455b69dSRui Feng int err; 201*e455b69dSRui Feng 202*e455b69dSRui Feng err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00); 203*e455b69dSRui Feng if (err < 0) 204*e455b69dSRui Feng return err; 205*e455b69dSRui Feng 206*e455b69dSRui Feng err = rtsx_pci_write_phy_register(pcr, PHY_REV, 207*e455b69dSRui Feng PHY_REV_RESV | PHY_REV_RXIDLE_LATCHED | 208*e455b69dSRui Feng PHY_REV_P1_EN | PHY_REV_RXIDLE_EN | 209*e455b69dSRui Feng PHY_REV_CLKREQ_TX_EN | PHY_REV_RX_PWST | 210*e455b69dSRui Feng PHY_REV_CLKREQ_DT_1_0 | PHY_REV_STOP_CLKRD | 211*e455b69dSRui Feng PHY_REV_STOP_CLKWR); 212*e455b69dSRui Feng if (err < 0) 213*e455b69dSRui Feng return err; 214*e455b69dSRui Feng 215*e455b69dSRui Feng msleep(1); 216*e455b69dSRui Feng 217*e455b69dSRui Feng err = rtsx_pci_write_phy_register(pcr, PHY_BPCR, 218*e455b69dSRui Feng PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL | 219*e455b69dSRui Feng PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN); 220*e455b69dSRui Feng if (err < 0) 221*e455b69dSRui Feng return err; 222*e455b69dSRui Feng 223*e455b69dSRui Feng err = rtsx_pci_write_phy_register(pcr, PHY_PCR, 224*e455b69dSRui Feng PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 | 225*e455b69dSRui Feng PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | 226*e455b69dSRui Feng PHY_PCR_RSSI_EN | PHY_PCR_RX10K); 227*e455b69dSRui Feng if (err < 0) 228*e455b69dSRui Feng return err; 229*e455b69dSRui Feng 230*e455b69dSRui Feng err = rtsx_pci_write_phy_register(pcr, PHY_RCR2, 231*e455b69dSRui Feng PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR | 232*e455b69dSRui Feng PHY_RCR2_CDR_SR_2 | PHY_RCR2_FREQSEL_12 | 233*e455b69dSRui Feng PHY_RCR2_CDR_SC_12P | PHY_RCR2_CALIB_LATE); 234*e455b69dSRui Feng if (err < 0) 235*e455b69dSRui Feng return err; 236*e455b69dSRui Feng 237*e455b69dSRui Feng err = rtsx_pci_write_phy_register(pcr, PHY_FLD4, 238*e455b69dSRui Feng PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF | 239*e455b69dSRui Feng PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA | 240*e455b69dSRui Feng PHY_FLD4_BER_COUNT | PHY_FLD4_BER_TIMER | 241*e455b69dSRui Feng PHY_FLD4_BER_CHK_EN); 242*e455b69dSRui Feng if (err < 0) 243*e455b69dSRui Feng return err; 244*e455b69dSRui Feng err = rtsx_pci_write_phy_register(pcr, PHY_RDR, 245*e455b69dSRui Feng PHY_RDR_RXDSEL_1_9 | PHY_SSC_AUTO_PWD); 246*e455b69dSRui Feng if (err < 0) 247*e455b69dSRui Feng return err; 248*e455b69dSRui Feng err = rtsx_pci_write_phy_register(pcr, PHY_RCR1, 249*e455b69dSRui Feng PHY_RCR1_ADP_TIME_4 | PHY_RCR1_VCO_COARSE); 250*e455b69dSRui Feng if (err < 0) 251*e455b69dSRui Feng return err; 252*e455b69dSRui Feng err = rtsx_pci_write_phy_register(pcr, PHY_FLD3, 253*e455b69dSRui Feng PHY_FLD3_TIMER_4 | PHY_FLD3_TIMER_6 | 254*e455b69dSRui Feng PHY_FLD3_RXDELINK); 255*e455b69dSRui Feng if (err < 0) 256*e455b69dSRui Feng return err; 257*e455b69dSRui Feng 258*e455b69dSRui Feng return rtsx_pci_write_phy_register(pcr, PHY_TUNE, 259*e455b69dSRui Feng PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 | 260*e455b69dSRui Feng PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 | 261*e455b69dSRui Feng PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12); 262*e455b69dSRui Feng } 263*e455b69dSRui Feng 264*e455b69dSRui Feng static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr) 265*e455b69dSRui Feng { 266*e455b69dSRui Feng return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02); 267*e455b69dSRui Feng } 268*e455b69dSRui Feng 269*e455b69dSRui Feng static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr) 270*e455b69dSRui Feng { 271*e455b69dSRui Feng return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00); 272*e455b69dSRui Feng } 273*e455b69dSRui Feng 274*e455b69dSRui Feng static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr) 275*e455b69dSRui Feng { 276*e455b69dSRui Feng return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08); 277*e455b69dSRui Feng } 278*e455b69dSRui Feng 279*e455b69dSRui Feng static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr) 280*e455b69dSRui Feng { 281*e455b69dSRui Feng return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00); 282*e455b69dSRui Feng } 283*e455b69dSRui Feng 284*e455b69dSRui Feng static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card) 285*e455b69dSRui Feng { 286*e455b69dSRui Feng int err; 287*e455b69dSRui Feng 288*e455b69dSRui Feng rtsx_pci_init_cmd(pcr); 289*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, 290*e455b69dSRui Feng SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON); 291*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, 292*e455b69dSRui Feng LDO3318_PWR_MASK, 0x02); 293*e455b69dSRui Feng err = rtsx_pci_send_cmd(pcr, 100); 294*e455b69dSRui Feng if (err < 0) 295*e455b69dSRui Feng return err; 296*e455b69dSRui Feng 297*e455b69dSRui Feng msleep(5); 298*e455b69dSRui Feng 299*e455b69dSRui Feng rtsx_pci_init_cmd(pcr); 300*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, 301*e455b69dSRui Feng SD_POWER_MASK, SD_VCC_POWER_ON); 302*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, 303*e455b69dSRui Feng LDO3318_PWR_MASK, 0x06); 304*e455b69dSRui Feng return rtsx_pci_send_cmd(pcr, 100); 305*e455b69dSRui Feng } 306*e455b69dSRui Feng 307*e455b69dSRui Feng static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card) 308*e455b69dSRui Feng { 309*e455b69dSRui Feng rtsx_pci_init_cmd(pcr); 310*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, 311*e455b69dSRui Feng SD_POWER_MASK, SD_POWER_OFF); 312*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, 313*e455b69dSRui Feng LDO3318_PWR_MASK, 0x00); 314*e455b69dSRui Feng return rtsx_pci_send_cmd(pcr, 100); 315*e455b69dSRui Feng } 316*e455b69dSRui Feng 317*e455b69dSRui Feng static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) 318*e455b69dSRui Feng { 319*e455b69dSRui Feng int err; 320*e455b69dSRui Feng u16 append; 321*e455b69dSRui Feng 322*e455b69dSRui Feng switch (voltage) { 323*e455b69dSRui Feng case OUTPUT_3V3: 324*e455b69dSRui Feng err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK, 325*e455b69dSRui Feng PHY_TUNE_VOLTAGE_3V3); 326*e455b69dSRui Feng if (err < 0) 327*e455b69dSRui Feng return err; 328*e455b69dSRui Feng break; 329*e455b69dSRui Feng case OUTPUT_1V8: 330*e455b69dSRui Feng append = PHY_TUNE_D18_1V8; 331*e455b69dSRui Feng if (CHK_PCI_PID(pcr, 0x5249)) { 332*e455b69dSRui Feng err = rtsx_pci_update_phy(pcr, PHY_BACR, 333*e455b69dSRui Feng PHY_BACR_BASIC_MASK, 0); 334*e455b69dSRui Feng if (err < 0) 335*e455b69dSRui Feng return err; 336*e455b69dSRui Feng append = PHY_TUNE_D18_1V7; 337*e455b69dSRui Feng } 338*e455b69dSRui Feng 339*e455b69dSRui Feng err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK, 340*e455b69dSRui Feng append); 341*e455b69dSRui Feng if (err < 0) 342*e455b69dSRui Feng return err; 343*e455b69dSRui Feng break; 344*e455b69dSRui Feng default: 345*e455b69dSRui Feng pcr_dbg(pcr, "unknown output voltage %d\n", voltage); 346*e455b69dSRui Feng return -EINVAL; 347*e455b69dSRui Feng } 348*e455b69dSRui Feng 349*e455b69dSRui Feng /* set pad drive */ 350*e455b69dSRui Feng rtsx_pci_init_cmd(pcr); 351*e455b69dSRui Feng rts5249_fill_driving(pcr, voltage); 352*e455b69dSRui Feng return rtsx_pci_send_cmd(pcr, 100); 353*e455b69dSRui Feng } 354*e455b69dSRui Feng 355*e455b69dSRui Feng static void rts5249_set_aspm(struct rtsx_pcr *pcr, bool enable) 356*e455b69dSRui Feng { 357*e455b69dSRui Feng struct rtsx_cr_option *option = &pcr->option; 358*e455b69dSRui Feng u8 val = 0; 359*e455b69dSRui Feng 360*e455b69dSRui Feng if (pcr->aspm_enabled == enable) 361*e455b69dSRui Feng return; 362*e455b69dSRui Feng 363*e455b69dSRui Feng if (option->dev_aspm_mode == DEV_ASPM_DYNAMIC) { 364*e455b69dSRui Feng if (enable) 365*e455b69dSRui Feng val = pcr->aspm_en; 366*e455b69dSRui Feng rtsx_pci_update_cfg_byte(pcr, 367*e455b69dSRui Feng pcr->pcie_cap + PCI_EXP_LNKCTL, 368*e455b69dSRui Feng ASPM_MASK_NEG, val); 369*e455b69dSRui Feng } else if (option->dev_aspm_mode == DEV_ASPM_BACKDOOR) { 370*e455b69dSRui Feng u8 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0; 371*e455b69dSRui Feng 372*e455b69dSRui Feng if (!enable) 373*e455b69dSRui Feng val = FORCE_ASPM_CTL0; 374*e455b69dSRui Feng rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); 375*e455b69dSRui Feng } 376*e455b69dSRui Feng 377*e455b69dSRui Feng pcr->aspm_enabled = enable; 378*e455b69dSRui Feng } 379*e455b69dSRui Feng 380*e455b69dSRui Feng static const struct pcr_ops rts5249_pcr_ops = { 381*e455b69dSRui Feng .fetch_vendor_settings = rtsx_base_fetch_vendor_settings, 382*e455b69dSRui Feng .extra_init_hw = rts5249_extra_init_hw, 383*e455b69dSRui Feng .optimize_phy = rts5249_optimize_phy, 384*e455b69dSRui Feng .turn_on_led = rtsx_base_turn_on_led, 385*e455b69dSRui Feng .turn_off_led = rtsx_base_turn_off_led, 386*e455b69dSRui Feng .enable_auto_blink = rtsx_base_enable_auto_blink, 387*e455b69dSRui Feng .disable_auto_blink = rtsx_base_disable_auto_blink, 388*e455b69dSRui Feng .card_power_on = rtsx_base_card_power_on, 389*e455b69dSRui Feng .card_power_off = rtsx_base_card_power_off, 390*e455b69dSRui Feng .switch_output_voltage = rtsx_base_switch_output_voltage, 391*e455b69dSRui Feng .force_power_down = rtsx_base_force_power_down, 392*e455b69dSRui Feng .set_aspm = rts5249_set_aspm, 393*e455b69dSRui Feng }; 394*e455b69dSRui Feng 395*e455b69dSRui Feng /* SD Pull Control Enable: 396*e455b69dSRui Feng * SD_DAT[3:0] ==> pull up 397*e455b69dSRui Feng * SD_CD ==> pull up 398*e455b69dSRui Feng * SD_WP ==> pull up 399*e455b69dSRui Feng * SD_CMD ==> pull up 400*e455b69dSRui Feng * SD_CLK ==> pull down 401*e455b69dSRui Feng */ 402*e455b69dSRui Feng static const u32 rts5249_sd_pull_ctl_enable_tbl[] = { 403*e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66), 404*e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA), 405*e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9), 406*e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA), 407*e455b69dSRui Feng 0, 408*e455b69dSRui Feng }; 409*e455b69dSRui Feng 410*e455b69dSRui Feng /* SD Pull Control Disable: 411*e455b69dSRui Feng * SD_DAT[3:0] ==> pull down 412*e455b69dSRui Feng * SD_CD ==> pull up 413*e455b69dSRui Feng * SD_WP ==> pull down 414*e455b69dSRui Feng * SD_CMD ==> pull down 415*e455b69dSRui Feng * SD_CLK ==> pull down 416*e455b69dSRui Feng */ 417*e455b69dSRui Feng static const u32 rts5249_sd_pull_ctl_disable_tbl[] = { 418*e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66), 419*e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 420*e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5), 421*e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55), 422*e455b69dSRui Feng 0, 423*e455b69dSRui Feng }; 424*e455b69dSRui Feng 425*e455b69dSRui Feng /* MS Pull Control Enable: 426*e455b69dSRui Feng * MS CD ==> pull up 427*e455b69dSRui Feng * others ==> pull down 428*e455b69dSRui Feng */ 429*e455b69dSRui Feng static const u32 rts5249_ms_pull_ctl_enable_tbl[] = { 430*e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55), 431*e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55), 432*e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15), 433*e455b69dSRui Feng 0, 434*e455b69dSRui Feng }; 435*e455b69dSRui Feng 436*e455b69dSRui Feng /* MS Pull Control Disable: 437*e455b69dSRui Feng * MS CD ==> pull up 438*e455b69dSRui Feng * others ==> pull down 439*e455b69dSRui Feng */ 440*e455b69dSRui Feng static const u32 rts5249_ms_pull_ctl_disable_tbl[] = { 441*e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55), 442*e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55), 443*e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15), 444*e455b69dSRui Feng 0, 445*e455b69dSRui Feng }; 446*e455b69dSRui Feng 447*e455b69dSRui Feng void rts5249_init_params(struct rtsx_pcr *pcr) 448*e455b69dSRui Feng { 449*e455b69dSRui Feng struct rtsx_cr_option *option = &(pcr->option); 450*e455b69dSRui Feng 451*e455b69dSRui Feng pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; 452*e455b69dSRui Feng pcr->num_slots = 2; 453*e455b69dSRui Feng pcr->ops = &rts5249_pcr_ops; 454*e455b69dSRui Feng 455*e455b69dSRui Feng pcr->flags = 0; 456*e455b69dSRui Feng pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; 457*e455b69dSRui Feng pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; 458*e455b69dSRui Feng pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; 459*e455b69dSRui Feng pcr->aspm_en = ASPM_L1_EN; 460*e455b69dSRui Feng pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16); 461*e455b69dSRui Feng pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); 462*e455b69dSRui Feng 463*e455b69dSRui Feng pcr->ic_version = rts5249_get_ic_version(pcr); 464*e455b69dSRui Feng pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl; 465*e455b69dSRui Feng pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl; 466*e455b69dSRui Feng pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl; 467*e455b69dSRui Feng pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl; 468*e455b69dSRui Feng 469*e455b69dSRui Feng pcr->reg_pm_ctrl3 = PM_CTRL3; 470*e455b69dSRui Feng 471*e455b69dSRui Feng option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN 472*e455b69dSRui Feng | LTR_L1SS_PWR_GATE_EN); 473*e455b69dSRui Feng option->ltr_en = true; 474*e455b69dSRui Feng 475*e455b69dSRui Feng /* Init latency of active, idle, L1OFF to 60us, 300us, 3ms */ 476*e455b69dSRui Feng option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF; 477*e455b69dSRui Feng option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF; 478*e455b69dSRui Feng option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF; 479*e455b69dSRui Feng option->dev_aspm_mode = DEV_ASPM_DYNAMIC; 480*e455b69dSRui Feng option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF; 481*e455b69dSRui Feng option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5249_DEF; 482*e455b69dSRui Feng option->ltr_l1off_snooze_sspwrgate = 483*e455b69dSRui Feng LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF; 484*e455b69dSRui Feng } 485*e455b69dSRui Feng 486*e455b69dSRui Feng static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val) 487*e455b69dSRui Feng { 488*e455b69dSRui Feng addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr; 489*e455b69dSRui Feng 490*e455b69dSRui Feng return __rtsx_pci_write_phy_register(pcr, addr, val); 491*e455b69dSRui Feng } 492*e455b69dSRui Feng 493*e455b69dSRui Feng static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val) 494*e455b69dSRui Feng { 495*e455b69dSRui Feng addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr; 496*e455b69dSRui Feng 497*e455b69dSRui Feng return __rtsx_pci_read_phy_register(pcr, addr, val); 498*e455b69dSRui Feng } 499*e455b69dSRui Feng 500*e455b69dSRui Feng static int rts524a_optimize_phy(struct rtsx_pcr *pcr) 501*e455b69dSRui Feng { 502*e455b69dSRui Feng int err; 503*e455b69dSRui Feng 504*e455b69dSRui Feng err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 505*e455b69dSRui Feng D3_DELINK_MODE_EN, 0x00); 506*e455b69dSRui Feng if (err < 0) 507*e455b69dSRui Feng return err; 508*e455b69dSRui Feng 509*e455b69dSRui Feng rtsx_pci_write_phy_register(pcr, PHY_PCR, 510*e455b69dSRui Feng PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 | 511*e455b69dSRui Feng PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN); 512*e455b69dSRui Feng rtsx_pci_write_phy_register(pcr, PHY_SSCCR3, 513*e455b69dSRui Feng PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY); 514*e455b69dSRui Feng 515*e455b69dSRui Feng if (is_version(pcr, 0x524A, IC_VER_A)) { 516*e455b69dSRui Feng rtsx_pci_write_phy_register(pcr, PHY_SSCCR3, 517*e455b69dSRui Feng PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY); 518*e455b69dSRui Feng rtsx_pci_write_phy_register(pcr, PHY_SSCCR2, 519*e455b69dSRui Feng PHY_SSCCR2_PLL_NCODE | PHY_SSCCR2_TIME0 | 520*e455b69dSRui Feng PHY_SSCCR2_TIME2_WIDTH); 521*e455b69dSRui Feng rtsx_pci_write_phy_register(pcr, PHY_ANA1A, 522*e455b69dSRui Feng PHY_ANA1A_TXR_LOOPBACK | PHY_ANA1A_RXT_BIST | 523*e455b69dSRui Feng PHY_ANA1A_TXR_BIST | PHY_ANA1A_REV); 524*e455b69dSRui Feng rtsx_pci_write_phy_register(pcr, PHY_ANA1D, 525*e455b69dSRui Feng PHY_ANA1D_DEBUG_ADDR); 526*e455b69dSRui Feng rtsx_pci_write_phy_register(pcr, PHY_DIG1E, 527*e455b69dSRui Feng PHY_DIG1E_REV | PHY_DIG1E_D0_X_D1 | 528*e455b69dSRui Feng PHY_DIG1E_RX_ON_HOST | PHY_DIG1E_RCLK_REF_HOST | 529*e455b69dSRui Feng PHY_DIG1E_RCLK_TX_EN_KEEP | 530*e455b69dSRui Feng PHY_DIG1E_RCLK_TX_TERM_KEEP | 531*e455b69dSRui Feng PHY_DIG1E_RCLK_RX_EIDLE_ON | PHY_DIG1E_TX_TERM_KEEP | 532*e455b69dSRui Feng PHY_DIG1E_RX_TERM_KEEP | PHY_DIG1E_TX_EN_KEEP | 533*e455b69dSRui Feng PHY_DIG1E_RX_EN_KEEP); 534*e455b69dSRui Feng } 535*e455b69dSRui Feng 536*e455b69dSRui Feng rtsx_pci_write_phy_register(pcr, PHY_ANA08, 537*e455b69dSRui Feng PHY_ANA08_RX_EQ_DCGAIN | PHY_ANA08_SEL_RX_EN | 538*e455b69dSRui Feng PHY_ANA08_RX_EQ_VAL | PHY_ANA08_SCP | PHY_ANA08_SEL_IPI); 539*e455b69dSRui Feng 540*e455b69dSRui Feng return 0; 541*e455b69dSRui Feng } 542*e455b69dSRui Feng 543*e455b69dSRui Feng static int rts524a_extra_init_hw(struct rtsx_pcr *pcr) 544*e455b69dSRui Feng { 545*e455b69dSRui Feng rts5249_extra_init_hw(pcr); 546*e455b69dSRui Feng 547*e455b69dSRui Feng rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, 548*e455b69dSRui Feng FORCE_ASPM_L1_EN, FORCE_ASPM_L1_EN); 549*e455b69dSRui Feng rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0); 550*e455b69dSRui Feng rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN, 551*e455b69dSRui Feng LDO_VCC_LMT_EN); 552*e455b69dSRui Feng rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL); 553*e455b69dSRui Feng if (is_version(pcr, 0x524A, IC_VER_A)) { 554*e455b69dSRui Feng rtsx_pci_write_register(pcr, LDO_DV18_CFG, 555*e455b69dSRui Feng LDO_DV18_SR_MASK, LDO_DV18_SR_DF); 556*e455b69dSRui Feng rtsx_pci_write_register(pcr, LDO_VCC_CFG1, 557*e455b69dSRui Feng LDO_VCC_REF_TUNE_MASK, LDO_VCC_REF_1V2); 558*e455b69dSRui Feng rtsx_pci_write_register(pcr, LDO_VIO_CFG, 559*e455b69dSRui Feng LDO_VIO_REF_TUNE_MASK, LDO_VIO_REF_1V2); 560*e455b69dSRui Feng rtsx_pci_write_register(pcr, LDO_VIO_CFG, 561*e455b69dSRui Feng LDO_VIO_SR_MASK, LDO_VIO_SR_DF); 562*e455b69dSRui Feng rtsx_pci_write_register(pcr, LDO_DV12S_CFG, 563*e455b69dSRui Feng LDO_REF12_TUNE_MASK, LDO_REF12_TUNE_DF); 564*e455b69dSRui Feng rtsx_pci_write_register(pcr, SD40_LDO_CTL1, 565*e455b69dSRui Feng SD40_VIO_TUNE_MASK, SD40_VIO_TUNE_1V7); 566*e455b69dSRui Feng } 567*e455b69dSRui Feng 568*e455b69dSRui Feng return 0; 569*e455b69dSRui Feng } 570*e455b69dSRui Feng 571*e455b69dSRui Feng static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active) 572*e455b69dSRui Feng { 573*e455b69dSRui Feng struct rtsx_cr_option *option = &(pcr->option); 574*e455b69dSRui Feng 575*e455b69dSRui Feng u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR); 576*e455b69dSRui Feng int card_exist = (interrupt & SD_EXIST) | (interrupt & MS_EXIST); 577*e455b69dSRui Feng int aspm_L1_1, aspm_L1_2; 578*e455b69dSRui Feng u8 val = 0; 579*e455b69dSRui Feng 580*e455b69dSRui Feng aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN); 581*e455b69dSRui Feng aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN); 582*e455b69dSRui Feng 583*e455b69dSRui Feng if (active) { 584*e455b69dSRui Feng /* Run, latency: 60us */ 585*e455b69dSRui Feng if (aspm_L1_1) 586*e455b69dSRui Feng val = option->ltr_l1off_snooze_sspwrgate; 587*e455b69dSRui Feng } else { 588*e455b69dSRui Feng /* L1off, latency: 300us */ 589*e455b69dSRui Feng if (aspm_L1_2) 590*e455b69dSRui Feng val = option->ltr_l1off_sspwrgate; 591*e455b69dSRui Feng } 592*e455b69dSRui Feng 593*e455b69dSRui Feng if (aspm_L1_1 || aspm_L1_2) { 594*e455b69dSRui Feng if (rtsx_check_dev_flag(pcr, 595*e455b69dSRui Feng LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) { 596*e455b69dSRui Feng if (card_exist) 597*e455b69dSRui Feng val &= ~L1OFF_MBIAS2_EN_5250; 598*e455b69dSRui Feng else 599*e455b69dSRui Feng val |= L1OFF_MBIAS2_EN_5250; 600*e455b69dSRui Feng } 601*e455b69dSRui Feng } 602*e455b69dSRui Feng rtsx_set_l1off_sub(pcr, val); 603*e455b69dSRui Feng } 604*e455b69dSRui Feng 605*e455b69dSRui Feng static const struct pcr_ops rts524a_pcr_ops = { 606*e455b69dSRui Feng .write_phy = rts524a_write_phy, 607*e455b69dSRui Feng .read_phy = rts524a_read_phy, 608*e455b69dSRui Feng .fetch_vendor_settings = rtsx_base_fetch_vendor_settings, 609*e455b69dSRui Feng .extra_init_hw = rts524a_extra_init_hw, 610*e455b69dSRui Feng .optimize_phy = rts524a_optimize_phy, 611*e455b69dSRui Feng .turn_on_led = rtsx_base_turn_on_led, 612*e455b69dSRui Feng .turn_off_led = rtsx_base_turn_off_led, 613*e455b69dSRui Feng .enable_auto_blink = rtsx_base_enable_auto_blink, 614*e455b69dSRui Feng .disable_auto_blink = rtsx_base_disable_auto_blink, 615*e455b69dSRui Feng .card_power_on = rtsx_base_card_power_on, 616*e455b69dSRui Feng .card_power_off = rtsx_base_card_power_off, 617*e455b69dSRui Feng .switch_output_voltage = rtsx_base_switch_output_voltage, 618*e455b69dSRui Feng .force_power_down = rtsx_base_force_power_down, 619*e455b69dSRui Feng .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0, 620*e455b69dSRui Feng .set_aspm = rts5249_set_aspm, 621*e455b69dSRui Feng }; 622*e455b69dSRui Feng 623*e455b69dSRui Feng void rts524a_init_params(struct rtsx_pcr *pcr) 624*e455b69dSRui Feng { 625*e455b69dSRui Feng rts5249_init_params(pcr); 626*e455b69dSRui Feng pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; 627*e455b69dSRui Feng pcr->option.ltr_l1off_snooze_sspwrgate = 628*e455b69dSRui Feng LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF; 629*e455b69dSRui Feng 630*e455b69dSRui Feng pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3; 631*e455b69dSRui Feng pcr->ops = &rts524a_pcr_ops; 632*e455b69dSRui Feng } 633*e455b69dSRui Feng 634*e455b69dSRui Feng static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card) 635*e455b69dSRui Feng { 636*e455b69dSRui Feng rtsx_pci_write_register(pcr, LDO_VCC_CFG1, 637*e455b69dSRui Feng LDO_VCC_TUNE_MASK, LDO_VCC_3V3); 638*e455b69dSRui Feng return rtsx_base_card_power_on(pcr, card); 639*e455b69dSRui Feng } 640*e455b69dSRui Feng 641*e455b69dSRui Feng static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) 642*e455b69dSRui Feng { 643*e455b69dSRui Feng switch (voltage) { 644*e455b69dSRui Feng case OUTPUT_3V3: 645*e455b69dSRui Feng rtsx_pci_write_register(pcr, LDO_CONFIG2, 646*e455b69dSRui Feng LDO_D3318_MASK, LDO_D3318_33V); 647*e455b69dSRui Feng rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0); 648*e455b69dSRui Feng break; 649*e455b69dSRui Feng case OUTPUT_1V8: 650*e455b69dSRui Feng rtsx_pci_write_register(pcr, LDO_CONFIG2, 651*e455b69dSRui Feng LDO_D3318_MASK, LDO_D3318_18V); 652*e455b69dSRui Feng rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 653*e455b69dSRui Feng SD_IO_USING_1V8); 654*e455b69dSRui Feng break; 655*e455b69dSRui Feng default: 656*e455b69dSRui Feng return -EINVAL; 657*e455b69dSRui Feng } 658*e455b69dSRui Feng 659*e455b69dSRui Feng rtsx_pci_init_cmd(pcr); 660*e455b69dSRui Feng rts5249_fill_driving(pcr, voltage); 661*e455b69dSRui Feng return rtsx_pci_send_cmd(pcr, 100); 662*e455b69dSRui Feng } 663*e455b69dSRui Feng 664*e455b69dSRui Feng static int rts525a_optimize_phy(struct rtsx_pcr *pcr) 665*e455b69dSRui Feng { 666*e455b69dSRui Feng int err; 667*e455b69dSRui Feng 668*e455b69dSRui Feng err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 669*e455b69dSRui Feng D3_DELINK_MODE_EN, 0x00); 670*e455b69dSRui Feng if (err < 0) 671*e455b69dSRui Feng return err; 672*e455b69dSRui Feng 673*e455b69dSRui Feng rtsx_pci_write_phy_register(pcr, _PHY_FLD0, 674*e455b69dSRui Feng _PHY_FLD0_CLK_REQ_20C | _PHY_FLD0_RX_IDLE_EN | 675*e455b69dSRui Feng _PHY_FLD0_BIT_ERR_RSTN | _PHY_FLD0_BER_COUNT | 676*e455b69dSRui Feng _PHY_FLD0_BER_TIMER | _PHY_FLD0_CHECK_EN); 677*e455b69dSRui Feng 678*e455b69dSRui Feng rtsx_pci_write_phy_register(pcr, _PHY_ANA03, 679*e455b69dSRui Feng _PHY_ANA03_TIMER_MAX | _PHY_ANA03_OOBS_DEB_EN | 680*e455b69dSRui Feng _PHY_CMU_DEBUG_EN); 681*e455b69dSRui Feng 682*e455b69dSRui Feng if (is_version(pcr, 0x525A, IC_VER_A)) 683*e455b69dSRui Feng rtsx_pci_write_phy_register(pcr, _PHY_REV0, 684*e455b69dSRui Feng _PHY_REV0_FILTER_OUT | _PHY_REV0_CDR_BYPASS_PFD | 685*e455b69dSRui Feng _PHY_REV0_CDR_RX_IDLE_BYPASS); 686*e455b69dSRui Feng 687*e455b69dSRui Feng return 0; 688*e455b69dSRui Feng } 689*e455b69dSRui Feng 690*e455b69dSRui Feng static int rts525a_extra_init_hw(struct rtsx_pcr *pcr) 691*e455b69dSRui Feng { 692*e455b69dSRui Feng rts5249_extra_init_hw(pcr); 693*e455b69dSRui Feng 694*e455b69dSRui Feng rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL); 695*e455b69dSRui Feng if (is_version(pcr, 0x525A, IC_VER_A)) { 696*e455b69dSRui Feng rtsx_pci_write_register(pcr, L1SUB_CONFIG2, 697*e455b69dSRui Feng L1SUB_AUTO_CFG, L1SUB_AUTO_CFG); 698*e455b69dSRui Feng rtsx_pci_write_register(pcr, RREF_CFG, 699*e455b69dSRui Feng RREF_VBGSEL_MASK, RREF_VBGSEL_1V25); 700*e455b69dSRui Feng rtsx_pci_write_register(pcr, LDO_VIO_CFG, 701*e455b69dSRui Feng LDO_VIO_TUNE_MASK, LDO_VIO_1V7); 702*e455b69dSRui Feng rtsx_pci_write_register(pcr, LDO_DV12S_CFG, 703*e455b69dSRui Feng LDO_D12_TUNE_MASK, LDO_D12_TUNE_DF); 704*e455b69dSRui Feng rtsx_pci_write_register(pcr, LDO_AV12S_CFG, 705*e455b69dSRui Feng LDO_AV12S_TUNE_MASK, LDO_AV12S_TUNE_DF); 706*e455b69dSRui Feng rtsx_pci_write_register(pcr, LDO_VCC_CFG0, 707*e455b69dSRui Feng LDO_VCC_LMTVTH_MASK, LDO_VCC_LMTVTH_2A); 708*e455b69dSRui Feng rtsx_pci_write_register(pcr, OOBS_CONFIG, 709*e455b69dSRui Feng OOBS_AUTOK_DIS | OOBS_VAL_MASK, 0x89); 710*e455b69dSRui Feng } 711*e455b69dSRui Feng 712*e455b69dSRui Feng return 0; 713*e455b69dSRui Feng } 714*e455b69dSRui Feng 715*e455b69dSRui Feng static const struct pcr_ops rts525a_pcr_ops = { 716*e455b69dSRui Feng .fetch_vendor_settings = rtsx_base_fetch_vendor_settings, 717*e455b69dSRui Feng .extra_init_hw = rts525a_extra_init_hw, 718*e455b69dSRui Feng .optimize_phy = rts525a_optimize_phy, 719*e455b69dSRui Feng .turn_on_led = rtsx_base_turn_on_led, 720*e455b69dSRui Feng .turn_off_led = rtsx_base_turn_off_led, 721*e455b69dSRui Feng .enable_auto_blink = rtsx_base_enable_auto_blink, 722*e455b69dSRui Feng .disable_auto_blink = rtsx_base_disable_auto_blink, 723*e455b69dSRui Feng .card_power_on = rts525a_card_power_on, 724*e455b69dSRui Feng .card_power_off = rtsx_base_card_power_off, 725*e455b69dSRui Feng .switch_output_voltage = rts525a_switch_output_voltage, 726*e455b69dSRui Feng .force_power_down = rtsx_base_force_power_down, 727*e455b69dSRui Feng .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0, 728*e455b69dSRui Feng .set_aspm = rts5249_set_aspm, 729*e455b69dSRui Feng }; 730*e455b69dSRui Feng 731*e455b69dSRui Feng void rts525a_init_params(struct rtsx_pcr *pcr) 732*e455b69dSRui Feng { 733*e455b69dSRui Feng rts5249_init_params(pcr); 734*e455b69dSRui Feng pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; 735*e455b69dSRui Feng pcr->option.ltr_l1off_snooze_sspwrgate = 736*e455b69dSRui Feng LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF; 737*e455b69dSRui Feng 738*e455b69dSRui Feng pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3; 739*e455b69dSRui Feng pcr->ops = &rts525a_pcr_ops; 740*e455b69dSRui Feng } 741