1aaf4989bSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2e455b69dSRui Feng /* Driver for Realtek PCI-Express card reader 3e455b69dSRui Feng * 4e455b69dSRui Feng * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 5e455b69dSRui Feng * 6e455b69dSRui Feng * Author: 7e455b69dSRui Feng * Wei WANG <wei_wang@realsil.com.cn> 8e455b69dSRui Feng */ 9e455b69dSRui Feng 10e455b69dSRui Feng #include <linux/module.h> 11e455b69dSRui Feng #include <linux/delay.h> 12e455b69dSRui Feng #include <linux/rtsx_pci.h> 13e455b69dSRui Feng 14e455b69dSRui Feng #include "rtsx_pcr.h" 15e455b69dSRui Feng 16e455b69dSRui Feng static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr) 17e455b69dSRui Feng { 18e455b69dSRui Feng u8 val; 19e455b69dSRui Feng 20e455b69dSRui Feng rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val); 21e455b69dSRui Feng return val & 0x0F; 22e455b69dSRui Feng } 23e455b69dSRui Feng 24e455b69dSRui Feng static void rts5249_fill_driving(struct rtsx_pcr *pcr, u8 voltage) 25e455b69dSRui Feng { 26e455b69dSRui Feng u8 driving_3v3[4][3] = { 27e455b69dSRui Feng {0x11, 0x11, 0x18}, 28e455b69dSRui Feng {0x55, 0x55, 0x5C}, 29e455b69dSRui Feng {0xFF, 0xFF, 0xFF}, 30e455b69dSRui Feng {0x96, 0x96, 0x96}, 31e455b69dSRui Feng }; 32e455b69dSRui Feng u8 driving_1v8[4][3] = { 33e455b69dSRui Feng {0xC4, 0xC4, 0xC4}, 34e455b69dSRui Feng {0x3C, 0x3C, 0x3C}, 35e455b69dSRui Feng {0xFE, 0xFE, 0xFE}, 36e455b69dSRui Feng {0xB3, 0xB3, 0xB3}, 37e455b69dSRui Feng }; 38e455b69dSRui Feng u8 (*driving)[3], drive_sel; 39e455b69dSRui Feng 40e455b69dSRui Feng if (voltage == OUTPUT_3V3) { 41e455b69dSRui Feng driving = driving_3v3; 42e455b69dSRui Feng drive_sel = pcr->sd30_drive_sel_3v3; 43e455b69dSRui Feng } else { 44e455b69dSRui Feng driving = driving_1v8; 45e455b69dSRui Feng drive_sel = pcr->sd30_drive_sel_1v8; 46e455b69dSRui Feng } 47e455b69dSRui Feng 48e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL, 49e455b69dSRui Feng 0xFF, driving[drive_sel][0]); 50e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL, 51e455b69dSRui Feng 0xFF, driving[drive_sel][1]); 52e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL, 53e455b69dSRui Feng 0xFF, driving[drive_sel][2]); 54e455b69dSRui Feng } 55e455b69dSRui Feng 56e455b69dSRui Feng static void rtsx_base_fetch_vendor_settings(struct rtsx_pcr *pcr) 57e455b69dSRui Feng { 5822bf3251SBjorn Helgaas struct pci_dev *pdev = pcr->pci; 59e455b69dSRui Feng u32 reg; 60e455b69dSRui Feng 6122bf3251SBjorn Helgaas pci_read_config_dword(pdev, PCR_SETTING_REG1, ®); 62e455b69dSRui Feng pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); 63e455b69dSRui Feng 64e455b69dSRui Feng if (!rtsx_vendor_setting_valid(reg)) { 65e455b69dSRui Feng pcr_dbg(pcr, "skip fetch vendor setting\n"); 66e455b69dSRui Feng return; 67e455b69dSRui Feng } 68e455b69dSRui Feng 69e455b69dSRui Feng pcr->aspm_en = rtsx_reg_to_aspm(reg); 70e455b69dSRui Feng pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg); 71e455b69dSRui Feng pcr->card_drive_sel &= 0x3F; 72e455b69dSRui Feng pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg); 73e455b69dSRui Feng 7422bf3251SBjorn Helgaas pci_read_config_dword(pdev, PCR_SETTING_REG2, ®); 75e455b69dSRui Feng pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg); 76*7c33e3c4SRicky Wu if (rtsx_check_mmc_support(reg)) 77*7c33e3c4SRicky Wu pcr->extra_caps |= EXTRA_CAPS_NO_MMC; 78e455b69dSRui Feng pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg); 79e455b69dSRui Feng if (rtsx_reg_check_reverse_socket(reg)) 80e455b69dSRui Feng pcr->flags |= PCR_REVERSE_SOCKET; 81e455b69dSRui Feng } 82e455b69dSRui Feng 83e455b69dSRui Feng static void rts5249_init_from_cfg(struct rtsx_pcr *pcr) 84e455b69dSRui Feng { 8522bf3251SBjorn Helgaas struct pci_dev *pdev = pcr->pci; 86ed86a987SBjorn Helgaas int l1ss; 87e455b69dSRui Feng struct rtsx_cr_option *option = &(pcr->option); 88e455b69dSRui Feng u32 lval; 89e455b69dSRui Feng 90ed86a987SBjorn Helgaas l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS); 91ed86a987SBjorn Helgaas if (!l1ss) 92ed86a987SBjorn Helgaas return; 93ed86a987SBjorn Helgaas 94ed86a987SBjorn Helgaas pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval); 95e455b69dSRui Feng 96*7c33e3c4SRicky Wu if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { 97*7c33e3c4SRicky Wu if (0 == (lval & 0x0F)) 98*7c33e3c4SRicky Wu rtsx_pci_enable_oobs_polling(pcr); 99*7c33e3c4SRicky Wu else 100*7c33e3c4SRicky Wu rtsx_pci_disable_oobs_polling(pcr); 101*7c33e3c4SRicky Wu } 102*7c33e3c4SRicky Wu 103*7c33e3c4SRicky Wu 1047a4462a9SBjorn Helgaas if (lval & PCI_L1SS_CTL1_ASPM_L1_1) 105e455b69dSRui Feng rtsx_set_dev_flag(pcr, ASPM_L1_1_EN); 106e455b69dSRui Feng 1077a4462a9SBjorn Helgaas if (lval & PCI_L1SS_CTL1_ASPM_L1_2) 108e455b69dSRui Feng rtsx_set_dev_flag(pcr, ASPM_L1_2_EN); 109e455b69dSRui Feng 1107a4462a9SBjorn Helgaas if (lval & PCI_L1SS_CTL1_PCIPM_L1_1) 111e455b69dSRui Feng rtsx_set_dev_flag(pcr, PM_L1_1_EN); 112e455b69dSRui Feng 1137a4462a9SBjorn Helgaas if (lval & PCI_L1SS_CTL1_PCIPM_L1_2) 114e455b69dSRui Feng rtsx_set_dev_flag(pcr, PM_L1_2_EN); 115e455b69dSRui Feng 116e455b69dSRui Feng if (option->ltr_en) { 117e455b69dSRui Feng u16 val; 118e455b69dSRui Feng 11922bf3251SBjorn Helgaas pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &val); 120e455b69dSRui Feng if (val & PCI_EXP_DEVCTL2_LTR_EN) { 121e455b69dSRui Feng option->ltr_enabled = true; 122e455b69dSRui Feng option->ltr_active = true; 123e455b69dSRui Feng rtsx_set_ltr_latency(pcr, option->ltr_active_latency); 124e455b69dSRui Feng } else { 125e455b69dSRui Feng option->ltr_enabled = false; 126e455b69dSRui Feng } 127e455b69dSRui Feng } 128e455b69dSRui Feng } 129e455b69dSRui Feng 130e455b69dSRui Feng static int rts5249_init_from_hw(struct rtsx_pcr *pcr) 131e455b69dSRui Feng { 132e455b69dSRui Feng struct rtsx_cr_option *option = &(pcr->option); 133e455b69dSRui Feng 134e455b69dSRui Feng if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN 135e455b69dSRui Feng | PM_L1_1_EN | PM_L1_2_EN)) 136e455b69dSRui Feng option->force_clkreq_0 = false; 137e455b69dSRui Feng else 138e455b69dSRui Feng option->force_clkreq_0 = true; 139e455b69dSRui Feng 140e455b69dSRui Feng return 0; 141e455b69dSRui Feng } 142e455b69dSRui Feng 143*7c33e3c4SRicky Wu static void rts52xa_save_content_from_efuse(struct rtsx_pcr *pcr) 144*7c33e3c4SRicky Wu { 145*7c33e3c4SRicky Wu u8 cnt, sv; 146*7c33e3c4SRicky Wu u16 j = 0; 147*7c33e3c4SRicky Wu u8 tmp; 148*7c33e3c4SRicky Wu u8 val; 149*7c33e3c4SRicky Wu int i; 150*7c33e3c4SRicky Wu 151*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 152*7c33e3c4SRicky Wu REG_EFUSE_BYPASS | REG_EFUSE_POR, REG_EFUSE_POR); 153*7c33e3c4SRicky Wu udelay(1); 154*7c33e3c4SRicky Wu 155*7c33e3c4SRicky Wu pcr_dbg(pcr, "Enable efuse por!"); 156*7c33e3c4SRicky Wu pcr_dbg(pcr, "save efuse to autoload"); 157*7c33e3c4SRicky Wu 158*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, REG_EFUSE_ADD_MASK, 0x00); 159*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL, 160*7c33e3c4SRicky Wu REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE); 161*7c33e3c4SRicky Wu /* Wait transfer end */ 162*7c33e3c4SRicky Wu for (j = 0; j < 1024; j++) { 163*7c33e3c4SRicky Wu rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp); 164*7c33e3c4SRicky Wu if ((tmp & 0x80) == 0) 165*7c33e3c4SRicky Wu break; 166*7c33e3c4SRicky Wu } 167*7c33e3c4SRicky Wu rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val); 168*7c33e3c4SRicky Wu cnt = val & 0x0F; 169*7c33e3c4SRicky Wu sv = val & 0x10; 170*7c33e3c4SRicky Wu 171*7c33e3c4SRicky Wu if (sv) { 172*7c33e3c4SRicky Wu for (i = 0; i < 4; i++) { 173*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, 174*7c33e3c4SRicky Wu REG_EFUSE_ADD_MASK, 0x04 + i); 175*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL, 176*7c33e3c4SRicky Wu REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE); 177*7c33e3c4SRicky Wu /* Wait transfer end */ 178*7c33e3c4SRicky Wu for (j = 0; j < 1024; j++) { 179*7c33e3c4SRicky Wu rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp); 180*7c33e3c4SRicky Wu if ((tmp & 0x80) == 0) 181*7c33e3c4SRicky Wu break; 182*7c33e3c4SRicky Wu } 183*7c33e3c4SRicky Wu rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val); 184*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, 0xFF04 + i, 0xFF, val); 185*7c33e3c4SRicky Wu } 186*7c33e3c4SRicky Wu } else { 187*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr)); 188*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8)); 189*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr)); 190*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8)); 191*7c33e3c4SRicky Wu } 192*7c33e3c4SRicky Wu 193*7c33e3c4SRicky Wu for (i = 0; i < cnt * 4; i++) { 194*7c33e3c4SRicky Wu if (sv) 195*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, 196*7c33e3c4SRicky Wu REG_EFUSE_ADD_MASK, 0x08 + i); 197*7c33e3c4SRicky Wu else 198*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, RTS525A_EFUSE_ADD, 199*7c33e3c4SRicky Wu REG_EFUSE_ADD_MASK, 0x04 + i); 200*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, RTS525A_EFUSE_CTL, 201*7c33e3c4SRicky Wu REG_EFUSE_ENABLE | REG_EFUSE_MODE, REG_EFUSE_ENABLE); 202*7c33e3c4SRicky Wu /* Wait transfer end */ 203*7c33e3c4SRicky Wu for (j = 0; j < 1024; j++) { 204*7c33e3c4SRicky Wu rtsx_pci_read_register(pcr, RTS525A_EFUSE_CTL, &tmp); 205*7c33e3c4SRicky Wu if ((tmp & 0x80) == 0) 206*7c33e3c4SRicky Wu break; 207*7c33e3c4SRicky Wu } 208*7c33e3c4SRicky Wu rtsx_pci_read_register(pcr, RTS525A_EFUSE_DATA, &val); 209*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, 0xFF08 + i, 0xFF, val); 210*7c33e3c4SRicky Wu } 211*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, 0xFF00, 0xFF, (cnt & 0x7F) | 0x80); 212*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 213*7c33e3c4SRicky Wu REG_EFUSE_BYPASS | REG_EFUSE_POR, REG_EFUSE_BYPASS); 214*7c33e3c4SRicky Wu pcr_dbg(pcr, "Disable efuse por!"); 215*7c33e3c4SRicky Wu } 216*7c33e3c4SRicky Wu 217*7c33e3c4SRicky Wu static void rts52xa_save_content_to_autoload_space(struct rtsx_pcr *pcr) 218*7c33e3c4SRicky Wu { 219*7c33e3c4SRicky Wu u8 val; 220*7c33e3c4SRicky Wu 221*7c33e3c4SRicky Wu rtsx_pci_read_register(pcr, RESET_LOAD_REG, &val); 222*7c33e3c4SRicky Wu if (val & 0x02) { 223*7c33e3c4SRicky Wu rtsx_pci_read_register(pcr, RTS525A_BIOS_CFG, &val); 224*7c33e3c4SRicky Wu if (val & RTS525A_LOAD_BIOS_FLAG) { 225*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, RTS525A_BIOS_CFG, 226*7c33e3c4SRicky Wu RTS525A_LOAD_BIOS_FLAG, RTS525A_CLEAR_BIOS_FLAG); 227*7c33e3c4SRicky Wu 228*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 229*7c33e3c4SRicky Wu REG_EFUSE_POWER_MASK, REG_EFUSE_POWERON); 230*7c33e3c4SRicky Wu 231*7c33e3c4SRicky Wu pcr_dbg(pcr, "Power ON efuse!"); 232*7c33e3c4SRicky Wu mdelay(1); 233*7c33e3c4SRicky Wu rts52xa_save_content_from_efuse(pcr); 234*7c33e3c4SRicky Wu } else { 235*7c33e3c4SRicky Wu rtsx_pci_read_register(pcr, RTS524A_PME_FORCE_CTL, &val); 236*7c33e3c4SRicky Wu if (!(val & 0x08)) 237*7c33e3c4SRicky Wu rts52xa_save_content_from_efuse(pcr); 238*7c33e3c4SRicky Wu } 239*7c33e3c4SRicky Wu } else { 240*7c33e3c4SRicky Wu pcr_dbg(pcr, "Load from autoload"); 241*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, 0xFF00, 0xFF, 0x80); 242*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, 0xFF04, 0xFF, (u8)PCI_VID(pcr)); 243*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, 0xFF05, 0xFF, (u8)(PCI_VID(pcr) >> 8)); 244*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, 0xFF06, 0xFF, (u8)PCI_PID(pcr)); 245*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, 0xFF07, 0xFF, (u8)(PCI_PID(pcr) >> 8)); 246*7c33e3c4SRicky Wu } 247*7c33e3c4SRicky Wu } 248*7c33e3c4SRicky Wu 249e455b69dSRui Feng static int rts5249_extra_init_hw(struct rtsx_pcr *pcr) 250e455b69dSRui Feng { 251e455b69dSRui Feng struct rtsx_cr_option *option = &(pcr->option); 252e455b69dSRui Feng 253e455b69dSRui Feng rts5249_init_from_cfg(pcr); 254e455b69dSRui Feng rts5249_init_from_hw(pcr); 255e455b69dSRui Feng 256e455b69dSRui Feng rtsx_pci_init_cmd(pcr); 257e455b69dSRui Feng 258*7c33e3c4SRicky Wu if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) 259*7c33e3c4SRicky Wu rts52xa_save_content_to_autoload_space(pcr); 260*7c33e3c4SRicky Wu 261e455b69dSRui Feng /* Rest L1SUB Config */ 262e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, L1SUB_CONFIG3, 0xFF, 0x00); 263e455b69dSRui Feng /* Configure GPIO as output */ 264e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02); 265e455b69dSRui Feng /* Reset ASPM state to default value */ 266e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0); 267e455b69dSRui Feng /* Switch LDO3318 source from DV33 to card_3v3 */ 268e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00); 269e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01); 270e455b69dSRui Feng /* LED shine disabled, set initial shine cycle period */ 271e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02); 272e455b69dSRui Feng /* Configure driving */ 273e455b69dSRui Feng rts5249_fill_driving(pcr, OUTPUT_3V3); 274e455b69dSRui Feng if (pcr->flags & PCR_REVERSE_SOCKET) 275e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0xB0); 276e455b69dSRui Feng else 277e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0xB0, 0x80); 278e455b69dSRui Feng 279*7c33e3c4SRicky Wu rtsx_pci_send_cmd(pcr, CMD_TIMEOUT_DEF); 280*7c33e3c4SRicky Wu 281*7c33e3c4SRicky Wu if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { 282*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, REG_VREF, PWD_SUSPND_EN, PWD_SUSPND_EN); 283*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 0x01, 0x00); 284*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 0x30, 0x20); 285*7c33e3c4SRicky Wu } else { 286*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, PME_FORCE_CTL, 0xFF, 0x30); 287*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, PM_CTRL3, 0x01, 0x00); 288*7c33e3c4SRicky Wu } 289*7c33e3c4SRicky Wu 290e455b69dSRui Feng /* 291e455b69dSRui Feng * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced 292e455b69dSRui Feng * to drive low, and we forcibly request clock. 293e455b69dSRui Feng */ 294e455b69dSRui Feng if (option->force_clkreq_0) 295*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, PETXCFG, 296e455b69dSRui Feng FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); 297e455b69dSRui Feng else 298*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, PETXCFG, 299e455b69dSRui Feng FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); 300e455b69dSRui Feng 301*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x10, 0x00); 302*7c33e3c4SRicky Wu if (CHK_PCI_PID(pcr, PID_524A) || CHK_PCI_PID(pcr, PID_525A)) { 303*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, RTS524A_PME_FORCE_CTL, 304*7c33e3c4SRicky Wu REG_EFUSE_POWER_MASK, REG_EFUSE_POWEROFF); 305*7c33e3c4SRicky Wu pcr_dbg(pcr, "Power OFF efuse!"); 306*7c33e3c4SRicky Wu } 307*7c33e3c4SRicky Wu 308*7c33e3c4SRicky Wu return 0; 309e455b69dSRui Feng } 310e455b69dSRui Feng 311e455b69dSRui Feng static int rts5249_optimize_phy(struct rtsx_pcr *pcr) 312e455b69dSRui Feng { 313e455b69dSRui Feng int err; 314e455b69dSRui Feng 315e455b69dSRui Feng err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00); 316e455b69dSRui Feng if (err < 0) 317e455b69dSRui Feng return err; 318e455b69dSRui Feng 319e455b69dSRui Feng err = rtsx_pci_write_phy_register(pcr, PHY_REV, 320e455b69dSRui Feng PHY_REV_RESV | PHY_REV_RXIDLE_LATCHED | 321e455b69dSRui Feng PHY_REV_P1_EN | PHY_REV_RXIDLE_EN | 322e455b69dSRui Feng PHY_REV_CLKREQ_TX_EN | PHY_REV_RX_PWST | 323e455b69dSRui Feng PHY_REV_CLKREQ_DT_1_0 | PHY_REV_STOP_CLKRD | 324e455b69dSRui Feng PHY_REV_STOP_CLKWR); 325e455b69dSRui Feng if (err < 0) 326e455b69dSRui Feng return err; 327e455b69dSRui Feng 328e455b69dSRui Feng msleep(1); 329e455b69dSRui Feng 330e455b69dSRui Feng err = rtsx_pci_write_phy_register(pcr, PHY_BPCR, 331e455b69dSRui Feng PHY_BPCR_IBRXSEL | PHY_BPCR_IBTXSEL | 332e455b69dSRui Feng PHY_BPCR_IB_FILTER | PHY_BPCR_CMIRROR_EN); 333e455b69dSRui Feng if (err < 0) 334e455b69dSRui Feng return err; 335e455b69dSRui Feng 336e455b69dSRui Feng err = rtsx_pci_write_phy_register(pcr, PHY_PCR, 337e455b69dSRui Feng PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 | 338e455b69dSRui Feng PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | 339e455b69dSRui Feng PHY_PCR_RSSI_EN | PHY_PCR_RX10K); 340e455b69dSRui Feng if (err < 0) 341e455b69dSRui Feng return err; 342e455b69dSRui Feng 343e455b69dSRui Feng err = rtsx_pci_write_phy_register(pcr, PHY_RCR2, 344e455b69dSRui Feng PHY_RCR2_EMPHASE_EN | PHY_RCR2_NADJR | 345e455b69dSRui Feng PHY_RCR2_CDR_SR_2 | PHY_RCR2_FREQSEL_12 | 346e455b69dSRui Feng PHY_RCR2_CDR_SC_12P | PHY_RCR2_CALIB_LATE); 347e455b69dSRui Feng if (err < 0) 348e455b69dSRui Feng return err; 349e455b69dSRui Feng 350e455b69dSRui Feng err = rtsx_pci_write_phy_register(pcr, PHY_FLD4, 351e455b69dSRui Feng PHY_FLD4_FLDEN_SEL | PHY_FLD4_REQ_REF | 352e455b69dSRui Feng PHY_FLD4_RXAMP_OFF | PHY_FLD4_REQ_ADDA | 353e455b69dSRui Feng PHY_FLD4_BER_COUNT | PHY_FLD4_BER_TIMER | 354e455b69dSRui Feng PHY_FLD4_BER_CHK_EN); 355e455b69dSRui Feng if (err < 0) 356e455b69dSRui Feng return err; 357e455b69dSRui Feng err = rtsx_pci_write_phy_register(pcr, PHY_RDR, 358e455b69dSRui Feng PHY_RDR_RXDSEL_1_9 | PHY_SSC_AUTO_PWD); 359e455b69dSRui Feng if (err < 0) 360e455b69dSRui Feng return err; 361e455b69dSRui Feng err = rtsx_pci_write_phy_register(pcr, PHY_RCR1, 362e455b69dSRui Feng PHY_RCR1_ADP_TIME_4 | PHY_RCR1_VCO_COARSE); 363e455b69dSRui Feng if (err < 0) 364e455b69dSRui Feng return err; 365e455b69dSRui Feng err = rtsx_pci_write_phy_register(pcr, PHY_FLD3, 366e455b69dSRui Feng PHY_FLD3_TIMER_4 | PHY_FLD3_TIMER_6 | 367e455b69dSRui Feng PHY_FLD3_RXDELINK); 368e455b69dSRui Feng if (err < 0) 369e455b69dSRui Feng return err; 370e455b69dSRui Feng 371e455b69dSRui Feng return rtsx_pci_write_phy_register(pcr, PHY_TUNE, 372e455b69dSRui Feng PHY_TUNE_TUNEREF_1_0 | PHY_TUNE_VBGSEL_1252 | 373e455b69dSRui Feng PHY_TUNE_SDBUS_33 | PHY_TUNE_TUNED18 | 374e455b69dSRui Feng PHY_TUNE_TUNED12 | PHY_TUNE_TUNEA12); 375e455b69dSRui Feng } 376e455b69dSRui Feng 377e455b69dSRui Feng static int rtsx_base_turn_on_led(struct rtsx_pcr *pcr) 378e455b69dSRui Feng { 379e455b69dSRui Feng return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02); 380e455b69dSRui Feng } 381e455b69dSRui Feng 382e455b69dSRui Feng static int rtsx_base_turn_off_led(struct rtsx_pcr *pcr) 383e455b69dSRui Feng { 384e455b69dSRui Feng return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00); 385e455b69dSRui Feng } 386e455b69dSRui Feng 387e455b69dSRui Feng static int rtsx_base_enable_auto_blink(struct rtsx_pcr *pcr) 388e455b69dSRui Feng { 389e455b69dSRui Feng return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08); 390e455b69dSRui Feng } 391e455b69dSRui Feng 392e455b69dSRui Feng static int rtsx_base_disable_auto_blink(struct rtsx_pcr *pcr) 393e455b69dSRui Feng { 394e455b69dSRui Feng return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00); 395e455b69dSRui Feng } 396e455b69dSRui Feng 397e455b69dSRui Feng static int rtsx_base_card_power_on(struct rtsx_pcr *pcr, int card) 398e455b69dSRui Feng { 399e455b69dSRui Feng int err; 400bede03a5SRickyWu struct rtsx_cr_option *option = &pcr->option; 401bede03a5SRickyWu 402bede03a5SRickyWu if (option->ocp_en) 403bede03a5SRickyWu rtsx_pci_enable_ocp(pcr); 404e455b69dSRui Feng 405e455b69dSRui Feng rtsx_pci_init_cmd(pcr); 406e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, 407e455b69dSRui Feng SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON); 408e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, 409e455b69dSRui Feng LDO3318_PWR_MASK, 0x02); 410e455b69dSRui Feng err = rtsx_pci_send_cmd(pcr, 100); 411e455b69dSRui Feng if (err < 0) 412e455b69dSRui Feng return err; 413e455b69dSRui Feng 414e455b69dSRui Feng msleep(5); 415e455b69dSRui Feng 416e455b69dSRui Feng rtsx_pci_init_cmd(pcr); 417e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, 418e455b69dSRui Feng SD_POWER_MASK, SD_VCC_POWER_ON); 419e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, 420e455b69dSRui Feng LDO3318_PWR_MASK, 0x06); 421e455b69dSRui Feng return rtsx_pci_send_cmd(pcr, 100); 422e455b69dSRui Feng } 423e455b69dSRui Feng 424e455b69dSRui Feng static int rtsx_base_card_power_off(struct rtsx_pcr *pcr, int card) 425e455b69dSRui Feng { 426bede03a5SRickyWu struct rtsx_cr_option *option = &pcr->option; 427bede03a5SRickyWu 428bede03a5SRickyWu if (option->ocp_en) 429bede03a5SRickyWu rtsx_pci_disable_ocp(pcr); 430bede03a5SRickyWu 431bede03a5SRickyWu rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK, SD_POWER_OFF); 432bede03a5SRickyWu 433bede03a5SRickyWu rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0x00); 434bede03a5SRickyWu return 0; 435e455b69dSRui Feng } 436e455b69dSRui Feng 437e455b69dSRui Feng static int rtsx_base_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) 438e455b69dSRui Feng { 439e455b69dSRui Feng int err; 440e455b69dSRui Feng u16 append; 441e455b69dSRui Feng 442e455b69dSRui Feng switch (voltage) { 443e455b69dSRui Feng case OUTPUT_3V3: 444e455b69dSRui Feng err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK, 445e455b69dSRui Feng PHY_TUNE_VOLTAGE_3V3); 446e455b69dSRui Feng if (err < 0) 447e455b69dSRui Feng return err; 448e455b69dSRui Feng break; 449e455b69dSRui Feng case OUTPUT_1V8: 450e455b69dSRui Feng append = PHY_TUNE_D18_1V8; 451e455b69dSRui Feng if (CHK_PCI_PID(pcr, 0x5249)) { 452e455b69dSRui Feng err = rtsx_pci_update_phy(pcr, PHY_BACR, 453e455b69dSRui Feng PHY_BACR_BASIC_MASK, 0); 454e455b69dSRui Feng if (err < 0) 455e455b69dSRui Feng return err; 456e455b69dSRui Feng append = PHY_TUNE_D18_1V7; 457e455b69dSRui Feng } 458e455b69dSRui Feng 459e455b69dSRui Feng err = rtsx_pci_update_phy(pcr, PHY_TUNE, PHY_TUNE_VOLTAGE_MASK, 460e455b69dSRui Feng append); 461e455b69dSRui Feng if (err < 0) 462e455b69dSRui Feng return err; 463e455b69dSRui Feng break; 464e455b69dSRui Feng default: 465e455b69dSRui Feng pcr_dbg(pcr, "unknown output voltage %d\n", voltage); 466e455b69dSRui Feng return -EINVAL; 467e455b69dSRui Feng } 468e455b69dSRui Feng 469e455b69dSRui Feng /* set pad drive */ 470e455b69dSRui Feng rtsx_pci_init_cmd(pcr); 471e455b69dSRui Feng rts5249_fill_driving(pcr, voltage); 472e455b69dSRui Feng return rtsx_pci_send_cmd(pcr, 100); 473e455b69dSRui Feng } 474e455b69dSRui Feng 475e455b69dSRui Feng static const struct pcr_ops rts5249_pcr_ops = { 476e455b69dSRui Feng .fetch_vendor_settings = rtsx_base_fetch_vendor_settings, 477e455b69dSRui Feng .extra_init_hw = rts5249_extra_init_hw, 478e455b69dSRui Feng .optimize_phy = rts5249_optimize_phy, 479e455b69dSRui Feng .turn_on_led = rtsx_base_turn_on_led, 480e455b69dSRui Feng .turn_off_led = rtsx_base_turn_off_led, 481e455b69dSRui Feng .enable_auto_blink = rtsx_base_enable_auto_blink, 482e455b69dSRui Feng .disable_auto_blink = rtsx_base_disable_auto_blink, 483e455b69dSRui Feng .card_power_on = rtsx_base_card_power_on, 484e455b69dSRui Feng .card_power_off = rtsx_base_card_power_off, 485e455b69dSRui Feng .switch_output_voltage = rtsx_base_switch_output_voltage, 486e455b69dSRui Feng }; 487e455b69dSRui Feng 488e455b69dSRui Feng /* SD Pull Control Enable: 489e455b69dSRui Feng * SD_DAT[3:0] ==> pull up 490e455b69dSRui Feng * SD_CD ==> pull up 491e455b69dSRui Feng * SD_WP ==> pull up 492e455b69dSRui Feng * SD_CMD ==> pull up 493e455b69dSRui Feng * SD_CLK ==> pull down 494e455b69dSRui Feng */ 495e455b69dSRui Feng static const u32 rts5249_sd_pull_ctl_enable_tbl[] = { 496e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66), 497e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA), 498e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9), 499e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA), 500e455b69dSRui Feng 0, 501e455b69dSRui Feng }; 502e455b69dSRui Feng 503e455b69dSRui Feng /* SD Pull Control Disable: 504e455b69dSRui Feng * SD_DAT[3:0] ==> pull down 505e455b69dSRui Feng * SD_CD ==> pull up 506e455b69dSRui Feng * SD_WP ==> pull down 507e455b69dSRui Feng * SD_CMD ==> pull down 508e455b69dSRui Feng * SD_CLK ==> pull down 509e455b69dSRui Feng */ 510e455b69dSRui Feng static const u32 rts5249_sd_pull_ctl_disable_tbl[] = { 511e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66), 512e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 513e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5), 514e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55), 515e455b69dSRui Feng 0, 516e455b69dSRui Feng }; 517e455b69dSRui Feng 518e455b69dSRui Feng /* MS Pull Control Enable: 519e455b69dSRui Feng * MS CD ==> pull up 520e455b69dSRui Feng * others ==> pull down 521e455b69dSRui Feng */ 522e455b69dSRui Feng static const u32 rts5249_ms_pull_ctl_enable_tbl[] = { 523e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55), 524e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55), 525e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15), 526e455b69dSRui Feng 0, 527e455b69dSRui Feng }; 528e455b69dSRui Feng 529e455b69dSRui Feng /* MS Pull Control Disable: 530e455b69dSRui Feng * MS CD ==> pull up 531e455b69dSRui Feng * others ==> pull down 532e455b69dSRui Feng */ 533e455b69dSRui Feng static const u32 rts5249_ms_pull_ctl_disable_tbl[] = { 534e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55), 535e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55), 536e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15), 537e455b69dSRui Feng 0, 538e455b69dSRui Feng }; 539e455b69dSRui Feng 540e455b69dSRui Feng void rts5249_init_params(struct rtsx_pcr *pcr) 541e455b69dSRui Feng { 542e455b69dSRui Feng struct rtsx_cr_option *option = &(pcr->option); 543e455b69dSRui Feng 544e455b69dSRui Feng pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; 545e455b69dSRui Feng pcr->num_slots = 2; 546e455b69dSRui Feng pcr->ops = &rts5249_pcr_ops; 547e455b69dSRui Feng 548e455b69dSRui Feng pcr->flags = 0; 549e455b69dSRui Feng pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; 550e455b69dSRui Feng pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; 551e455b69dSRui Feng pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; 552e455b69dSRui Feng pcr->aspm_en = ASPM_L1_EN; 553e455b69dSRui Feng pcr->tx_initial_phase = SET_CLOCK_PHASE(1, 29, 16); 554e455b69dSRui Feng pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); 555e455b69dSRui Feng 556e455b69dSRui Feng pcr->ic_version = rts5249_get_ic_version(pcr); 557e455b69dSRui Feng pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl; 558e455b69dSRui Feng pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl; 559e455b69dSRui Feng pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl; 560e455b69dSRui Feng pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl; 561e455b69dSRui Feng 562e455b69dSRui Feng pcr->reg_pm_ctrl3 = PM_CTRL3; 563e455b69dSRui Feng 564e455b69dSRui Feng option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN 565e455b69dSRui Feng | LTR_L1SS_PWR_GATE_EN); 566e455b69dSRui Feng option->ltr_en = true; 567e455b69dSRui Feng 568e455b69dSRui Feng /* Init latency of active, idle, L1OFF to 60us, 300us, 3ms */ 569e455b69dSRui Feng option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF; 570e455b69dSRui Feng option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF; 571e455b69dSRui Feng option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF; 572e455b69dSRui Feng option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF; 573e455b69dSRui Feng option->ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5249_DEF; 574e455b69dSRui Feng option->ltr_l1off_snooze_sspwrgate = 575e455b69dSRui Feng LTR_L1OFF_SNOOZE_SSPWRGATE_5249_DEF; 576e455b69dSRui Feng } 577e455b69dSRui Feng 578e455b69dSRui Feng static int rts524a_write_phy(struct rtsx_pcr *pcr, u8 addr, u16 val) 579e455b69dSRui Feng { 580e455b69dSRui Feng addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr; 581e455b69dSRui Feng 582e455b69dSRui Feng return __rtsx_pci_write_phy_register(pcr, addr, val); 583e455b69dSRui Feng } 584e455b69dSRui Feng 585e455b69dSRui Feng static int rts524a_read_phy(struct rtsx_pcr *pcr, u8 addr, u16 *val) 586e455b69dSRui Feng { 587e455b69dSRui Feng addr = addr & 0x80 ? (addr & 0x7F) | 0x40 : addr; 588e455b69dSRui Feng 589e455b69dSRui Feng return __rtsx_pci_read_phy_register(pcr, addr, val); 590e455b69dSRui Feng } 591e455b69dSRui Feng 592e455b69dSRui Feng static int rts524a_optimize_phy(struct rtsx_pcr *pcr) 593e455b69dSRui Feng { 594e455b69dSRui Feng int err; 595e455b69dSRui Feng 596e455b69dSRui Feng err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 597e455b69dSRui Feng D3_DELINK_MODE_EN, 0x00); 598e455b69dSRui Feng if (err < 0) 599e455b69dSRui Feng return err; 600e455b69dSRui Feng 601e455b69dSRui Feng rtsx_pci_write_phy_register(pcr, PHY_PCR, 602e455b69dSRui Feng PHY_PCR_FORCE_CODE | PHY_PCR_OOBS_CALI_50 | 603e455b69dSRui Feng PHY_PCR_OOBS_VCM_08 | PHY_PCR_OOBS_SEN_90 | PHY_PCR_RSSI_EN); 604e455b69dSRui Feng rtsx_pci_write_phy_register(pcr, PHY_SSCCR3, 605e455b69dSRui Feng PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY); 606e455b69dSRui Feng 607e455b69dSRui Feng if (is_version(pcr, 0x524A, IC_VER_A)) { 608e455b69dSRui Feng rtsx_pci_write_phy_register(pcr, PHY_SSCCR3, 609e455b69dSRui Feng PHY_SSCCR3_STEP_IN | PHY_SSCCR3_CHECK_DELAY); 610e455b69dSRui Feng rtsx_pci_write_phy_register(pcr, PHY_SSCCR2, 611e455b69dSRui Feng PHY_SSCCR2_PLL_NCODE | PHY_SSCCR2_TIME0 | 612e455b69dSRui Feng PHY_SSCCR2_TIME2_WIDTH); 613e455b69dSRui Feng rtsx_pci_write_phy_register(pcr, PHY_ANA1A, 614e455b69dSRui Feng PHY_ANA1A_TXR_LOOPBACK | PHY_ANA1A_RXT_BIST | 615e455b69dSRui Feng PHY_ANA1A_TXR_BIST | PHY_ANA1A_REV); 616e455b69dSRui Feng rtsx_pci_write_phy_register(pcr, PHY_ANA1D, 617e455b69dSRui Feng PHY_ANA1D_DEBUG_ADDR); 618e455b69dSRui Feng rtsx_pci_write_phy_register(pcr, PHY_DIG1E, 619e455b69dSRui Feng PHY_DIG1E_REV | PHY_DIG1E_D0_X_D1 | 620e455b69dSRui Feng PHY_DIG1E_RX_ON_HOST | PHY_DIG1E_RCLK_REF_HOST | 621e455b69dSRui Feng PHY_DIG1E_RCLK_TX_EN_KEEP | 622e455b69dSRui Feng PHY_DIG1E_RCLK_TX_TERM_KEEP | 623e455b69dSRui Feng PHY_DIG1E_RCLK_RX_EIDLE_ON | PHY_DIG1E_TX_TERM_KEEP | 624e455b69dSRui Feng PHY_DIG1E_RX_TERM_KEEP | PHY_DIG1E_TX_EN_KEEP | 625e455b69dSRui Feng PHY_DIG1E_RX_EN_KEEP); 626e455b69dSRui Feng } 627e455b69dSRui Feng 628e455b69dSRui Feng rtsx_pci_write_phy_register(pcr, PHY_ANA08, 629e455b69dSRui Feng PHY_ANA08_RX_EQ_DCGAIN | PHY_ANA08_SEL_RX_EN | 630e455b69dSRui Feng PHY_ANA08_RX_EQ_VAL | PHY_ANA08_SCP | PHY_ANA08_SEL_IPI); 631e455b69dSRui Feng 632e455b69dSRui Feng return 0; 633e455b69dSRui Feng } 634e455b69dSRui Feng 635e455b69dSRui Feng static int rts524a_extra_init_hw(struct rtsx_pcr *pcr) 636e455b69dSRui Feng { 637e455b69dSRui Feng rts5249_extra_init_hw(pcr); 638e455b69dSRui Feng 639e455b69dSRui Feng rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, 640e455b69dSRui Feng FORCE_ASPM_L1_EN, FORCE_ASPM_L1_EN); 641e455b69dSRui Feng rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0); 642e455b69dSRui Feng rtsx_pci_write_register(pcr, LDO_VCC_CFG1, LDO_VCC_LMT_EN, 643e455b69dSRui Feng LDO_VCC_LMT_EN); 644e455b69dSRui Feng rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL); 645e455b69dSRui Feng if (is_version(pcr, 0x524A, IC_VER_A)) { 646e455b69dSRui Feng rtsx_pci_write_register(pcr, LDO_DV18_CFG, 647e455b69dSRui Feng LDO_DV18_SR_MASK, LDO_DV18_SR_DF); 648e455b69dSRui Feng rtsx_pci_write_register(pcr, LDO_VCC_CFG1, 649e455b69dSRui Feng LDO_VCC_REF_TUNE_MASK, LDO_VCC_REF_1V2); 650e455b69dSRui Feng rtsx_pci_write_register(pcr, LDO_VIO_CFG, 651e455b69dSRui Feng LDO_VIO_REF_TUNE_MASK, LDO_VIO_REF_1V2); 652e455b69dSRui Feng rtsx_pci_write_register(pcr, LDO_VIO_CFG, 653e455b69dSRui Feng LDO_VIO_SR_MASK, LDO_VIO_SR_DF); 654e455b69dSRui Feng rtsx_pci_write_register(pcr, LDO_DV12S_CFG, 655e455b69dSRui Feng LDO_REF12_TUNE_MASK, LDO_REF12_TUNE_DF); 656e455b69dSRui Feng rtsx_pci_write_register(pcr, SD40_LDO_CTL1, 657e455b69dSRui Feng SD40_VIO_TUNE_MASK, SD40_VIO_TUNE_1V7); 658e455b69dSRui Feng } 659e455b69dSRui Feng 660e455b69dSRui Feng return 0; 661e455b69dSRui Feng } 662e455b69dSRui Feng 663e455b69dSRui Feng static void rts5250_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active) 664e455b69dSRui Feng { 665e455b69dSRui Feng struct rtsx_cr_option *option = &(pcr->option); 666e455b69dSRui Feng 667e455b69dSRui Feng u32 interrupt = rtsx_pci_readl(pcr, RTSX_BIPR); 668e455b69dSRui Feng int card_exist = (interrupt & SD_EXIST) | (interrupt & MS_EXIST); 669e455b69dSRui Feng int aspm_L1_1, aspm_L1_2; 670e455b69dSRui Feng u8 val = 0; 671e455b69dSRui Feng 672e455b69dSRui Feng aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN); 673e455b69dSRui Feng aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN); 674e455b69dSRui Feng 675e455b69dSRui Feng if (active) { 676e455b69dSRui Feng /* Run, latency: 60us */ 677e455b69dSRui Feng if (aspm_L1_1) 678e455b69dSRui Feng val = option->ltr_l1off_snooze_sspwrgate; 679e455b69dSRui Feng } else { 680e455b69dSRui Feng /* L1off, latency: 300us */ 681e455b69dSRui Feng if (aspm_L1_2) 682e455b69dSRui Feng val = option->ltr_l1off_sspwrgate; 683e455b69dSRui Feng } 684e455b69dSRui Feng 685e455b69dSRui Feng if (aspm_L1_1 || aspm_L1_2) { 686e455b69dSRui Feng if (rtsx_check_dev_flag(pcr, 687e455b69dSRui Feng LTR_L1SS_PWR_GATE_CHECK_CARD_EN)) { 688e455b69dSRui Feng if (card_exist) 689e455b69dSRui Feng val &= ~L1OFF_MBIAS2_EN_5250; 690e455b69dSRui Feng else 691e455b69dSRui Feng val |= L1OFF_MBIAS2_EN_5250; 692e455b69dSRui Feng } 693e455b69dSRui Feng } 694e455b69dSRui Feng rtsx_set_l1off_sub(pcr, val); 695e455b69dSRui Feng } 696e455b69dSRui Feng 697e455b69dSRui Feng static const struct pcr_ops rts524a_pcr_ops = { 698e455b69dSRui Feng .write_phy = rts524a_write_phy, 699e455b69dSRui Feng .read_phy = rts524a_read_phy, 700e455b69dSRui Feng .fetch_vendor_settings = rtsx_base_fetch_vendor_settings, 701e455b69dSRui Feng .extra_init_hw = rts524a_extra_init_hw, 702e455b69dSRui Feng .optimize_phy = rts524a_optimize_phy, 703e455b69dSRui Feng .turn_on_led = rtsx_base_turn_on_led, 704e455b69dSRui Feng .turn_off_led = rtsx_base_turn_off_led, 705e455b69dSRui Feng .enable_auto_blink = rtsx_base_enable_auto_blink, 706e455b69dSRui Feng .disable_auto_blink = rtsx_base_disable_auto_blink, 707e455b69dSRui Feng .card_power_on = rtsx_base_card_power_on, 708e455b69dSRui Feng .card_power_off = rtsx_base_card_power_off, 709e455b69dSRui Feng .switch_output_voltage = rtsx_base_switch_output_voltage, 710e455b69dSRui Feng .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0, 711e455b69dSRui Feng }; 712e455b69dSRui Feng 713e455b69dSRui Feng void rts524a_init_params(struct rtsx_pcr *pcr) 714e455b69dSRui Feng { 715e455b69dSRui Feng rts5249_init_params(pcr); 7164686392cSRicky Wu pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 29, 11); 717e455b69dSRui Feng pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; 718e455b69dSRui Feng pcr->option.ltr_l1off_snooze_sspwrgate = 719e455b69dSRui Feng LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF; 720e455b69dSRui Feng 721e455b69dSRui Feng pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3; 722e455b69dSRui Feng pcr->ops = &rts524a_pcr_ops; 723bede03a5SRickyWu 724bede03a5SRickyWu pcr->option.ocp_en = 1; 725bede03a5SRickyWu if (pcr->option.ocp_en) 726bede03a5SRickyWu pcr->hw_param.interrupt_en |= SD_OC_INT_EN; 727bede03a5SRickyWu pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M; 728bede03a5SRickyWu pcr->option.sd_800mA_ocp_thd = RTS524A_OCP_THD_800; 729bede03a5SRickyWu 730e455b69dSRui Feng } 731e455b69dSRui Feng 732e455b69dSRui Feng static int rts525a_card_power_on(struct rtsx_pcr *pcr, int card) 733e455b69dSRui Feng { 734e455b69dSRui Feng rtsx_pci_write_register(pcr, LDO_VCC_CFG1, 735e455b69dSRui Feng LDO_VCC_TUNE_MASK, LDO_VCC_3V3); 736e455b69dSRui Feng return rtsx_base_card_power_on(pcr, card); 737e455b69dSRui Feng } 738e455b69dSRui Feng 739e455b69dSRui Feng static int rts525a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) 740e455b69dSRui Feng { 741e455b69dSRui Feng switch (voltage) { 742e455b69dSRui Feng case OUTPUT_3V3: 743e455b69dSRui Feng rtsx_pci_write_register(pcr, LDO_CONFIG2, 744e455b69dSRui Feng LDO_D3318_MASK, LDO_D3318_33V); 745e455b69dSRui Feng rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 0); 746e455b69dSRui Feng break; 747e455b69dSRui Feng case OUTPUT_1V8: 748e455b69dSRui Feng rtsx_pci_write_register(pcr, LDO_CONFIG2, 749e455b69dSRui Feng LDO_D3318_MASK, LDO_D3318_18V); 750e455b69dSRui Feng rtsx_pci_write_register(pcr, SD_PAD_CTL, SD_IO_USING_1V8, 751e455b69dSRui Feng SD_IO_USING_1V8); 752e455b69dSRui Feng break; 753e455b69dSRui Feng default: 754e455b69dSRui Feng return -EINVAL; 755e455b69dSRui Feng } 756e455b69dSRui Feng 757e455b69dSRui Feng rtsx_pci_init_cmd(pcr); 758e455b69dSRui Feng rts5249_fill_driving(pcr, voltage); 759e455b69dSRui Feng return rtsx_pci_send_cmd(pcr, 100); 760e455b69dSRui Feng } 761e455b69dSRui Feng 762e455b69dSRui Feng static int rts525a_optimize_phy(struct rtsx_pcr *pcr) 763e455b69dSRui Feng { 764e455b69dSRui Feng int err; 765e455b69dSRui Feng 766e455b69dSRui Feng err = rtsx_pci_write_register(pcr, RTS524A_PM_CTRL3, 767e455b69dSRui Feng D3_DELINK_MODE_EN, 0x00); 768e455b69dSRui Feng if (err < 0) 769e455b69dSRui Feng return err; 770e455b69dSRui Feng 771e455b69dSRui Feng rtsx_pci_write_phy_register(pcr, _PHY_FLD0, 772e455b69dSRui Feng _PHY_FLD0_CLK_REQ_20C | _PHY_FLD0_RX_IDLE_EN | 773e455b69dSRui Feng _PHY_FLD0_BIT_ERR_RSTN | _PHY_FLD0_BER_COUNT | 774e455b69dSRui Feng _PHY_FLD0_BER_TIMER | _PHY_FLD0_CHECK_EN); 775e455b69dSRui Feng 776e455b69dSRui Feng rtsx_pci_write_phy_register(pcr, _PHY_ANA03, 777e455b69dSRui Feng _PHY_ANA03_TIMER_MAX | _PHY_ANA03_OOBS_DEB_EN | 778e455b69dSRui Feng _PHY_CMU_DEBUG_EN); 779e455b69dSRui Feng 780e455b69dSRui Feng if (is_version(pcr, 0x525A, IC_VER_A)) 781e455b69dSRui Feng rtsx_pci_write_phy_register(pcr, _PHY_REV0, 782e455b69dSRui Feng _PHY_REV0_FILTER_OUT | _PHY_REV0_CDR_BYPASS_PFD | 783e455b69dSRui Feng _PHY_REV0_CDR_RX_IDLE_BYPASS); 784e455b69dSRui Feng 785e455b69dSRui Feng return 0; 786e455b69dSRui Feng } 787e455b69dSRui Feng 788e455b69dSRui Feng static int rts525a_extra_init_hw(struct rtsx_pcr *pcr) 789e455b69dSRui Feng { 790e455b69dSRui Feng rts5249_extra_init_hw(pcr); 791e455b69dSRui Feng 792*7c33e3c4SRicky Wu rtsx_pci_write_register(pcr, RTS5250_CLK_CFG3, RTS525A_CFG_MEM_PD, RTS525A_CFG_MEM_PD); 793*7c33e3c4SRicky Wu 794e455b69dSRui Feng rtsx_pci_write_register(pcr, PCLK_CTL, PCLK_MODE_SEL, PCLK_MODE_SEL); 795e455b69dSRui Feng if (is_version(pcr, 0x525A, IC_VER_A)) { 796e455b69dSRui Feng rtsx_pci_write_register(pcr, L1SUB_CONFIG2, 797e455b69dSRui Feng L1SUB_AUTO_CFG, L1SUB_AUTO_CFG); 798e455b69dSRui Feng rtsx_pci_write_register(pcr, RREF_CFG, 799e455b69dSRui Feng RREF_VBGSEL_MASK, RREF_VBGSEL_1V25); 800e455b69dSRui Feng rtsx_pci_write_register(pcr, LDO_VIO_CFG, 801e455b69dSRui Feng LDO_VIO_TUNE_MASK, LDO_VIO_1V7); 802e455b69dSRui Feng rtsx_pci_write_register(pcr, LDO_DV12S_CFG, 803e455b69dSRui Feng LDO_D12_TUNE_MASK, LDO_D12_TUNE_DF); 804e455b69dSRui Feng rtsx_pci_write_register(pcr, LDO_AV12S_CFG, 805e455b69dSRui Feng LDO_AV12S_TUNE_MASK, LDO_AV12S_TUNE_DF); 806e455b69dSRui Feng rtsx_pci_write_register(pcr, LDO_VCC_CFG0, 807e455b69dSRui Feng LDO_VCC_LMTVTH_MASK, LDO_VCC_LMTVTH_2A); 808e455b69dSRui Feng rtsx_pci_write_register(pcr, OOBS_CONFIG, 809e455b69dSRui Feng OOBS_AUTOK_DIS | OOBS_VAL_MASK, 0x89); 810e455b69dSRui Feng } 811e455b69dSRui Feng 812e455b69dSRui Feng return 0; 813e455b69dSRui Feng } 814e455b69dSRui Feng 815e455b69dSRui Feng static const struct pcr_ops rts525a_pcr_ops = { 816e455b69dSRui Feng .fetch_vendor_settings = rtsx_base_fetch_vendor_settings, 817e455b69dSRui Feng .extra_init_hw = rts525a_extra_init_hw, 818e455b69dSRui Feng .optimize_phy = rts525a_optimize_phy, 819e455b69dSRui Feng .turn_on_led = rtsx_base_turn_on_led, 820e455b69dSRui Feng .turn_off_led = rtsx_base_turn_off_led, 821e455b69dSRui Feng .enable_auto_blink = rtsx_base_enable_auto_blink, 822e455b69dSRui Feng .disable_auto_blink = rtsx_base_disable_auto_blink, 823e455b69dSRui Feng .card_power_on = rts525a_card_power_on, 824e455b69dSRui Feng .card_power_off = rtsx_base_card_power_off, 825e455b69dSRui Feng .switch_output_voltage = rts525a_switch_output_voltage, 826e455b69dSRui Feng .set_l1off_cfg_sub_d0 = rts5250_set_l1off_cfg_sub_d0, 827e455b69dSRui Feng }; 828e455b69dSRui Feng 829e455b69dSRui Feng void rts525a_init_params(struct rtsx_pcr *pcr) 830e455b69dSRui Feng { 831e455b69dSRui Feng rts5249_init_params(pcr); 8324686392cSRicky Wu pcr->tx_initial_phase = SET_CLOCK_PHASE(25, 29, 11); 833e455b69dSRui Feng pcr->option.ltr_l1off_sspwrgate = LTR_L1OFF_SSPWRGATE_5250_DEF; 834e455b69dSRui Feng pcr->option.ltr_l1off_snooze_sspwrgate = 835e455b69dSRui Feng LTR_L1OFF_SNOOZE_SSPWRGATE_5250_DEF; 836e455b69dSRui Feng 837e455b69dSRui Feng pcr->reg_pm_ctrl3 = RTS524A_PM_CTRL3; 838e455b69dSRui Feng pcr->ops = &rts525a_pcr_ops; 839bede03a5SRickyWu 840bede03a5SRickyWu pcr->option.ocp_en = 1; 841bede03a5SRickyWu if (pcr->option.ocp_en) 842bede03a5SRickyWu pcr->hw_param.interrupt_en |= SD_OC_INT_EN; 843bede03a5SRickyWu pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M; 844bede03a5SRickyWu pcr->option.sd_800mA_ocp_thd = RTS525A_OCP_THD_800; 845e455b69dSRui Feng } 846