1*e455b69dSRui Feng /* Driver for Realtek PCI-Express card reader 2*e455b69dSRui Feng * 3*e455b69dSRui Feng * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 4*e455b69dSRui Feng * 5*e455b69dSRui Feng * This program is free software; you can redistribute it and/or modify it 6*e455b69dSRui Feng * under the terms of the GNU General Public License as published by the 7*e455b69dSRui Feng * Free Software Foundation; either version 2, or (at your option) any 8*e455b69dSRui Feng * later version. 9*e455b69dSRui Feng * 10*e455b69dSRui Feng * This program is distributed in the hope that it will be useful, but 11*e455b69dSRui Feng * WITHOUT ANY WARRANTY; without even the implied warranty of 12*e455b69dSRui Feng * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13*e455b69dSRui Feng * General Public License for more details. 14*e455b69dSRui Feng * 15*e455b69dSRui Feng * You should have received a copy of the GNU General Public License along 16*e455b69dSRui Feng * with this program; if not, see <http://www.gnu.org/licenses/>. 17*e455b69dSRui Feng * 18*e455b69dSRui Feng * Author: 19*e455b69dSRui Feng * Wei WANG <wei_wang@realsil.com.cn> 20*e455b69dSRui Feng */ 21*e455b69dSRui Feng 22*e455b69dSRui Feng #include <linux/module.h> 23*e455b69dSRui Feng #include <linux/delay.h> 24*e455b69dSRui Feng #include <linux/rtsx_pci.h> 25*e455b69dSRui Feng 26*e455b69dSRui Feng #include "rtsx_pcr.h" 27*e455b69dSRui Feng 28*e455b69dSRui Feng static u8 rts5229_get_ic_version(struct rtsx_pcr *pcr) 29*e455b69dSRui Feng { 30*e455b69dSRui Feng u8 val; 31*e455b69dSRui Feng 32*e455b69dSRui Feng rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val); 33*e455b69dSRui Feng return val & 0x0F; 34*e455b69dSRui Feng } 35*e455b69dSRui Feng 36*e455b69dSRui Feng static void rts5229_fetch_vendor_settings(struct rtsx_pcr *pcr) 37*e455b69dSRui Feng { 38*e455b69dSRui Feng u32 reg; 39*e455b69dSRui Feng 40*e455b69dSRui Feng rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®); 41*e455b69dSRui Feng pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); 42*e455b69dSRui Feng 43*e455b69dSRui Feng if (!rtsx_vendor_setting_valid(reg)) 44*e455b69dSRui Feng return; 45*e455b69dSRui Feng 46*e455b69dSRui Feng pcr->aspm_en = rtsx_reg_to_aspm(reg); 47*e455b69dSRui Feng pcr->sd30_drive_sel_1v8 = 48*e455b69dSRui Feng map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg)); 49*e455b69dSRui Feng pcr->card_drive_sel &= 0x3F; 50*e455b69dSRui Feng pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg); 51*e455b69dSRui Feng 52*e455b69dSRui Feng rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG2, ®); 53*e455b69dSRui Feng pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg); 54*e455b69dSRui Feng pcr->sd30_drive_sel_3v3 = 55*e455b69dSRui Feng map_sd_drive(rtsx_reg_to_sd30_drive_sel_3v3(reg)); 56*e455b69dSRui Feng } 57*e455b69dSRui Feng 58*e455b69dSRui Feng static void rts5229_force_power_down(struct rtsx_pcr *pcr, u8 pm_state) 59*e455b69dSRui Feng { 60*e455b69dSRui Feng rtsx_pci_write_register(pcr, FPDCTL, 0x03, 0x03); 61*e455b69dSRui Feng } 62*e455b69dSRui Feng 63*e455b69dSRui Feng static int rts5229_extra_init_hw(struct rtsx_pcr *pcr) 64*e455b69dSRui Feng { 65*e455b69dSRui Feng rtsx_pci_init_cmd(pcr); 66*e455b69dSRui Feng 67*e455b69dSRui Feng /* Configure GPIO as output */ 68*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02); 69*e455b69dSRui Feng /* Reset ASPM state to default value */ 70*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0); 71*e455b69dSRui Feng /* Force CLKREQ# PIN to drive 0 to request clock */ 72*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x08, 0x08); 73*e455b69dSRui Feng /* Switch LDO3318 source from DV33 to card_3v3 */ 74*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00); 75*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01); 76*e455b69dSRui Feng /* LED shine disabled, set initial shine cycle period */ 77*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02); 78*e455b69dSRui Feng /* Configure driving */ 79*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL, 80*e455b69dSRui Feng 0xFF, pcr->sd30_drive_sel_3v3); 81*e455b69dSRui Feng 82*e455b69dSRui Feng return rtsx_pci_send_cmd(pcr, 100); 83*e455b69dSRui Feng } 84*e455b69dSRui Feng 85*e455b69dSRui Feng static int rts5229_optimize_phy(struct rtsx_pcr *pcr) 86*e455b69dSRui Feng { 87*e455b69dSRui Feng /* Optimize RX sensitivity */ 88*e455b69dSRui Feng return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42); 89*e455b69dSRui Feng } 90*e455b69dSRui Feng 91*e455b69dSRui Feng static int rts5229_turn_on_led(struct rtsx_pcr *pcr) 92*e455b69dSRui Feng { 93*e455b69dSRui Feng return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02); 94*e455b69dSRui Feng } 95*e455b69dSRui Feng 96*e455b69dSRui Feng static int rts5229_turn_off_led(struct rtsx_pcr *pcr) 97*e455b69dSRui Feng { 98*e455b69dSRui Feng return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00); 99*e455b69dSRui Feng } 100*e455b69dSRui Feng 101*e455b69dSRui Feng static int rts5229_enable_auto_blink(struct rtsx_pcr *pcr) 102*e455b69dSRui Feng { 103*e455b69dSRui Feng return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08); 104*e455b69dSRui Feng } 105*e455b69dSRui Feng 106*e455b69dSRui Feng static int rts5229_disable_auto_blink(struct rtsx_pcr *pcr) 107*e455b69dSRui Feng { 108*e455b69dSRui Feng return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00); 109*e455b69dSRui Feng } 110*e455b69dSRui Feng 111*e455b69dSRui Feng static int rts5229_card_power_on(struct rtsx_pcr *pcr, int card) 112*e455b69dSRui Feng { 113*e455b69dSRui Feng int err; 114*e455b69dSRui Feng 115*e455b69dSRui Feng rtsx_pci_init_cmd(pcr); 116*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, 117*e455b69dSRui Feng SD_POWER_MASK, SD_PARTIAL_POWER_ON); 118*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, 119*e455b69dSRui Feng LDO3318_PWR_MASK, 0x02); 120*e455b69dSRui Feng err = rtsx_pci_send_cmd(pcr, 100); 121*e455b69dSRui Feng if (err < 0) 122*e455b69dSRui Feng return err; 123*e455b69dSRui Feng 124*e455b69dSRui Feng /* To avoid too large in-rush current */ 125*e455b69dSRui Feng udelay(150); 126*e455b69dSRui Feng 127*e455b69dSRui Feng rtsx_pci_init_cmd(pcr); 128*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, 129*e455b69dSRui Feng SD_POWER_MASK, SD_POWER_ON); 130*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, 131*e455b69dSRui Feng LDO3318_PWR_MASK, 0x06); 132*e455b69dSRui Feng return rtsx_pci_send_cmd(pcr, 100); 133*e455b69dSRui Feng } 134*e455b69dSRui Feng 135*e455b69dSRui Feng static int rts5229_card_power_off(struct rtsx_pcr *pcr, int card) 136*e455b69dSRui Feng { 137*e455b69dSRui Feng rtsx_pci_init_cmd(pcr); 138*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, 139*e455b69dSRui Feng SD_POWER_MASK | PMOS_STRG_MASK, 140*e455b69dSRui Feng SD_POWER_OFF | PMOS_STRG_400mA); 141*e455b69dSRui Feng rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL, 142*e455b69dSRui Feng LDO3318_PWR_MASK, 0x00); 143*e455b69dSRui Feng return rtsx_pci_send_cmd(pcr, 100); 144*e455b69dSRui Feng } 145*e455b69dSRui Feng 146*e455b69dSRui Feng static int rts5229_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) 147*e455b69dSRui Feng { 148*e455b69dSRui Feng int err; 149*e455b69dSRui Feng 150*e455b69dSRui Feng if (voltage == OUTPUT_3V3) { 151*e455b69dSRui Feng err = rtsx_pci_write_register(pcr, 152*e455b69dSRui Feng SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_3v3); 153*e455b69dSRui Feng if (err < 0) 154*e455b69dSRui Feng return err; 155*e455b69dSRui Feng err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24); 156*e455b69dSRui Feng if (err < 0) 157*e455b69dSRui Feng return err; 158*e455b69dSRui Feng } else if (voltage == OUTPUT_1V8) { 159*e455b69dSRui Feng err = rtsx_pci_write_register(pcr, 160*e455b69dSRui Feng SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_1v8); 161*e455b69dSRui Feng if (err < 0) 162*e455b69dSRui Feng return err; 163*e455b69dSRui Feng err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C40 | 0x24); 164*e455b69dSRui Feng if (err < 0) 165*e455b69dSRui Feng return err; 166*e455b69dSRui Feng } else { 167*e455b69dSRui Feng return -EINVAL; 168*e455b69dSRui Feng } 169*e455b69dSRui Feng 170*e455b69dSRui Feng return 0; 171*e455b69dSRui Feng } 172*e455b69dSRui Feng 173*e455b69dSRui Feng static const struct pcr_ops rts5229_pcr_ops = { 174*e455b69dSRui Feng .fetch_vendor_settings = rts5229_fetch_vendor_settings, 175*e455b69dSRui Feng .extra_init_hw = rts5229_extra_init_hw, 176*e455b69dSRui Feng .optimize_phy = rts5229_optimize_phy, 177*e455b69dSRui Feng .turn_on_led = rts5229_turn_on_led, 178*e455b69dSRui Feng .turn_off_led = rts5229_turn_off_led, 179*e455b69dSRui Feng .enable_auto_blink = rts5229_enable_auto_blink, 180*e455b69dSRui Feng .disable_auto_blink = rts5229_disable_auto_blink, 181*e455b69dSRui Feng .card_power_on = rts5229_card_power_on, 182*e455b69dSRui Feng .card_power_off = rts5229_card_power_off, 183*e455b69dSRui Feng .switch_output_voltage = rts5229_switch_output_voltage, 184*e455b69dSRui Feng .cd_deglitch = NULL, 185*e455b69dSRui Feng .conv_clk_and_div_n = NULL, 186*e455b69dSRui Feng .force_power_down = rts5229_force_power_down, 187*e455b69dSRui Feng }; 188*e455b69dSRui Feng 189*e455b69dSRui Feng /* SD Pull Control Enable: 190*e455b69dSRui Feng * SD_DAT[3:0] ==> pull up 191*e455b69dSRui Feng * SD_CD ==> pull up 192*e455b69dSRui Feng * SD_WP ==> pull up 193*e455b69dSRui Feng * SD_CMD ==> pull up 194*e455b69dSRui Feng * SD_CLK ==> pull down 195*e455b69dSRui Feng */ 196*e455b69dSRui Feng static const u32 rts5229_sd_pull_ctl_enable_tbl1[] = { 197*e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA), 198*e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9), 199*e455b69dSRui Feng 0, 200*e455b69dSRui Feng }; 201*e455b69dSRui Feng 202*e455b69dSRui Feng /* For RTS5229 version C */ 203*e455b69dSRui Feng static const u32 rts5229_sd_pull_ctl_enable_tbl2[] = { 204*e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA), 205*e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD9), 206*e455b69dSRui Feng 0, 207*e455b69dSRui Feng }; 208*e455b69dSRui Feng 209*e455b69dSRui Feng /* SD Pull Control Disable: 210*e455b69dSRui Feng * SD_DAT[3:0] ==> pull down 211*e455b69dSRui Feng * SD_CD ==> pull up 212*e455b69dSRui Feng * SD_WP ==> pull down 213*e455b69dSRui Feng * SD_CMD ==> pull down 214*e455b69dSRui Feng * SD_CLK ==> pull down 215*e455b69dSRui Feng */ 216*e455b69dSRui Feng static const u32 rts5229_sd_pull_ctl_disable_tbl1[] = { 217*e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 218*e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5), 219*e455b69dSRui Feng 0, 220*e455b69dSRui Feng }; 221*e455b69dSRui Feng 222*e455b69dSRui Feng /* For RTS5229 version C */ 223*e455b69dSRui Feng static const u32 rts5229_sd_pull_ctl_disable_tbl2[] = { 224*e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 225*e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE5), 226*e455b69dSRui Feng 0, 227*e455b69dSRui Feng }; 228*e455b69dSRui Feng 229*e455b69dSRui Feng /* MS Pull Control Enable: 230*e455b69dSRui Feng * MS CD ==> pull up 231*e455b69dSRui Feng * others ==> pull down 232*e455b69dSRui Feng */ 233*e455b69dSRui Feng static const u32 rts5229_ms_pull_ctl_enable_tbl[] = { 234*e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55), 235*e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15), 236*e455b69dSRui Feng 0, 237*e455b69dSRui Feng }; 238*e455b69dSRui Feng 239*e455b69dSRui Feng /* MS Pull Control Disable: 240*e455b69dSRui Feng * MS CD ==> pull up 241*e455b69dSRui Feng * others ==> pull down 242*e455b69dSRui Feng */ 243*e455b69dSRui Feng static const u32 rts5229_ms_pull_ctl_disable_tbl[] = { 244*e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55), 245*e455b69dSRui Feng RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15), 246*e455b69dSRui Feng 0, 247*e455b69dSRui Feng }; 248*e455b69dSRui Feng 249*e455b69dSRui Feng void rts5229_init_params(struct rtsx_pcr *pcr) 250*e455b69dSRui Feng { 251*e455b69dSRui Feng pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; 252*e455b69dSRui Feng pcr->num_slots = 2; 253*e455b69dSRui Feng pcr->ops = &rts5229_pcr_ops; 254*e455b69dSRui Feng 255*e455b69dSRui Feng pcr->flags = 0; 256*e455b69dSRui Feng pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; 257*e455b69dSRui Feng pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B; 258*e455b69dSRui Feng pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D; 259*e455b69dSRui Feng pcr->aspm_en = ASPM_L1_EN; 260*e455b69dSRui Feng pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15); 261*e455b69dSRui Feng pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 6, 6); 262*e455b69dSRui Feng 263*e455b69dSRui Feng pcr->ic_version = rts5229_get_ic_version(pcr); 264*e455b69dSRui Feng if (pcr->ic_version == IC_VER_C) { 265*e455b69dSRui Feng pcr->sd_pull_ctl_enable_tbl = rts5229_sd_pull_ctl_enable_tbl2; 266*e455b69dSRui Feng pcr->sd_pull_ctl_disable_tbl = rts5229_sd_pull_ctl_disable_tbl2; 267*e455b69dSRui Feng } else { 268*e455b69dSRui Feng pcr->sd_pull_ctl_enable_tbl = rts5229_sd_pull_ctl_enable_tbl1; 269*e455b69dSRui Feng pcr->sd_pull_ctl_disable_tbl = rts5229_sd_pull_ctl_disable_tbl1; 270*e455b69dSRui Feng } 271*e455b69dSRui Feng pcr->ms_pull_ctl_enable_tbl = rts5229_ms_pull_ctl_enable_tbl; 272*e455b69dSRui Feng pcr->ms_pull_ctl_disable_tbl = rts5229_ms_pull_ctl_disable_tbl; 273*e455b69dSRui Feng } 274