1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Driver for Realtek PCI-Express card reader 3 * 4 * Copyright(c) 2018-2019 Realtek Semiconductor Corp. All rights reserved. 5 * 6 * Author: 7 * Ricky WU <ricky_wu@realtek.com> 8 * Rui FENG <rui_feng@realsil.com.cn> 9 * Wei WANG <wei_wang@realsil.com.cn> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/delay.h> 14 #include <linux/rtsx_pci.h> 15 16 #include "rts5228.h" 17 #include "rtsx_pcr.h" 18 19 static u8 rts5228_get_ic_version(struct rtsx_pcr *pcr) 20 { 21 u8 val; 22 23 rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val); 24 return val & IC_VERSION_MASK; 25 } 26 27 static void rts5228_fill_driving(struct rtsx_pcr *pcr, u8 voltage) 28 { 29 u8 driving_3v3[4][3] = { 30 {0x13, 0x13, 0x13}, 31 {0x96, 0x96, 0x96}, 32 {0x7F, 0x7F, 0x7F}, 33 {0x96, 0x96, 0x96}, 34 }; 35 u8 driving_1v8[4][3] = { 36 {0x99, 0x99, 0x99}, 37 {0xB5, 0xB5, 0xB5}, 38 {0xE6, 0x7E, 0xFE}, 39 {0x6B, 0x6B, 0x6B}, 40 }; 41 u8 (*driving)[3], drive_sel; 42 43 if (voltage == OUTPUT_3V3) { 44 driving = driving_3v3; 45 drive_sel = pcr->sd30_drive_sel_3v3; 46 } else { 47 driving = driving_1v8; 48 drive_sel = pcr->sd30_drive_sel_1v8; 49 } 50 51 rtsx_pci_write_register(pcr, SD30_CLK_DRIVE_SEL, 52 0xFF, driving[drive_sel][0]); 53 54 rtsx_pci_write_register(pcr, SD30_CMD_DRIVE_SEL, 55 0xFF, driving[drive_sel][1]); 56 57 rtsx_pci_write_register(pcr, SD30_DAT_DRIVE_SEL, 58 0xFF, driving[drive_sel][2]); 59 } 60 61 static void rtsx5228_fetch_vendor_settings(struct rtsx_pcr *pcr) 62 { 63 struct pci_dev *pdev = pcr->pci; 64 u32 reg; 65 66 /* 0x724~0x727 */ 67 pci_read_config_dword(pdev, PCR_SETTING_REG1, ®); 68 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg); 69 70 if (!rtsx_vendor_setting_valid(reg)) { 71 pcr_dbg(pcr, "skip fetch vendor setting\n"); 72 return; 73 } 74 pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg); 75 pcr->aspm_en = rtsx_reg_to_aspm(reg); 76 77 /* 0x814~0x817 */ 78 pci_read_config_dword(pdev, PCR_SETTING_REG2, ®); 79 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg); 80 81 pcr->rtd3_en = rtsx_reg_to_rtd3(reg); 82 if (rtsx_check_mmc_support(reg)) 83 pcr->extra_caps |= EXTRA_CAPS_NO_MMC; 84 pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg); 85 if (rtsx_reg_check_reverse_socket(reg)) 86 pcr->flags |= PCR_REVERSE_SOCKET; 87 if (rtsx_reg_check_cd_reverse(reg)) 88 pcr->option.sd_cd_reverse_en = 1; 89 if (rtsx_reg_check_wp_reverse(reg)) 90 pcr->option.sd_wp_reverse_en = 1; 91 } 92 93 static int rts5228_optimize_phy(struct rtsx_pcr *pcr) 94 { 95 return rtsx_pci_write_phy_register(pcr, 0x07, 0x8F40); 96 } 97 98 static void rts5228_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime) 99 { 100 /* Set relink_time to 0 */ 101 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0); 102 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0); 103 rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3, 104 RELINK_TIME_MASK, 0); 105 106 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 107 D3_DELINK_MODE_EN, D3_DELINK_MODE_EN); 108 109 if (!runtime) { 110 rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1, 111 CD_RESUME_EN_MASK, 0); 112 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00); 113 rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL, 114 FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL); 115 } 116 117 rtsx_pci_write_register(pcr, FPDCTL, 118 SSC_POWER_DOWN, SSC_POWER_DOWN); 119 } 120 121 static int rts5228_enable_auto_blink(struct rtsx_pcr *pcr) 122 { 123 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 124 LED_SHINE_MASK, LED_SHINE_EN); 125 } 126 127 static int rts5228_disable_auto_blink(struct rtsx_pcr *pcr) 128 { 129 return rtsx_pci_write_register(pcr, OLT_LED_CTL, 130 LED_SHINE_MASK, LED_SHINE_DISABLE); 131 } 132 133 static int rts5228_turn_on_led(struct rtsx_pcr *pcr) 134 { 135 return rtsx_pci_write_register(pcr, GPIO_CTL, 136 0x02, 0x02); 137 } 138 139 static int rts5228_turn_off_led(struct rtsx_pcr *pcr) 140 { 141 return rtsx_pci_write_register(pcr, GPIO_CTL, 142 0x02, 0x00); 143 } 144 145 /* SD Pull Control Enable: 146 * SD_DAT[3:0] ==> pull up 147 * SD_CD ==> pull up 148 * SD_WP ==> pull up 149 * SD_CMD ==> pull up 150 * SD_CLK ==> pull down 151 */ 152 static const u32 rts5228_sd_pull_ctl_enable_tbl[] = { 153 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA), 154 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9), 155 0, 156 }; 157 158 /* SD Pull Control Disable: 159 * SD_DAT[3:0] ==> pull down 160 * SD_CD ==> pull up 161 * SD_WP ==> pull down 162 * SD_CMD ==> pull down 163 * SD_CLK ==> pull down 164 */ 165 static const u32 rts5228_sd_pull_ctl_disable_tbl[] = { 166 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55), 167 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5), 168 0, 169 }; 170 171 static int rts5228_sd_set_sample_push_timing_sd30(struct rtsx_pcr *pcr) 172 { 173 rtsx_pci_write_register(pcr, SD_CFG1, SD_MODE_SELECT_MASK 174 | SD_ASYNC_FIFO_NOT_RST, SD_30_MODE | SD_ASYNC_FIFO_NOT_RST); 175 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); 176 rtsx_pci_write_register(pcr, CARD_CLK_SOURCE, 0xFF, 177 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 178 rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); 179 180 return 0; 181 } 182 183 static int rts5228_card_power_on(struct rtsx_pcr *pcr, int card) 184 { 185 struct rtsx_cr_option *option = &pcr->option; 186 187 if (option->ocp_en) 188 rtsx_pci_enable_ocp(pcr); 189 190 rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0, 191 CFG_SD_POW_AUTO_PD, CFG_SD_POW_AUTO_PD); 192 193 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG1, 194 RTS5228_LDO1_TUNE_MASK, RTS5228_LDO1_33); 195 196 rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL, 197 RTS5228_LDO1_POWERON_MASK, RTS5228_LDO1_SOFTSTART); 198 mdelay(2); 199 rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL, 200 RTS5228_LDO1_POWERON_MASK, RTS5228_LDO1_FULLON); 201 202 203 rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL, 204 RTS5228_LDO3318_POWERON, RTS5228_LDO3318_POWERON); 205 206 msleep(20); 207 208 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); 209 210 /* Initialize SD_CFG1 register */ 211 rtsx_pci_write_register(pcr, SD_CFG1, 0xFF, 212 SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1BIT); 213 214 rtsx_pci_write_register(pcr, SD_SAMPLE_POINT_CTL, 215 0xFF, SD20_RX_POS_EDGE); 216 rtsx_pci_write_register(pcr, SD_PUSH_POINT_CTL, 0xFF, 0); 217 rtsx_pci_write_register(pcr, CARD_STOP, SD_STOP | SD_CLR_ERR, 218 SD_STOP | SD_CLR_ERR); 219 220 /* Reset SD_CFG3 register */ 221 rtsx_pci_write_register(pcr, SD_CFG3, SD30_CLK_END_EN, 0); 222 rtsx_pci_write_register(pcr, REG_SD_STOP_SDCLK_CFG, 223 SD30_CLK_STOP_CFG_EN | SD30_CLK_STOP_CFG1 | 224 SD30_CLK_STOP_CFG0, 0); 225 226 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50 || 227 pcr->extra_caps & EXTRA_CAPS_SD_SDR104) 228 rts5228_sd_set_sample_push_timing_sd30(pcr); 229 230 return 0; 231 } 232 233 static int rts5228_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage) 234 { 235 int err; 236 u16 val = 0; 237 238 rtsx_pci_write_register(pcr, RTS5228_CARD_PWR_CTL, 239 RTS5228_PUPDC, RTS5228_PUPDC); 240 241 switch (voltage) { 242 case OUTPUT_3V3: 243 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val); 244 val |= PHY_TUNE_SDBUS_33; 245 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val); 246 if (err < 0) 247 return err; 248 249 rtsx_pci_write_register(pcr, RTS5228_DV3318_CFG, 250 RTS5228_DV3318_TUNE_MASK, RTS5228_DV3318_33); 251 rtsx_pci_write_register(pcr, SD_PAD_CTL, 252 SD_IO_USING_1V8, 0); 253 break; 254 case OUTPUT_1V8: 255 rtsx_pci_read_phy_register(pcr, PHY_TUNE, &val); 256 val &= ~PHY_TUNE_SDBUS_33; 257 err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, val); 258 if (err < 0) 259 return err; 260 261 rtsx_pci_write_register(pcr, RTS5228_DV3318_CFG, 262 RTS5228_DV3318_TUNE_MASK, RTS5228_DV3318_18); 263 rtsx_pci_write_register(pcr, SD_PAD_CTL, 264 SD_IO_USING_1V8, SD_IO_USING_1V8); 265 break; 266 default: 267 return -EINVAL; 268 } 269 270 /* set pad drive */ 271 rts5228_fill_driving(pcr, voltage); 272 273 return 0; 274 } 275 276 static void rts5228_stop_cmd(struct rtsx_pcr *pcr) 277 { 278 rtsx_pci_writel(pcr, RTSX_HCBCTLR, STOP_CMD); 279 rtsx_pci_writel(pcr, RTSX_HDBCTLR, STOP_DMA); 280 rtsx_pci_write_register(pcr, RTS5260_DMA_RST_CTL_0, 281 RTS5260_DMA_RST | RTS5260_ADMA3_RST, 282 RTS5260_DMA_RST | RTS5260_ADMA3_RST); 283 rtsx_pci_write_register(pcr, RBCTL, RB_FLUSH, RB_FLUSH); 284 } 285 286 static void rts5228_card_before_power_off(struct rtsx_pcr *pcr) 287 { 288 rts5228_stop_cmd(pcr); 289 rts5228_switch_output_voltage(pcr, OUTPUT_3V3); 290 } 291 292 static void rts5228_enable_ocp(struct rtsx_pcr *pcr) 293 { 294 u8 val = 0; 295 296 val = SD_OCP_INT_EN | SD_DETECT_EN; 297 rtsx_pci_write_register(pcr, REG_OCPCTL, 0xFF, val); 298 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0, 299 RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN, 300 RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN); 301 } 302 303 static void rts5228_disable_ocp(struct rtsx_pcr *pcr) 304 { 305 u8 mask = 0; 306 307 mask = SD_OCP_INT_EN | SD_DETECT_EN; 308 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); 309 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0, 310 RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN, 0); 311 } 312 313 static int rts5228_card_power_off(struct rtsx_pcr *pcr, int card) 314 { 315 int err = 0; 316 317 rts5228_card_before_power_off(pcr); 318 err = rtsx_pci_write_register(pcr, RTS5228_LDO1233318_POW_CTL, 319 RTS5228_LDO_POWERON_MASK, 0); 320 rtsx_pci_write_register(pcr, REG_CRC_DUMMY_0, CFG_SD_POW_AUTO_PD, 0); 321 322 if (pcr->option.ocp_en) 323 rtsx_pci_disable_ocp(pcr); 324 325 return err; 326 } 327 328 static void rts5228_init_ocp(struct rtsx_pcr *pcr) 329 { 330 struct rtsx_cr_option *option = &pcr->option; 331 332 if (option->ocp_en) { 333 u8 mask, val; 334 335 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0, 336 RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN, 337 RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN); 338 339 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0, 340 RTS5228_LDO1_OCP_THD_MASK, option->sd_800mA_ocp_thd); 341 342 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0, 343 RTS5228_LDO1_OCP_LMT_THD_MASK, 344 RTS5228_LDO1_LMT_THD_1500); 345 346 rtsx_pci_read_register(pcr, RTS5228_LDO1_CFG0, &val); 347 348 mask = SD_OCP_GLITCH_MASK; 349 val = pcr->hw_param.ocp_glitch; 350 rtsx_pci_write_register(pcr, REG_OCPGLITCH, mask, val); 351 352 rts5228_enable_ocp(pcr); 353 354 } else { 355 rtsx_pci_write_register(pcr, RTS5228_LDO1_CFG0, 356 RTS5228_LDO1_OCP_EN | RTS5228_LDO1_OCP_LMT_EN, 0); 357 } 358 } 359 360 static void rts5228_clear_ocpstat(struct rtsx_pcr *pcr) 361 { 362 u8 mask = 0; 363 u8 val = 0; 364 365 mask = SD_OCP_INT_CLR | SD_OC_CLR; 366 val = SD_OCP_INT_CLR | SD_OC_CLR; 367 368 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, val); 369 370 udelay(1000); 371 rtsx_pci_write_register(pcr, REG_OCPCTL, mask, 0); 372 373 } 374 375 static void rts5228_process_ocp(struct rtsx_pcr *pcr) 376 { 377 if (!pcr->option.ocp_en) 378 return; 379 380 rtsx_pci_get_ocpstat(pcr, &pcr->ocp_stat); 381 382 if (pcr->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) { 383 rts5228_clear_ocpstat(pcr); 384 rts5228_card_power_off(pcr, RTSX_SD_CARD); 385 rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, 0); 386 pcr->ocp_stat = 0; 387 } 388 389 } 390 391 static void rts5228_init_from_cfg(struct rtsx_pcr *pcr) 392 { 393 struct rtsx_cr_option *option = &pcr->option; 394 395 if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN 396 | PM_L1_1_EN | PM_L1_2_EN)) 397 rtsx_pci_disable_oobs_polling(pcr); 398 else 399 rtsx_pci_enable_oobs_polling(pcr); 400 401 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, 0xFF, 0); 402 403 if (option->ltr_en) { 404 if (option->ltr_enabled) 405 rtsx_set_ltr_latency(pcr, option->ltr_active_latency); 406 } 407 } 408 409 static int rts5228_extra_init_hw(struct rtsx_pcr *pcr) 410 { 411 struct rtsx_cr_option *option = &pcr->option; 412 413 rtsx_pci_write_register(pcr, RTS5228_AUTOLOAD_CFG1, 414 CD_RESUME_EN_MASK, CD_RESUME_EN_MASK); 415 416 rts5228_init_from_cfg(pcr); 417 418 rtsx_pci_write_register(pcr, L1SUB_CONFIG1, 419 AUX_CLK_ACTIVE_SEL_MASK, MAC_CKSW_DONE); 420 rtsx_pci_write_register(pcr, L1SUB_CONFIG3, 0xFF, 0); 421 422 rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, 423 FUNC_FORCE_UPME_XMT_DBG, FUNC_FORCE_UPME_XMT_DBG); 424 425 rtsx_pci_write_register(pcr, PCLK_CTL, 426 PCLK_MODE_SEL, PCLK_MODE_SEL); 427 428 rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0); 429 rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, CLK_PM_EN, CLK_PM_EN); 430 431 /* LED shine disabled, set initial shine cycle period */ 432 rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x0F, 0x02); 433 434 /* Configure driving */ 435 rts5228_fill_driving(pcr, OUTPUT_3V3); 436 437 if (pcr->flags & PCR_REVERSE_SOCKET) 438 rtsx_pci_write_register(pcr, PETXCFG, 0x30, 0x30); 439 else { 440 rtsx_pci_write_register(pcr, PETXCFG, 0x20, option->sd_cd_reverse_en << 5); 441 rtsx_pci_write_register(pcr, PETXCFG, 0x10, option->sd_wp_reverse_en << 4); 442 } 443 444 /* 445 * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced 446 * to drive low, and we forcibly request clock. 447 */ 448 if (option->force_clkreq_0) 449 rtsx_pci_write_register(pcr, PETXCFG, 450 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW); 451 else 452 rtsx_pci_write_register(pcr, PETXCFG, 453 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH); 454 455 rtsx_pci_write_register(pcr, PWD_SUSPEND_EN, 0xFF, 0xFB); 456 457 if (pcr->rtd3_en) { 458 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x01); 459 rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL, 460 FORCE_PM_CONTROL | FORCE_PM_VALUE, 461 FORCE_PM_CONTROL | FORCE_PM_VALUE); 462 } else { 463 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, 0x01, 0x00); 464 rtsx_pci_write_register(pcr, RTS5228_REG_PME_FORCE_CTL, 465 FORCE_PM_CONTROL | FORCE_PM_VALUE, FORCE_PM_CONTROL); 466 } 467 rtsx_pci_write_register(pcr, pcr->reg_pm_ctrl3, D3_DELINK_MODE_EN, 0x00); 468 469 return 0; 470 } 471 472 static void rts5228_enable_aspm(struct rtsx_pcr *pcr, bool enable) 473 { 474 u8 mask, val; 475 476 if (pcr->aspm_enabled == enable) 477 return; 478 479 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1; 480 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1; 481 val |= (pcr->aspm_en & 0x02); 482 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); 483 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, 484 PCI_EXP_LNKCTL_ASPMC, pcr->aspm_en); 485 pcr->aspm_enabled = enable; 486 } 487 488 static void rts5228_disable_aspm(struct rtsx_pcr *pcr, bool enable) 489 { 490 u8 mask, val; 491 492 if (pcr->aspm_enabled == enable) 493 return; 494 495 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL, 496 PCI_EXP_LNKCTL_ASPMC, 0); 497 mask = FORCE_ASPM_VAL_MASK | FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1; 498 val = FORCE_ASPM_CTL0 | FORCE_ASPM_CTL1; 499 rtsx_pci_write_register(pcr, ASPM_FORCE_CTL, mask, val); 500 rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); 501 mdelay(10); 502 pcr->aspm_enabled = enable; 503 } 504 505 static void rts5228_set_aspm(struct rtsx_pcr *pcr, bool enable) 506 { 507 if (enable) 508 rts5228_enable_aspm(pcr, true); 509 else 510 rts5228_disable_aspm(pcr, false); 511 } 512 513 static void rts5228_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active) 514 { 515 struct rtsx_cr_option *option = &pcr->option; 516 int aspm_L1_1, aspm_L1_2; 517 u8 val = 0; 518 519 aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN); 520 aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN); 521 522 if (active) { 523 /* run, latency: 60us */ 524 if (aspm_L1_1) 525 val = option->ltr_l1off_snooze_sspwrgate; 526 } else { 527 /* l1off, latency: 300us */ 528 if (aspm_L1_2) 529 val = option->ltr_l1off_sspwrgate; 530 } 531 532 rtsx_set_l1off_sub(pcr, val); 533 } 534 535 static const struct pcr_ops rts5228_pcr_ops = { 536 .fetch_vendor_settings = rtsx5228_fetch_vendor_settings, 537 .turn_on_led = rts5228_turn_on_led, 538 .turn_off_led = rts5228_turn_off_led, 539 .extra_init_hw = rts5228_extra_init_hw, 540 .enable_auto_blink = rts5228_enable_auto_blink, 541 .disable_auto_blink = rts5228_disable_auto_blink, 542 .card_power_on = rts5228_card_power_on, 543 .card_power_off = rts5228_card_power_off, 544 .switch_output_voltage = rts5228_switch_output_voltage, 545 .force_power_down = rts5228_force_power_down, 546 .stop_cmd = rts5228_stop_cmd, 547 .set_aspm = rts5228_set_aspm, 548 .set_l1off_cfg_sub_d0 = rts5228_set_l1off_cfg_sub_d0, 549 .enable_ocp = rts5228_enable_ocp, 550 .disable_ocp = rts5228_disable_ocp, 551 .init_ocp = rts5228_init_ocp, 552 .process_ocp = rts5228_process_ocp, 553 .clear_ocpstat = rts5228_clear_ocpstat, 554 .optimize_phy = rts5228_optimize_phy, 555 }; 556 557 558 static inline u8 double_ssc_depth(u8 depth) 559 { 560 return ((depth > 1) ? (depth - 1) : depth); 561 } 562 563 int rts5228_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, 564 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk) 565 { 566 int err, clk; 567 u16 n; 568 u8 clk_divider, mcu_cnt, div; 569 static const u8 depth[] = { 570 [RTSX_SSC_DEPTH_4M] = RTS5228_SSC_DEPTH_4M, 571 [RTSX_SSC_DEPTH_2M] = RTS5228_SSC_DEPTH_2M, 572 [RTSX_SSC_DEPTH_1M] = RTS5228_SSC_DEPTH_1M, 573 [RTSX_SSC_DEPTH_500K] = RTS5228_SSC_DEPTH_512K, 574 }; 575 576 if (initial_mode) { 577 /* We use 250k(around) here, in initial stage */ 578 clk_divider = SD_CLK_DIVIDE_128; 579 card_clock = 30000000; 580 } else { 581 clk_divider = SD_CLK_DIVIDE_0; 582 } 583 err = rtsx_pci_write_register(pcr, SD_CFG1, 584 SD_CLK_DIVIDE_MASK, clk_divider); 585 if (err < 0) 586 return err; 587 588 card_clock /= 1000000; 589 pcr_dbg(pcr, "Switch card clock to %dMHz\n", card_clock); 590 591 clk = card_clock; 592 if (!initial_mode && double_clk) 593 clk = card_clock * 2; 594 pcr_dbg(pcr, "Internal SSC clock: %dMHz (cur_clock = %d)\n", 595 clk, pcr->cur_clock); 596 597 if (clk == pcr->cur_clock) 598 return 0; 599 600 if (pcr->ops->conv_clk_and_div_n) 601 n = pcr->ops->conv_clk_and_div_n(clk, CLK_TO_DIV_N); 602 else 603 n = clk - 4; 604 if ((clk <= 4) || (n > 396)) 605 return -EINVAL; 606 607 mcu_cnt = 125/clk + 3; 608 if (mcu_cnt > 15) 609 mcu_cnt = 15; 610 611 div = CLK_DIV_1; 612 while ((n < MIN_DIV_N_PCR - 4) && (div < CLK_DIV_8)) { 613 if (pcr->ops->conv_clk_and_div_n) { 614 int dbl_clk = pcr->ops->conv_clk_and_div_n(n, 615 DIV_N_TO_CLK) * 2; 616 n = pcr->ops->conv_clk_and_div_n(dbl_clk, 617 CLK_TO_DIV_N); 618 } else { 619 n = (n + 4) * 2 - 4; 620 } 621 div++; 622 } 623 624 n = (n / 2) - 1; 625 pcr_dbg(pcr, "n = %d, div = %d\n", n, div); 626 627 ssc_depth = depth[ssc_depth]; 628 if (double_clk) 629 ssc_depth = double_ssc_depth(ssc_depth); 630 631 if (ssc_depth) { 632 if (div == CLK_DIV_2) { 633 if (ssc_depth > 1) 634 ssc_depth -= 1; 635 else 636 ssc_depth = RTS5228_SSC_DEPTH_8M; 637 } else if (div == CLK_DIV_4) { 638 if (ssc_depth > 2) 639 ssc_depth -= 2; 640 else 641 ssc_depth = RTS5228_SSC_DEPTH_8M; 642 } else if (div == CLK_DIV_8) { 643 if (ssc_depth > 3) 644 ssc_depth -= 3; 645 else 646 ssc_depth = RTS5228_SSC_DEPTH_8M; 647 } 648 } else { 649 ssc_depth = 0; 650 } 651 pcr_dbg(pcr, "ssc_depth = %d\n", ssc_depth); 652 653 rtsx_pci_init_cmd(pcr); 654 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 655 CLK_LOW_FREQ, CLK_LOW_FREQ); 656 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_DIV, 657 0xFF, (div << 4) | mcu_cnt); 658 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); 659 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL2, 660 SSC_DEPTH_MASK, ssc_depth); 661 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n); 662 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB); 663 if (vpclk) { 664 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, 665 PHASE_NOT_RESET, 0); 666 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL, 667 PHASE_NOT_RESET, 0); 668 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, 669 PHASE_NOT_RESET, PHASE_NOT_RESET); 670 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK1_CTL, 671 PHASE_NOT_RESET, PHASE_NOT_RESET); 672 } 673 674 err = rtsx_pci_send_cmd(pcr, 2000); 675 if (err < 0) 676 return err; 677 678 /* Wait SSC clock stable */ 679 udelay(SSC_CLOCK_STABLE_WAIT); 680 err = rtsx_pci_write_register(pcr, CLK_CTL, CLK_LOW_FREQ, 0); 681 if (err < 0) 682 return err; 683 684 pcr->cur_clock = clk; 685 return 0; 686 687 } 688 689 void rts5228_init_params(struct rtsx_pcr *pcr) 690 { 691 struct rtsx_cr_option *option = &pcr->option; 692 struct rtsx_hw_param *hw_param = &pcr->hw_param; 693 694 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104; 695 pcr->num_slots = 1; 696 pcr->ops = &rts5228_pcr_ops; 697 698 pcr->flags = 0; 699 pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT; 700 pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B; 701 pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B; 702 pcr->aspm_en = ASPM_L1_EN; 703 pcr->aspm_mode = ASPM_MODE_REG; 704 pcr->tx_initial_phase = SET_CLOCK_PHASE(28, 27, 11); 705 pcr->rx_initial_phase = SET_CLOCK_PHASE(24, 6, 5); 706 707 pcr->ic_version = rts5228_get_ic_version(pcr); 708 pcr->sd_pull_ctl_enable_tbl = rts5228_sd_pull_ctl_enable_tbl; 709 pcr->sd_pull_ctl_disable_tbl = rts5228_sd_pull_ctl_disable_tbl; 710 711 pcr->reg_pm_ctrl3 = RTS5228_AUTOLOAD_CFG3; 712 713 option->dev_flags = (LTR_L1SS_PWR_GATE_CHECK_CARD_EN 714 | LTR_L1SS_PWR_GATE_EN); 715 option->ltr_en = true; 716 717 /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */ 718 option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF; 719 option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF; 720 option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF; 721 option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF; 722 option->ltr_l1off_sspwrgate = 0x7F; 723 option->ltr_l1off_snooze_sspwrgate = 0x78; 724 725 option->ocp_en = 1; 726 hw_param->interrupt_en |= SD_OC_INT_EN; 727 hw_param->ocp_glitch = SD_OCP_GLITCH_800U; 728 option->sd_800mA_ocp_thd = RTS5228_LDO1_OCP_THD_930; 729 option->sd_cd_reverse_en = 0; 730 option->sd_wp_reverse_en = 0; 731 } 732