1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2018-2020 Broadcom. 4 */ 5 6 #include <linux/delay.h> 7 #include <linux/dma-mapping.h> 8 #include <linux/firmware.h> 9 #include <linux/fs.h> 10 #include <linux/idr.h> 11 #include <linux/module.h> 12 #include <linux/pci.h> 13 #include <linux/pci_regs.h> 14 #include <uapi/linux/misc/bcm_vk.h> 15 16 #include "bcm_vk.h" 17 18 #define PCI_DEVICE_ID_VALKYRIE 0x5e87 19 #define PCI_DEVICE_ID_VIPER 0x5e88 20 21 static DEFINE_IDA(bcm_vk_ida); 22 23 enum soc_idx { 24 VALKYRIE_A0 = 0, 25 VALKYRIE_B0, 26 VIPER, 27 VK_IDX_INVALID 28 }; 29 30 enum img_idx { 31 IMG_PRI = 0, 32 IMG_SEC, 33 IMG_PER_TYPE_MAX 34 }; 35 36 struct load_image_entry { 37 const u32 image_type; 38 const char *image_name[IMG_PER_TYPE_MAX]; 39 }; 40 41 #define NUM_BOOT_STAGES 2 42 /* default firmware images names */ 43 static const struct load_image_entry image_tab[][NUM_BOOT_STAGES] = { 44 [VALKYRIE_A0] = { 45 {VK_IMAGE_TYPE_BOOT1, {"vk_a0-boot1.bin", "vk-boot1.bin"}}, 46 {VK_IMAGE_TYPE_BOOT2, {"vk_a0-boot2.bin", "vk-boot2.bin"}} 47 }, 48 [VALKYRIE_B0] = { 49 {VK_IMAGE_TYPE_BOOT1, {"vk_b0-boot1.bin", "vk-boot1.bin"}}, 50 {VK_IMAGE_TYPE_BOOT2, {"vk_b0-boot2.bin", "vk-boot2.bin"}} 51 }, 52 53 [VIPER] = { 54 {VK_IMAGE_TYPE_BOOT1, {"vp-boot1.bin", ""}}, 55 {VK_IMAGE_TYPE_BOOT2, {"vp-boot2.bin", ""}} 56 }, 57 }; 58 59 /* Location of memory base addresses of interest in BAR1 */ 60 /* Load Boot1 to start of ITCM */ 61 #define BAR1_CODEPUSH_BASE_BOOT1 0x100000 62 63 /* Allow minimum 1s for Load Image timeout responses */ 64 #define LOAD_IMAGE_TIMEOUT_MS (1 * MSEC_PER_SEC) 65 66 /* Image startup timeouts */ 67 #define BOOT1_STARTUP_TIMEOUT_MS (5 * MSEC_PER_SEC) 68 #define BOOT2_STARTUP_TIMEOUT_MS (10 * MSEC_PER_SEC) 69 70 /* 1ms wait for checking the transfer complete status */ 71 #define TXFR_COMPLETE_TIMEOUT_MS 1 72 73 /* MSIX usages */ 74 #define VK_MSIX_MSGQ_MAX 3 75 #define VK_MSIX_NOTF_MAX 1 76 #define VK_MSIX_TTY_MAX BCM_VK_NUM_TTY 77 #define VK_MSIX_IRQ_MAX (VK_MSIX_MSGQ_MAX + VK_MSIX_NOTF_MAX + \ 78 VK_MSIX_TTY_MAX) 79 #define VK_MSIX_IRQ_MIN_REQ (VK_MSIX_MSGQ_MAX + VK_MSIX_NOTF_MAX) 80 81 /* Number of bits set in DMA mask*/ 82 #define BCM_VK_DMA_BITS 64 83 84 /* Ucode boot wait time */ 85 #define BCM_VK_UCODE_BOOT_US (100 * USEC_PER_MSEC) 86 /* 50% margin */ 87 #define BCM_VK_UCODE_BOOT_MAX_US ((BCM_VK_UCODE_BOOT_US * 3) >> 1) 88 89 /* deinit time for the card os after receiving doorbell */ 90 #define BCM_VK_DEINIT_TIME_MS (2 * MSEC_PER_SEC) 91 92 /* 93 * module parameters 94 */ 95 static bool auto_load = true; 96 module_param(auto_load, bool, 0444); 97 MODULE_PARM_DESC(auto_load, 98 "Load images automatically at PCIe probe time.\n"); 99 static uint nr_scratch_pages = VK_BAR1_SCRATCH_DEF_NR_PAGES; 100 module_param(nr_scratch_pages, uint, 0444); 101 MODULE_PARM_DESC(nr_scratch_pages, 102 "Number of pre allocated DMAable coherent pages.\n"); 103 104 static int bcm_vk_intf_ver_chk(struct bcm_vk *vk) 105 { 106 struct device *dev = &vk->pdev->dev; 107 u32 reg; 108 u16 major, minor; 109 int ret = 0; 110 111 /* read interface register */ 112 reg = vkread32(vk, BAR_0, BAR_INTF_VER); 113 major = (reg >> BAR_INTF_VER_MAJOR_SHIFT) & BAR_INTF_VER_MASK; 114 minor = reg & BAR_INTF_VER_MASK; 115 116 /* 117 * if major number is 0, it is pre-release and it would be allowed 118 * to continue, else, check versions accordingly 119 */ 120 if (!major) { 121 dev_warn(dev, "Pre-release major.minor=%d.%d - drv %d.%d\n", 122 major, minor, SEMANTIC_MAJOR, SEMANTIC_MINOR); 123 } else if (major != SEMANTIC_MAJOR) { 124 dev_err(dev, 125 "Intf major.minor=%d.%d rejected - drv %d.%d\n", 126 major, minor, SEMANTIC_MAJOR, SEMANTIC_MINOR); 127 ret = -EPFNOSUPPORT; 128 } else { 129 dev_dbg(dev, 130 "Intf major.minor=%d.%d passed - drv %d.%d\n", 131 major, minor, SEMANTIC_MAJOR, SEMANTIC_MINOR); 132 } 133 return ret; 134 } 135 136 static inline int bcm_vk_wait(struct bcm_vk *vk, enum pci_barno bar, 137 u64 offset, u32 mask, u32 value, 138 unsigned long timeout_ms) 139 { 140 struct device *dev = &vk->pdev->dev; 141 unsigned long start_time; 142 unsigned long timeout; 143 u32 rd_val, boot_status; 144 145 start_time = jiffies; 146 timeout = start_time + msecs_to_jiffies(timeout_ms); 147 148 do { 149 rd_val = vkread32(vk, bar, offset); 150 dev_dbg(dev, "BAR%d Offset=0x%llx: 0x%x\n", 151 bar, offset, rd_val); 152 153 /* check for any boot err condition */ 154 boot_status = vkread32(vk, BAR_0, BAR_BOOT_STATUS); 155 if (boot_status & BOOT_ERR_MASK) { 156 dev_err(dev, "Boot Err 0x%x, progress 0x%x after %d ms\n", 157 (boot_status & BOOT_ERR_MASK) >> BOOT_ERR_SHIFT, 158 boot_status & BOOT_PROG_MASK, 159 jiffies_to_msecs(jiffies - start_time)); 160 return -EFAULT; 161 } 162 163 if (time_after(jiffies, timeout)) 164 return -ETIMEDOUT; 165 166 cpu_relax(); 167 cond_resched(); 168 } while ((rd_val & mask) != value); 169 170 return 0; 171 } 172 173 static int bcm_vk_sync_card_info(struct bcm_vk *vk) 174 { 175 u32 rdy_marker = vkread32(vk, BAR_1, VK_BAR1_MSGQ_DEF_RDY); 176 177 /* check for marker, but allow diags mode to skip sync */ 178 if (!bcm_vk_msgq_marker_valid(vk)) 179 return (rdy_marker == VK_BAR1_DIAG_RDY_MARKER ? 0 : -EINVAL); 180 181 /* 182 * Write down scratch addr which is used for DMA. For 183 * signed part, BAR1 is accessible only after boot2 has come 184 * up 185 */ 186 if (vk->tdma_addr) { 187 vkwrite32(vk, (u64)vk->tdma_addr >> 32, BAR_1, 188 VK_BAR1_SCRATCH_OFF_HI); 189 vkwrite32(vk, (u32)vk->tdma_addr, BAR_1, 190 VK_BAR1_SCRATCH_OFF_LO); 191 vkwrite32(vk, nr_scratch_pages * PAGE_SIZE, BAR_1, 192 VK_BAR1_SCRATCH_SZ_ADDR); 193 } 194 return 0; 195 } 196 197 static void bcm_vk_buf_notify(struct bcm_vk *vk, void *bufp, 198 dma_addr_t host_buf_addr, u32 buf_size) 199 { 200 /* update the dma address to the card */ 201 vkwrite32(vk, (u64)host_buf_addr >> 32, BAR_1, 202 VK_BAR1_DMA_BUF_OFF_HI); 203 vkwrite32(vk, (u32)host_buf_addr, BAR_1, 204 VK_BAR1_DMA_BUF_OFF_LO); 205 vkwrite32(vk, buf_size, BAR_1, VK_BAR1_DMA_BUF_SZ); 206 } 207 208 static int bcm_vk_load_image_by_type(struct bcm_vk *vk, u32 load_type, 209 const char *filename) 210 { 211 struct device *dev = &vk->pdev->dev; 212 const struct firmware *fw = NULL; 213 void *bufp = NULL; 214 size_t max_buf, offset; 215 int ret; 216 u64 offset_codepush; 217 u32 codepush; 218 u32 value; 219 dma_addr_t boot_dma_addr; 220 bool is_stdalone; 221 222 if (load_type == VK_IMAGE_TYPE_BOOT1) { 223 /* 224 * After POR, enable VK soft BOOTSRC so bootrom do not clear 225 * the pushed image (the TCM memories). 226 */ 227 value = vkread32(vk, BAR_0, BAR_BOOTSRC_SELECT); 228 value |= BOOTSRC_SOFT_ENABLE; 229 vkwrite32(vk, value, BAR_0, BAR_BOOTSRC_SELECT); 230 231 codepush = CODEPUSH_BOOTSTART + CODEPUSH_BOOT1_ENTRY; 232 offset_codepush = BAR_CODEPUSH_SBL; 233 234 /* Write a 1 to request SRAM open bit */ 235 vkwrite32(vk, CODEPUSH_BOOTSTART, BAR_0, offset_codepush); 236 237 /* Wait for VK to respond */ 238 ret = bcm_vk_wait(vk, BAR_0, BAR_BOOT_STATUS, SRAM_OPEN, 239 SRAM_OPEN, LOAD_IMAGE_TIMEOUT_MS); 240 if (ret < 0) { 241 dev_err(dev, "boot1 wait SRAM err - ret(%d)\n", ret); 242 goto err_buf_out; 243 } 244 245 max_buf = SZ_256K; 246 bufp = dma_alloc_coherent(dev, 247 max_buf, 248 &boot_dma_addr, GFP_KERNEL); 249 if (!bufp) { 250 dev_err(dev, "Error allocating 0x%zx\n", max_buf); 251 ret = -ENOMEM; 252 goto err_buf_out; 253 } 254 } else if (load_type == VK_IMAGE_TYPE_BOOT2) { 255 codepush = CODEPUSH_BOOT2_ENTRY; 256 offset_codepush = BAR_CODEPUSH_SBI; 257 258 /* Wait for VK to respond */ 259 ret = bcm_vk_wait(vk, BAR_0, BAR_BOOT_STATUS, DDR_OPEN, 260 DDR_OPEN, LOAD_IMAGE_TIMEOUT_MS); 261 if (ret < 0) { 262 dev_err(dev, "boot2 wait DDR open error - ret(%d)\n", 263 ret); 264 goto err_buf_out; 265 } 266 267 max_buf = SZ_4M; 268 bufp = dma_alloc_coherent(dev, 269 max_buf, 270 &boot_dma_addr, GFP_KERNEL); 271 if (!bufp) { 272 dev_err(dev, "Error allocating 0x%zx\n", max_buf); 273 ret = -ENOMEM; 274 goto err_buf_out; 275 } 276 277 bcm_vk_buf_notify(vk, bufp, boot_dma_addr, max_buf); 278 } else { 279 dev_err(dev, "Error invalid image type 0x%x\n", load_type); 280 ret = -EINVAL; 281 goto err_buf_out; 282 } 283 284 offset = 0; 285 ret = request_partial_firmware_into_buf(&fw, filename, dev, 286 bufp, max_buf, offset); 287 if (ret) { 288 dev_err(dev, "Error %d requesting firmware file: %s\n", 289 ret, filename); 290 goto err_firmware_out; 291 } 292 dev_dbg(dev, "size=0x%zx\n", fw->size); 293 if (load_type == VK_IMAGE_TYPE_BOOT1) 294 memcpy_toio(vk->bar[BAR_1] + BAR1_CODEPUSH_BASE_BOOT1, 295 bufp, 296 fw->size); 297 298 dev_dbg(dev, "Signaling 0x%x to 0x%llx\n", codepush, offset_codepush); 299 vkwrite32(vk, codepush, BAR_0, offset_codepush); 300 301 if (load_type == VK_IMAGE_TYPE_BOOT1) { 302 u32 boot_status; 303 304 /* wait until done */ 305 ret = bcm_vk_wait(vk, BAR_0, BAR_BOOT_STATUS, 306 BOOT1_RUNNING, 307 BOOT1_RUNNING, 308 BOOT1_STARTUP_TIMEOUT_MS); 309 310 boot_status = vkread32(vk, BAR_0, BAR_BOOT_STATUS); 311 is_stdalone = !BCM_VK_INTF_IS_DOWN(boot_status) && 312 (boot_status & BOOT_STDALONE_RUNNING); 313 if (ret && !is_stdalone) { 314 dev_err(dev, 315 "Timeout %ld ms waiting for boot1 to come up - ret(%d)\n", 316 BOOT1_STARTUP_TIMEOUT_MS, ret); 317 goto err_firmware_out; 318 } else if (is_stdalone) { 319 u32 reg; 320 321 reg = vkread32(vk, BAR_0, BAR_BOOT1_STDALONE_PROGRESS); 322 if ((reg & BOOT1_STDALONE_PROGRESS_MASK) == 323 BOOT1_STDALONE_SUCCESS) { 324 dev_info(dev, "Boot1 standalone success\n"); 325 ret = 0; 326 } else { 327 dev_err(dev, "Timeout %ld ms - Boot1 standalone failure\n", 328 BOOT1_STARTUP_TIMEOUT_MS); 329 ret = -EINVAL; 330 goto err_firmware_out; 331 } 332 } 333 } else if (load_type == VK_IMAGE_TYPE_BOOT2) { 334 unsigned long timeout; 335 336 timeout = jiffies + msecs_to_jiffies(LOAD_IMAGE_TIMEOUT_MS); 337 338 /* To send more data to VK than max_buf allowed at a time */ 339 do { 340 /* 341 * Check for ack from card. when Ack is received, 342 * it means all the data is received by card. 343 * Exit the loop after ack is received. 344 */ 345 ret = bcm_vk_wait(vk, BAR_0, BAR_BOOT_STATUS, 346 FW_LOADER_ACK_RCVD_ALL_DATA, 347 FW_LOADER_ACK_RCVD_ALL_DATA, 348 TXFR_COMPLETE_TIMEOUT_MS); 349 if (ret == 0) { 350 dev_dbg(dev, "Exit boot2 download\n"); 351 break; 352 } else if (ret == -EFAULT) { 353 dev_err(dev, "Error detected during ACK waiting"); 354 goto err_firmware_out; 355 } 356 357 /* exit the loop, if there is no response from card */ 358 if (time_after(jiffies, timeout)) { 359 dev_err(dev, "Error. No reply from card\n"); 360 ret = -ETIMEDOUT; 361 goto err_firmware_out; 362 } 363 364 /* Wait for VK to open BAR space to copy new data */ 365 ret = bcm_vk_wait(vk, BAR_0, offset_codepush, 366 codepush, 0, 367 TXFR_COMPLETE_TIMEOUT_MS); 368 if (ret == 0) { 369 offset += max_buf; 370 ret = request_partial_firmware_into_buf 371 (&fw, 372 filename, 373 dev, bufp, 374 max_buf, 375 offset); 376 if (ret) { 377 dev_err(dev, 378 "Error %d requesting firmware file: %s offset: 0x%zx\n", 379 ret, filename, offset); 380 goto err_firmware_out; 381 } 382 dev_dbg(dev, "size=0x%zx\n", fw->size); 383 dev_dbg(dev, "Signaling 0x%x to 0x%llx\n", 384 codepush, offset_codepush); 385 vkwrite32(vk, codepush, BAR_0, offset_codepush); 386 /* reload timeout after every codepush */ 387 timeout = jiffies + 388 msecs_to_jiffies(LOAD_IMAGE_TIMEOUT_MS); 389 } else if (ret == -EFAULT) { 390 dev_err(dev, "Error detected waiting for transfer\n"); 391 goto err_firmware_out; 392 } 393 } while (1); 394 395 /* wait for fw status bits to indicate app ready */ 396 ret = bcm_vk_wait(vk, BAR_0, VK_BAR_FWSTS, 397 VK_FWSTS_READY, 398 VK_FWSTS_READY, 399 BOOT2_STARTUP_TIMEOUT_MS); 400 if (ret < 0) { 401 dev_err(dev, "Boot2 not ready - ret(%d)\n", ret); 402 goto err_firmware_out; 403 } 404 405 is_stdalone = vkread32(vk, BAR_0, BAR_BOOT_STATUS) & 406 BOOT_STDALONE_RUNNING; 407 if (!is_stdalone) { 408 ret = bcm_vk_intf_ver_chk(vk); 409 if (ret) { 410 dev_err(dev, "failure in intf version check\n"); 411 goto err_firmware_out; 412 } 413 414 /* sync & channel other info */ 415 ret = bcm_vk_sync_card_info(vk); 416 if (ret) { 417 dev_err(dev, "Syncing Card Info failure\n"); 418 goto err_firmware_out; 419 } 420 } 421 } 422 423 err_firmware_out: 424 release_firmware(fw); 425 426 err_buf_out: 427 if (bufp) 428 dma_free_coherent(dev, max_buf, bufp, boot_dma_addr); 429 430 return ret; 431 } 432 433 static u32 bcm_vk_next_boot_image(struct bcm_vk *vk) 434 { 435 u32 boot_status; 436 u32 fw_status; 437 u32 load_type = 0; /* default for unknown */ 438 439 boot_status = vkread32(vk, BAR_0, BAR_BOOT_STATUS); 440 fw_status = vkread32(vk, BAR_0, VK_BAR_FWSTS); 441 442 if (!BCM_VK_INTF_IS_DOWN(boot_status) && (boot_status & SRAM_OPEN)) 443 load_type = VK_IMAGE_TYPE_BOOT1; 444 else if (boot_status == BOOT1_RUNNING) 445 load_type = VK_IMAGE_TYPE_BOOT2; 446 447 /* Log status so that we know different stages */ 448 dev_info(&vk->pdev->dev, 449 "boot-status value for next image: 0x%x : fw-status 0x%x\n", 450 boot_status, fw_status); 451 452 return load_type; 453 } 454 455 static enum soc_idx get_soc_idx(struct bcm_vk *vk) 456 { 457 struct pci_dev *pdev = vk->pdev; 458 enum soc_idx idx = VK_IDX_INVALID; 459 u32 rev; 460 static enum soc_idx const vk_soc_tab[] = { VALKYRIE_A0, VALKYRIE_B0 }; 461 462 switch (pdev->device) { 463 case PCI_DEVICE_ID_VALKYRIE: 464 /* get the chip id to decide sub-class */ 465 rev = MAJOR_SOC_REV(vkread32(vk, BAR_0, BAR_CHIP_ID)); 466 if (rev < ARRAY_SIZE(vk_soc_tab)) { 467 idx = vk_soc_tab[rev]; 468 } else { 469 /* Default to A0 firmware for all other chip revs */ 470 idx = VALKYRIE_A0; 471 dev_warn(&pdev->dev, 472 "Rev %d not in image lookup table, default to idx=%d\n", 473 rev, idx); 474 } 475 break; 476 477 case PCI_DEVICE_ID_VIPER: 478 idx = VIPER; 479 break; 480 481 default: 482 dev_err(&pdev->dev, "no images for 0x%x\n", pdev->device); 483 } 484 return idx; 485 } 486 487 static const char *get_load_fw_name(struct bcm_vk *vk, 488 const struct load_image_entry *entry) 489 { 490 const struct firmware *fw; 491 struct device *dev = &vk->pdev->dev; 492 int ret; 493 unsigned long dummy; 494 int i; 495 496 for (i = 0; i < IMG_PER_TYPE_MAX; i++) { 497 fw = NULL; 498 ret = request_partial_firmware_into_buf(&fw, 499 entry->image_name[i], 500 dev, &dummy, 501 sizeof(dummy), 502 0); 503 release_firmware(fw); 504 if (!ret) 505 return entry->image_name[i]; 506 } 507 return NULL; 508 } 509 510 int bcm_vk_auto_load_all_images(struct bcm_vk *vk) 511 { 512 int i, ret = -1; 513 enum soc_idx idx; 514 struct device *dev = &vk->pdev->dev; 515 u32 curr_type; 516 const char *curr_name; 517 518 idx = get_soc_idx(vk); 519 if (idx == VK_IDX_INVALID) 520 goto auto_load_all_exit; 521 522 /* log a message to know the relative loading order */ 523 dev_dbg(dev, "Load All for device %d\n", vk->devid); 524 525 for (i = 0; i < NUM_BOOT_STAGES; i++) { 526 curr_type = image_tab[idx][i].image_type; 527 if (bcm_vk_next_boot_image(vk) == curr_type) { 528 curr_name = get_load_fw_name(vk, &image_tab[idx][i]); 529 if (!curr_name) { 530 dev_err(dev, "No suitable firmware exists for type %d", 531 curr_type); 532 ret = -ENOENT; 533 goto auto_load_all_exit; 534 } 535 ret = bcm_vk_load_image_by_type(vk, curr_type, 536 curr_name); 537 dev_info(dev, "Auto load %s, ret %d\n", 538 curr_name, ret); 539 540 if (ret) { 541 dev_err(dev, "Error loading default %s\n", 542 curr_name); 543 goto auto_load_all_exit; 544 } 545 } 546 } 547 548 auto_load_all_exit: 549 return ret; 550 } 551 552 static int bcm_vk_trigger_autoload(struct bcm_vk *vk) 553 { 554 if (test_and_set_bit(BCM_VK_WQ_DWNLD_PEND, vk->wq_offload) != 0) 555 return -EPERM; 556 557 set_bit(BCM_VK_WQ_DWNLD_AUTO, vk->wq_offload); 558 queue_work(vk->wq_thread, &vk->wq_work); 559 560 return 0; 561 } 562 563 /* 564 * deferred work queue for auto download. 565 */ 566 static void bcm_vk_wq_handler(struct work_struct *work) 567 { 568 struct bcm_vk *vk = container_of(work, struct bcm_vk, wq_work); 569 570 if (test_bit(BCM_VK_WQ_DWNLD_AUTO, vk->wq_offload)) { 571 bcm_vk_auto_load_all_images(vk); 572 573 /* 574 * at the end of operation, clear AUTO bit and pending 575 * bit 576 */ 577 clear_bit(BCM_VK_WQ_DWNLD_AUTO, vk->wq_offload); 578 clear_bit(BCM_VK_WQ_DWNLD_PEND, vk->wq_offload); 579 } 580 } 581 582 static void bcm_to_v_reset_doorbell(struct bcm_vk *vk, u32 db_val) 583 { 584 vkwrite32(vk, db_val, BAR_0, VK_BAR0_RESET_DB_BASE); 585 } 586 587 static int bcm_vk_trigger_reset(struct bcm_vk *vk) 588 { 589 u32 i; 590 u32 value, boot_status; 591 static const u32 bar0_reg_clr_list[] = { BAR_OS_UPTIME, 592 BAR_INTF_VER, 593 BAR_CARD_VOLTAGE, 594 BAR_CARD_TEMPERATURE, 595 BAR_CARD_PWR_AND_THRE }; 596 597 /* make tag '\0' terminated */ 598 vkwrite32(vk, 0, BAR_1, VK_BAR1_BOOT1_VER_TAG); 599 600 for (i = 0; i < VK_BAR1_DAUTH_MAX; i++) { 601 vkwrite32(vk, 0, BAR_1, VK_BAR1_DAUTH_STORE_ADDR(i)); 602 vkwrite32(vk, 0, BAR_1, VK_BAR1_DAUTH_VALID_ADDR(i)); 603 } 604 for (i = 0; i < VK_BAR1_SOTP_REVID_MAX; i++) 605 vkwrite32(vk, 0, BAR_1, VK_BAR1_SOTP_REVID_ADDR(i)); 606 607 /* 608 * When boot request fails, the CODE_PUSH_OFFSET stays persistent. 609 * Allowing us to debug the failure. When we call reset, 610 * we should clear CODE_PUSH_OFFSET so ROM does not execute 611 * boot again (and fails again) and instead waits for a new 612 * codepush. And, if previous boot has encountered error, need 613 * to clear the entry values 614 */ 615 boot_status = vkread32(vk, BAR_0, BAR_BOOT_STATUS); 616 if (boot_status & BOOT_ERR_MASK) { 617 dev_info(&vk->pdev->dev, 618 "Card in boot error 0x%x, clear CODEPUSH val\n", 619 boot_status); 620 value = 0; 621 } else { 622 value = vkread32(vk, BAR_0, BAR_CODEPUSH_SBL); 623 value &= CODEPUSH_MASK; 624 } 625 vkwrite32(vk, value, BAR_0, BAR_CODEPUSH_SBL); 626 627 /* reset fw_status with proper reason, and press db */ 628 vkwrite32(vk, VK_FWSTS_RESET_MBOX_DB, BAR_0, VK_BAR_FWSTS); 629 bcm_to_v_reset_doorbell(vk, VK_BAR0_RESET_DB_SOFT); 630 631 /* clear other necessary registers records */ 632 for (i = 0; i < ARRAY_SIZE(bar0_reg_clr_list); i++) 633 vkwrite32(vk, 0, BAR_0, bar0_reg_clr_list[i]); 634 635 return 0; 636 } 637 638 static int bcm_vk_on_panic(struct notifier_block *nb, 639 unsigned long e, void *p) 640 { 641 struct bcm_vk *vk = container_of(nb, struct bcm_vk, panic_nb); 642 643 bcm_to_v_reset_doorbell(vk, VK_BAR0_RESET_DB_HARD); 644 645 return 0; 646 } 647 648 static int bcm_vk_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 649 { 650 int err; 651 int i; 652 int id; 653 int irq; 654 char name[20]; 655 struct bcm_vk *vk; 656 struct device *dev = &pdev->dev; 657 struct miscdevice *misc_device; 658 u32 boot_status; 659 660 vk = kzalloc(sizeof(*vk), GFP_KERNEL); 661 if (!vk) 662 return -ENOMEM; 663 664 err = pci_enable_device(pdev); 665 if (err) { 666 dev_err(dev, "Cannot enable PCI device\n"); 667 goto err_free_exit; 668 } 669 vk->pdev = pci_dev_get(pdev); 670 671 err = pci_request_regions(pdev, DRV_MODULE_NAME); 672 if (err) { 673 dev_err(dev, "Cannot obtain PCI resources\n"); 674 goto err_disable_pdev; 675 } 676 677 /* make sure DMA is good */ 678 err = dma_set_mask_and_coherent(&pdev->dev, 679 DMA_BIT_MASK(BCM_VK_DMA_BITS)); 680 if (err) { 681 dev_err(dev, "failed to set DMA mask\n"); 682 goto err_disable_pdev; 683 } 684 685 /* The tdma is a scratch area for some DMA testings. */ 686 if (nr_scratch_pages) { 687 vk->tdma_vaddr = dma_alloc_coherent 688 (dev, 689 nr_scratch_pages * PAGE_SIZE, 690 &vk->tdma_addr, GFP_KERNEL); 691 if (!vk->tdma_vaddr) { 692 err = -ENOMEM; 693 goto err_disable_pdev; 694 } 695 } 696 697 pci_set_master(pdev); 698 pci_set_drvdata(pdev, vk); 699 700 irq = pci_alloc_irq_vectors(pdev, 701 1, 702 VK_MSIX_IRQ_MAX, 703 PCI_IRQ_MSI | PCI_IRQ_MSIX); 704 705 if (irq < VK_MSIX_IRQ_MIN_REQ) { 706 dev_err(dev, "failed to get min %d MSIX interrupts, irq(%d)\n", 707 VK_MSIX_IRQ_MIN_REQ, irq); 708 err = (irq >= 0) ? -EINVAL : irq; 709 goto err_disable_pdev; 710 } 711 712 if (irq != VK_MSIX_IRQ_MAX) 713 dev_warn(dev, "Number of IRQs %d allocated - requested(%d).\n", 714 irq, VK_MSIX_IRQ_MAX); 715 716 for (i = 0; i < MAX_BAR; i++) { 717 /* multiple by 2 for 64 bit BAR mapping */ 718 vk->bar[i] = pci_ioremap_bar(pdev, i * 2); 719 if (!vk->bar[i]) { 720 dev_err(dev, "failed to remap BAR%d\n", i); 721 goto err_iounmap; 722 } 723 } 724 725 id = ida_simple_get(&bcm_vk_ida, 0, 0, GFP_KERNEL); 726 if (id < 0) { 727 err = id; 728 dev_err(dev, "unable to get id\n"); 729 goto err_iounmap; 730 } 731 732 vk->devid = id; 733 snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id); 734 misc_device = &vk->miscdev; 735 misc_device->minor = MISC_DYNAMIC_MINOR; 736 misc_device->name = kstrdup(name, GFP_KERNEL); 737 if (!misc_device->name) { 738 err = -ENOMEM; 739 goto err_ida_remove; 740 } 741 742 err = misc_register(misc_device); 743 if (err) { 744 dev_err(dev, "failed to register device\n"); 745 goto err_kfree_name; 746 } 747 748 INIT_WORK(&vk->wq_work, bcm_vk_wq_handler); 749 750 /* create dedicated workqueue */ 751 vk->wq_thread = create_singlethread_workqueue(name); 752 if (!vk->wq_thread) { 753 dev_err(dev, "Fail to create workqueue thread\n"); 754 err = -ENOMEM; 755 goto err_misc_deregister; 756 } 757 758 /* sync other info */ 759 bcm_vk_sync_card_info(vk); 760 761 /* register for panic notifier */ 762 vk->panic_nb.notifier_call = bcm_vk_on_panic; 763 err = atomic_notifier_chain_register(&panic_notifier_list, 764 &vk->panic_nb); 765 if (err) { 766 dev_err(dev, "Fail to register panic notifier\n"); 767 goto err_destroy_workqueue; 768 } 769 770 /* 771 * lets trigger an auto download. We don't want to do it serially here 772 * because at probing time, it is not supposed to block for a long time. 773 */ 774 boot_status = vkread32(vk, BAR_0, BAR_BOOT_STATUS); 775 if (auto_load) { 776 if ((boot_status & BOOT_STATE_MASK) == BROM_RUNNING) { 777 if (bcm_vk_trigger_autoload(vk)) 778 goto err_unregister_panic_notifier; 779 } else { 780 dev_err(dev, 781 "Auto-load skipped - BROM not in proper state (0x%x)\n", 782 boot_status); 783 } 784 } 785 786 dev_dbg(dev, "BCM-VK:%u created\n", id); 787 788 return 0; 789 790 err_unregister_panic_notifier: 791 atomic_notifier_chain_unregister(&panic_notifier_list, 792 &vk->panic_nb); 793 794 err_destroy_workqueue: 795 destroy_workqueue(vk->wq_thread); 796 797 err_misc_deregister: 798 misc_deregister(misc_device); 799 800 err_kfree_name: 801 kfree(misc_device->name); 802 misc_device->name = NULL; 803 804 err_ida_remove: 805 ida_simple_remove(&bcm_vk_ida, id); 806 807 err_iounmap: 808 for (i = 0; i < MAX_BAR; i++) { 809 if (vk->bar[i]) 810 pci_iounmap(pdev, vk->bar[i]); 811 } 812 pci_release_regions(pdev); 813 814 err_disable_pdev: 815 if (vk->tdma_vaddr) 816 dma_free_coherent(&pdev->dev, nr_scratch_pages * PAGE_SIZE, 817 vk->tdma_vaddr, vk->tdma_addr); 818 819 pci_free_irq_vectors(pdev); 820 pci_disable_device(pdev); 821 pci_dev_put(pdev); 822 823 err_free_exit: 824 kfree(vk); 825 826 return err; 827 } 828 829 static void bcm_vk_remove(struct pci_dev *pdev) 830 { 831 int i; 832 struct bcm_vk *vk = pci_get_drvdata(pdev); 833 struct miscdevice *misc_device = &vk->miscdev; 834 835 /* 836 * Trigger a reset to card and wait enough time for UCODE to rerun, 837 * which re-initialize the card into its default state. 838 * This ensures when driver is re-enumerated it will start from 839 * a completely clean state. 840 */ 841 bcm_vk_trigger_reset(vk); 842 usleep_range(BCM_VK_UCODE_BOOT_US, BCM_VK_UCODE_BOOT_MAX_US); 843 844 /* unregister panic notifier */ 845 atomic_notifier_chain_unregister(&panic_notifier_list, 846 &vk->panic_nb); 847 848 if (vk->tdma_vaddr) 849 dma_free_coherent(&pdev->dev, nr_scratch_pages * PAGE_SIZE, 850 vk->tdma_vaddr, vk->tdma_addr); 851 852 /* remove if name is set which means misc dev registered */ 853 if (misc_device->name) { 854 misc_deregister(misc_device); 855 kfree(misc_device->name); 856 ida_simple_remove(&bcm_vk_ida, vk->devid); 857 } 858 859 cancel_work_sync(&vk->wq_work); 860 destroy_workqueue(vk->wq_thread); 861 862 for (i = 0; i < MAX_BAR; i++) { 863 if (vk->bar[i]) 864 pci_iounmap(pdev, vk->bar[i]); 865 } 866 867 dev_dbg(&pdev->dev, "BCM-VK:%d released\n", vk->devid); 868 869 pci_release_regions(pdev); 870 pci_free_irq_vectors(pdev); 871 pci_disable_device(pdev); 872 } 873 874 static void bcm_vk_shutdown(struct pci_dev *pdev) 875 { 876 struct bcm_vk *vk = pci_get_drvdata(pdev); 877 u32 reg, boot_stat; 878 879 reg = vkread32(vk, BAR_0, BAR_BOOT_STATUS); 880 boot_stat = reg & BOOT_STATE_MASK; 881 882 if (boot_stat == BOOT1_RUNNING) { 883 /* simply trigger a reset interrupt to park it */ 884 bcm_vk_trigger_reset(vk); 885 } else if (boot_stat == BROM_NOT_RUN) { 886 int err; 887 u16 lnksta; 888 889 /* 890 * The boot status only reflects boot condition since last reset 891 * As ucode will run only once to configure pcie, if multiple 892 * resets happen, we lost track if ucode has run or not. 893 * Here, read the current link speed and use that to 894 * sync up the bootstatus properly so that on reboot-back-up, 895 * it has the proper state to start with autoload 896 */ 897 err = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnksta); 898 if (!err && 899 (lnksta & PCI_EXP_LNKSTA_CLS) != PCI_EXP_LNKSTA_CLS_2_5GB) { 900 reg |= BROM_STATUS_COMPLETE; 901 vkwrite32(vk, reg, BAR_0, BAR_BOOT_STATUS); 902 } 903 } 904 } 905 906 static const struct pci_device_id bcm_vk_ids[] = { 907 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_VALKYRIE), }, 908 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_VIPER), }, 909 { } 910 }; 911 MODULE_DEVICE_TABLE(pci, bcm_vk_ids); 912 913 static struct pci_driver pci_driver = { 914 .name = DRV_MODULE_NAME, 915 .id_table = bcm_vk_ids, 916 .probe = bcm_vk_probe, 917 .remove = bcm_vk_remove, 918 .shutdown = bcm_vk_shutdown, 919 }; 920 module_pci_driver(pci_driver); 921 922 MODULE_DESCRIPTION("Broadcom VK Host Driver"); 923 MODULE_AUTHOR("Scott Branden <scott.branden@broadcom.com>"); 924 MODULE_LICENSE("GPL v2"); 925 MODULE_VERSION("1.0"); 926