1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2018-2020 Broadcom. 4 */ 5 6 #include <linux/delay.h> 7 #include <linux/dma-mapping.h> 8 #include <linux/firmware.h> 9 #include <linux/fs.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/pci_regs.h> 13 #include <uapi/linux/misc/bcm_vk.h> 14 15 #include "bcm_vk.h" 16 17 #define PCI_DEVICE_ID_VALKYRIE 0x5e87 18 #define PCI_DEVICE_ID_VIPER 0x5e88 19 20 static DEFINE_IDA(bcm_vk_ida); 21 22 enum soc_idx { 23 VALKYRIE_A0 = 0, 24 VALKYRIE_B0, 25 VIPER, 26 VK_IDX_INVALID 27 }; 28 29 enum img_idx { 30 IMG_PRI = 0, 31 IMG_SEC, 32 IMG_PER_TYPE_MAX 33 }; 34 35 struct load_image_entry { 36 const u32 image_type; 37 const char *image_name[IMG_PER_TYPE_MAX]; 38 }; 39 40 #define NUM_BOOT_STAGES 2 41 /* default firmware images names */ 42 static const struct load_image_entry image_tab[][NUM_BOOT_STAGES] = { 43 [VALKYRIE_A0] = { 44 {VK_IMAGE_TYPE_BOOT1, {"vk_a0-boot1.bin", "vk-boot1.bin"}}, 45 {VK_IMAGE_TYPE_BOOT2, {"vk_a0-boot2.bin", "vk-boot2.bin"}} 46 }, 47 [VALKYRIE_B0] = { 48 {VK_IMAGE_TYPE_BOOT1, {"vk_b0-boot1.bin", "vk-boot1.bin"}}, 49 {VK_IMAGE_TYPE_BOOT2, {"vk_b0-boot2.bin", "vk-boot2.bin"}} 50 }, 51 52 [VIPER] = { 53 {VK_IMAGE_TYPE_BOOT1, {"vp-boot1.bin", ""}}, 54 {VK_IMAGE_TYPE_BOOT2, {"vp-boot2.bin", ""}} 55 }, 56 }; 57 58 /* Location of memory base addresses of interest in BAR1 */ 59 /* Load Boot1 to start of ITCM */ 60 #define BAR1_CODEPUSH_BASE_BOOT1 0x100000 61 62 /* Allow minimum 1s for Load Image timeout responses */ 63 #define LOAD_IMAGE_TIMEOUT_MS (1 * MSEC_PER_SEC) 64 65 /* Image startup timeouts */ 66 #define BOOT1_STARTUP_TIMEOUT_MS (5 * MSEC_PER_SEC) 67 #define BOOT2_STARTUP_TIMEOUT_MS (10 * MSEC_PER_SEC) 68 69 /* 1ms wait for checking the transfer complete status */ 70 #define TXFR_COMPLETE_TIMEOUT_MS 1 71 72 /* MSIX usages */ 73 #define VK_MSIX_MSGQ_MAX 3 74 #define VK_MSIX_NOTF_MAX 1 75 #define VK_MSIX_TTY_MAX BCM_VK_NUM_TTY 76 #define VK_MSIX_IRQ_MAX (VK_MSIX_MSGQ_MAX + VK_MSIX_NOTF_MAX + \ 77 VK_MSIX_TTY_MAX) 78 #define VK_MSIX_IRQ_MIN_REQ (VK_MSIX_MSGQ_MAX + VK_MSIX_NOTF_MAX) 79 80 /* Number of bits set in DMA mask*/ 81 #define BCM_VK_DMA_BITS 64 82 83 /* Ucode boot wait time */ 84 #define BCM_VK_UCODE_BOOT_US (100 * USEC_PER_MSEC) 85 /* 50% margin */ 86 #define BCM_VK_UCODE_BOOT_MAX_US ((BCM_VK_UCODE_BOOT_US * 3) >> 1) 87 88 /* deinit time for the card os after receiving doorbell */ 89 #define BCM_VK_DEINIT_TIME_MS (2 * MSEC_PER_SEC) 90 91 /* 92 * module parameters 93 */ 94 static bool auto_load = true; 95 module_param(auto_load, bool, 0444); 96 MODULE_PARM_DESC(auto_load, 97 "Load images automatically at PCIe probe time.\n"); 98 static uint nr_scratch_pages = VK_BAR1_SCRATCH_DEF_NR_PAGES; 99 module_param(nr_scratch_pages, uint, 0444); 100 MODULE_PARM_DESC(nr_scratch_pages, 101 "Number of pre allocated DMAable coherent pages.\n"); 102 103 static int bcm_vk_intf_ver_chk(struct bcm_vk *vk) 104 { 105 struct device *dev = &vk->pdev->dev; 106 u32 reg; 107 u16 major, minor; 108 int ret = 0; 109 110 /* read interface register */ 111 reg = vkread32(vk, BAR_0, BAR_INTF_VER); 112 major = (reg >> BAR_INTF_VER_MAJOR_SHIFT) & BAR_INTF_VER_MASK; 113 minor = reg & BAR_INTF_VER_MASK; 114 115 /* 116 * if major number is 0, it is pre-release and it would be allowed 117 * to continue, else, check versions accordingly 118 */ 119 if (!major) { 120 dev_warn(dev, "Pre-release major.minor=%d.%d - drv %d.%d\n", 121 major, minor, SEMANTIC_MAJOR, SEMANTIC_MINOR); 122 } else if (major != SEMANTIC_MAJOR) { 123 dev_err(dev, 124 "Intf major.minor=%d.%d rejected - drv %d.%d\n", 125 major, minor, SEMANTIC_MAJOR, SEMANTIC_MINOR); 126 ret = -EPFNOSUPPORT; 127 } else { 128 dev_dbg(dev, 129 "Intf major.minor=%d.%d passed - drv %d.%d\n", 130 major, minor, SEMANTIC_MAJOR, SEMANTIC_MINOR); 131 } 132 return ret; 133 } 134 135 static inline int bcm_vk_wait(struct bcm_vk *vk, enum pci_barno bar, 136 u64 offset, u32 mask, u32 value, 137 unsigned long timeout_ms) 138 { 139 struct device *dev = &vk->pdev->dev; 140 unsigned long start_time; 141 unsigned long timeout; 142 u32 rd_val, boot_status; 143 144 start_time = jiffies; 145 timeout = start_time + msecs_to_jiffies(timeout_ms); 146 147 do { 148 rd_val = vkread32(vk, bar, offset); 149 dev_dbg(dev, "BAR%d Offset=0x%llx: 0x%x\n", 150 bar, offset, rd_val); 151 152 /* check for any boot err condition */ 153 boot_status = vkread32(vk, BAR_0, BAR_BOOT_STATUS); 154 if (boot_status & BOOT_ERR_MASK) { 155 dev_err(dev, "Boot Err 0x%x, progress 0x%x after %d ms\n", 156 (boot_status & BOOT_ERR_MASK) >> BOOT_ERR_SHIFT, 157 boot_status & BOOT_PROG_MASK, 158 jiffies_to_msecs(jiffies - start_time)); 159 return -EFAULT; 160 } 161 162 if (time_after(jiffies, timeout)) 163 return -ETIMEDOUT; 164 165 cpu_relax(); 166 cond_resched(); 167 } while ((rd_val & mask) != value); 168 169 return 0; 170 } 171 172 static int bcm_vk_sync_card_info(struct bcm_vk *vk) 173 { 174 u32 rdy_marker = vkread32(vk, BAR_1, VK_BAR1_MSGQ_DEF_RDY); 175 176 /* check for marker, but allow diags mode to skip sync */ 177 if (!bcm_vk_msgq_marker_valid(vk)) 178 return (rdy_marker == VK_BAR1_DIAG_RDY_MARKER ? 0 : -EINVAL); 179 180 /* 181 * Write down scratch addr which is used for DMA. For 182 * signed part, BAR1 is accessible only after boot2 has come 183 * up 184 */ 185 if (vk->tdma_addr) { 186 vkwrite32(vk, (u64)vk->tdma_addr >> 32, BAR_1, 187 VK_BAR1_SCRATCH_OFF_HI); 188 vkwrite32(vk, (u32)vk->tdma_addr, BAR_1, 189 VK_BAR1_SCRATCH_OFF_LO); 190 vkwrite32(vk, nr_scratch_pages * PAGE_SIZE, BAR_1, 191 VK_BAR1_SCRATCH_SZ_ADDR); 192 } 193 return 0; 194 } 195 196 static void bcm_vk_buf_notify(struct bcm_vk *vk, void *bufp, 197 dma_addr_t host_buf_addr, u32 buf_size) 198 { 199 /* update the dma address to the card */ 200 vkwrite32(vk, (u64)host_buf_addr >> 32, BAR_1, 201 VK_BAR1_DMA_BUF_OFF_HI); 202 vkwrite32(vk, (u32)host_buf_addr, BAR_1, 203 VK_BAR1_DMA_BUF_OFF_LO); 204 vkwrite32(vk, buf_size, BAR_1, VK_BAR1_DMA_BUF_SZ); 205 } 206 207 static int bcm_vk_load_image_by_type(struct bcm_vk *vk, u32 load_type, 208 const char *filename) 209 { 210 struct device *dev = &vk->pdev->dev; 211 const struct firmware *fw = NULL; 212 void *bufp = NULL; 213 size_t max_buf, offset; 214 int ret; 215 u64 offset_codepush; 216 u32 codepush; 217 u32 value; 218 dma_addr_t boot_dma_addr; 219 bool is_stdalone; 220 221 if (load_type == VK_IMAGE_TYPE_BOOT1) { 222 /* 223 * After POR, enable VK soft BOOTSRC so bootrom do not clear 224 * the pushed image (the TCM memories). 225 */ 226 value = vkread32(vk, BAR_0, BAR_BOOTSRC_SELECT); 227 value |= BOOTSRC_SOFT_ENABLE; 228 vkwrite32(vk, value, BAR_0, BAR_BOOTSRC_SELECT); 229 230 codepush = CODEPUSH_BOOTSTART + CODEPUSH_BOOT1_ENTRY; 231 offset_codepush = BAR_CODEPUSH_SBL; 232 233 /* Write a 1 to request SRAM open bit */ 234 vkwrite32(vk, CODEPUSH_BOOTSTART, BAR_0, offset_codepush); 235 236 /* Wait for VK to respond */ 237 ret = bcm_vk_wait(vk, BAR_0, BAR_BOOT_STATUS, SRAM_OPEN, 238 SRAM_OPEN, LOAD_IMAGE_TIMEOUT_MS); 239 if (ret < 0) { 240 dev_err(dev, "boot1 wait SRAM err - ret(%d)\n", ret); 241 goto err_buf_out; 242 } 243 244 max_buf = SZ_256K; 245 bufp = dma_alloc_coherent(dev, 246 max_buf, 247 &boot_dma_addr, GFP_KERNEL); 248 if (!bufp) { 249 dev_err(dev, "Error allocating 0x%zx\n", max_buf); 250 ret = -ENOMEM; 251 goto err_buf_out; 252 } 253 } else if (load_type == VK_IMAGE_TYPE_BOOT2) { 254 codepush = CODEPUSH_BOOT2_ENTRY; 255 offset_codepush = BAR_CODEPUSH_SBI; 256 257 /* Wait for VK to respond */ 258 ret = bcm_vk_wait(vk, BAR_0, BAR_BOOT_STATUS, DDR_OPEN, 259 DDR_OPEN, LOAD_IMAGE_TIMEOUT_MS); 260 if (ret < 0) { 261 dev_err(dev, "boot2 wait DDR open error - ret(%d)\n", 262 ret); 263 goto err_buf_out; 264 } 265 266 max_buf = SZ_4M; 267 bufp = dma_alloc_coherent(dev, 268 max_buf, 269 &boot_dma_addr, GFP_KERNEL); 270 if (!bufp) { 271 dev_err(dev, "Error allocating 0x%zx\n", max_buf); 272 ret = -ENOMEM; 273 goto err_buf_out; 274 } 275 276 bcm_vk_buf_notify(vk, bufp, boot_dma_addr, max_buf); 277 } else { 278 dev_err(dev, "Error invalid image type 0x%x\n", load_type); 279 ret = -EINVAL; 280 goto err_buf_out; 281 } 282 283 offset = 0; 284 ret = request_partial_firmware_into_buf(&fw, filename, dev, 285 bufp, max_buf, offset); 286 if (ret) { 287 dev_err(dev, "Error %d requesting firmware file: %s\n", 288 ret, filename); 289 goto err_firmware_out; 290 } 291 dev_dbg(dev, "size=0x%zx\n", fw->size); 292 if (load_type == VK_IMAGE_TYPE_BOOT1) 293 memcpy_toio(vk->bar[BAR_1] + BAR1_CODEPUSH_BASE_BOOT1, 294 bufp, 295 fw->size); 296 297 dev_dbg(dev, "Signaling 0x%x to 0x%llx\n", codepush, offset_codepush); 298 vkwrite32(vk, codepush, BAR_0, offset_codepush); 299 300 if (load_type == VK_IMAGE_TYPE_BOOT1) { 301 u32 boot_status; 302 303 /* wait until done */ 304 ret = bcm_vk_wait(vk, BAR_0, BAR_BOOT_STATUS, 305 BOOT1_RUNNING, 306 BOOT1_RUNNING, 307 BOOT1_STARTUP_TIMEOUT_MS); 308 309 boot_status = vkread32(vk, BAR_0, BAR_BOOT_STATUS); 310 is_stdalone = !BCM_VK_INTF_IS_DOWN(boot_status) && 311 (boot_status & BOOT_STDALONE_RUNNING); 312 if (ret && !is_stdalone) { 313 dev_err(dev, 314 "Timeout %ld ms waiting for boot1 to come up - ret(%d)\n", 315 BOOT1_STARTUP_TIMEOUT_MS, ret); 316 goto err_firmware_out; 317 } else if (is_stdalone) { 318 u32 reg; 319 320 reg = vkread32(vk, BAR_0, BAR_BOOT1_STDALONE_PROGRESS); 321 if ((reg & BOOT1_STDALONE_PROGRESS_MASK) == 322 BOOT1_STDALONE_SUCCESS) { 323 dev_info(dev, "Boot1 standalone success\n"); 324 ret = 0; 325 } else { 326 dev_err(dev, "Timeout %ld ms - Boot1 standalone failure\n", 327 BOOT1_STARTUP_TIMEOUT_MS); 328 ret = -EINVAL; 329 goto err_firmware_out; 330 } 331 } 332 } else if (load_type == VK_IMAGE_TYPE_BOOT2) { 333 unsigned long timeout; 334 335 timeout = jiffies + msecs_to_jiffies(LOAD_IMAGE_TIMEOUT_MS); 336 337 /* To send more data to VK than max_buf allowed at a time */ 338 do { 339 /* 340 * Check for ack from card. when Ack is received, 341 * it means all the data is received by card. 342 * Exit the loop after ack is received. 343 */ 344 ret = bcm_vk_wait(vk, BAR_0, BAR_BOOT_STATUS, 345 FW_LOADER_ACK_RCVD_ALL_DATA, 346 FW_LOADER_ACK_RCVD_ALL_DATA, 347 TXFR_COMPLETE_TIMEOUT_MS); 348 if (ret == 0) { 349 dev_dbg(dev, "Exit boot2 download\n"); 350 break; 351 } else if (ret == -EFAULT) { 352 dev_err(dev, "Error detected during ACK waiting"); 353 goto err_firmware_out; 354 } 355 356 /* exit the loop, if there is no response from card */ 357 if (time_after(jiffies, timeout)) { 358 dev_err(dev, "Error. No reply from card\n"); 359 ret = -ETIMEDOUT; 360 goto err_firmware_out; 361 } 362 363 /* Wait for VK to open BAR space to copy new data */ 364 ret = bcm_vk_wait(vk, BAR_0, offset_codepush, 365 codepush, 0, 366 TXFR_COMPLETE_TIMEOUT_MS); 367 if (ret == 0) { 368 offset += max_buf; 369 ret = request_partial_firmware_into_buf 370 (&fw, 371 filename, 372 dev, bufp, 373 max_buf, 374 offset); 375 if (ret) { 376 dev_err(dev, 377 "Error %d requesting firmware file: %s offset: 0x%zx\n", 378 ret, filename, offset); 379 goto err_firmware_out; 380 } 381 dev_dbg(dev, "size=0x%zx\n", fw->size); 382 dev_dbg(dev, "Signaling 0x%x to 0x%llx\n", 383 codepush, offset_codepush); 384 vkwrite32(vk, codepush, BAR_0, offset_codepush); 385 /* reload timeout after every codepush */ 386 timeout = jiffies + 387 msecs_to_jiffies(LOAD_IMAGE_TIMEOUT_MS); 388 } else if (ret == -EFAULT) { 389 dev_err(dev, "Error detected waiting for transfer\n"); 390 goto err_firmware_out; 391 } 392 } while (1); 393 394 /* wait for fw status bits to indicate app ready */ 395 ret = bcm_vk_wait(vk, BAR_0, VK_BAR_FWSTS, 396 VK_FWSTS_READY, 397 VK_FWSTS_READY, 398 BOOT2_STARTUP_TIMEOUT_MS); 399 if (ret < 0) { 400 dev_err(dev, "Boot2 not ready - ret(%d)\n", ret); 401 goto err_firmware_out; 402 } 403 404 is_stdalone = vkread32(vk, BAR_0, BAR_BOOT_STATUS) & 405 BOOT_STDALONE_RUNNING; 406 if (!is_stdalone) { 407 ret = bcm_vk_intf_ver_chk(vk); 408 if (ret) { 409 dev_err(dev, "failure in intf version check\n"); 410 goto err_firmware_out; 411 } 412 413 /* sync & channel other info */ 414 ret = bcm_vk_sync_card_info(vk); 415 if (ret) { 416 dev_err(dev, "Syncing Card Info failure\n"); 417 goto err_firmware_out; 418 } 419 } 420 } 421 422 err_firmware_out: 423 release_firmware(fw); 424 425 err_buf_out: 426 if (bufp) 427 dma_free_coherent(dev, max_buf, bufp, boot_dma_addr); 428 429 return ret; 430 } 431 432 static u32 bcm_vk_next_boot_image(struct bcm_vk *vk) 433 { 434 u32 boot_status; 435 u32 fw_status; 436 u32 load_type = 0; /* default for unknown */ 437 438 boot_status = vkread32(vk, BAR_0, BAR_BOOT_STATUS); 439 fw_status = vkread32(vk, BAR_0, VK_BAR_FWSTS); 440 441 if (!BCM_VK_INTF_IS_DOWN(boot_status) && (boot_status & SRAM_OPEN)) 442 load_type = VK_IMAGE_TYPE_BOOT1; 443 else if (boot_status == BOOT1_RUNNING) 444 load_type = VK_IMAGE_TYPE_BOOT2; 445 446 /* Log status so that we know different stages */ 447 dev_info(&vk->pdev->dev, 448 "boot-status value for next image: 0x%x : fw-status 0x%x\n", 449 boot_status, fw_status); 450 451 return load_type; 452 } 453 454 static enum soc_idx get_soc_idx(struct bcm_vk *vk) 455 { 456 struct pci_dev *pdev = vk->pdev; 457 enum soc_idx idx = VK_IDX_INVALID; 458 u32 rev; 459 static enum soc_idx const vk_soc_tab[] = { VALKYRIE_A0, VALKYRIE_B0 }; 460 461 switch (pdev->device) { 462 case PCI_DEVICE_ID_VALKYRIE: 463 /* get the chip id to decide sub-class */ 464 rev = MAJOR_SOC_REV(vkread32(vk, BAR_0, BAR_CHIP_ID)); 465 if (rev < ARRAY_SIZE(vk_soc_tab)) { 466 idx = vk_soc_tab[rev]; 467 } else { 468 /* Default to A0 firmware for all other chip revs */ 469 idx = VALKYRIE_A0; 470 dev_warn(&pdev->dev, 471 "Rev %d not in image lookup table, default to idx=%d\n", 472 rev, idx); 473 } 474 break; 475 476 case PCI_DEVICE_ID_VIPER: 477 idx = VIPER; 478 break; 479 480 default: 481 dev_err(&pdev->dev, "no images for 0x%x\n", pdev->device); 482 } 483 return idx; 484 } 485 486 static const char *get_load_fw_name(struct bcm_vk *vk, 487 const struct load_image_entry *entry) 488 { 489 const struct firmware *fw; 490 struct device *dev = &vk->pdev->dev; 491 int ret; 492 unsigned long dummy; 493 int i; 494 495 for (i = 0; i < IMG_PER_TYPE_MAX; i++) { 496 fw = NULL; 497 ret = request_partial_firmware_into_buf(&fw, 498 entry->image_name[i], 499 dev, &dummy, 500 sizeof(dummy), 501 0); 502 release_firmware(fw); 503 if (!ret) 504 return entry->image_name[i]; 505 } 506 return NULL; 507 } 508 509 int bcm_vk_auto_load_all_images(struct bcm_vk *vk) 510 { 511 int i, ret = -1; 512 enum soc_idx idx; 513 struct device *dev = &vk->pdev->dev; 514 u32 curr_type; 515 const char *curr_name; 516 517 idx = get_soc_idx(vk); 518 if (idx == VK_IDX_INVALID) 519 goto auto_load_all_exit; 520 521 /* log a message to know the relative loading order */ 522 dev_dbg(dev, "Load All for device %d\n", vk->devid); 523 524 for (i = 0; i < NUM_BOOT_STAGES; i++) { 525 curr_type = image_tab[idx][i].image_type; 526 if (bcm_vk_next_boot_image(vk) == curr_type) { 527 curr_name = get_load_fw_name(vk, &image_tab[idx][i]); 528 if (!curr_name) { 529 dev_err(dev, "No suitable firmware exists for type %d", 530 curr_type); 531 ret = -ENOENT; 532 goto auto_load_all_exit; 533 } 534 ret = bcm_vk_load_image_by_type(vk, curr_type, 535 curr_name); 536 dev_info(dev, "Auto load %s, ret %d\n", 537 curr_name, ret); 538 539 if (ret) { 540 dev_err(dev, "Error loading default %s\n", 541 curr_name); 542 goto auto_load_all_exit; 543 } 544 } 545 } 546 547 auto_load_all_exit: 548 return ret; 549 } 550 551 static int bcm_vk_trigger_autoload(struct bcm_vk *vk) 552 { 553 if (test_and_set_bit(BCM_VK_WQ_DWNLD_PEND, vk->wq_offload) != 0) 554 return -EPERM; 555 556 set_bit(BCM_VK_WQ_DWNLD_AUTO, vk->wq_offload); 557 queue_work(vk->wq_thread, &vk->wq_work); 558 559 return 0; 560 } 561 562 /* 563 * deferred work queue for auto download. 564 */ 565 static void bcm_vk_wq_handler(struct work_struct *work) 566 { 567 struct bcm_vk *vk = container_of(work, struct bcm_vk, wq_work); 568 569 if (test_bit(BCM_VK_WQ_DWNLD_AUTO, vk->wq_offload)) { 570 bcm_vk_auto_load_all_images(vk); 571 572 /* 573 * at the end of operation, clear AUTO bit and pending 574 * bit 575 */ 576 clear_bit(BCM_VK_WQ_DWNLD_AUTO, vk->wq_offload); 577 clear_bit(BCM_VK_WQ_DWNLD_PEND, vk->wq_offload); 578 } 579 } 580 581 static void bcm_to_v_reset_doorbell(struct bcm_vk *vk, u32 db_val) 582 { 583 vkwrite32(vk, db_val, BAR_0, VK_BAR0_RESET_DB_BASE); 584 } 585 586 static int bcm_vk_trigger_reset(struct bcm_vk *vk) 587 { 588 u32 i; 589 u32 value, boot_status; 590 static const u32 bar0_reg_clr_list[] = { BAR_OS_UPTIME, 591 BAR_INTF_VER, 592 BAR_CARD_VOLTAGE, 593 BAR_CARD_TEMPERATURE, 594 BAR_CARD_PWR_AND_THRE }; 595 596 /* make tag '\0' terminated */ 597 vkwrite32(vk, 0, BAR_1, VK_BAR1_BOOT1_VER_TAG); 598 599 for (i = 0; i < VK_BAR1_DAUTH_MAX; i++) { 600 vkwrite32(vk, 0, BAR_1, VK_BAR1_DAUTH_STORE_ADDR(i)); 601 vkwrite32(vk, 0, BAR_1, VK_BAR1_DAUTH_VALID_ADDR(i)); 602 } 603 for (i = 0; i < VK_BAR1_SOTP_REVID_MAX; i++) 604 vkwrite32(vk, 0, BAR_1, VK_BAR1_SOTP_REVID_ADDR(i)); 605 606 /* 607 * When boot request fails, the CODE_PUSH_OFFSET stays persistent. 608 * Allowing us to debug the failure. When we call reset, 609 * we should clear CODE_PUSH_OFFSET so ROM does not execute 610 * boot again (and fails again) and instead waits for a new 611 * codepush. And, if previous boot has encountered error, need 612 * to clear the entry values 613 */ 614 boot_status = vkread32(vk, BAR_0, BAR_BOOT_STATUS); 615 if (boot_status & BOOT_ERR_MASK) { 616 dev_info(&vk->pdev->dev, 617 "Card in boot error 0x%x, clear CODEPUSH val\n", 618 boot_status); 619 value = 0; 620 } else { 621 value = vkread32(vk, BAR_0, BAR_CODEPUSH_SBL); 622 value &= CODEPUSH_MASK; 623 } 624 vkwrite32(vk, value, BAR_0, BAR_CODEPUSH_SBL); 625 626 /* reset fw_status with proper reason, and press db */ 627 vkwrite32(vk, VK_FWSTS_RESET_MBOX_DB, BAR_0, VK_BAR_FWSTS); 628 bcm_to_v_reset_doorbell(vk, VK_BAR0_RESET_DB_SOFT); 629 630 /* clear other necessary registers records */ 631 for (i = 0; i < ARRAY_SIZE(bar0_reg_clr_list); i++) 632 vkwrite32(vk, 0, BAR_0, bar0_reg_clr_list[i]); 633 634 return 0; 635 } 636 637 static int bcm_vk_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 638 { 639 int err; 640 int i; 641 int id; 642 int irq; 643 char name[20]; 644 struct bcm_vk *vk; 645 struct device *dev = &pdev->dev; 646 u32 boot_status; 647 648 vk = kzalloc(sizeof(*vk), GFP_KERNEL); 649 if (!vk) 650 return -ENOMEM; 651 652 err = pci_enable_device(pdev); 653 if (err) { 654 dev_err(dev, "Cannot enable PCI device\n"); 655 goto err_free_exit; 656 } 657 vk->pdev = pci_dev_get(pdev); 658 659 err = pci_request_regions(pdev, DRV_MODULE_NAME); 660 if (err) { 661 dev_err(dev, "Cannot obtain PCI resources\n"); 662 goto err_disable_pdev; 663 } 664 665 /* make sure DMA is good */ 666 err = dma_set_mask_and_coherent(&pdev->dev, 667 DMA_BIT_MASK(BCM_VK_DMA_BITS)); 668 if (err) { 669 dev_err(dev, "failed to set DMA mask\n"); 670 goto err_disable_pdev; 671 } 672 673 /* The tdma is a scratch area for some DMA testings. */ 674 if (nr_scratch_pages) { 675 vk->tdma_vaddr = dma_alloc_coherent 676 (dev, 677 nr_scratch_pages * PAGE_SIZE, 678 &vk->tdma_addr, GFP_KERNEL); 679 if (!vk->tdma_vaddr) { 680 err = -ENOMEM; 681 goto err_disable_pdev; 682 } 683 } 684 685 pci_set_master(pdev); 686 pci_set_drvdata(pdev, vk); 687 688 irq = pci_alloc_irq_vectors(pdev, 689 1, 690 VK_MSIX_IRQ_MAX, 691 PCI_IRQ_MSI | PCI_IRQ_MSIX); 692 693 if (irq < VK_MSIX_IRQ_MIN_REQ) { 694 dev_err(dev, "failed to get min %d MSIX interrupts, irq(%d)\n", 695 VK_MSIX_IRQ_MIN_REQ, irq); 696 err = (irq >= 0) ? -EINVAL : irq; 697 goto err_disable_pdev; 698 } 699 700 if (irq != VK_MSIX_IRQ_MAX) 701 dev_warn(dev, "Number of IRQs %d allocated - requested(%d).\n", 702 irq, VK_MSIX_IRQ_MAX); 703 704 for (i = 0; i < MAX_BAR; i++) { 705 /* multiple by 2 for 64 bit BAR mapping */ 706 vk->bar[i] = pci_ioremap_bar(pdev, i * 2); 707 if (!vk->bar[i]) { 708 dev_err(dev, "failed to remap BAR%d\n", i); 709 goto err_iounmap; 710 } 711 } 712 713 id = ida_simple_get(&bcm_vk_ida, 0, 0, GFP_KERNEL); 714 if (id < 0) { 715 err = id; 716 dev_err(dev, "unable to get id\n"); 717 goto err_iounmap; 718 } 719 720 vk->devid = id; 721 snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id); 722 723 INIT_WORK(&vk->wq_work, bcm_vk_wq_handler); 724 725 /* create dedicated workqueue */ 726 vk->wq_thread = create_singlethread_workqueue(name); 727 if (!vk->wq_thread) { 728 dev_err(dev, "Fail to create workqueue thread\n"); 729 err = -ENOMEM; 730 goto err_ida_remove; 731 } 732 733 /* sync other info */ 734 bcm_vk_sync_card_info(vk); 735 736 /* 737 * lets trigger an auto download. We don't want to do it serially here 738 * because at probing time, it is not supposed to block for a long time. 739 */ 740 boot_status = vkread32(vk, BAR_0, BAR_BOOT_STATUS); 741 if (auto_load) { 742 if ((boot_status & BOOT_STATE_MASK) == BROM_RUNNING) { 743 if (bcm_vk_trigger_autoload(vk)) 744 goto err_destroy_workqueue; 745 } else { 746 dev_err(dev, 747 "Auto-load skipped - BROM not in proper state (0x%x)\n", 748 boot_status); 749 } 750 } 751 752 return 0; 753 754 err_destroy_workqueue: 755 destroy_workqueue(vk->wq_thread); 756 757 err_ida_remove: 758 ida_simple_remove(&bcm_vk_ida, id); 759 760 err_iounmap: 761 for (i = 0; i < MAX_BAR; i++) { 762 if (vk->bar[i]) 763 pci_iounmap(pdev, vk->bar[i]); 764 } 765 pci_release_regions(pdev); 766 767 err_disable_pdev: 768 if (vk->tdma_vaddr) 769 dma_free_coherent(&pdev->dev, nr_scratch_pages * PAGE_SIZE, 770 vk->tdma_vaddr, vk->tdma_addr); 771 772 pci_free_irq_vectors(pdev); 773 pci_disable_device(pdev); 774 pci_dev_put(pdev); 775 776 err_free_exit: 777 kfree(vk); 778 779 return err; 780 } 781 782 static void bcm_vk_remove(struct pci_dev *pdev) 783 { 784 int i; 785 struct bcm_vk *vk = pci_get_drvdata(pdev); 786 787 /* 788 * Trigger a reset to card and wait enough time for UCODE to rerun, 789 * which re-initialize the card into its default state. 790 * This ensures when driver is re-enumerated it will start from 791 * a completely clean state. 792 */ 793 bcm_vk_trigger_reset(vk); 794 usleep_range(BCM_VK_UCODE_BOOT_US, BCM_VK_UCODE_BOOT_MAX_US); 795 796 if (vk->tdma_vaddr) 797 dma_free_coherent(&pdev->dev, nr_scratch_pages * PAGE_SIZE, 798 vk->tdma_vaddr, vk->tdma_addr); 799 800 cancel_work_sync(&vk->wq_work); 801 destroy_workqueue(vk->wq_thread); 802 803 for (i = 0; i < MAX_BAR; i++) { 804 if (vk->bar[i]) 805 pci_iounmap(pdev, vk->bar[i]); 806 } 807 808 pci_release_regions(pdev); 809 pci_free_irq_vectors(pdev); 810 pci_disable_device(pdev); 811 } 812 813 static void bcm_vk_shutdown(struct pci_dev *pdev) 814 { 815 struct bcm_vk *vk = pci_get_drvdata(pdev); 816 u32 reg, boot_stat; 817 818 reg = vkread32(vk, BAR_0, BAR_BOOT_STATUS); 819 boot_stat = reg & BOOT_STATE_MASK; 820 821 if (boot_stat == BOOT1_RUNNING) { 822 /* simply trigger a reset interrupt to park it */ 823 bcm_vk_trigger_reset(vk); 824 } else if (boot_stat == BROM_NOT_RUN) { 825 int err; 826 u16 lnksta; 827 828 /* 829 * The boot status only reflects boot condition since last reset 830 * As ucode will run only once to configure pcie, if multiple 831 * resets happen, we lost track if ucode has run or not. 832 * Here, read the current link speed and use that to 833 * sync up the bootstatus properly so that on reboot-back-up, 834 * it has the proper state to start with autoload 835 */ 836 err = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnksta); 837 if (!err && 838 (lnksta & PCI_EXP_LNKSTA_CLS) != PCI_EXP_LNKSTA_CLS_2_5GB) { 839 reg |= BROM_STATUS_COMPLETE; 840 vkwrite32(vk, reg, BAR_0, BAR_BOOT_STATUS); 841 } 842 } 843 } 844 845 static const struct pci_device_id bcm_vk_ids[] = { 846 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_VALKYRIE), }, 847 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_VIPER), }, 848 { } 849 }; 850 MODULE_DEVICE_TABLE(pci, bcm_vk_ids); 851 852 static struct pci_driver pci_driver = { 853 .name = DRV_MODULE_NAME, 854 .id_table = bcm_vk_ids, 855 .probe = bcm_vk_probe, 856 .remove = bcm_vk_remove, 857 .shutdown = bcm_vk_shutdown, 858 }; 859 module_pci_driver(pci_driver); 860 861 MODULE_DESCRIPTION("Broadcom VK Host Driver"); 862 MODULE_AUTHOR("Scott Branden <scott.branden@broadcom.com>"); 863 MODULE_LICENSE("GPL v2"); 864 MODULE_VERSION("1.0"); 865