11d9f9f04SMark Brown /* 21d9f9f04SMark Brown * Core driver for WM8400. 31d9f9f04SMark Brown * 41d9f9f04SMark Brown * Copyright 2008 Wolfson Microelectronics PLC. 51d9f9f04SMark Brown * 61d9f9f04SMark Brown * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 71d9f9f04SMark Brown * 81d9f9f04SMark Brown * This program is free software; you can redistribute it and/or 91d9f9f04SMark Brown * modify it under the terms of the GNU General Public License as 101d9f9f04SMark Brown * published by the Free Software Foundation; either version 2 of the 111d9f9f04SMark Brown * License, or (at your option) any later version. 121d9f9f04SMark Brown * 131d9f9f04SMark Brown */ 141d9f9f04SMark Brown 151d9f9f04SMark Brown #include <linux/bug.h> 161d9f9f04SMark Brown #include <linux/i2c.h> 171d9f9f04SMark Brown #include <linux/kernel.h> 18b8380c1aSMark Brown #include <linux/mfd/core.h> 191d9f9f04SMark Brown #include <linux/mfd/wm8400-private.h> 201d9f9f04SMark Brown #include <linux/mfd/wm8400-audio.h> 211d9f9f04SMark Brown 221d9f9f04SMark Brown static struct { 231d9f9f04SMark Brown u16 readable; /* Mask of readable bits */ 241d9f9f04SMark Brown u16 writable; /* Mask of writable bits */ 251d9f9f04SMark Brown u16 vol; /* Mask of volatile bits */ 261d9f9f04SMark Brown int is_codec; /* Register controlled by codec reset */ 271d9f9f04SMark Brown u16 default_val; /* Value on reset */ 281d9f9f04SMark Brown } reg_data[] = { 291d9f9f04SMark Brown { 0xFFFF, 0xFFFF, 0x0000, 0, 0x6172 }, /* R0 */ 301d9f9f04SMark Brown { 0x7000, 0x0000, 0x8000, 0, 0x0000 }, /* R1 */ 311d9f9f04SMark Brown { 0xFF17, 0xFF17, 0x0000, 0, 0x0000 }, /* R2 */ 321d9f9f04SMark Brown { 0xEBF3, 0xEBF3, 0x0000, 1, 0x6000 }, /* R3 */ 331d9f9f04SMark Brown { 0x3CF3, 0x3CF3, 0x0000, 1, 0x0000 }, /* R4 */ 341d9f9f04SMark Brown { 0xF1F8, 0xF1F8, 0x0000, 1, 0x4050 }, /* R5 */ 351d9f9f04SMark Brown { 0xFC1F, 0xFC1F, 0x0000, 1, 0x4000 }, /* R6 */ 361d9f9f04SMark Brown { 0xDFDE, 0xDFDE, 0x0000, 1, 0x01C8 }, /* R7 */ 371d9f9f04SMark Brown { 0xFCFC, 0xFCFC, 0x0000, 1, 0x0000 }, /* R8 */ 381d9f9f04SMark Brown { 0xEFFF, 0xEFFF, 0x0000, 1, 0x0040 }, /* R9 */ 391d9f9f04SMark Brown { 0xEFFF, 0xEFFF, 0x0000, 1, 0x0040 }, /* R10 */ 401d9f9f04SMark Brown { 0x27F7, 0x27F7, 0x0000, 1, 0x0004 }, /* R11 */ 411d9f9f04SMark Brown { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R12 */ 421d9f9f04SMark Brown { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R13 */ 431d9f9f04SMark Brown { 0x1FEF, 0x1FEF, 0x0000, 1, 0x0000 }, /* R14 */ 441d9f9f04SMark Brown { 0x0163, 0x0163, 0x0000, 1, 0x0100 }, /* R15 */ 451d9f9f04SMark Brown { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R16 */ 461d9f9f04SMark Brown { 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R17 */ 471d9f9f04SMark Brown { 0x1FFF, 0x0FFF, 0x0000, 1, 0x0000 }, /* R18 */ 481d9f9f04SMark Brown { 0xFFFF, 0xFFFF, 0x0000, 1, 0x1000 }, /* R19 */ 491d9f9f04SMark Brown { 0xFFFF, 0xFFFF, 0x0000, 1, 0x1010 }, /* R20 */ 501d9f9f04SMark Brown { 0xFFFF, 0xFFFF, 0x0000, 1, 0x1010 }, /* R21 */ 511d9f9f04SMark Brown { 0x0FDD, 0x0FDD, 0x0000, 1, 0x8000 }, /* R22 */ 521d9f9f04SMark Brown { 0x1FFF, 0x1FFF, 0x0000, 1, 0x0800 }, /* R23 */ 531d9f9f04SMark Brown { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R24 */ 541d9f9f04SMark Brown { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R25 */ 551d9f9f04SMark Brown { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R26 */ 561d9f9f04SMark Brown { 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R27 */ 571d9f9f04SMark Brown { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R28 */ 581d9f9f04SMark Brown { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R29 */ 591d9f9f04SMark Brown { 0x0000, 0x0077, 0x0000, 1, 0x0066 }, /* R30 */ 601d9f9f04SMark Brown { 0x0000, 0x0033, 0x0000, 1, 0x0022 }, /* R31 */ 611d9f9f04SMark Brown { 0x0000, 0x01FF, 0x0000, 1, 0x0079 }, /* R32 */ 621d9f9f04SMark Brown { 0x0000, 0x01FF, 0x0000, 1, 0x0079 }, /* R33 */ 631d9f9f04SMark Brown { 0x0000, 0x0003, 0x0000, 1, 0x0003 }, /* R34 */ 641d9f9f04SMark Brown { 0x0000, 0x01FF, 0x0000, 1, 0x0003 }, /* R35 */ 651d9f9f04SMark Brown { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R36 */ 661d9f9f04SMark Brown { 0x0000, 0x003F, 0x0000, 1, 0x0100 }, /* R37 */ 671d9f9f04SMark Brown { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R38 */ 681d9f9f04SMark Brown { 0x0000, 0x000F, 0x0000, 0, 0x0000 }, /* R39 */ 691d9f9f04SMark Brown { 0x0000, 0x00FF, 0x0000, 1, 0x0000 }, /* R40 */ 701d9f9f04SMark Brown { 0x0000, 0x01B7, 0x0000, 1, 0x0000 }, /* R41 */ 711d9f9f04SMark Brown { 0x0000, 0x01B7, 0x0000, 1, 0x0000 }, /* R42 */ 721d9f9f04SMark Brown { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R43 */ 731d9f9f04SMark Brown { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R44 */ 741d9f9f04SMark Brown { 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R45 */ 751d9f9f04SMark Brown { 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R46 */ 761d9f9f04SMark Brown { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R47 */ 771d9f9f04SMark Brown { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R48 */ 781d9f9f04SMark Brown { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R49 */ 791d9f9f04SMark Brown { 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R50 */ 801d9f9f04SMark Brown { 0x0000, 0x01B3, 0x0000, 1, 0x0180 }, /* R51 */ 811d9f9f04SMark Brown { 0x0000, 0x0077, 0x0000, 1, 0x0000 }, /* R52 */ 821d9f9f04SMark Brown { 0x0000, 0x0077, 0x0000, 1, 0x0000 }, /* R53 */ 831d9f9f04SMark Brown { 0x0000, 0x00FF, 0x0000, 1, 0x0000 }, /* R54 */ 841d9f9f04SMark Brown { 0x0000, 0x0001, 0x0000, 1, 0x0000 }, /* R55 */ 851d9f9f04SMark Brown { 0x0000, 0x003F, 0x0000, 1, 0x0000 }, /* R56 */ 861d9f9f04SMark Brown { 0x0000, 0x004F, 0x0000, 1, 0x0000 }, /* R57 */ 871d9f9f04SMark Brown { 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R58 */ 881d9f9f04SMark Brown { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R59 */ 891d9f9f04SMark Brown { 0x1FFF, 0x1FFF, 0x0000, 1, 0x0000 }, /* R60 */ 901d9f9f04SMark Brown { 0xFFFF, 0xFFFF, 0x0000, 1, 0x0000 }, /* R61 */ 911d9f9f04SMark Brown { 0x03FF, 0x03FF, 0x0000, 1, 0x0000 }, /* R62 */ 921d9f9f04SMark Brown { 0x007F, 0x007F, 0x0000, 1, 0x0000 }, /* R63 */ 931d9f9f04SMark Brown { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R64 */ 941d9f9f04SMark Brown { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R65 */ 951d9f9f04SMark Brown { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R66 */ 961d9f9f04SMark Brown { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R67 */ 971d9f9f04SMark Brown { 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R68 */ 981d9f9f04SMark Brown { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R69 */ 991d9f9f04SMark Brown { 0xFFFF, 0xFFFF, 0x0000, 0, 0x4400 }, /* R70 */ 1001d9f9f04SMark Brown { 0x23FF, 0x23FF, 0x0000, 0, 0x0000 }, /* R71 */ 1011d9f9f04SMark Brown { 0xFFFF, 0xFFFF, 0x0000, 0, 0x4400 }, /* R72 */ 1021d9f9f04SMark Brown { 0x23FF, 0x23FF, 0x0000, 0, 0x0000 }, /* R73 */ 1031d9f9f04SMark Brown { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R74 */ 1041d9f9f04SMark Brown { 0x000E, 0x000E, 0x0000, 0, 0x0008 }, /* R75 */ 1051d9f9f04SMark Brown { 0xE00F, 0xE00F, 0x0000, 0, 0x0000 }, /* R76 */ 1061d9f9f04SMark Brown { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R77 */ 1071d9f9f04SMark Brown { 0x03C0, 0x03C0, 0x0000, 0, 0x02C0 }, /* R78 */ 1081d9f9f04SMark Brown { 0xFFFF, 0x0000, 0xffff, 0, 0x0000 }, /* R79 */ 1091d9f9f04SMark Brown { 0xFFFF, 0xFFFF, 0x0000, 0, 0x0000 }, /* R80 */ 1101d9f9f04SMark Brown { 0xFFFF, 0x0000, 0xffff, 0, 0x0000 }, /* R81 */ 1111d9f9f04SMark Brown { 0x2BFF, 0x0000, 0xffff, 0, 0x0000 }, /* R82 */ 1121d9f9f04SMark Brown { 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R83 */ 1131d9f9f04SMark Brown { 0x80FF, 0x80FF, 0x0000, 0, 0x00ff }, /* R84 */ 1141d9f9f04SMark Brown }; 1151d9f9f04SMark Brown 1161d9f9f04SMark Brown static int wm8400_read(struct wm8400 *wm8400, u8 reg, int num_regs, u16 *dest) 1171d9f9f04SMark Brown { 1181d9f9f04SMark Brown int i, ret = 0; 1191d9f9f04SMark Brown 1201d9f9f04SMark Brown BUG_ON(reg + num_regs - 1 > ARRAY_SIZE(wm8400->reg_cache)); 1211d9f9f04SMark Brown 1221d9f9f04SMark Brown /* If there are any volatile reads then read back the entire block */ 1231d9f9f04SMark Brown for (i = reg; i < reg + num_regs; i++) 1241d9f9f04SMark Brown if (reg_data[i].vol) { 1251d9f9f04SMark Brown ret = wm8400->read_dev(wm8400->io_data, reg, 1261d9f9f04SMark Brown num_regs, dest); 1271d9f9f04SMark Brown if (ret != 0) 1281d9f9f04SMark Brown return ret; 1291d9f9f04SMark Brown for (i = 0; i < num_regs; i++) 1301d9f9f04SMark Brown dest[i] = be16_to_cpu(dest[i]); 1311d9f9f04SMark Brown 1321d9f9f04SMark Brown return 0; 1331d9f9f04SMark Brown } 1341d9f9f04SMark Brown 1351d9f9f04SMark Brown /* Otherwise use the cache */ 1361d9f9f04SMark Brown memcpy(dest, &wm8400->reg_cache[reg], num_regs * sizeof(u16)); 1371d9f9f04SMark Brown 1381d9f9f04SMark Brown return 0; 1391d9f9f04SMark Brown } 1401d9f9f04SMark Brown 1411d9f9f04SMark Brown static int wm8400_write(struct wm8400 *wm8400, u8 reg, int num_regs, 1421d9f9f04SMark Brown u16 *src) 1431d9f9f04SMark Brown { 1441d9f9f04SMark Brown int ret, i; 1451d9f9f04SMark Brown 1461d9f9f04SMark Brown BUG_ON(reg + num_regs - 1 > ARRAY_SIZE(wm8400->reg_cache)); 1471d9f9f04SMark Brown 1481d9f9f04SMark Brown for (i = 0; i < num_regs; i++) { 1491d9f9f04SMark Brown BUG_ON(!reg_data[reg + i].writable); 1501d9f9f04SMark Brown wm8400->reg_cache[reg + i] = src[i]; 1511d9f9f04SMark Brown src[i] = cpu_to_be16(src[i]); 1521d9f9f04SMark Brown } 1531d9f9f04SMark Brown 1541d9f9f04SMark Brown /* Do the actual I/O */ 1551d9f9f04SMark Brown ret = wm8400->write_dev(wm8400->io_data, reg, num_regs, src); 1561d9f9f04SMark Brown if (ret != 0) 1571d9f9f04SMark Brown return -EIO; 1581d9f9f04SMark Brown 1591d9f9f04SMark Brown return 0; 1601d9f9f04SMark Brown } 1611d9f9f04SMark Brown 1621d9f9f04SMark Brown /** 1631d9f9f04SMark Brown * wm8400_reg_read - Single register read 1641d9f9f04SMark Brown * 1651d9f9f04SMark Brown * @wm8400: Pointer to wm8400 control structure 1661d9f9f04SMark Brown * @reg: Register to read 1671d9f9f04SMark Brown * 1681d9f9f04SMark Brown * @return Read value 1691d9f9f04SMark Brown */ 1701d9f9f04SMark Brown u16 wm8400_reg_read(struct wm8400 *wm8400, u8 reg) 1711d9f9f04SMark Brown { 1721d9f9f04SMark Brown u16 val; 1731d9f9f04SMark Brown 1741d9f9f04SMark Brown mutex_lock(&wm8400->io_lock); 1751d9f9f04SMark Brown 1761d9f9f04SMark Brown wm8400_read(wm8400, reg, 1, &val); 1771d9f9f04SMark Brown 1781d9f9f04SMark Brown mutex_unlock(&wm8400->io_lock); 1791d9f9f04SMark Brown 1801d9f9f04SMark Brown return val; 1811d9f9f04SMark Brown } 1821d9f9f04SMark Brown EXPORT_SYMBOL_GPL(wm8400_reg_read); 1831d9f9f04SMark Brown 1841d9f9f04SMark Brown int wm8400_block_read(struct wm8400 *wm8400, u8 reg, int count, u16 *data) 1851d9f9f04SMark Brown { 1861d9f9f04SMark Brown int ret; 1871d9f9f04SMark Brown 1881d9f9f04SMark Brown mutex_lock(&wm8400->io_lock); 1891d9f9f04SMark Brown 1901d9f9f04SMark Brown ret = wm8400_read(wm8400, reg, count, data); 1911d9f9f04SMark Brown 1921d9f9f04SMark Brown mutex_unlock(&wm8400->io_lock); 1931d9f9f04SMark Brown 1941d9f9f04SMark Brown return ret; 1951d9f9f04SMark Brown } 1961d9f9f04SMark Brown EXPORT_SYMBOL_GPL(wm8400_block_read); 1971d9f9f04SMark Brown 1981d9f9f04SMark Brown /** 1991d9f9f04SMark Brown * wm8400_set_bits - Bitmask write 2001d9f9f04SMark Brown * 2011d9f9f04SMark Brown * @wm8400: Pointer to wm8400 control structure 2021d9f9f04SMark Brown * @reg: Register to access 2031d9f9f04SMark Brown * @mask: Mask of bits to change 2041d9f9f04SMark Brown * @val: Value to set for masked bits 2051d9f9f04SMark Brown */ 2061d9f9f04SMark Brown int wm8400_set_bits(struct wm8400 *wm8400, u8 reg, u16 mask, u16 val) 2071d9f9f04SMark Brown { 2081d9f9f04SMark Brown u16 tmp; 2091d9f9f04SMark Brown int ret; 2101d9f9f04SMark Brown 2111d9f9f04SMark Brown mutex_lock(&wm8400->io_lock); 2121d9f9f04SMark Brown 2131d9f9f04SMark Brown ret = wm8400_read(wm8400, reg, 1, &tmp); 2141d9f9f04SMark Brown tmp = (tmp & ~mask) | val; 2151d9f9f04SMark Brown if (ret == 0) 2161d9f9f04SMark Brown ret = wm8400_write(wm8400, reg, 1, &tmp); 2171d9f9f04SMark Brown 2181d9f9f04SMark Brown mutex_unlock(&wm8400->io_lock); 2191d9f9f04SMark Brown 2201d9f9f04SMark Brown return ret; 2211d9f9f04SMark Brown } 2221d9f9f04SMark Brown EXPORT_SYMBOL_GPL(wm8400_set_bits); 2231d9f9f04SMark Brown 2241d9f9f04SMark Brown /** 2251d9f9f04SMark Brown * wm8400_reset_codec_reg_cache - Reset cached codec registers to 2261d9f9f04SMark Brown * their default values. 2271d9f9f04SMark Brown */ 2281d9f9f04SMark Brown void wm8400_reset_codec_reg_cache(struct wm8400 *wm8400) 2291d9f9f04SMark Brown { 2301d9f9f04SMark Brown int i; 2311d9f9f04SMark Brown 2321d9f9f04SMark Brown mutex_lock(&wm8400->io_lock); 2331d9f9f04SMark Brown 2341d9f9f04SMark Brown /* Reset all codec registers to their initial value */ 2351d9f9f04SMark Brown for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++) 2361d9f9f04SMark Brown if (reg_data[i].is_codec) 2371d9f9f04SMark Brown wm8400->reg_cache[i] = reg_data[i].default_val; 2381d9f9f04SMark Brown 2391d9f9f04SMark Brown mutex_unlock(&wm8400->io_lock); 2401d9f9f04SMark Brown } 2411d9f9f04SMark Brown EXPORT_SYMBOL_GPL(wm8400_reset_codec_reg_cache); 2421d9f9f04SMark Brown 243b8380c1aSMark Brown static int wm8400_register_codec(struct wm8400 *wm8400) 244b8380c1aSMark Brown { 245b8380c1aSMark Brown struct mfd_cell cell = { 246b8380c1aSMark Brown .name = "wm8400-codec", 247b8380c1aSMark Brown .driver_data = wm8400, 248b8380c1aSMark Brown }; 249b8380c1aSMark Brown 250b8380c1aSMark Brown return mfd_add_devices(wm8400->dev, -1, &cell, 1, NULL, 0); 251b8380c1aSMark Brown } 252b8380c1aSMark Brown 2531d9f9f04SMark Brown /* 2541d9f9f04SMark Brown * wm8400_init - Generic initialisation 2551d9f9f04SMark Brown * 2561d9f9f04SMark Brown * The WM8400 can be configured as either an I2C or SPI device. Probe 2571d9f9f04SMark Brown * functions for each bus set up the accessors then call into this to 2581d9f9f04SMark Brown * set up the device itself. 2591d9f9f04SMark Brown */ 2601d9f9f04SMark Brown static int wm8400_init(struct wm8400 *wm8400, 2611d9f9f04SMark Brown struct wm8400_platform_data *pdata) 2621d9f9f04SMark Brown { 2631d9f9f04SMark Brown u16 reg; 2641d9f9f04SMark Brown int ret, i; 2651d9f9f04SMark Brown 2661d9f9f04SMark Brown mutex_init(&wm8400->io_lock); 2671d9f9f04SMark Brown 2681902a9e6SGreg Kroah-Hartman dev_set_drvdata(wm8400->dev, wm8400); 2691d9f9f04SMark Brown 2701d9f9f04SMark Brown /* Check that this is actually a WM8400 */ 2711d9f9f04SMark Brown ret = wm8400->read_dev(wm8400->io_data, WM8400_RESET_ID, 1, ®); 2721d9f9f04SMark Brown if (ret != 0) { 2731d9f9f04SMark Brown dev_err(wm8400->dev, "Chip ID register read failed\n"); 2741d9f9f04SMark Brown return -EIO; 2751d9f9f04SMark Brown } 2761d9f9f04SMark Brown if (be16_to_cpu(reg) != reg_data[WM8400_RESET_ID].default_val) { 2771d9f9f04SMark Brown dev_err(wm8400->dev, "Device is not a WM8400, ID is %x\n", 2781d9f9f04SMark Brown be16_to_cpu(reg)); 2791d9f9f04SMark Brown return -ENODEV; 2801d9f9f04SMark Brown } 2811d9f9f04SMark Brown 2821d9f9f04SMark Brown /* We don't know what state the hardware is in and since this 2831d9f9f04SMark Brown * is a PMIC we can't reset it safely so initialise the register 2841d9f9f04SMark Brown * cache from the hardware. 2851d9f9f04SMark Brown */ 2861d9f9f04SMark Brown ret = wm8400->read_dev(wm8400->io_data, 0, 2871d9f9f04SMark Brown ARRAY_SIZE(wm8400->reg_cache), 2881d9f9f04SMark Brown wm8400->reg_cache); 2891d9f9f04SMark Brown if (ret != 0) { 2901d9f9f04SMark Brown dev_err(wm8400->dev, "Register cache read failed\n"); 2911d9f9f04SMark Brown return -EIO; 2921d9f9f04SMark Brown } 2931d9f9f04SMark Brown for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++) 2941d9f9f04SMark Brown wm8400->reg_cache[i] = be16_to_cpu(wm8400->reg_cache[i]); 2951d9f9f04SMark Brown 2961d9f9f04SMark Brown /* If the codec is in reset use hard coded values */ 2971d9f9f04SMark Brown if (!(wm8400->reg_cache[WM8400_POWER_MANAGEMENT_1] & WM8400_CODEC_ENA)) 2981d9f9f04SMark Brown for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++) 2991d9f9f04SMark Brown if (reg_data[i].is_codec) 3001d9f9f04SMark Brown wm8400->reg_cache[i] = reg_data[i].default_val; 3011d9f9f04SMark Brown 3021d9f9f04SMark Brown ret = wm8400_read(wm8400, WM8400_ID, 1, ®); 3031d9f9f04SMark Brown if (ret != 0) { 3041d9f9f04SMark Brown dev_err(wm8400->dev, "ID register read failed: %d\n", ret); 3051d9f9f04SMark Brown return ret; 3061d9f9f04SMark Brown } 3071d9f9f04SMark Brown reg = (reg & WM8400_CHIP_REV_MASK) >> WM8400_CHIP_REV_SHIFT; 3081d9f9f04SMark Brown dev_info(wm8400->dev, "WM8400 revision %x\n", reg); 3091d9f9f04SMark Brown 310b8380c1aSMark Brown ret = wm8400_register_codec(wm8400); 311b8380c1aSMark Brown if (ret != 0) { 312b8380c1aSMark Brown dev_err(wm8400->dev, "Failed to register codec\n"); 313b8380c1aSMark Brown goto err_children; 314b8380c1aSMark Brown } 315b8380c1aSMark Brown 3161d9f9f04SMark Brown if (pdata && pdata->platform_init) { 3171d9f9f04SMark Brown ret = pdata->platform_init(wm8400->dev); 318b8380c1aSMark Brown if (ret != 0) { 3191d9f9f04SMark Brown dev_err(wm8400->dev, "Platform init failed: %d\n", 3201d9f9f04SMark Brown ret); 321b8380c1aSMark Brown goto err_children; 322b8380c1aSMark Brown } 3231d9f9f04SMark Brown } else 3241d9f9f04SMark Brown dev_warn(wm8400->dev, "No platform initialisation supplied\n"); 3251d9f9f04SMark Brown 326b8380c1aSMark Brown return 0; 327b8380c1aSMark Brown 328b8380c1aSMark Brown err_children: 329b8380c1aSMark Brown mfd_remove_devices(wm8400->dev); 3301d9f9f04SMark Brown return ret; 3311d9f9f04SMark Brown } 3321d9f9f04SMark Brown 3331d9f9f04SMark Brown static void wm8400_release(struct wm8400 *wm8400) 3341d9f9f04SMark Brown { 335b8380c1aSMark Brown mfd_remove_devices(wm8400->dev); 3361d9f9f04SMark Brown } 3371d9f9f04SMark Brown 3381d9f9f04SMark Brown #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 3391d9f9f04SMark Brown static int wm8400_i2c_read(void *io_data, char reg, int count, u16 *dest) 3401d9f9f04SMark Brown { 3411d9f9f04SMark Brown struct i2c_client *i2c = io_data; 3421d9f9f04SMark Brown struct i2c_msg xfer[2]; 3431d9f9f04SMark Brown int ret; 3441d9f9f04SMark Brown 3451d9f9f04SMark Brown /* Write register */ 3461d9f9f04SMark Brown xfer[0].addr = i2c->addr; 3471d9f9f04SMark Brown xfer[0].flags = 0; 3481d9f9f04SMark Brown xfer[0].len = 1; 3491d9f9f04SMark Brown xfer[0].buf = ® 3501d9f9f04SMark Brown 3511d9f9f04SMark Brown /* Read data */ 3521d9f9f04SMark Brown xfer[1].addr = i2c->addr; 3531d9f9f04SMark Brown xfer[1].flags = I2C_M_RD; 3541d9f9f04SMark Brown xfer[1].len = count * sizeof(u16); 3551d9f9f04SMark Brown xfer[1].buf = (u8 *)dest; 3561d9f9f04SMark Brown 3571d9f9f04SMark Brown ret = i2c_transfer(i2c->adapter, xfer, 2); 3581d9f9f04SMark Brown if (ret == 2) 3591d9f9f04SMark Brown ret = 0; 3601d9f9f04SMark Brown else if (ret >= 0) 3611d9f9f04SMark Brown ret = -EIO; 3621d9f9f04SMark Brown 3631d9f9f04SMark Brown return ret; 3641d9f9f04SMark Brown } 3651d9f9f04SMark Brown 3661d9f9f04SMark Brown static int wm8400_i2c_write(void *io_data, char reg, int count, const u16 *src) 3671d9f9f04SMark Brown { 3681d9f9f04SMark Brown struct i2c_client *i2c = io_data; 3691d9f9f04SMark Brown u8 *msg; 3701d9f9f04SMark Brown int ret; 3711d9f9f04SMark Brown 3721d9f9f04SMark Brown /* We add 1 byte for device register - ideally I2C would gather. */ 3731d9f9f04SMark Brown msg = kmalloc((count * sizeof(u16)) + 1, GFP_KERNEL); 3741d9f9f04SMark Brown if (msg == NULL) 3751d9f9f04SMark Brown return -ENOMEM; 3761d9f9f04SMark Brown 3771d9f9f04SMark Brown msg[0] = reg; 3781d9f9f04SMark Brown memcpy(&msg[1], src, count * sizeof(u16)); 3791d9f9f04SMark Brown 3801d9f9f04SMark Brown ret = i2c_master_send(i2c, msg, (count * sizeof(u16)) + 1); 3811d9f9f04SMark Brown 3821d9f9f04SMark Brown if (ret == (count * 2) + 1) 3831d9f9f04SMark Brown ret = 0; 3841d9f9f04SMark Brown else if (ret >= 0) 3851d9f9f04SMark Brown ret = -EIO; 3861d9f9f04SMark Brown 3871d9f9f04SMark Brown kfree(msg); 3881d9f9f04SMark Brown 3891d9f9f04SMark Brown return ret; 3901d9f9f04SMark Brown } 3911d9f9f04SMark Brown 3921d9f9f04SMark Brown static int wm8400_i2c_probe(struct i2c_client *i2c, 3931d9f9f04SMark Brown const struct i2c_device_id *id) 3941d9f9f04SMark Brown { 3951d9f9f04SMark Brown struct wm8400 *wm8400; 3961d9f9f04SMark Brown int ret; 3971d9f9f04SMark Brown 3981d9f9f04SMark Brown wm8400 = kzalloc(sizeof(struct wm8400), GFP_KERNEL); 3991d9f9f04SMark Brown if (wm8400 == NULL) { 4001d9f9f04SMark Brown ret = -ENOMEM; 4011d9f9f04SMark Brown goto err; 4021d9f9f04SMark Brown } 4031d9f9f04SMark Brown 4041d9f9f04SMark Brown wm8400->io_data = i2c; 4051d9f9f04SMark Brown wm8400->read_dev = wm8400_i2c_read; 4061d9f9f04SMark Brown wm8400->write_dev = wm8400_i2c_write; 4071d9f9f04SMark Brown wm8400->dev = &i2c->dev; 4081d9f9f04SMark Brown i2c_set_clientdata(i2c, wm8400); 4091d9f9f04SMark Brown 4101d9f9f04SMark Brown ret = wm8400_init(wm8400, i2c->dev.platform_data); 4111d9f9f04SMark Brown if (ret != 0) 4121d9f9f04SMark Brown goto struct_err; 4131d9f9f04SMark Brown 4141d9f9f04SMark Brown return 0; 4151d9f9f04SMark Brown 4161d9f9f04SMark Brown struct_err: 4171d9f9f04SMark Brown i2c_set_clientdata(i2c, NULL); 4181d9f9f04SMark Brown kfree(wm8400); 4191d9f9f04SMark Brown err: 4201d9f9f04SMark Brown return ret; 4211d9f9f04SMark Brown } 4221d9f9f04SMark Brown 4231d9f9f04SMark Brown static int wm8400_i2c_remove(struct i2c_client *i2c) 4241d9f9f04SMark Brown { 4251d9f9f04SMark Brown struct wm8400 *wm8400 = i2c_get_clientdata(i2c); 4261d9f9f04SMark Brown 4271d9f9f04SMark Brown wm8400_release(wm8400); 4281d9f9f04SMark Brown i2c_set_clientdata(i2c, NULL); 4291d9f9f04SMark Brown kfree(wm8400); 4301d9f9f04SMark Brown 4311d9f9f04SMark Brown return 0; 4321d9f9f04SMark Brown } 4331d9f9f04SMark Brown 4341d9f9f04SMark Brown static const struct i2c_device_id wm8400_i2c_id[] = { 4351d9f9f04SMark Brown { "wm8400", 0 }, 4361d9f9f04SMark Brown { } 4371d9f9f04SMark Brown }; 4381d9f9f04SMark Brown MODULE_DEVICE_TABLE(i2c, wm8400_i2c_id); 4391d9f9f04SMark Brown 4401d9f9f04SMark Brown static struct i2c_driver wm8400_i2c_driver = { 4411d9f9f04SMark Brown .driver = { 4421d9f9f04SMark Brown .name = "WM8400", 4431d9f9f04SMark Brown .owner = THIS_MODULE, 4441d9f9f04SMark Brown }, 4451d9f9f04SMark Brown .probe = wm8400_i2c_probe, 4461d9f9f04SMark Brown .remove = wm8400_i2c_remove, 4471d9f9f04SMark Brown .id_table = wm8400_i2c_id, 4481d9f9f04SMark Brown }; 4491d9f9f04SMark Brown #endif 4501d9f9f04SMark Brown 4511d9f9f04SMark Brown static int __init wm8400_module_init(void) 4521d9f9f04SMark Brown { 4531d9f9f04SMark Brown int ret = -ENODEV; 4541d9f9f04SMark Brown 4551d9f9f04SMark Brown #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 4561d9f9f04SMark Brown ret = i2c_add_driver(&wm8400_i2c_driver); 4571d9f9f04SMark Brown if (ret != 0) 4581d9f9f04SMark Brown pr_err("Failed to register I2C driver: %d\n", ret); 4591d9f9f04SMark Brown #endif 4601d9f9f04SMark Brown 4611d9f9f04SMark Brown return ret; 4621d9f9f04SMark Brown } 463*2021de87SSamuel Ortiz subsys_initcall(wm8400_module_init); 4641d9f9f04SMark Brown 4651d9f9f04SMark Brown static void __exit wm8400_module_exit(void) 4661d9f9f04SMark Brown { 4671d9f9f04SMark Brown #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) 4681d9f9f04SMark Brown i2c_del_driver(&wm8400_i2c_driver); 4691d9f9f04SMark Brown #endif 4701d9f9f04SMark Brown } 4711d9f9f04SMark Brown module_exit(wm8400_module_exit); 4721d9f9f04SMark Brown 4731d9f9f04SMark Brown MODULE_LICENSE("GPL"); 4741d9f9f04SMark Brown MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 475