xref: /linux/drivers/mfd/wm8400-core.c (revision 1d9f9f040035da73d6ee5d2b3b3a25483a980da3)
1*1d9f9f04SMark Brown /*
2*1d9f9f04SMark Brown  * Core driver for WM8400.
3*1d9f9f04SMark Brown  *
4*1d9f9f04SMark Brown  * Copyright 2008 Wolfson Microelectronics PLC.
5*1d9f9f04SMark Brown  *
6*1d9f9f04SMark Brown  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7*1d9f9f04SMark Brown  *
8*1d9f9f04SMark Brown  * This program is free software; you can redistribute it and/or
9*1d9f9f04SMark Brown  * modify it under the terms of the GNU General Public License as
10*1d9f9f04SMark Brown  * published by the Free Software Foundation; either version 2 of the
11*1d9f9f04SMark Brown  * License, or (at your option) any later version.
12*1d9f9f04SMark Brown  *
13*1d9f9f04SMark Brown  */
14*1d9f9f04SMark Brown 
15*1d9f9f04SMark Brown #include <linux/bug.h>
16*1d9f9f04SMark Brown #include <linux/i2c.h>
17*1d9f9f04SMark Brown #include <linux/kernel.h>
18*1d9f9f04SMark Brown #include <linux/mfd/wm8400-private.h>
19*1d9f9f04SMark Brown #include <linux/mfd/wm8400-audio.h>
20*1d9f9f04SMark Brown 
21*1d9f9f04SMark Brown static struct {
22*1d9f9f04SMark Brown 	u16  readable;    /* Mask of readable bits */
23*1d9f9f04SMark Brown 	u16  writable;    /* Mask of writable bits */
24*1d9f9f04SMark Brown 	u16  vol;         /* Mask of volatile bits */
25*1d9f9f04SMark Brown 	int  is_codec;    /* Register controlled by codec reset */
26*1d9f9f04SMark Brown 	u16  default_val; /* Value on reset */
27*1d9f9f04SMark Brown } reg_data[] = {
28*1d9f9f04SMark Brown 	{ 0xFFFF, 0xFFFF, 0x0000, 0, 0x6172 }, /* R0 */
29*1d9f9f04SMark Brown 	{ 0x7000, 0x0000, 0x8000, 0, 0x0000 }, /* R1 */
30*1d9f9f04SMark Brown 	{ 0xFF17, 0xFF17, 0x0000, 0, 0x0000 }, /* R2 */
31*1d9f9f04SMark Brown 	{ 0xEBF3, 0xEBF3, 0x0000, 1, 0x6000 }, /* R3 */
32*1d9f9f04SMark Brown 	{ 0x3CF3, 0x3CF3, 0x0000, 1, 0x0000 }, /* R4  */
33*1d9f9f04SMark Brown 	{ 0xF1F8, 0xF1F8, 0x0000, 1, 0x4050 }, /* R5  */
34*1d9f9f04SMark Brown 	{ 0xFC1F, 0xFC1F, 0x0000, 1, 0x4000 }, /* R6  */
35*1d9f9f04SMark Brown 	{ 0xDFDE, 0xDFDE, 0x0000, 1, 0x01C8 }, /* R7  */
36*1d9f9f04SMark Brown 	{ 0xFCFC, 0xFCFC, 0x0000, 1, 0x0000 }, /* R8  */
37*1d9f9f04SMark Brown 	{ 0xEFFF, 0xEFFF, 0x0000, 1, 0x0040 }, /* R9  */
38*1d9f9f04SMark Brown 	{ 0xEFFF, 0xEFFF, 0x0000, 1, 0x0040 }, /* R10 */
39*1d9f9f04SMark Brown 	{ 0x27F7, 0x27F7, 0x0000, 1, 0x0004 }, /* R11 */
40*1d9f9f04SMark Brown 	{ 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R12 */
41*1d9f9f04SMark Brown 	{ 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R13 */
42*1d9f9f04SMark Brown 	{ 0x1FEF, 0x1FEF, 0x0000, 1, 0x0000 }, /* R14 */
43*1d9f9f04SMark Brown 	{ 0x0163, 0x0163, 0x0000, 1, 0x0100 }, /* R15 */
44*1d9f9f04SMark Brown 	{ 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R16 */
45*1d9f9f04SMark Brown 	{ 0x01FF, 0x01FF, 0x0000, 1, 0x00C0 }, /* R17 */
46*1d9f9f04SMark Brown 	{ 0x1FFF, 0x0FFF, 0x0000, 1, 0x0000 }, /* R18 */
47*1d9f9f04SMark Brown 	{ 0xFFFF, 0xFFFF, 0x0000, 1, 0x1000 }, /* R19 */
48*1d9f9f04SMark Brown 	{ 0xFFFF, 0xFFFF, 0x0000, 1, 0x1010 }, /* R20 */
49*1d9f9f04SMark Brown 	{ 0xFFFF, 0xFFFF, 0x0000, 1, 0x1010 }, /* R21 */
50*1d9f9f04SMark Brown 	{ 0x0FDD, 0x0FDD, 0x0000, 1, 0x8000 }, /* R22 */
51*1d9f9f04SMark Brown 	{ 0x1FFF, 0x1FFF, 0x0000, 1, 0x0800 }, /* R23 */
52*1d9f9f04SMark Brown 	{ 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R24 */
53*1d9f9f04SMark Brown 	{ 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R25 */
54*1d9f9f04SMark Brown 	{ 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R26 */
55*1d9f9f04SMark Brown 	{ 0x0000, 0x01DF, 0x0000, 1, 0x008B }, /* R27 */
56*1d9f9f04SMark Brown 	{ 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R28 */
57*1d9f9f04SMark Brown 	{ 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R29 */
58*1d9f9f04SMark Brown 	{ 0x0000, 0x0077, 0x0000, 1, 0x0066 }, /* R30 */
59*1d9f9f04SMark Brown 	{ 0x0000, 0x0033, 0x0000, 1, 0x0022 }, /* R31 */
60*1d9f9f04SMark Brown 	{ 0x0000, 0x01FF, 0x0000, 1, 0x0079 }, /* R32 */
61*1d9f9f04SMark Brown 	{ 0x0000, 0x01FF, 0x0000, 1, 0x0079 }, /* R33 */
62*1d9f9f04SMark Brown 	{ 0x0000, 0x0003, 0x0000, 1, 0x0003 }, /* R34 */
63*1d9f9f04SMark Brown 	{ 0x0000, 0x01FF, 0x0000, 1, 0x0003 }, /* R35 */
64*1d9f9f04SMark Brown 	{ 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R36 */
65*1d9f9f04SMark Brown 	{ 0x0000, 0x003F, 0x0000, 1, 0x0100 }, /* R37 */
66*1d9f9f04SMark Brown 	{ 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R38 */
67*1d9f9f04SMark Brown 	{ 0x0000, 0x000F, 0x0000, 0, 0x0000 }, /* R39 */
68*1d9f9f04SMark Brown 	{ 0x0000, 0x00FF, 0x0000, 1, 0x0000 }, /* R40 */
69*1d9f9f04SMark Brown 	{ 0x0000, 0x01B7, 0x0000, 1, 0x0000 }, /* R41 */
70*1d9f9f04SMark Brown 	{ 0x0000, 0x01B7, 0x0000, 1, 0x0000 }, /* R42 */
71*1d9f9f04SMark Brown 	{ 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R43 */
72*1d9f9f04SMark Brown 	{ 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R44 */
73*1d9f9f04SMark Brown 	{ 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R45 */
74*1d9f9f04SMark Brown 	{ 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R46 */
75*1d9f9f04SMark Brown 	{ 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R47 */
76*1d9f9f04SMark Brown 	{ 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R48 */
77*1d9f9f04SMark Brown 	{ 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R49 */
78*1d9f9f04SMark Brown 	{ 0x0000, 0x01FF, 0x0000, 1, 0x0000 }, /* R50 */
79*1d9f9f04SMark Brown 	{ 0x0000, 0x01B3, 0x0000, 1, 0x0180 }, /* R51 */
80*1d9f9f04SMark Brown 	{ 0x0000, 0x0077, 0x0000, 1, 0x0000 }, /* R52 */
81*1d9f9f04SMark Brown 	{ 0x0000, 0x0077, 0x0000, 1, 0x0000 }, /* R53 */
82*1d9f9f04SMark Brown 	{ 0x0000, 0x00FF, 0x0000, 1, 0x0000 }, /* R54 */
83*1d9f9f04SMark Brown 	{ 0x0000, 0x0001, 0x0000, 1, 0x0000 }, /* R55 */
84*1d9f9f04SMark Brown 	{ 0x0000, 0x003F, 0x0000, 1, 0x0000 }, /* R56 */
85*1d9f9f04SMark Brown 	{ 0x0000, 0x004F, 0x0000, 1, 0x0000 }, /* R57 */
86*1d9f9f04SMark Brown 	{ 0x0000, 0x00FD, 0x0000, 1, 0x0000 }, /* R58 */
87*1d9f9f04SMark Brown 	{ 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R59 */
88*1d9f9f04SMark Brown 	{ 0x1FFF, 0x1FFF, 0x0000, 1, 0x0000 }, /* R60 */
89*1d9f9f04SMark Brown 	{ 0xFFFF, 0xFFFF, 0x0000, 1, 0x0000 }, /* R61 */
90*1d9f9f04SMark Brown 	{ 0x03FF, 0x03FF, 0x0000, 1, 0x0000 }, /* R62 */
91*1d9f9f04SMark Brown 	{ 0x007F, 0x007F, 0x0000, 1, 0x0000 }, /* R63 */
92*1d9f9f04SMark Brown 	{ 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R64 */
93*1d9f9f04SMark Brown 	{ 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R65 */
94*1d9f9f04SMark Brown 	{ 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R66 */
95*1d9f9f04SMark Brown 	{ 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R67 */
96*1d9f9f04SMark Brown 	{ 0xDFFF, 0xDFFF, 0x0000, 0, 0x0000 }, /* R68 */
97*1d9f9f04SMark Brown 	{ 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R69 */
98*1d9f9f04SMark Brown 	{ 0xFFFF, 0xFFFF, 0x0000, 0, 0x4400 }, /* R70 */
99*1d9f9f04SMark Brown 	{ 0x23FF, 0x23FF, 0x0000, 0, 0x0000 }, /* R71 */
100*1d9f9f04SMark Brown 	{ 0xFFFF, 0xFFFF, 0x0000, 0, 0x4400 }, /* R72 */
101*1d9f9f04SMark Brown 	{ 0x23FF, 0x23FF, 0x0000, 0, 0x0000 }, /* R73 */
102*1d9f9f04SMark Brown 	{ 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R74 */
103*1d9f9f04SMark Brown 	{ 0x000E, 0x000E, 0x0000, 0, 0x0008 }, /* R75 */
104*1d9f9f04SMark Brown 	{ 0xE00F, 0xE00F, 0x0000, 0, 0x0000 }, /* R76 */
105*1d9f9f04SMark Brown 	{ 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R77 */
106*1d9f9f04SMark Brown 	{ 0x03C0, 0x03C0, 0x0000, 0, 0x02C0 }, /* R78 */
107*1d9f9f04SMark Brown 	{ 0xFFFF, 0x0000, 0xffff, 0, 0x0000 }, /* R79 */
108*1d9f9f04SMark Brown 	{ 0xFFFF, 0xFFFF, 0x0000, 0, 0x0000 }, /* R80 */
109*1d9f9f04SMark Brown 	{ 0xFFFF, 0x0000, 0xffff, 0, 0x0000 }, /* R81 */
110*1d9f9f04SMark Brown 	{ 0x2BFF, 0x0000, 0xffff, 0, 0x0000 }, /* R82 */
111*1d9f9f04SMark Brown 	{ 0x0000, 0x0000, 0x0000, 0, 0x0000 }, /* R83 */
112*1d9f9f04SMark Brown 	{ 0x80FF, 0x80FF, 0x0000, 0, 0x00ff }, /* R84 */
113*1d9f9f04SMark Brown };
114*1d9f9f04SMark Brown 
115*1d9f9f04SMark Brown static int wm8400_read(struct wm8400 *wm8400, u8 reg, int num_regs, u16 *dest)
116*1d9f9f04SMark Brown {
117*1d9f9f04SMark Brown 	int i, ret = 0;
118*1d9f9f04SMark Brown 
119*1d9f9f04SMark Brown 	BUG_ON(reg + num_regs - 1 > ARRAY_SIZE(wm8400->reg_cache));
120*1d9f9f04SMark Brown 
121*1d9f9f04SMark Brown 	/* If there are any volatile reads then read back the entire block */
122*1d9f9f04SMark Brown 	for (i = reg; i < reg + num_regs; i++)
123*1d9f9f04SMark Brown 		if (reg_data[i].vol) {
124*1d9f9f04SMark Brown 			ret = wm8400->read_dev(wm8400->io_data, reg,
125*1d9f9f04SMark Brown 					       num_regs, dest);
126*1d9f9f04SMark Brown 			if (ret != 0)
127*1d9f9f04SMark Brown 				return ret;
128*1d9f9f04SMark Brown 			for (i = 0; i < num_regs; i++)
129*1d9f9f04SMark Brown 				dest[i] = be16_to_cpu(dest[i]);
130*1d9f9f04SMark Brown 
131*1d9f9f04SMark Brown 			return 0;
132*1d9f9f04SMark Brown 		}
133*1d9f9f04SMark Brown 
134*1d9f9f04SMark Brown 	/* Otherwise use the cache */
135*1d9f9f04SMark Brown 	memcpy(dest, &wm8400->reg_cache[reg], num_regs * sizeof(u16));
136*1d9f9f04SMark Brown 
137*1d9f9f04SMark Brown 	return 0;
138*1d9f9f04SMark Brown }
139*1d9f9f04SMark Brown 
140*1d9f9f04SMark Brown static int wm8400_write(struct wm8400 *wm8400, u8 reg, int num_regs,
141*1d9f9f04SMark Brown 			u16 *src)
142*1d9f9f04SMark Brown {
143*1d9f9f04SMark Brown 	int ret, i;
144*1d9f9f04SMark Brown 
145*1d9f9f04SMark Brown 	BUG_ON(reg + num_regs - 1 > ARRAY_SIZE(wm8400->reg_cache));
146*1d9f9f04SMark Brown 
147*1d9f9f04SMark Brown 	for (i = 0; i < num_regs; i++) {
148*1d9f9f04SMark Brown 		BUG_ON(!reg_data[reg + i].writable);
149*1d9f9f04SMark Brown 		wm8400->reg_cache[reg + i] = src[i];
150*1d9f9f04SMark Brown 		src[i] = cpu_to_be16(src[i]);
151*1d9f9f04SMark Brown 	}
152*1d9f9f04SMark Brown 
153*1d9f9f04SMark Brown 	/* Do the actual I/O */
154*1d9f9f04SMark Brown 	ret = wm8400->write_dev(wm8400->io_data, reg, num_regs, src);
155*1d9f9f04SMark Brown 	if (ret != 0)
156*1d9f9f04SMark Brown 		return -EIO;
157*1d9f9f04SMark Brown 
158*1d9f9f04SMark Brown 	return 0;
159*1d9f9f04SMark Brown }
160*1d9f9f04SMark Brown 
161*1d9f9f04SMark Brown /**
162*1d9f9f04SMark Brown  * wm8400_reg_read - Single register read
163*1d9f9f04SMark Brown  *
164*1d9f9f04SMark Brown  * @wm8400: Pointer to wm8400 control structure
165*1d9f9f04SMark Brown  * @reg:    Register to read
166*1d9f9f04SMark Brown  *
167*1d9f9f04SMark Brown  * @return  Read value
168*1d9f9f04SMark Brown  */
169*1d9f9f04SMark Brown u16 wm8400_reg_read(struct wm8400 *wm8400, u8 reg)
170*1d9f9f04SMark Brown {
171*1d9f9f04SMark Brown 	u16 val;
172*1d9f9f04SMark Brown 
173*1d9f9f04SMark Brown 	mutex_lock(&wm8400->io_lock);
174*1d9f9f04SMark Brown 
175*1d9f9f04SMark Brown 	wm8400_read(wm8400, reg, 1, &val);
176*1d9f9f04SMark Brown 
177*1d9f9f04SMark Brown 	mutex_unlock(&wm8400->io_lock);
178*1d9f9f04SMark Brown 
179*1d9f9f04SMark Brown 	return val;
180*1d9f9f04SMark Brown }
181*1d9f9f04SMark Brown EXPORT_SYMBOL_GPL(wm8400_reg_read);
182*1d9f9f04SMark Brown 
183*1d9f9f04SMark Brown int wm8400_block_read(struct wm8400 *wm8400, u8 reg, int count, u16 *data)
184*1d9f9f04SMark Brown {
185*1d9f9f04SMark Brown 	int ret;
186*1d9f9f04SMark Brown 
187*1d9f9f04SMark Brown 	mutex_lock(&wm8400->io_lock);
188*1d9f9f04SMark Brown 
189*1d9f9f04SMark Brown 	ret = wm8400_read(wm8400, reg, count, data);
190*1d9f9f04SMark Brown 
191*1d9f9f04SMark Brown 	mutex_unlock(&wm8400->io_lock);
192*1d9f9f04SMark Brown 
193*1d9f9f04SMark Brown 	return ret;
194*1d9f9f04SMark Brown }
195*1d9f9f04SMark Brown EXPORT_SYMBOL_GPL(wm8400_block_read);
196*1d9f9f04SMark Brown 
197*1d9f9f04SMark Brown /**
198*1d9f9f04SMark Brown  * wm8400_set_bits - Bitmask write
199*1d9f9f04SMark Brown  *
200*1d9f9f04SMark Brown  * @wm8400: Pointer to wm8400 control structure
201*1d9f9f04SMark Brown  * @reg:    Register to access
202*1d9f9f04SMark Brown  * @mask:   Mask of bits to change
203*1d9f9f04SMark Brown  * @val:    Value to set for masked bits
204*1d9f9f04SMark Brown  */
205*1d9f9f04SMark Brown int wm8400_set_bits(struct wm8400 *wm8400, u8 reg, u16 mask, u16 val)
206*1d9f9f04SMark Brown {
207*1d9f9f04SMark Brown 	u16 tmp;
208*1d9f9f04SMark Brown 	int ret;
209*1d9f9f04SMark Brown 
210*1d9f9f04SMark Brown 	mutex_lock(&wm8400->io_lock);
211*1d9f9f04SMark Brown 
212*1d9f9f04SMark Brown 	ret = wm8400_read(wm8400, reg, 1, &tmp);
213*1d9f9f04SMark Brown 	tmp = (tmp & ~mask) | val;
214*1d9f9f04SMark Brown 	if (ret == 0)
215*1d9f9f04SMark Brown 		ret = wm8400_write(wm8400, reg, 1, &tmp);
216*1d9f9f04SMark Brown 
217*1d9f9f04SMark Brown 	mutex_unlock(&wm8400->io_lock);
218*1d9f9f04SMark Brown 
219*1d9f9f04SMark Brown 	return ret;
220*1d9f9f04SMark Brown }
221*1d9f9f04SMark Brown EXPORT_SYMBOL_GPL(wm8400_set_bits);
222*1d9f9f04SMark Brown 
223*1d9f9f04SMark Brown /**
224*1d9f9f04SMark Brown  * wm8400_reset_codec_reg_cache - Reset cached codec registers to
225*1d9f9f04SMark Brown  * their default values.
226*1d9f9f04SMark Brown  */
227*1d9f9f04SMark Brown void wm8400_reset_codec_reg_cache(struct wm8400 *wm8400)
228*1d9f9f04SMark Brown {
229*1d9f9f04SMark Brown 	int i;
230*1d9f9f04SMark Brown 
231*1d9f9f04SMark Brown 	mutex_lock(&wm8400->io_lock);
232*1d9f9f04SMark Brown 
233*1d9f9f04SMark Brown 	/* Reset all codec registers to their initial value */
234*1d9f9f04SMark Brown 	for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
235*1d9f9f04SMark Brown 		if (reg_data[i].is_codec)
236*1d9f9f04SMark Brown 			wm8400->reg_cache[i] = reg_data[i].default_val;
237*1d9f9f04SMark Brown 
238*1d9f9f04SMark Brown 	mutex_unlock(&wm8400->io_lock);
239*1d9f9f04SMark Brown }
240*1d9f9f04SMark Brown EXPORT_SYMBOL_GPL(wm8400_reset_codec_reg_cache);
241*1d9f9f04SMark Brown 
242*1d9f9f04SMark Brown /*
243*1d9f9f04SMark Brown  * wm8400_init - Generic initialisation
244*1d9f9f04SMark Brown  *
245*1d9f9f04SMark Brown  * The WM8400 can be configured as either an I2C or SPI device.  Probe
246*1d9f9f04SMark Brown  * functions for each bus set up the accessors then call into this to
247*1d9f9f04SMark Brown  * set up the device itself.
248*1d9f9f04SMark Brown  */
249*1d9f9f04SMark Brown static int wm8400_init(struct wm8400 *wm8400,
250*1d9f9f04SMark Brown 		       struct wm8400_platform_data *pdata)
251*1d9f9f04SMark Brown {
252*1d9f9f04SMark Brown 	u16 reg;
253*1d9f9f04SMark Brown 	int ret, i;
254*1d9f9f04SMark Brown 
255*1d9f9f04SMark Brown 	mutex_init(&wm8400->io_lock);
256*1d9f9f04SMark Brown 
257*1d9f9f04SMark Brown 	wm8400->dev->driver_data = wm8400;
258*1d9f9f04SMark Brown 
259*1d9f9f04SMark Brown 	/* Check that this is actually a WM8400 */
260*1d9f9f04SMark Brown 	ret = wm8400->read_dev(wm8400->io_data, WM8400_RESET_ID, 1, &reg);
261*1d9f9f04SMark Brown 	if (ret != 0) {
262*1d9f9f04SMark Brown 		dev_err(wm8400->dev, "Chip ID register read failed\n");
263*1d9f9f04SMark Brown 		return -EIO;
264*1d9f9f04SMark Brown 	}
265*1d9f9f04SMark Brown 	if (be16_to_cpu(reg) != reg_data[WM8400_RESET_ID].default_val) {
266*1d9f9f04SMark Brown 		dev_err(wm8400->dev, "Device is not a WM8400, ID is %x\n",
267*1d9f9f04SMark Brown 			be16_to_cpu(reg));
268*1d9f9f04SMark Brown 		return -ENODEV;
269*1d9f9f04SMark Brown 	}
270*1d9f9f04SMark Brown 
271*1d9f9f04SMark Brown 	/* We don't know what state the hardware is in and since this
272*1d9f9f04SMark Brown 	 * is a PMIC we can't reset it safely so initialise the register
273*1d9f9f04SMark Brown 	 * cache from the hardware.
274*1d9f9f04SMark Brown 	 */
275*1d9f9f04SMark Brown 	ret = wm8400->read_dev(wm8400->io_data, 0,
276*1d9f9f04SMark Brown 			       ARRAY_SIZE(wm8400->reg_cache),
277*1d9f9f04SMark Brown 			       wm8400->reg_cache);
278*1d9f9f04SMark Brown 	if (ret != 0) {
279*1d9f9f04SMark Brown 		dev_err(wm8400->dev, "Register cache read failed\n");
280*1d9f9f04SMark Brown 		return -EIO;
281*1d9f9f04SMark Brown 	}
282*1d9f9f04SMark Brown 	for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
283*1d9f9f04SMark Brown 		wm8400->reg_cache[i] = be16_to_cpu(wm8400->reg_cache[i]);
284*1d9f9f04SMark Brown 
285*1d9f9f04SMark Brown 	/* If the codec is in reset use hard coded values */
286*1d9f9f04SMark Brown 	if (!(wm8400->reg_cache[WM8400_POWER_MANAGEMENT_1] & WM8400_CODEC_ENA))
287*1d9f9f04SMark Brown 		for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++)
288*1d9f9f04SMark Brown 			if (reg_data[i].is_codec)
289*1d9f9f04SMark Brown 				wm8400->reg_cache[i] = reg_data[i].default_val;
290*1d9f9f04SMark Brown 
291*1d9f9f04SMark Brown 	ret = wm8400_read(wm8400, WM8400_ID, 1, &reg);
292*1d9f9f04SMark Brown 	if (ret != 0) {
293*1d9f9f04SMark Brown 		dev_err(wm8400->dev, "ID register read failed: %d\n", ret);
294*1d9f9f04SMark Brown 		return ret;
295*1d9f9f04SMark Brown 	}
296*1d9f9f04SMark Brown 	reg = (reg & WM8400_CHIP_REV_MASK) >> WM8400_CHIP_REV_SHIFT;
297*1d9f9f04SMark Brown 	dev_info(wm8400->dev, "WM8400 revision %x\n", reg);
298*1d9f9f04SMark Brown 
299*1d9f9f04SMark Brown 	if (pdata && pdata->platform_init) {
300*1d9f9f04SMark Brown 		ret = pdata->platform_init(wm8400->dev);
301*1d9f9f04SMark Brown 		if (ret != 0)
302*1d9f9f04SMark Brown 			dev_err(wm8400->dev, "Platform init failed: %d\n",
303*1d9f9f04SMark Brown 				ret);
304*1d9f9f04SMark Brown 	} else
305*1d9f9f04SMark Brown 		dev_warn(wm8400->dev, "No platform initialisation supplied\n");
306*1d9f9f04SMark Brown 
307*1d9f9f04SMark Brown 	return ret;
308*1d9f9f04SMark Brown }
309*1d9f9f04SMark Brown 
310*1d9f9f04SMark Brown static void wm8400_release(struct wm8400 *wm8400)
311*1d9f9f04SMark Brown {
312*1d9f9f04SMark Brown 	int i;
313*1d9f9f04SMark Brown 
314*1d9f9f04SMark Brown 	for (i = 0; i < ARRAY_SIZE(wm8400->regulators); i++)
315*1d9f9f04SMark Brown 		if (wm8400->regulators[i].name)
316*1d9f9f04SMark Brown 			platform_device_unregister(&wm8400->regulators[i]);
317*1d9f9f04SMark Brown }
318*1d9f9f04SMark Brown 
319*1d9f9f04SMark Brown #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
320*1d9f9f04SMark Brown static int wm8400_i2c_read(void *io_data, char reg, int count, u16 *dest)
321*1d9f9f04SMark Brown {
322*1d9f9f04SMark Brown 	struct i2c_client *i2c = io_data;
323*1d9f9f04SMark Brown 	struct i2c_msg xfer[2];
324*1d9f9f04SMark Brown 	int ret;
325*1d9f9f04SMark Brown 
326*1d9f9f04SMark Brown 	/* Write register */
327*1d9f9f04SMark Brown 	xfer[0].addr = i2c->addr;
328*1d9f9f04SMark Brown 	xfer[0].flags = 0;
329*1d9f9f04SMark Brown 	xfer[0].len = 1;
330*1d9f9f04SMark Brown 	xfer[0].buf = &reg;
331*1d9f9f04SMark Brown 
332*1d9f9f04SMark Brown 	/* Read data */
333*1d9f9f04SMark Brown 	xfer[1].addr = i2c->addr;
334*1d9f9f04SMark Brown 	xfer[1].flags = I2C_M_RD;
335*1d9f9f04SMark Brown 	xfer[1].len = count * sizeof(u16);
336*1d9f9f04SMark Brown 	xfer[1].buf = (u8 *)dest;
337*1d9f9f04SMark Brown 
338*1d9f9f04SMark Brown 	ret = i2c_transfer(i2c->adapter, xfer, 2);
339*1d9f9f04SMark Brown 	if (ret == 2)
340*1d9f9f04SMark Brown 		ret = 0;
341*1d9f9f04SMark Brown 	else if (ret >= 0)
342*1d9f9f04SMark Brown 		ret = -EIO;
343*1d9f9f04SMark Brown 
344*1d9f9f04SMark Brown 	return ret;
345*1d9f9f04SMark Brown }
346*1d9f9f04SMark Brown 
347*1d9f9f04SMark Brown static int wm8400_i2c_write(void *io_data, char reg, int count, const u16 *src)
348*1d9f9f04SMark Brown {
349*1d9f9f04SMark Brown 	struct i2c_client *i2c = io_data;
350*1d9f9f04SMark Brown 	u8 *msg;
351*1d9f9f04SMark Brown 	int ret;
352*1d9f9f04SMark Brown 
353*1d9f9f04SMark Brown 	/* We add 1 byte for device register - ideally I2C would gather. */
354*1d9f9f04SMark Brown 	msg = kmalloc((count * sizeof(u16)) + 1, GFP_KERNEL);
355*1d9f9f04SMark Brown 	if (msg == NULL)
356*1d9f9f04SMark Brown 		return -ENOMEM;
357*1d9f9f04SMark Brown 
358*1d9f9f04SMark Brown 	msg[0] = reg;
359*1d9f9f04SMark Brown 	memcpy(&msg[1], src, count * sizeof(u16));
360*1d9f9f04SMark Brown 
361*1d9f9f04SMark Brown 	ret = i2c_master_send(i2c, msg, (count * sizeof(u16)) + 1);
362*1d9f9f04SMark Brown 
363*1d9f9f04SMark Brown 	if (ret == (count * 2) + 1)
364*1d9f9f04SMark Brown 		ret = 0;
365*1d9f9f04SMark Brown 	else if (ret >= 0)
366*1d9f9f04SMark Brown 		ret = -EIO;
367*1d9f9f04SMark Brown 
368*1d9f9f04SMark Brown 	kfree(msg);
369*1d9f9f04SMark Brown 
370*1d9f9f04SMark Brown 	return ret;
371*1d9f9f04SMark Brown }
372*1d9f9f04SMark Brown 
373*1d9f9f04SMark Brown static int wm8400_i2c_probe(struct i2c_client *i2c,
374*1d9f9f04SMark Brown 			    const struct i2c_device_id *id)
375*1d9f9f04SMark Brown {
376*1d9f9f04SMark Brown 	struct wm8400 *wm8400;
377*1d9f9f04SMark Brown 	int ret;
378*1d9f9f04SMark Brown 
379*1d9f9f04SMark Brown 	wm8400 = kzalloc(sizeof(struct wm8400), GFP_KERNEL);
380*1d9f9f04SMark Brown 	if (wm8400 == NULL) {
381*1d9f9f04SMark Brown 		ret = -ENOMEM;
382*1d9f9f04SMark Brown 		goto err;
383*1d9f9f04SMark Brown 	}
384*1d9f9f04SMark Brown 
385*1d9f9f04SMark Brown 	wm8400->io_data = i2c;
386*1d9f9f04SMark Brown 	wm8400->read_dev = wm8400_i2c_read;
387*1d9f9f04SMark Brown 	wm8400->write_dev = wm8400_i2c_write;
388*1d9f9f04SMark Brown 	wm8400->dev = &i2c->dev;
389*1d9f9f04SMark Brown 	i2c_set_clientdata(i2c, wm8400);
390*1d9f9f04SMark Brown 
391*1d9f9f04SMark Brown 	ret = wm8400_init(wm8400, i2c->dev.platform_data);
392*1d9f9f04SMark Brown 	if (ret != 0)
393*1d9f9f04SMark Brown 		goto struct_err;
394*1d9f9f04SMark Brown 
395*1d9f9f04SMark Brown 	return 0;
396*1d9f9f04SMark Brown 
397*1d9f9f04SMark Brown struct_err:
398*1d9f9f04SMark Brown 	i2c_set_clientdata(i2c, NULL);
399*1d9f9f04SMark Brown 	kfree(wm8400);
400*1d9f9f04SMark Brown err:
401*1d9f9f04SMark Brown 	return ret;
402*1d9f9f04SMark Brown }
403*1d9f9f04SMark Brown 
404*1d9f9f04SMark Brown static int wm8400_i2c_remove(struct i2c_client *i2c)
405*1d9f9f04SMark Brown {
406*1d9f9f04SMark Brown 	struct wm8400 *wm8400 = i2c_get_clientdata(i2c);
407*1d9f9f04SMark Brown 
408*1d9f9f04SMark Brown 	wm8400_release(wm8400);
409*1d9f9f04SMark Brown 	i2c_set_clientdata(i2c, NULL);
410*1d9f9f04SMark Brown 	kfree(wm8400);
411*1d9f9f04SMark Brown 
412*1d9f9f04SMark Brown 	return 0;
413*1d9f9f04SMark Brown }
414*1d9f9f04SMark Brown 
415*1d9f9f04SMark Brown static const struct i2c_device_id wm8400_i2c_id[] = {
416*1d9f9f04SMark Brown        { "wm8400", 0 },
417*1d9f9f04SMark Brown        { }
418*1d9f9f04SMark Brown };
419*1d9f9f04SMark Brown MODULE_DEVICE_TABLE(i2c, wm8400_i2c_id);
420*1d9f9f04SMark Brown 
421*1d9f9f04SMark Brown static struct i2c_driver wm8400_i2c_driver = {
422*1d9f9f04SMark Brown 	.driver = {
423*1d9f9f04SMark Brown 		.name = "WM8400",
424*1d9f9f04SMark Brown 		.owner = THIS_MODULE,
425*1d9f9f04SMark Brown 	},
426*1d9f9f04SMark Brown 	.probe    = wm8400_i2c_probe,
427*1d9f9f04SMark Brown 	.remove   = wm8400_i2c_remove,
428*1d9f9f04SMark Brown 	.id_table = wm8400_i2c_id,
429*1d9f9f04SMark Brown };
430*1d9f9f04SMark Brown #endif
431*1d9f9f04SMark Brown 
432*1d9f9f04SMark Brown static int __init wm8400_module_init(void)
433*1d9f9f04SMark Brown {
434*1d9f9f04SMark Brown 	int ret = -ENODEV;
435*1d9f9f04SMark Brown 
436*1d9f9f04SMark Brown #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
437*1d9f9f04SMark Brown 	ret = i2c_add_driver(&wm8400_i2c_driver);
438*1d9f9f04SMark Brown 	if (ret != 0)
439*1d9f9f04SMark Brown 		pr_err("Failed to register I2C driver: %d\n", ret);
440*1d9f9f04SMark Brown #endif
441*1d9f9f04SMark Brown 
442*1d9f9f04SMark Brown 	return ret;
443*1d9f9f04SMark Brown }
444*1d9f9f04SMark Brown module_init(wm8400_module_init);
445*1d9f9f04SMark Brown 
446*1d9f9f04SMark Brown static void __exit wm8400_module_exit(void)
447*1d9f9f04SMark Brown {
448*1d9f9f04SMark Brown #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
449*1d9f9f04SMark Brown 	i2c_del_driver(&wm8400_i2c_driver);
450*1d9f9f04SMark Brown #endif
451*1d9f9f04SMark Brown }
452*1d9f9f04SMark Brown module_exit(wm8400_module_exit);
453*1d9f9f04SMark Brown 
454*1d9f9f04SMark Brown MODULE_LICENSE("GPL");
455*1d9f9f04SMark Brown MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
456