1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/drivers/mfd/ucb1x00-core.c 4 * 5 * Copyright (C) 2001 Russell King, All Rights Reserved. 6 * 7 * The UCB1x00 core driver provides basic services for handling IO, 8 * the ADC, interrupts, and accessing registers. It is designed 9 * such that everything goes through this layer, thereby providing 10 * a consistent locking methodology, as well as allowing the drivers 11 * to be used on other non-MCP-enabled hardware platforms. 12 * 13 * Note that all locks are private to this file. Nothing else may 14 * touch them. 15 */ 16 #include <linux/module.h> 17 #include <linux/kernel.h> 18 #include <linux/sched.h> 19 #include <linux/slab.h> 20 #include <linux/init.h> 21 #include <linux/errno.h> 22 #include <linux/interrupt.h> 23 #include <linux/irq.h> 24 #include <linux/device.h> 25 #include <linux/mutex.h> 26 #include <linux/mfd/ucb1x00.h> 27 #include <linux/pm.h> 28 #include <linux/property.h> 29 #include <linux/gpio/driver.h> 30 31 static DEFINE_MUTEX(ucb1x00_mutex); 32 static LIST_HEAD(ucb1x00_drivers); 33 static LIST_HEAD(ucb1x00_devices); 34 35 /** 36 * ucb1x00_io_set_dir - set IO direction 37 * @ucb: UCB1x00 structure describing chip 38 * @in: bitfield of IO pins to be set as inputs 39 * @out: bitfield of IO pins to be set as outputs 40 * 41 * Set the IO direction of the ten general purpose IO pins on 42 * the UCB1x00 chip. The @in bitfield has priority over the 43 * @out bitfield, in that if you specify a pin as both input 44 * and output, it will end up as an input. 45 * 46 * ucb1x00_enable must have been called to enable the comms 47 * before using this function. 48 * 49 * This function takes a spinlock, disabling interrupts. 50 */ 51 void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int in, unsigned int out) 52 { 53 unsigned long flags; 54 55 spin_lock_irqsave(&ucb->io_lock, flags); 56 ucb->io_dir |= out; 57 ucb->io_dir &= ~in; 58 59 ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); 60 spin_unlock_irqrestore(&ucb->io_lock, flags); 61 } 62 63 /** 64 * ucb1x00_io_write - set or clear IO outputs 65 * @ucb: UCB1x00 structure describing chip 66 * @set: bitfield of IO pins to set to logic '1' 67 * @clear: bitfield of IO pins to set to logic '0' 68 * 69 * Set the IO output state of the specified IO pins. The value 70 * is retained if the pins are subsequently configured as inputs. 71 * The @clear bitfield has priority over the @set bitfield - 72 * outputs will be cleared. 73 * 74 * ucb1x00_enable must have been called to enable the comms 75 * before using this function. 76 * 77 * This function takes a spinlock, disabling interrupts. 78 */ 79 void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int set, unsigned int clear) 80 { 81 unsigned long flags; 82 83 spin_lock_irqsave(&ucb->io_lock, flags); 84 ucb->io_out |= set; 85 ucb->io_out &= ~clear; 86 87 ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); 88 spin_unlock_irqrestore(&ucb->io_lock, flags); 89 } 90 91 /** 92 * ucb1x00_io_read - read the current state of the IO pins 93 * @ucb: UCB1x00 structure describing chip 94 * 95 * Return a bitfield describing the logic state of the ten 96 * general purpose IO pins. 97 * 98 * ucb1x00_enable must have been called to enable the comms 99 * before using this function. 100 * 101 * This function does not take any mutexes or spinlocks. 102 */ 103 unsigned int ucb1x00_io_read(struct ucb1x00 *ucb) 104 { 105 return ucb1x00_reg_read(ucb, UCB_IO_DATA); 106 } 107 108 static int ucb1x00_gpio_set(struct gpio_chip *chip, unsigned int offset, 109 int value) 110 { 111 struct ucb1x00 *ucb = gpiochip_get_data(chip); 112 unsigned long flags; 113 114 spin_lock_irqsave(&ucb->io_lock, flags); 115 if (value) 116 ucb->io_out |= 1 << offset; 117 else 118 ucb->io_out &= ~(1 << offset); 119 120 ucb1x00_enable(ucb); 121 ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); 122 ucb1x00_disable(ucb); 123 spin_unlock_irqrestore(&ucb->io_lock, flags); 124 125 return 0; 126 } 127 128 static int ucb1x00_gpio_get(struct gpio_chip *chip, unsigned offset) 129 { 130 struct ucb1x00 *ucb = gpiochip_get_data(chip); 131 unsigned val; 132 133 ucb1x00_enable(ucb); 134 val = ucb1x00_reg_read(ucb, UCB_IO_DATA); 135 ucb1x00_disable(ucb); 136 137 return !!(val & (1 << offset)); 138 } 139 140 static int ucb1x00_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 141 { 142 struct ucb1x00 *ucb = gpiochip_get_data(chip); 143 unsigned long flags; 144 145 spin_lock_irqsave(&ucb->io_lock, flags); 146 ucb->io_dir &= ~(1 << offset); 147 ucb1x00_enable(ucb); 148 ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); 149 ucb1x00_disable(ucb); 150 spin_unlock_irqrestore(&ucb->io_lock, flags); 151 152 return 0; 153 } 154 155 static int ucb1x00_gpio_direction_output(struct gpio_chip *chip, unsigned offset 156 , int value) 157 { 158 struct ucb1x00 *ucb = gpiochip_get_data(chip); 159 unsigned long flags; 160 unsigned old, mask = 1 << offset; 161 162 spin_lock_irqsave(&ucb->io_lock, flags); 163 old = ucb->io_out; 164 if (value) 165 ucb->io_out |= mask; 166 else 167 ucb->io_out &= ~mask; 168 169 ucb1x00_enable(ucb); 170 if (old != ucb->io_out) 171 ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); 172 173 if (!(ucb->io_dir & mask)) { 174 ucb->io_dir |= mask; 175 ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); 176 } 177 ucb1x00_disable(ucb); 178 spin_unlock_irqrestore(&ucb->io_lock, flags); 179 180 return 0; 181 } 182 183 static int ucb1x00_to_irq(struct gpio_chip *chip, unsigned offset) 184 { 185 struct ucb1x00 *ucb = gpiochip_get_data(chip); 186 187 return ucb->irq_base > 0 ? ucb->irq_base + offset : -ENXIO; 188 } 189 190 /* 191 * UCB1300 data sheet says we must: 192 * 1. enable ADC => 5us (including reference startup time) 193 * 2. select input => 51*tsibclk => 4.3us 194 * 3. start conversion => 102*tsibclk => 8.5us 195 * (tsibclk = 1/11981000) 196 * Period between SIB 128-bit frames = 10.7us 197 */ 198 199 /** 200 * ucb1x00_adc_enable - enable the ADC converter 201 * @ucb: UCB1x00 structure describing chip 202 * 203 * Enable the ucb1x00 and ADC converter on the UCB1x00 for use. 204 * Any code wishing to use the ADC converter must call this 205 * function prior to using it. 206 * 207 * This function takes the ADC mutex to prevent two or more 208 * concurrent uses, and therefore may sleep. As a result, it 209 * can only be called from process context, not interrupt 210 * context. 211 * 212 * You should release the ADC as soon as possible using 213 * ucb1x00_adc_disable. 214 */ 215 void ucb1x00_adc_enable(struct ucb1x00 *ucb) 216 { 217 mutex_lock(&ucb->adc_mutex); 218 219 ucb->adc_cr |= UCB_ADC_ENA; 220 221 ucb1x00_enable(ucb); 222 ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr); 223 } 224 225 /** 226 * ucb1x00_adc_read - read the specified ADC channel 227 * @ucb: UCB1x00 structure describing chip 228 * @adc_channel: ADC channel mask 229 * @sync: wait for syncronisation pulse. 230 * 231 * Start an ADC conversion and wait for the result. Note that 232 * synchronised ADC conversions (via the ADCSYNC pin) must wait 233 * until the trigger is asserted and the conversion is finished. 234 * 235 * This function currently spins waiting for the conversion to 236 * complete (2 frames max without sync). 237 * 238 * If called for a synchronised ADC conversion, it may sleep 239 * with the ADC mutex held. 240 */ 241 unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync) 242 { 243 unsigned int val; 244 245 if (sync) 246 adc_channel |= UCB_ADC_SYNC_ENA; 247 248 ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel); 249 ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr | adc_channel | UCB_ADC_START); 250 251 for (;;) { 252 val = ucb1x00_reg_read(ucb, UCB_ADC_DATA); 253 if (val & UCB_ADC_DAT_VAL) 254 break; 255 /* yield to other processes */ 256 set_current_state(TASK_INTERRUPTIBLE); 257 schedule_timeout(1); 258 } 259 260 return UCB_ADC_DAT(val); 261 } 262 263 /** 264 * ucb1x00_adc_disable - disable the ADC converter 265 * @ucb: UCB1x00 structure describing chip 266 * 267 * Disable the ADC converter and release the ADC mutex. 268 */ 269 void ucb1x00_adc_disable(struct ucb1x00 *ucb) 270 { 271 ucb->adc_cr &= ~UCB_ADC_ENA; 272 ucb1x00_reg_write(ucb, UCB_ADC_CR, ucb->adc_cr); 273 ucb1x00_disable(ucb); 274 275 mutex_unlock(&ucb->adc_mutex); 276 } 277 278 /* 279 * UCB1x00 Interrupt handling. 280 * 281 * The UCB1x00 can generate interrupts when the SIBCLK is stopped. 282 * Since we need to read an internal register, we must re-enable 283 * SIBCLK to talk to the chip. We leave the clock running until 284 * we have finished processing all interrupts from the chip. 285 */ 286 static void ucb1x00_irq(struct irq_desc *desc) 287 { 288 struct ucb1x00 *ucb = irq_desc_get_handler_data(desc); 289 unsigned int isr, i; 290 291 ucb1x00_enable(ucb); 292 isr = ucb1x00_reg_read(ucb, UCB_IE_STATUS); 293 ucb1x00_reg_write(ucb, UCB_IE_CLEAR, isr); 294 ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); 295 296 for (i = 0; i < 16 && isr; i++, isr >>= 1) 297 if (isr & 1) 298 generic_handle_irq(ucb->irq_base + i); 299 ucb1x00_disable(ucb); 300 } 301 302 static void ucb1x00_irq_update(struct ucb1x00 *ucb, unsigned mask) 303 { 304 ucb1x00_enable(ucb); 305 if (ucb->irq_ris_enbl & mask) 306 ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl & 307 ucb->irq_mask); 308 if (ucb->irq_fal_enbl & mask) 309 ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl & 310 ucb->irq_mask); 311 ucb1x00_disable(ucb); 312 } 313 314 static void ucb1x00_irq_noop(struct irq_data *data) 315 { 316 } 317 318 static void ucb1x00_irq_mask(struct irq_data *data) 319 { 320 struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data); 321 unsigned mask = 1 << (data->irq - ucb->irq_base); 322 323 raw_spin_lock(&ucb->irq_lock); 324 ucb->irq_mask &= ~mask; 325 ucb1x00_irq_update(ucb, mask); 326 raw_spin_unlock(&ucb->irq_lock); 327 } 328 329 static void ucb1x00_irq_unmask(struct irq_data *data) 330 { 331 struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data); 332 unsigned mask = 1 << (data->irq - ucb->irq_base); 333 334 raw_spin_lock(&ucb->irq_lock); 335 ucb->irq_mask |= mask; 336 ucb1x00_irq_update(ucb, mask); 337 raw_spin_unlock(&ucb->irq_lock); 338 } 339 340 static int ucb1x00_irq_set_type(struct irq_data *data, unsigned int type) 341 { 342 struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data); 343 unsigned mask = 1 << (data->irq - ucb->irq_base); 344 345 raw_spin_lock(&ucb->irq_lock); 346 if (type & IRQ_TYPE_EDGE_RISING) 347 ucb->irq_ris_enbl |= mask; 348 else 349 ucb->irq_ris_enbl &= ~mask; 350 351 if (type & IRQ_TYPE_EDGE_FALLING) 352 ucb->irq_fal_enbl |= mask; 353 else 354 ucb->irq_fal_enbl &= ~mask; 355 if (ucb->irq_mask & mask) { 356 ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl & 357 ucb->irq_mask); 358 ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl & 359 ucb->irq_mask); 360 } 361 raw_spin_unlock(&ucb->irq_lock); 362 363 return 0; 364 } 365 366 static int ucb1x00_irq_set_wake(struct irq_data *data, unsigned int on) 367 { 368 struct ucb1x00 *ucb = irq_data_get_irq_chip_data(data); 369 struct ucb1x00_plat_data *pdata = ucb->mcp->attached_device.platform_data; 370 unsigned mask = 1 << (data->irq - ucb->irq_base); 371 372 if (!pdata || !pdata->can_wakeup) 373 return -EINVAL; 374 375 raw_spin_lock(&ucb->irq_lock); 376 if (on) 377 ucb->irq_wake |= mask; 378 else 379 ucb->irq_wake &= ~mask; 380 raw_spin_unlock(&ucb->irq_lock); 381 382 return 0; 383 } 384 385 static struct irq_chip ucb1x00_irqchip = { 386 .name = "ucb1x00", 387 .irq_ack = ucb1x00_irq_noop, 388 .irq_mask = ucb1x00_irq_mask, 389 .irq_unmask = ucb1x00_irq_unmask, 390 .irq_set_type = ucb1x00_irq_set_type, 391 .irq_set_wake = ucb1x00_irq_set_wake, 392 }; 393 394 static int ucb1x00_add_dev(struct ucb1x00 *ucb, struct ucb1x00_driver *drv) 395 { 396 struct ucb1x00_dev *dev; 397 int ret; 398 399 dev = kmalloc_obj(struct ucb1x00_dev); 400 if (!dev) 401 return -ENOMEM; 402 403 dev->ucb = ucb; 404 dev->drv = drv; 405 406 ret = drv->add(dev); 407 if (ret) { 408 kfree(dev); 409 return ret; 410 } 411 412 list_add_tail(&dev->dev_node, &ucb->devs); 413 list_add_tail(&dev->drv_node, &drv->devs); 414 415 return ret; 416 } 417 418 static void ucb1x00_remove_dev(struct ucb1x00_dev *dev) 419 { 420 dev->drv->remove(dev); 421 list_del(&dev->dev_node); 422 list_del(&dev->drv_node); 423 kfree(dev); 424 } 425 426 /* 427 * Try to probe our interrupt, rather than relying on lots of 428 * hard-coded machine dependencies. For reference, the expected 429 * IRQ mappings are: 430 * 431 * Machine Default IRQ 432 * adsbitsy IRQ_GPCIN4 433 * cerf IRQ_GPIO_UCB1200_IRQ 434 * flexanet IRQ_GPIO_GUI 435 * freebird IRQ_GPIO_FREEBIRD_UCB1300_IRQ 436 * graphicsclient ADS_EXT_IRQ(8) 437 * graphicsmaster ADS_EXT_IRQ(8) 438 * lart LART_IRQ_UCB1200 439 * omnimeter IRQ_GPIO23 440 * pfs168 IRQ_GPIO_UCB1300_IRQ 441 * simpad IRQ_GPIO_UCB1300_IRQ 442 * shannon SHANNON_IRQ_GPIO_IRQ_CODEC 443 * yopy IRQ_GPIO_UCB1200_IRQ 444 */ 445 static int ucb1x00_detect_irq(struct ucb1x00 *ucb) 446 { 447 unsigned long mask; 448 449 mask = probe_irq_on(); 450 451 /* 452 * Enable the ADC interrupt. 453 */ 454 ucb1x00_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC); 455 ucb1x00_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC); 456 ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff); 457 ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); 458 459 /* 460 * Cause an ADC interrupt. 461 */ 462 ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA); 463 ucb1x00_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START); 464 465 /* 466 * Wait for the conversion to complete. 467 */ 468 while ((ucb1x00_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VAL) == 0); 469 ucb1x00_reg_write(ucb, UCB_ADC_CR, 0); 470 471 /* 472 * Disable and clear interrupt. 473 */ 474 ucb1x00_reg_write(ucb, UCB_IE_RIS, 0); 475 ucb1x00_reg_write(ucb, UCB_IE_FAL, 0); 476 ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0xffff); 477 ucb1x00_reg_write(ucb, UCB_IE_CLEAR, 0); 478 479 /* 480 * Read triggered interrupt. 481 */ 482 return probe_irq_off(mask); 483 } 484 485 static void ucb1x00_release(struct device *dev) 486 { 487 struct ucb1x00 *ucb = classdev_to_ucb1x00(dev); 488 kfree(ucb); 489 } 490 491 static struct class ucb1x00_class = { 492 .name = "ucb1x00", 493 .dev_release = ucb1x00_release, 494 }; 495 496 const struct software_node ucb1x00_gpiochip_node = { 497 .name = "ucb1x00-gpio", 498 }; 499 EXPORT_SYMBOL_GPL(ucb1x00_gpiochip_node); 500 501 static int ucb1x00_probe(struct mcp *mcp) 502 { 503 struct ucb1x00_plat_data *pdata = mcp->attached_device.platform_data; 504 struct ucb1x00_driver *drv; 505 struct ucb1x00 *ucb; 506 unsigned id, i, irq_base; 507 int ret = -ENODEV; 508 509 /* Tell the platform to deassert the UCB1x00 reset */ 510 if (pdata && pdata->reset) 511 pdata->reset(UCB_RST_PROBE); 512 513 mcp_enable(mcp); 514 id = mcp_reg_read(mcp, UCB_ID); 515 mcp_disable(mcp); 516 517 if (id != UCB_ID_1200 && id != UCB_ID_1300 && id != UCB_ID_TC35143) { 518 printk(KERN_WARNING "UCB1x00 ID not found: %04x\n", id); 519 goto out; 520 } 521 522 ucb = kzalloc_obj(struct ucb1x00); 523 ret = -ENOMEM; 524 if (!ucb) 525 goto out; 526 527 device_initialize(&ucb->dev); 528 ucb->dev.class = &ucb1x00_class; 529 ucb->dev.parent = &mcp->attached_device; 530 dev_set_name(&ucb->dev, "ucb1x00"); 531 532 raw_spin_lock_init(&ucb->irq_lock); 533 spin_lock_init(&ucb->io_lock); 534 mutex_init(&ucb->adc_mutex); 535 536 ucb->id = id; 537 ucb->mcp = mcp; 538 539 ret = device_add_software_node(&ucb->dev, &ucb1x00_gpiochip_node); 540 if (ret) 541 goto err_swnode_add; 542 543 ret = device_add(&ucb->dev); 544 if (ret) 545 goto err_dev_add; 546 547 ucb1x00_enable(ucb); 548 ucb->irq = ucb1x00_detect_irq(ucb); 549 ucb1x00_disable(ucb); 550 if (!ucb->irq) { 551 dev_err(&ucb->dev, "IRQ probe failed\n"); 552 ret = -ENODEV; 553 goto err_no_irq; 554 } 555 556 ucb->gpio.base = -1; 557 irq_base = pdata ? pdata->irq_base : 0; 558 ucb->irq_base = irq_alloc_descs(-1, irq_base, 16, -1); 559 if (ucb->irq_base < 0) { 560 dev_err(&ucb->dev, "unable to allocate 16 irqs: %d\n", 561 ucb->irq_base); 562 ret = ucb->irq_base; 563 goto err_irq_alloc; 564 } 565 566 for (i = 0; i < 16; i++) { 567 unsigned irq = ucb->irq_base + i; 568 569 irq_set_chip_and_handler(irq, &ucb1x00_irqchip, handle_edge_irq); 570 irq_set_chip_data(irq, ucb); 571 irq_clear_status_flags(irq, IRQ_NOREQUEST); 572 } 573 574 irq_set_irq_type(ucb->irq, IRQ_TYPE_EDGE_RISING); 575 irq_set_chained_handler_and_data(ucb->irq, ucb1x00_irq, ucb); 576 577 if (pdata && pdata->gpio_base) { 578 ucb->gpio.label = dev_name(&ucb->dev); 579 ucb->gpio.parent = &ucb->dev; 580 ucb->gpio.owner = THIS_MODULE; 581 ucb->gpio.base = pdata->gpio_base; 582 ucb->gpio.ngpio = 10; 583 ucb->gpio.set = ucb1x00_gpio_set; 584 ucb->gpio.get = ucb1x00_gpio_get; 585 ucb->gpio.direction_input = ucb1x00_gpio_direction_input; 586 ucb->gpio.direction_output = ucb1x00_gpio_direction_output; 587 ucb->gpio.to_irq = ucb1x00_to_irq; 588 ret = gpiochip_add_data(&ucb->gpio, ucb); 589 if (ret) 590 goto err_gpio_add; 591 } else 592 dev_info(&ucb->dev, "gpio_base not set so no gpiolib support"); 593 594 mcp_set_drvdata(mcp, ucb); 595 596 if (pdata) 597 device_set_wakeup_capable(&ucb->dev, pdata->can_wakeup); 598 599 INIT_LIST_HEAD(&ucb->devs); 600 mutex_lock(&ucb1x00_mutex); 601 list_add_tail(&ucb->node, &ucb1x00_devices); 602 list_for_each_entry(drv, &ucb1x00_drivers, node) { 603 ucb1x00_add_dev(ucb, drv); 604 } 605 mutex_unlock(&ucb1x00_mutex); 606 607 return ret; 608 609 err_gpio_add: 610 irq_set_chained_handler(ucb->irq, NULL); 611 err_irq_alloc: 612 if (ucb->irq_base > 0) 613 irq_free_descs(ucb->irq_base, 16); 614 err_no_irq: 615 device_del(&ucb->dev); 616 err_dev_add: 617 device_remove_software_node(&ucb->dev); 618 err_swnode_add: 619 put_device(&ucb->dev); 620 out: 621 if (pdata && pdata->reset) 622 pdata->reset(UCB_RST_PROBE_FAIL); 623 return ret; 624 } 625 626 static void ucb1x00_remove(struct mcp *mcp) 627 { 628 struct ucb1x00_plat_data *pdata = mcp->attached_device.platform_data; 629 struct ucb1x00 *ucb = mcp_get_drvdata(mcp); 630 struct list_head *l, *n; 631 632 mutex_lock(&ucb1x00_mutex); 633 list_del(&ucb->node); 634 list_for_each_safe(l, n, &ucb->devs) { 635 struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, dev_node); 636 ucb1x00_remove_dev(dev); 637 } 638 mutex_unlock(&ucb1x00_mutex); 639 640 if (ucb->gpio.base != -1) 641 gpiochip_remove(&ucb->gpio); 642 643 irq_set_chained_handler(ucb->irq, NULL); 644 irq_free_descs(ucb->irq_base, 16); 645 device_del(&ucb->dev); 646 device_remove_software_node(&ucb->dev); 647 put_device(&ucb->dev); 648 649 if (pdata && pdata->reset) 650 pdata->reset(UCB_RST_REMOVE); 651 } 652 653 int ucb1x00_register_driver(struct ucb1x00_driver *drv) 654 { 655 struct ucb1x00 *ucb; 656 657 INIT_LIST_HEAD(&drv->devs); 658 mutex_lock(&ucb1x00_mutex); 659 list_add_tail(&drv->node, &ucb1x00_drivers); 660 list_for_each_entry(ucb, &ucb1x00_devices, node) { 661 ucb1x00_add_dev(ucb, drv); 662 } 663 mutex_unlock(&ucb1x00_mutex); 664 return 0; 665 } 666 667 void ucb1x00_unregister_driver(struct ucb1x00_driver *drv) 668 { 669 struct list_head *n, *l; 670 671 mutex_lock(&ucb1x00_mutex); 672 list_del(&drv->node); 673 list_for_each_safe(l, n, &drv->devs) { 674 struct ucb1x00_dev *dev = list_entry(l, struct ucb1x00_dev, drv_node); 675 ucb1x00_remove_dev(dev); 676 } 677 mutex_unlock(&ucb1x00_mutex); 678 } 679 680 static int ucb1x00_suspend(struct device *dev) 681 { 682 struct ucb1x00_plat_data *pdata = dev_get_platdata(dev); 683 struct ucb1x00 *ucb = dev_get_drvdata(dev); 684 struct ucb1x00_dev *udev; 685 686 mutex_lock(&ucb1x00_mutex); 687 list_for_each_entry(udev, &ucb->devs, dev_node) { 688 if (udev->drv->suspend) 689 udev->drv->suspend(udev); 690 } 691 mutex_unlock(&ucb1x00_mutex); 692 693 if (ucb->irq_wake) { 694 unsigned long flags; 695 696 raw_spin_lock_irqsave(&ucb->irq_lock, flags); 697 ucb1x00_enable(ucb); 698 ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl & 699 ucb->irq_wake); 700 ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl & 701 ucb->irq_wake); 702 ucb1x00_disable(ucb); 703 raw_spin_unlock_irqrestore(&ucb->irq_lock, flags); 704 705 enable_irq_wake(ucb->irq); 706 } else if (pdata && pdata->reset) 707 pdata->reset(UCB_RST_SUSPEND); 708 709 return 0; 710 } 711 712 static int ucb1x00_resume(struct device *dev) 713 { 714 struct ucb1x00_plat_data *pdata = dev_get_platdata(dev); 715 struct ucb1x00 *ucb = dev_get_drvdata(dev); 716 struct ucb1x00_dev *udev; 717 718 if (!ucb->irq_wake && pdata && pdata->reset) 719 pdata->reset(UCB_RST_RESUME); 720 721 ucb1x00_enable(ucb); 722 ucb1x00_reg_write(ucb, UCB_IO_DATA, ucb->io_out); 723 ucb1x00_reg_write(ucb, UCB_IO_DIR, ucb->io_dir); 724 725 if (ucb->irq_wake) { 726 unsigned long flags; 727 728 raw_spin_lock_irqsave(&ucb->irq_lock, flags); 729 ucb1x00_reg_write(ucb, UCB_IE_RIS, ucb->irq_ris_enbl & 730 ucb->irq_mask); 731 ucb1x00_reg_write(ucb, UCB_IE_FAL, ucb->irq_fal_enbl & 732 ucb->irq_mask); 733 raw_spin_unlock_irqrestore(&ucb->irq_lock, flags); 734 735 disable_irq_wake(ucb->irq); 736 } 737 ucb1x00_disable(ucb); 738 739 mutex_lock(&ucb1x00_mutex); 740 list_for_each_entry(udev, &ucb->devs, dev_node) { 741 if (udev->drv->resume) 742 udev->drv->resume(udev); 743 } 744 mutex_unlock(&ucb1x00_mutex); 745 return 0; 746 } 747 748 static DEFINE_SIMPLE_DEV_PM_OPS(ucb1x00_pm_ops, 749 ucb1x00_suspend, ucb1x00_resume); 750 751 static struct mcp_driver ucb1x00_driver = { 752 .drv = { 753 .name = "ucb1x00", 754 .owner = THIS_MODULE, 755 .pm = pm_sleep_ptr(&ucb1x00_pm_ops), 756 }, 757 .probe = ucb1x00_probe, 758 .remove = ucb1x00_remove, 759 }; 760 761 static int __init ucb1x00_init(void) 762 { 763 int ret = class_register(&ucb1x00_class); 764 if (ret == 0) { 765 ret = mcp_driver_register(&ucb1x00_driver); 766 if (ret) 767 class_unregister(&ucb1x00_class); 768 } 769 return ret; 770 } 771 772 static void __exit ucb1x00_exit(void) 773 { 774 mcp_driver_unregister(&ucb1x00_driver); 775 class_unregister(&ucb1x00_class); 776 } 777 778 module_init(ucb1x00_init); 779 module_exit(ucb1x00_exit); 780 781 EXPORT_SYMBOL(ucb1x00_io_set_dir); 782 EXPORT_SYMBOL(ucb1x00_io_write); 783 EXPORT_SYMBOL(ucb1x00_io_read); 784 785 EXPORT_SYMBOL(ucb1x00_adc_enable); 786 EXPORT_SYMBOL(ucb1x00_adc_read); 787 EXPORT_SYMBOL(ucb1x00_adc_disable); 788 789 EXPORT_SYMBOL(ucb1x00_register_driver); 790 EXPORT_SYMBOL(ucb1x00_unregister_driver); 791 792 MODULE_ALIAS("mcp:ucb1x00"); 793 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>"); 794 MODULE_DESCRIPTION("UCB1x00 core driver"); 795 MODULE_LICENSE("GPL"); 796