1a30d46c0SDavid Brownell /* 2a30d46c0SDavid Brownell * twl4030-irq.c - TWL4030/TPS659x0 irq support 3a30d46c0SDavid Brownell * 4a30d46c0SDavid Brownell * Copyright (C) 2005-2006 Texas Instruments, Inc. 5a30d46c0SDavid Brownell * 6a30d46c0SDavid Brownell * Modifications to defer interrupt handling to a kernel thread: 7a30d46c0SDavid Brownell * Copyright (C) 2006 MontaVista Software, Inc. 8a30d46c0SDavid Brownell * 9a30d46c0SDavid Brownell * Based on tlv320aic23.c: 10a30d46c0SDavid Brownell * Copyright (c) by Kai Svahn <kai.svahn@nokia.com> 11a30d46c0SDavid Brownell * 12a30d46c0SDavid Brownell * Code cleanup and modifications to IRQ handler. 13a30d46c0SDavid Brownell * by syed khasim <x0khasim@ti.com> 14a30d46c0SDavid Brownell * 15a30d46c0SDavid Brownell * This program is free software; you can redistribute it and/or modify 16a30d46c0SDavid Brownell * it under the terms of the GNU General Public License as published by 17a30d46c0SDavid Brownell * the Free Software Foundation; either version 2 of the License, or 18a30d46c0SDavid Brownell * (at your option) any later version. 19a30d46c0SDavid Brownell * 20a30d46c0SDavid Brownell * This program is distributed in the hope that it will be useful, 21a30d46c0SDavid Brownell * but WITHOUT ANY WARRANTY; without even the implied warranty of 22a30d46c0SDavid Brownell * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23a30d46c0SDavid Brownell * GNU General Public License for more details. 24a30d46c0SDavid Brownell * 25a30d46c0SDavid Brownell * You should have received a copy of the GNU General Public License 26a30d46c0SDavid Brownell * along with this program; if not, write to the Free Software 27a30d46c0SDavid Brownell * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 28a30d46c0SDavid Brownell */ 29a30d46c0SDavid Brownell 30a30d46c0SDavid Brownell #include <linux/init.h> 31a30d46c0SDavid Brownell #include <linux/interrupt.h> 32a30d46c0SDavid Brownell #include <linux/irq.h> 33a30d46c0SDavid Brownell #include <linux/kthread.h> 34a30d46c0SDavid Brownell 35a30d46c0SDavid Brownell #include <linux/i2c/twl4030.h> 36a30d46c0SDavid Brownell 37a30d46c0SDavid Brownell 38a30d46c0SDavid Brownell /* 39a30d46c0SDavid Brownell * TWL4030 IRQ handling has two stages in hardware, and thus in software. 40a30d46c0SDavid Brownell * The Primary Interrupt Handler (PIH) stage exposes status bits saying 41a30d46c0SDavid Brownell * which Secondary Interrupt Handler (SIH) stage is raising an interrupt. 42a30d46c0SDavid Brownell * SIH modules are more traditional IRQ components, which support per-IRQ 43a30d46c0SDavid Brownell * enable/disable and trigger controls; they do most of the work. 44a30d46c0SDavid Brownell * 45a30d46c0SDavid Brownell * These chips are designed to support IRQ handling from two different 46a30d46c0SDavid Brownell * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status 47a30d46c0SDavid Brownell * and mask registers in the PIH and SIH modules. 48a30d46c0SDavid Brownell * 49a30d46c0SDavid Brownell * We set up IRQs starting at a platform-specified base, always starting 50a30d46c0SDavid Brownell * with PIH and the SIH for PWR_INT and then usually adding GPIO: 51a30d46c0SDavid Brownell * base + 0 .. base + 7 PIH 52a30d46c0SDavid Brownell * base + 8 .. base + 15 SIH for PWR_INT 53a30d46c0SDavid Brownell * base + 16 .. base + 33 SIH for GPIO 54a30d46c0SDavid Brownell */ 55a30d46c0SDavid Brownell 56a30d46c0SDavid Brownell /* PIH register offsets */ 57a30d46c0SDavid Brownell #define REG_PIH_ISR_P1 0x01 58a30d46c0SDavid Brownell #define REG_PIH_ISR_P2 0x02 59a30d46c0SDavid Brownell #define REG_PIH_SIR 0x03 /* for testing */ 60a30d46c0SDavid Brownell 61a30d46c0SDavid Brownell 62a30d46c0SDavid Brownell /* Linux could (eventually) use either IRQ line */ 63a30d46c0SDavid Brownell static int irq_line; 64a30d46c0SDavid Brownell 65a30d46c0SDavid Brownell struct sih { 66a30d46c0SDavid Brownell char name[8]; 67a30d46c0SDavid Brownell u8 module; /* module id */ 68a30d46c0SDavid Brownell u8 control_offset; /* for SIH_CTRL */ 69a30d46c0SDavid Brownell bool set_cor; 70a30d46c0SDavid Brownell 71a30d46c0SDavid Brownell u8 bits; /* valid in isr/imr */ 72a30d46c0SDavid Brownell u8 bytes_ixr; /* bytelen of ISR/IMR/SIR */ 73a30d46c0SDavid Brownell 74a30d46c0SDavid Brownell u8 edr_offset; 75a30d46c0SDavid Brownell u8 bytes_edr; /* bytelen of EDR */ 76a30d46c0SDavid Brownell 77a30d46c0SDavid Brownell /* SIR ignored -- set interrupt, for testing only */ 78a30d46c0SDavid Brownell struct irq_data { 79a30d46c0SDavid Brownell u8 isr_offset; 80a30d46c0SDavid Brownell u8 imr_offset; 81a30d46c0SDavid Brownell } mask[2]; 82a30d46c0SDavid Brownell /* + 2 bytes padding */ 83a30d46c0SDavid Brownell }; 84a30d46c0SDavid Brownell 85a30d46c0SDavid Brownell #define SIH_INITIALIZER(modname, nbits) \ 86a30d46c0SDavid Brownell .module = TWL4030_MODULE_ ## modname, \ 87a30d46c0SDavid Brownell .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \ 88a30d46c0SDavid Brownell .bits = nbits, \ 89a30d46c0SDavid Brownell .bytes_ixr = DIV_ROUND_UP(nbits, 8), \ 90a30d46c0SDavid Brownell .edr_offset = TWL4030_ ## modname ## _EDR, \ 91a30d46c0SDavid Brownell .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \ 92a30d46c0SDavid Brownell .mask = { { \ 93a30d46c0SDavid Brownell .isr_offset = TWL4030_ ## modname ## _ISR1, \ 94a30d46c0SDavid Brownell .imr_offset = TWL4030_ ## modname ## _IMR1, \ 95a30d46c0SDavid Brownell }, \ 96a30d46c0SDavid Brownell { \ 97a30d46c0SDavid Brownell .isr_offset = TWL4030_ ## modname ## _ISR2, \ 98a30d46c0SDavid Brownell .imr_offset = TWL4030_ ## modname ## _IMR2, \ 99a30d46c0SDavid Brownell }, }, 100a30d46c0SDavid Brownell 101a30d46c0SDavid Brownell /* register naming policies are inconsistent ... */ 102a30d46c0SDavid Brownell #define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1 103a30d46c0SDavid Brownell #define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD 104a30d46c0SDavid Brownell #define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT 105a30d46c0SDavid Brownell 106a30d46c0SDavid Brownell 107a30d46c0SDavid Brownell /* Order in this table matches order in PIH_ISR. That is, 108a30d46c0SDavid Brownell * BIT(n) in PIH_ISR is sih_modules[n]. 109a30d46c0SDavid Brownell */ 110a30d46c0SDavid Brownell static const struct sih sih_modules[6] = { 111a30d46c0SDavid Brownell [0] = { 112a30d46c0SDavid Brownell .name = "gpio", 113a30d46c0SDavid Brownell .module = TWL4030_MODULE_GPIO, 114a30d46c0SDavid Brownell .control_offset = REG_GPIO_SIH_CTRL, 115a30d46c0SDavid Brownell .set_cor = true, 116a30d46c0SDavid Brownell .bits = TWL4030_GPIO_MAX, 117a30d46c0SDavid Brownell .bytes_ixr = 3, 118a30d46c0SDavid Brownell /* Note: *all* of these IRQs default to no-trigger */ 119a30d46c0SDavid Brownell .edr_offset = REG_GPIO_EDR1, 120a30d46c0SDavid Brownell .bytes_edr = 5, 121a30d46c0SDavid Brownell .mask = { { 122a30d46c0SDavid Brownell .isr_offset = REG_GPIO_ISR1A, 123a30d46c0SDavid Brownell .imr_offset = REG_GPIO_IMR1A, 124a30d46c0SDavid Brownell }, { 125a30d46c0SDavid Brownell .isr_offset = REG_GPIO_ISR1B, 126a30d46c0SDavid Brownell .imr_offset = REG_GPIO_IMR1B, 127a30d46c0SDavid Brownell }, }, 128a30d46c0SDavid Brownell }, 129a30d46c0SDavid Brownell [1] = { 130a30d46c0SDavid Brownell .name = "keypad", 131a30d46c0SDavid Brownell .set_cor = true, 132a30d46c0SDavid Brownell SIH_INITIALIZER(KEYPAD_KEYP, 4) 133a30d46c0SDavid Brownell }, 134a30d46c0SDavid Brownell [2] = { 135a30d46c0SDavid Brownell .name = "bci", 136a30d46c0SDavid Brownell .module = TWL4030_MODULE_INTERRUPTS, 137a30d46c0SDavid Brownell .control_offset = TWL4030_INTERRUPTS_BCISIHCTRL, 138a30d46c0SDavid Brownell .bits = 12, 139a30d46c0SDavid Brownell .bytes_ixr = 2, 140a30d46c0SDavid Brownell .edr_offset = TWL4030_INTERRUPTS_BCIEDR1, 141a30d46c0SDavid Brownell /* Note: most of these IRQs default to no-trigger */ 142a30d46c0SDavid Brownell .bytes_edr = 3, 143a30d46c0SDavid Brownell .mask = { { 144a30d46c0SDavid Brownell .isr_offset = TWL4030_INTERRUPTS_BCIISR1A, 145a30d46c0SDavid Brownell .imr_offset = TWL4030_INTERRUPTS_BCIIMR1A, 146a30d46c0SDavid Brownell }, { 147a30d46c0SDavid Brownell .isr_offset = TWL4030_INTERRUPTS_BCIISR1B, 148a30d46c0SDavid Brownell .imr_offset = TWL4030_INTERRUPTS_BCIIMR1B, 149a30d46c0SDavid Brownell }, }, 150a30d46c0SDavid Brownell }, 151a30d46c0SDavid Brownell [3] = { 152a30d46c0SDavid Brownell .name = "madc", 153a30d46c0SDavid Brownell SIH_INITIALIZER(MADC, 4) 154a30d46c0SDavid Brownell }, 155a30d46c0SDavid Brownell [4] = { 156a30d46c0SDavid Brownell /* USB doesn't use the same SIH organization */ 157a30d46c0SDavid Brownell .name = "usb", 158a30d46c0SDavid Brownell }, 159a30d46c0SDavid Brownell [5] = { 160a30d46c0SDavid Brownell .name = "power", 161a30d46c0SDavid Brownell .set_cor = true, 162a30d46c0SDavid Brownell SIH_INITIALIZER(INT_PWR, 8) 163a30d46c0SDavid Brownell }, 164a30d46c0SDavid Brownell /* there are no SIH modules #6 or #7 ... */ 165a30d46c0SDavid Brownell }; 166a30d46c0SDavid Brownell 167a30d46c0SDavid Brownell #undef TWL4030_MODULE_KEYPAD_KEYP 168a30d46c0SDavid Brownell #undef TWL4030_MODULE_INT_PWR 169a30d46c0SDavid Brownell #undef TWL4030_INT_PWR_EDR 170a30d46c0SDavid Brownell 171a30d46c0SDavid Brownell /*----------------------------------------------------------------------*/ 172a30d46c0SDavid Brownell 173a30d46c0SDavid Brownell static unsigned twl4030_irq_base; 174a30d46c0SDavid Brownell 175a30d46c0SDavid Brownell static struct completion irq_event; 176a30d46c0SDavid Brownell 177a30d46c0SDavid Brownell /* 178a30d46c0SDavid Brownell * This thread processes interrupts reported by the Primary Interrupt Handler. 179a30d46c0SDavid Brownell */ 180a30d46c0SDavid Brownell static int twl4030_irq_thread(void *data) 181a30d46c0SDavid Brownell { 182a30d46c0SDavid Brownell long irq = (long)data; 18394964f96SSamuel Ortiz struct irq_desc *desc = irq_to_desc(irq); 184a30d46c0SDavid Brownell static unsigned i2c_errors; 185*3446d4bbSTobias Klauser static const unsigned max_i2c_errors = 100; 186a30d46c0SDavid Brownell 18794964f96SSamuel Ortiz if (!desc) { 18894964f96SSamuel Ortiz pr_err("twl4030: Invalid IRQ: %ld\n", irq); 18994964f96SSamuel Ortiz return -EINVAL; 19094964f96SSamuel Ortiz } 19194964f96SSamuel Ortiz 192a30d46c0SDavid Brownell current->flags |= PF_NOFREEZE; 193a30d46c0SDavid Brownell 194a30d46c0SDavid Brownell while (!kthread_should_stop()) { 195a30d46c0SDavid Brownell int ret; 196a30d46c0SDavid Brownell int module_irq; 197a30d46c0SDavid Brownell u8 pih_isr; 198a30d46c0SDavid Brownell 199a30d46c0SDavid Brownell /* Wait for IRQ, then read PIH irq status (also blocking) */ 200a30d46c0SDavid Brownell wait_for_completion_interruptible(&irq_event); 201a30d46c0SDavid Brownell 202a30d46c0SDavid Brownell ret = twl4030_i2c_read_u8(TWL4030_MODULE_PIH, &pih_isr, 203a30d46c0SDavid Brownell REG_PIH_ISR_P1); 204a30d46c0SDavid Brownell if (ret) { 205a30d46c0SDavid Brownell pr_warning("twl4030: I2C error %d reading PIH ISR\n", 206a30d46c0SDavid Brownell ret); 207a30d46c0SDavid Brownell if (++i2c_errors >= max_i2c_errors) { 208a30d46c0SDavid Brownell printk(KERN_ERR "Maximum I2C error count" 209a30d46c0SDavid Brownell " exceeded. Terminating %s.\n", 210a30d46c0SDavid Brownell __func__); 211a30d46c0SDavid Brownell break; 212a30d46c0SDavid Brownell } 213a30d46c0SDavid Brownell complete(&irq_event); 214a30d46c0SDavid Brownell continue; 215a30d46c0SDavid Brownell } 216a30d46c0SDavid Brownell 217a30d46c0SDavid Brownell /* these handlers deal with the relevant SIH irq status */ 218a30d46c0SDavid Brownell local_irq_disable(); 219a30d46c0SDavid Brownell for (module_irq = twl4030_irq_base; 220a30d46c0SDavid Brownell pih_isr; 221a30d46c0SDavid Brownell pih_isr >>= 1, module_irq++) { 222a30d46c0SDavid Brownell if (pih_isr & 0x1) { 22394964f96SSamuel Ortiz struct irq_desc *d = irq_to_desc(module_irq); 22494964f96SSamuel Ortiz 22594964f96SSamuel Ortiz if (!d) { 22694964f96SSamuel Ortiz pr_err("twl4030: Invalid SIH IRQ: %d\n", 22794964f96SSamuel Ortiz module_irq); 22894964f96SSamuel Ortiz return -EINVAL; 22994964f96SSamuel Ortiz } 230a30d46c0SDavid Brownell 231a30d46c0SDavid Brownell /* These can't be masked ... always warn 232a30d46c0SDavid Brownell * if we get any surprises. 233a30d46c0SDavid Brownell */ 234a30d46c0SDavid Brownell if (d->status & IRQ_DISABLED) 235a30d46c0SDavid Brownell note_interrupt(module_irq, d, 236a30d46c0SDavid Brownell IRQ_NONE); 237a30d46c0SDavid Brownell else 238a30d46c0SDavid Brownell d->handle_irq(module_irq, d); 239a30d46c0SDavid Brownell } 240a30d46c0SDavid Brownell } 241a30d46c0SDavid Brownell local_irq_enable(); 242a30d46c0SDavid Brownell 243a30d46c0SDavid Brownell desc->chip->unmask(irq); 244a30d46c0SDavid Brownell } 245a30d46c0SDavid Brownell 246a30d46c0SDavid Brownell return 0; 247a30d46c0SDavid Brownell } 248a30d46c0SDavid Brownell 249a30d46c0SDavid Brownell /* 250a30d46c0SDavid Brownell * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt. 251a30d46c0SDavid Brownell * This is a chained interrupt, so there is no desc->action method for it. 252a30d46c0SDavid Brownell * Now we need to query the interrupt controller in the twl4030 to determine 253a30d46c0SDavid Brownell * which module is generating the interrupt request. However, we can't do i2c 254a30d46c0SDavid Brownell * transactions in interrupt context, so we must defer that work to a kernel 255a30d46c0SDavid Brownell * thread. All we do here is acknowledge and mask the interrupt and wakeup 256a30d46c0SDavid Brownell * the kernel thread. 257a30d46c0SDavid Brownell */ 258a30d46c0SDavid Brownell static void handle_twl4030_pih(unsigned int irq, irq_desc_t *desc) 259a30d46c0SDavid Brownell { 260a30d46c0SDavid Brownell /* Acknowledge, clear *AND* mask the interrupt... */ 261a30d46c0SDavid Brownell desc->chip->ack(irq); 262a30d46c0SDavid Brownell complete(&irq_event); 263a30d46c0SDavid Brownell } 264a30d46c0SDavid Brownell 265a30d46c0SDavid Brownell static struct task_struct *start_twl4030_irq_thread(long irq) 266a30d46c0SDavid Brownell { 267a30d46c0SDavid Brownell struct task_struct *thread; 268a30d46c0SDavid Brownell 269a30d46c0SDavid Brownell init_completion(&irq_event); 270a30d46c0SDavid Brownell thread = kthread_run(twl4030_irq_thread, (void *)irq, "twl4030-irq"); 271a30d46c0SDavid Brownell if (!thread) 272a30d46c0SDavid Brownell pr_err("twl4030: could not create irq %ld thread!\n", irq); 273a30d46c0SDavid Brownell 274a30d46c0SDavid Brownell return thread; 275a30d46c0SDavid Brownell } 276a30d46c0SDavid Brownell 277a30d46c0SDavid Brownell /*----------------------------------------------------------------------*/ 278a30d46c0SDavid Brownell 279a30d46c0SDavid Brownell /* 280a30d46c0SDavid Brownell * twl4030_init_sih_modules() ... start from a known state where no 281a30d46c0SDavid Brownell * IRQs will be coming in, and where we can quickly enable them then 282a30d46c0SDavid Brownell * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL. 283a30d46c0SDavid Brownell * 284a30d46c0SDavid Brownell * NOTE: we don't touch EDR registers here; they stay with hardware 285a30d46c0SDavid Brownell * defaults or whatever the last value was. Note that when both EDR 286a30d46c0SDavid Brownell * bits for an IRQ are clear, that's as if its IMR bit is set... 287a30d46c0SDavid Brownell */ 288a30d46c0SDavid Brownell static int twl4030_init_sih_modules(unsigned line) 289a30d46c0SDavid Brownell { 290a30d46c0SDavid Brownell const struct sih *sih; 291a30d46c0SDavid Brownell u8 buf[4]; 292a30d46c0SDavid Brownell int i; 293a30d46c0SDavid Brownell int status; 294a30d46c0SDavid Brownell 295a30d46c0SDavid Brownell /* line 0 == int1_n signal; line 1 == int2_n signal */ 296a30d46c0SDavid Brownell if (line > 1) 297a30d46c0SDavid Brownell return -EINVAL; 298a30d46c0SDavid Brownell 299a30d46c0SDavid Brownell irq_line = line; 300a30d46c0SDavid Brownell 301a30d46c0SDavid Brownell /* disable all interrupts on our line */ 302a30d46c0SDavid Brownell memset(buf, 0xff, sizeof buf); 303a30d46c0SDavid Brownell sih = sih_modules; 304a30d46c0SDavid Brownell for (i = 0; i < ARRAY_SIZE(sih_modules); i++, sih++) { 305a30d46c0SDavid Brownell 306a30d46c0SDavid Brownell /* skip USB -- it's funky */ 307a30d46c0SDavid Brownell if (!sih->bytes_ixr) 308a30d46c0SDavid Brownell continue; 309a30d46c0SDavid Brownell 310a30d46c0SDavid Brownell status = twl4030_i2c_write(sih->module, buf, 311a30d46c0SDavid Brownell sih->mask[line].imr_offset, sih->bytes_ixr); 312a30d46c0SDavid Brownell if (status < 0) 313a30d46c0SDavid Brownell pr_err("twl4030: err %d initializing %s %s\n", 314a30d46c0SDavid Brownell status, sih->name, "IMR"); 315a30d46c0SDavid Brownell 316a30d46c0SDavid Brownell /* Maybe disable "exclusive" mode; buffer second pending irq; 317a30d46c0SDavid Brownell * set Clear-On-Read (COR) bit. 318a30d46c0SDavid Brownell * 319a30d46c0SDavid Brownell * NOTE that sometimes COR polarity is documented as being 320a30d46c0SDavid Brownell * inverted: for MADC and BCI, COR=1 means "clear on write". 321a30d46c0SDavid Brownell * And for PWR_INT it's not documented... 322a30d46c0SDavid Brownell */ 323a30d46c0SDavid Brownell if (sih->set_cor) { 324a30d46c0SDavid Brownell status = twl4030_i2c_write_u8(sih->module, 325a30d46c0SDavid Brownell TWL4030_SIH_CTRL_COR_MASK, 326a30d46c0SDavid Brownell sih->control_offset); 327a30d46c0SDavid Brownell if (status < 0) 328a30d46c0SDavid Brownell pr_err("twl4030: err %d initializing %s %s\n", 329a30d46c0SDavid Brownell status, sih->name, "SIH_CTRL"); 330a30d46c0SDavid Brownell } 331a30d46c0SDavid Brownell } 332a30d46c0SDavid Brownell 333a30d46c0SDavid Brownell sih = sih_modules; 334a30d46c0SDavid Brownell for (i = 0; i < ARRAY_SIZE(sih_modules); i++, sih++) { 335a30d46c0SDavid Brownell u8 rxbuf[4]; 336a30d46c0SDavid Brownell int j; 337a30d46c0SDavid Brownell 338a30d46c0SDavid Brownell /* skip USB */ 339a30d46c0SDavid Brownell if (!sih->bytes_ixr) 340a30d46c0SDavid Brownell continue; 341a30d46c0SDavid Brownell 342a30d46c0SDavid Brownell /* Clear pending interrupt status. Either the read was 343a30d46c0SDavid Brownell * enough, or we need to write those bits. Repeat, in 344a30d46c0SDavid Brownell * case an IRQ is pending (PENDDIS=0) ... that's not 345a30d46c0SDavid Brownell * uncommon with PWR_INT.PWRON. 346a30d46c0SDavid Brownell */ 347a30d46c0SDavid Brownell for (j = 0; j < 2; j++) { 348a30d46c0SDavid Brownell status = twl4030_i2c_read(sih->module, rxbuf, 349a30d46c0SDavid Brownell sih->mask[line].isr_offset, sih->bytes_ixr); 350a30d46c0SDavid Brownell if (status < 0) 351a30d46c0SDavid Brownell pr_err("twl4030: err %d initializing %s %s\n", 352a30d46c0SDavid Brownell status, sih->name, "ISR"); 353a30d46c0SDavid Brownell 354a30d46c0SDavid Brownell if (!sih->set_cor) 355a30d46c0SDavid Brownell status = twl4030_i2c_write(sih->module, buf, 356a30d46c0SDavid Brownell sih->mask[line].isr_offset, 357a30d46c0SDavid Brownell sih->bytes_ixr); 358a30d46c0SDavid Brownell /* else COR=1 means read sufficed. 359a30d46c0SDavid Brownell * (for most SIH modules...) 360a30d46c0SDavid Brownell */ 361a30d46c0SDavid Brownell } 362a30d46c0SDavid Brownell } 363a30d46c0SDavid Brownell 364a30d46c0SDavid Brownell return 0; 365a30d46c0SDavid Brownell } 366a30d46c0SDavid Brownell 367a30d46c0SDavid Brownell static inline void activate_irq(int irq) 368a30d46c0SDavid Brownell { 369a30d46c0SDavid Brownell #ifdef CONFIG_ARM 370a30d46c0SDavid Brownell /* ARM requires an extra step to clear IRQ_NOREQUEST, which it 371a30d46c0SDavid Brownell * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE. 372a30d46c0SDavid Brownell */ 373a30d46c0SDavid Brownell set_irq_flags(irq, IRQF_VALID); 374a30d46c0SDavid Brownell #else 375a30d46c0SDavid Brownell /* same effect on other architectures */ 376a30d46c0SDavid Brownell set_irq_noprobe(irq); 377a30d46c0SDavid Brownell #endif 378a30d46c0SDavid Brownell } 379a30d46c0SDavid Brownell 380a30d46c0SDavid Brownell /*----------------------------------------------------------------------*/ 381a30d46c0SDavid Brownell 382a30d46c0SDavid Brownell static DEFINE_SPINLOCK(sih_agent_lock); 383a30d46c0SDavid Brownell 384a30d46c0SDavid Brownell static struct workqueue_struct *wq; 385a30d46c0SDavid Brownell 386a30d46c0SDavid Brownell struct sih_agent { 387a30d46c0SDavid Brownell int irq_base; 388a30d46c0SDavid Brownell const struct sih *sih; 389a30d46c0SDavid Brownell 390a30d46c0SDavid Brownell u32 imr; 391a30d46c0SDavid Brownell bool imr_change_pending; 392a30d46c0SDavid Brownell struct work_struct mask_work; 393a30d46c0SDavid Brownell 394a30d46c0SDavid Brownell u32 edge_change; 395a30d46c0SDavid Brownell struct work_struct edge_work; 396a30d46c0SDavid Brownell }; 397a30d46c0SDavid Brownell 398a30d46c0SDavid Brownell static void twl4030_sih_do_mask(struct work_struct *work) 399a30d46c0SDavid Brownell { 400a30d46c0SDavid Brownell struct sih_agent *agent; 401a30d46c0SDavid Brownell const struct sih *sih; 402a30d46c0SDavid Brownell union { 403a30d46c0SDavid Brownell u8 bytes[4]; 404a30d46c0SDavid Brownell u32 word; 405a30d46c0SDavid Brownell } imr; 406a30d46c0SDavid Brownell int status; 407a30d46c0SDavid Brownell 408a30d46c0SDavid Brownell agent = container_of(work, struct sih_agent, mask_work); 409a30d46c0SDavid Brownell 410a30d46c0SDavid Brownell /* see what work we have */ 411a30d46c0SDavid Brownell spin_lock_irq(&sih_agent_lock); 412a30d46c0SDavid Brownell if (agent->imr_change_pending) { 413a30d46c0SDavid Brownell sih = agent->sih; 414a30d46c0SDavid Brownell /* byte[0] gets overwritten as we write ... */ 415a30d46c0SDavid Brownell imr.word = cpu_to_le32(agent->imr << 8); 416a30d46c0SDavid Brownell agent->imr_change_pending = false; 417a30d46c0SDavid Brownell } else 418a30d46c0SDavid Brownell sih = NULL; 419a30d46c0SDavid Brownell spin_unlock_irq(&sih_agent_lock); 420a30d46c0SDavid Brownell if (!sih) 421a30d46c0SDavid Brownell return; 422a30d46c0SDavid Brownell 423a30d46c0SDavid Brownell /* write the whole mask ... simpler than subsetting it */ 424a30d46c0SDavid Brownell status = twl4030_i2c_write(sih->module, imr.bytes, 425a30d46c0SDavid Brownell sih->mask[irq_line].imr_offset, sih->bytes_ixr); 426a30d46c0SDavid Brownell if (status) 427a30d46c0SDavid Brownell pr_err("twl4030: %s, %s --> %d\n", __func__, 428a30d46c0SDavid Brownell "write", status); 429a30d46c0SDavid Brownell } 430a30d46c0SDavid Brownell 431a30d46c0SDavid Brownell static void twl4030_sih_do_edge(struct work_struct *work) 432a30d46c0SDavid Brownell { 433a30d46c0SDavid Brownell struct sih_agent *agent; 434a30d46c0SDavid Brownell const struct sih *sih; 435a30d46c0SDavid Brownell u8 bytes[6]; 436a30d46c0SDavid Brownell u32 edge_change; 437a30d46c0SDavid Brownell int status; 438a30d46c0SDavid Brownell 439a30d46c0SDavid Brownell agent = container_of(work, struct sih_agent, edge_work); 440a30d46c0SDavid Brownell 441a30d46c0SDavid Brownell /* see what work we have */ 442a30d46c0SDavid Brownell spin_lock_irq(&sih_agent_lock); 443a30d46c0SDavid Brownell edge_change = agent->edge_change; 444a30d46c0SDavid Brownell agent->edge_change = 0;; 445a30d46c0SDavid Brownell sih = edge_change ? agent->sih : NULL; 446a30d46c0SDavid Brownell spin_unlock_irq(&sih_agent_lock); 447a30d46c0SDavid Brownell if (!sih) 448a30d46c0SDavid Brownell return; 449a30d46c0SDavid Brownell 450a30d46c0SDavid Brownell /* Read, reserving first byte for write scratch. Yes, this 451a30d46c0SDavid Brownell * could be cached for some speedup ... but be careful about 452a30d46c0SDavid Brownell * any processor on the other IRQ line, EDR registers are 453a30d46c0SDavid Brownell * shared. 454a30d46c0SDavid Brownell */ 455a30d46c0SDavid Brownell status = twl4030_i2c_read(sih->module, bytes + 1, 456a30d46c0SDavid Brownell sih->edr_offset, sih->bytes_edr); 457a30d46c0SDavid Brownell if (status) { 458a30d46c0SDavid Brownell pr_err("twl4030: %s, %s --> %d\n", __func__, 459a30d46c0SDavid Brownell "read", status); 460a30d46c0SDavid Brownell return; 461a30d46c0SDavid Brownell } 462a30d46c0SDavid Brownell 463a30d46c0SDavid Brownell /* Modify only the bits we know must change */ 464a30d46c0SDavid Brownell while (edge_change) { 465a30d46c0SDavid Brownell int i = fls(edge_change) - 1; 46694964f96SSamuel Ortiz struct irq_desc *d = irq_to_desc(i + agent->irq_base); 467a30d46c0SDavid Brownell int byte = 1 + (i >> 2); 468a30d46c0SDavid Brownell int off = (i & 0x3) * 2; 469a30d46c0SDavid Brownell 47094964f96SSamuel Ortiz if (!d) { 47194964f96SSamuel Ortiz pr_err("twl4030: Invalid IRQ: %d\n", 47294964f96SSamuel Ortiz i + agent->irq_base); 47394964f96SSamuel Ortiz return; 47494964f96SSamuel Ortiz } 47594964f96SSamuel Ortiz 476a30d46c0SDavid Brownell bytes[byte] &= ~(0x03 << off); 477a30d46c0SDavid Brownell 478a30d46c0SDavid Brownell spin_lock_irq(&d->lock); 479a30d46c0SDavid Brownell if (d->status & IRQ_TYPE_EDGE_RISING) 480a30d46c0SDavid Brownell bytes[byte] |= BIT(off + 1); 481a30d46c0SDavid Brownell if (d->status & IRQ_TYPE_EDGE_FALLING) 482a30d46c0SDavid Brownell bytes[byte] |= BIT(off + 0); 483a30d46c0SDavid Brownell spin_unlock_irq(&d->lock); 484a30d46c0SDavid Brownell 485a30d46c0SDavid Brownell edge_change &= ~BIT(i); 486a30d46c0SDavid Brownell } 487a30d46c0SDavid Brownell 488a30d46c0SDavid Brownell /* Write */ 489a30d46c0SDavid Brownell status = twl4030_i2c_write(sih->module, bytes, 490a30d46c0SDavid Brownell sih->edr_offset, sih->bytes_edr); 491a30d46c0SDavid Brownell if (status) 492a30d46c0SDavid Brownell pr_err("twl4030: %s, %s --> %d\n", __func__, 493a30d46c0SDavid Brownell "write", status); 494a30d46c0SDavid Brownell } 495a30d46c0SDavid Brownell 496a30d46c0SDavid Brownell /*----------------------------------------------------------------------*/ 497a30d46c0SDavid Brownell 498a30d46c0SDavid Brownell /* 499a30d46c0SDavid Brownell * All irq_chip methods get issued from code holding irq_desc[irq].lock, 500a30d46c0SDavid Brownell * which can't perform the underlying I2C operations (because they sleep). 501a30d46c0SDavid Brownell * So we must hand them off to a thread (workqueue) and cope with asynch 502a30d46c0SDavid Brownell * completion, potentially including some re-ordering, of these requests. 503a30d46c0SDavid Brownell */ 504a30d46c0SDavid Brownell 505a30d46c0SDavid Brownell static void twl4030_sih_mask(unsigned irq) 506a30d46c0SDavid Brownell { 507a30d46c0SDavid Brownell struct sih_agent *sih = get_irq_chip_data(irq); 508a30d46c0SDavid Brownell unsigned long flags; 509a30d46c0SDavid Brownell 510a30d46c0SDavid Brownell spin_lock_irqsave(&sih_agent_lock, flags); 511a30d46c0SDavid Brownell sih->imr |= BIT(irq - sih->irq_base); 512a30d46c0SDavid Brownell sih->imr_change_pending = true; 513a30d46c0SDavid Brownell queue_work(wq, &sih->mask_work); 514a30d46c0SDavid Brownell spin_unlock_irqrestore(&sih_agent_lock, flags); 515a30d46c0SDavid Brownell } 516a30d46c0SDavid Brownell 517a30d46c0SDavid Brownell static void twl4030_sih_unmask(unsigned irq) 518a30d46c0SDavid Brownell { 519a30d46c0SDavid Brownell struct sih_agent *sih = get_irq_chip_data(irq); 520a30d46c0SDavid Brownell unsigned long flags; 521a30d46c0SDavid Brownell 522a30d46c0SDavid Brownell spin_lock_irqsave(&sih_agent_lock, flags); 523a30d46c0SDavid Brownell sih->imr &= ~BIT(irq - sih->irq_base); 524a30d46c0SDavid Brownell sih->imr_change_pending = true; 525a30d46c0SDavid Brownell queue_work(wq, &sih->mask_work); 526a30d46c0SDavid Brownell spin_unlock_irqrestore(&sih_agent_lock, flags); 527a30d46c0SDavid Brownell } 528a30d46c0SDavid Brownell 529a30d46c0SDavid Brownell static int twl4030_sih_set_type(unsigned irq, unsigned trigger) 530a30d46c0SDavid Brownell { 531a30d46c0SDavid Brownell struct sih_agent *sih = get_irq_chip_data(irq); 53294964f96SSamuel Ortiz struct irq_desc *desc = irq_to_desc(irq); 533a30d46c0SDavid Brownell unsigned long flags; 534a30d46c0SDavid Brownell 53594964f96SSamuel Ortiz if (!desc) { 53694964f96SSamuel Ortiz pr_err("twl4030: Invalid IRQ: %d\n", irq); 53794964f96SSamuel Ortiz return -EINVAL; 53894964f96SSamuel Ortiz } 53994964f96SSamuel Ortiz 540a30d46c0SDavid Brownell if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 541a30d46c0SDavid Brownell return -EINVAL; 542a30d46c0SDavid Brownell 543a30d46c0SDavid Brownell spin_lock_irqsave(&sih_agent_lock, flags); 544a30d46c0SDavid Brownell if ((desc->status & IRQ_TYPE_SENSE_MASK) != trigger) { 545a30d46c0SDavid Brownell desc->status &= ~IRQ_TYPE_SENSE_MASK; 546a30d46c0SDavid Brownell desc->status |= trigger; 547a30d46c0SDavid Brownell sih->edge_change |= BIT(irq - sih->irq_base); 548a30d46c0SDavid Brownell queue_work(wq, &sih->edge_work); 549a30d46c0SDavid Brownell } 550a30d46c0SDavid Brownell spin_unlock_irqrestore(&sih_agent_lock, flags); 551a30d46c0SDavid Brownell return 0; 552a30d46c0SDavid Brownell } 553a30d46c0SDavid Brownell 554a30d46c0SDavid Brownell static struct irq_chip twl4030_sih_irq_chip = { 555a30d46c0SDavid Brownell .name = "twl4030", 556a30d46c0SDavid Brownell .mask = twl4030_sih_mask, 557a30d46c0SDavid Brownell .unmask = twl4030_sih_unmask, 558a30d46c0SDavid Brownell .set_type = twl4030_sih_set_type, 559a30d46c0SDavid Brownell }; 560a30d46c0SDavid Brownell 561a30d46c0SDavid Brownell /*----------------------------------------------------------------------*/ 562a30d46c0SDavid Brownell 563a30d46c0SDavid Brownell static inline int sih_read_isr(const struct sih *sih) 564a30d46c0SDavid Brownell { 565a30d46c0SDavid Brownell int status; 566a30d46c0SDavid Brownell union { 567a30d46c0SDavid Brownell u8 bytes[4]; 568a30d46c0SDavid Brownell u32 word; 569a30d46c0SDavid Brownell } isr; 570a30d46c0SDavid Brownell 571a30d46c0SDavid Brownell /* FIXME need retry-on-error ... */ 572a30d46c0SDavid Brownell 573a30d46c0SDavid Brownell isr.word = 0; 574a30d46c0SDavid Brownell status = twl4030_i2c_read(sih->module, isr.bytes, 575a30d46c0SDavid Brownell sih->mask[irq_line].isr_offset, sih->bytes_ixr); 576a30d46c0SDavid Brownell 577a30d46c0SDavid Brownell return (status < 0) ? status : le32_to_cpu(isr.word); 578a30d46c0SDavid Brownell } 579a30d46c0SDavid Brownell 580a30d46c0SDavid Brownell /* 581a30d46c0SDavid Brownell * Generic handler for SIH interrupts ... we "know" this is called 582a30d46c0SDavid Brownell * in task context, with IRQs enabled. 583a30d46c0SDavid Brownell */ 584a30d46c0SDavid Brownell static void handle_twl4030_sih(unsigned irq, struct irq_desc *desc) 585a30d46c0SDavid Brownell { 586a30d46c0SDavid Brownell struct sih_agent *agent = get_irq_data(irq); 587a30d46c0SDavid Brownell const struct sih *sih = agent->sih; 588a30d46c0SDavid Brownell int isr; 589a30d46c0SDavid Brownell 590a30d46c0SDavid Brownell /* reading ISR acks the IRQs, using clear-on-read mode */ 591a30d46c0SDavid Brownell local_irq_enable(); 592a30d46c0SDavid Brownell isr = sih_read_isr(sih); 593a30d46c0SDavid Brownell local_irq_disable(); 594a30d46c0SDavid Brownell 595a30d46c0SDavid Brownell if (isr < 0) { 596a30d46c0SDavid Brownell pr_err("twl4030: %s SIH, read ISR error %d\n", 597a30d46c0SDavid Brownell sih->name, isr); 598a30d46c0SDavid Brownell /* REVISIT: recover; eventually mask it all, etc */ 599a30d46c0SDavid Brownell return; 600a30d46c0SDavid Brownell } 601a30d46c0SDavid Brownell 602a30d46c0SDavid Brownell while (isr) { 603a30d46c0SDavid Brownell irq = fls(isr); 604a30d46c0SDavid Brownell irq--; 605a30d46c0SDavid Brownell isr &= ~BIT(irq); 606a30d46c0SDavid Brownell 607a30d46c0SDavid Brownell if (irq < sih->bits) 608a30d46c0SDavid Brownell generic_handle_irq(agent->irq_base + irq); 609a30d46c0SDavid Brownell else 610a30d46c0SDavid Brownell pr_err("twl4030: %s SIH, invalid ISR bit %d\n", 611a30d46c0SDavid Brownell sih->name, irq); 612a30d46c0SDavid Brownell } 613a30d46c0SDavid Brownell } 614a30d46c0SDavid Brownell 615a30d46c0SDavid Brownell static unsigned twl4030_irq_next; 616a30d46c0SDavid Brownell 617a30d46c0SDavid Brownell /* returns the first IRQ used by this SIH bank, 618a30d46c0SDavid Brownell * or negative errno 619a30d46c0SDavid Brownell */ 620a30d46c0SDavid Brownell int twl4030_sih_setup(int module) 621a30d46c0SDavid Brownell { 622a30d46c0SDavid Brownell int sih_mod; 623a30d46c0SDavid Brownell const struct sih *sih = NULL; 624a30d46c0SDavid Brownell struct sih_agent *agent; 625a30d46c0SDavid Brownell int i, irq; 626a30d46c0SDavid Brownell int status = -EINVAL; 627a30d46c0SDavid Brownell unsigned irq_base = twl4030_irq_next; 628a30d46c0SDavid Brownell 629a30d46c0SDavid Brownell /* only support modules with standard clear-on-read for now */ 630a30d46c0SDavid Brownell for (sih_mod = 0, sih = sih_modules; 631a30d46c0SDavid Brownell sih_mod < ARRAY_SIZE(sih_modules); 632a30d46c0SDavid Brownell sih_mod++, sih++) { 633a30d46c0SDavid Brownell if (sih->module == module && sih->set_cor) { 634a30d46c0SDavid Brownell if (!WARN((irq_base + sih->bits) > NR_IRQS, 635a30d46c0SDavid Brownell "irq %d for %s too big\n", 636a30d46c0SDavid Brownell irq_base + sih->bits, 637a30d46c0SDavid Brownell sih->name)) 638a30d46c0SDavid Brownell status = 0; 639a30d46c0SDavid Brownell break; 640a30d46c0SDavid Brownell } 641a30d46c0SDavid Brownell } 642a30d46c0SDavid Brownell if (status < 0) 643a30d46c0SDavid Brownell return status; 644a30d46c0SDavid Brownell 645a30d46c0SDavid Brownell agent = kzalloc(sizeof *agent, GFP_KERNEL); 646a30d46c0SDavid Brownell if (!agent) 647a30d46c0SDavid Brownell return -ENOMEM; 648a30d46c0SDavid Brownell 649a30d46c0SDavid Brownell status = 0; 650a30d46c0SDavid Brownell 651a30d46c0SDavid Brownell agent->irq_base = irq_base; 652a30d46c0SDavid Brownell agent->sih = sih; 653a30d46c0SDavid Brownell agent->imr = ~0; 654a30d46c0SDavid Brownell INIT_WORK(&agent->mask_work, twl4030_sih_do_mask); 655a30d46c0SDavid Brownell INIT_WORK(&agent->edge_work, twl4030_sih_do_edge); 656a30d46c0SDavid Brownell 657a30d46c0SDavid Brownell for (i = 0; i < sih->bits; i++) { 658a30d46c0SDavid Brownell irq = irq_base + i; 659a30d46c0SDavid Brownell 660a30d46c0SDavid Brownell set_irq_chip_and_handler(irq, &twl4030_sih_irq_chip, 661a30d46c0SDavid Brownell handle_edge_irq); 662a30d46c0SDavid Brownell set_irq_chip_data(irq, agent); 663a30d46c0SDavid Brownell activate_irq(irq); 664a30d46c0SDavid Brownell } 665a30d46c0SDavid Brownell 666a30d46c0SDavid Brownell status = irq_base; 667a30d46c0SDavid Brownell twl4030_irq_next += i; 668a30d46c0SDavid Brownell 669a30d46c0SDavid Brownell /* replace generic PIH handler (handle_simple_irq) */ 670a30d46c0SDavid Brownell irq = sih_mod + twl4030_irq_base; 671a30d46c0SDavid Brownell set_irq_data(irq, agent); 672a30d46c0SDavid Brownell set_irq_chained_handler(irq, handle_twl4030_sih); 673a30d46c0SDavid Brownell 674a30d46c0SDavid Brownell pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", sih->name, 675a30d46c0SDavid Brownell irq, irq_base, twl4030_irq_next - 1); 676a30d46c0SDavid Brownell 677a30d46c0SDavid Brownell return status; 678a30d46c0SDavid Brownell } 679a30d46c0SDavid Brownell 680a30d46c0SDavid Brownell /* FIXME need a call to reverse twl4030_sih_setup() ... */ 681a30d46c0SDavid Brownell 682a30d46c0SDavid Brownell 683a30d46c0SDavid Brownell /*----------------------------------------------------------------------*/ 684a30d46c0SDavid Brownell 685a30d46c0SDavid Brownell /* FIXME pass in which interrupt line we'll use ... */ 686a30d46c0SDavid Brownell #define twl_irq_line 0 687a30d46c0SDavid Brownell 688a30d46c0SDavid Brownell int twl_init_irq(int irq_num, unsigned irq_base, unsigned irq_end) 689a30d46c0SDavid Brownell { 690a30d46c0SDavid Brownell static struct irq_chip twl4030_irq_chip; 691a30d46c0SDavid Brownell 692a30d46c0SDavid Brownell int status; 693a30d46c0SDavid Brownell int i; 694a30d46c0SDavid Brownell struct task_struct *task; 695a30d46c0SDavid Brownell 696a30d46c0SDavid Brownell /* 697a30d46c0SDavid Brownell * Mask and clear all TWL4030 interrupts since initially we do 698a30d46c0SDavid Brownell * not have any TWL4030 module interrupt handlers present 699a30d46c0SDavid Brownell */ 700a30d46c0SDavid Brownell status = twl4030_init_sih_modules(twl_irq_line); 701a30d46c0SDavid Brownell if (status < 0) 702a30d46c0SDavid Brownell return status; 703a30d46c0SDavid Brownell 704a30d46c0SDavid Brownell wq = create_singlethread_workqueue("twl4030-irqchip"); 705a30d46c0SDavid Brownell if (!wq) { 706a30d46c0SDavid Brownell pr_err("twl4030: workqueue FAIL\n"); 707a30d46c0SDavid Brownell return -ESRCH; 708a30d46c0SDavid Brownell } 709a30d46c0SDavid Brownell 710a30d46c0SDavid Brownell twl4030_irq_base = irq_base; 711a30d46c0SDavid Brownell 712a30d46c0SDavid Brownell /* install an irq handler for each of the SIH modules; 713a30d46c0SDavid Brownell * clone dummy irq_chip since PIH can't *do* anything 714a30d46c0SDavid Brownell */ 715a30d46c0SDavid Brownell twl4030_irq_chip = dummy_irq_chip; 716a30d46c0SDavid Brownell twl4030_irq_chip.name = "twl4030"; 717a30d46c0SDavid Brownell 718a30d46c0SDavid Brownell twl4030_sih_irq_chip.ack = dummy_irq_chip.ack; 719a30d46c0SDavid Brownell 720a30d46c0SDavid Brownell for (i = irq_base; i < irq_end; i++) { 721a30d46c0SDavid Brownell set_irq_chip_and_handler(i, &twl4030_irq_chip, 722a30d46c0SDavid Brownell handle_simple_irq); 723a30d46c0SDavid Brownell activate_irq(i); 724a30d46c0SDavid Brownell } 725a30d46c0SDavid Brownell twl4030_irq_next = i; 726a30d46c0SDavid Brownell pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", "PIH", 727a30d46c0SDavid Brownell irq_num, irq_base, twl4030_irq_next - 1); 728a30d46c0SDavid Brownell 729a30d46c0SDavid Brownell /* ... and the PWR_INT module ... */ 730a30d46c0SDavid Brownell status = twl4030_sih_setup(TWL4030_MODULE_INT); 731a30d46c0SDavid Brownell if (status < 0) { 732a30d46c0SDavid Brownell pr_err("twl4030: sih_setup PWR INT --> %d\n", status); 733a30d46c0SDavid Brownell goto fail; 734a30d46c0SDavid Brownell } 735a30d46c0SDavid Brownell 736a30d46c0SDavid Brownell /* install an irq handler to demultiplex the TWL4030 interrupt */ 737a30d46c0SDavid Brownell task = start_twl4030_irq_thread(irq_num); 738a30d46c0SDavid Brownell if (!task) { 739a30d46c0SDavid Brownell pr_err("twl4030: irq thread FAIL\n"); 740a30d46c0SDavid Brownell status = -ESRCH; 741a30d46c0SDavid Brownell goto fail; 742a30d46c0SDavid Brownell } 743a30d46c0SDavid Brownell 744a30d46c0SDavid Brownell set_irq_data(irq_num, task); 745a30d46c0SDavid Brownell set_irq_chained_handler(irq_num, handle_twl4030_pih); 746a30d46c0SDavid Brownell 747a30d46c0SDavid Brownell return status; 748a30d46c0SDavid Brownell 749a30d46c0SDavid Brownell fail: 750a30d46c0SDavid Brownell for (i = irq_base; i < irq_end; i++) 751a30d46c0SDavid Brownell set_irq_chip_and_handler(i, NULL, NULL); 752a30d46c0SDavid Brownell destroy_workqueue(wq); 753a30d46c0SDavid Brownell wq = NULL; 754a30d46c0SDavid Brownell return status; 755a30d46c0SDavid Brownell } 756a30d46c0SDavid Brownell 757a30d46c0SDavid Brownell int twl_exit_irq(void) 758a30d46c0SDavid Brownell { 759a30d46c0SDavid Brownell /* FIXME undo twl_init_irq() */ 760a30d46c0SDavid Brownell if (twl4030_irq_base) { 761a30d46c0SDavid Brownell pr_err("twl4030: can't yet clean up IRQs?\n"); 762a30d46c0SDavid Brownell return -ENOSYS; 763a30d46c0SDavid Brownell } 764a30d46c0SDavid Brownell return 0; 765a30d46c0SDavid Brownell } 766