151908d2eSPascal PAILLET-LME // SPDX-License-Identifier: GPL-2.0
251908d2eSPascal PAILLET-LME // Copyright (C) STMicroelectronics 2018
351908d2eSPascal PAILLET-LME // Author: Pascal Paillet <p.paillet@st.com>
451908d2eSPascal PAILLET-LME
551908d2eSPascal PAILLET-LME #include <linux/i2c.h>
651908d2eSPascal PAILLET-LME #include <linux/interrupt.h>
751908d2eSPascal PAILLET-LME #include <linux/mfd/core.h>
851908d2eSPascal PAILLET-LME #include <linux/mfd/stpmic1.h>
951908d2eSPascal PAILLET-LME #include <linux/module.h>
106e9df38fSSean Nyekjaer #include <linux/reboot.h>
1151908d2eSPascal PAILLET-LME #include <linux/of.h>
1251908d2eSPascal PAILLET-LME #include <linux/of_irq.h>
1351908d2eSPascal PAILLET-LME #include <linux/of_platform.h>
1451908d2eSPascal PAILLET-LME #include <linux/pm_wakeirq.h>
1551908d2eSPascal PAILLET-LME #include <linux/regmap.h>
1651908d2eSPascal PAILLET-LME
1751908d2eSPascal PAILLET-LME #include <dt-bindings/mfd/st,stpmic1.h>
1851908d2eSPascal PAILLET-LME
1951908d2eSPascal PAILLET-LME #define STPMIC1_MAIN_IRQ 0
2051908d2eSPascal PAILLET-LME
2151908d2eSPascal PAILLET-LME static const struct regmap_range stpmic1_readable_ranges[] = {
2251908d2eSPascal PAILLET-LME regmap_reg_range(TURN_ON_SR, VERSION_SR),
2348b4371bSSean Nyekjaer regmap_reg_range(MAIN_CR, LDO6_STDBY_CR),
2451908d2eSPascal PAILLET-LME regmap_reg_range(BST_SW_CR, BST_SW_CR),
2551908d2eSPascal PAILLET-LME regmap_reg_range(INT_PENDING_R1, INT_PENDING_R4),
2651908d2eSPascal PAILLET-LME regmap_reg_range(INT_CLEAR_R1, INT_CLEAR_R4),
2751908d2eSPascal PAILLET-LME regmap_reg_range(INT_MASK_R1, INT_MASK_R4),
2851908d2eSPascal PAILLET-LME regmap_reg_range(INT_SET_MASK_R1, INT_SET_MASK_R4),
2951908d2eSPascal PAILLET-LME regmap_reg_range(INT_CLEAR_MASK_R1, INT_CLEAR_MASK_R4),
3051908d2eSPascal PAILLET-LME regmap_reg_range(INT_SRC_R1, INT_SRC_R1),
3151908d2eSPascal PAILLET-LME };
3251908d2eSPascal PAILLET-LME
3351908d2eSPascal PAILLET-LME static const struct regmap_range stpmic1_writeable_ranges[] = {
3448b4371bSSean Nyekjaer regmap_reg_range(MAIN_CR, LDO6_STDBY_CR),
3551908d2eSPascal PAILLET-LME regmap_reg_range(BST_SW_CR, BST_SW_CR),
3651908d2eSPascal PAILLET-LME regmap_reg_range(INT_CLEAR_R1, INT_CLEAR_R4),
3751908d2eSPascal PAILLET-LME regmap_reg_range(INT_SET_MASK_R1, INT_SET_MASK_R4),
3851908d2eSPascal PAILLET-LME regmap_reg_range(INT_CLEAR_MASK_R1, INT_CLEAR_MASK_R4),
3951908d2eSPascal PAILLET-LME };
4051908d2eSPascal PAILLET-LME
4151908d2eSPascal PAILLET-LME static const struct regmap_range stpmic1_volatile_ranges[] = {
4251908d2eSPascal PAILLET-LME regmap_reg_range(TURN_ON_SR, VERSION_SR),
4351908d2eSPascal PAILLET-LME regmap_reg_range(WCHDG_CR, WCHDG_CR),
4451908d2eSPascal PAILLET-LME regmap_reg_range(INT_PENDING_R1, INT_PENDING_R4),
4551908d2eSPascal PAILLET-LME regmap_reg_range(INT_SRC_R1, INT_SRC_R4),
4651908d2eSPascal PAILLET-LME };
4751908d2eSPascal PAILLET-LME
4851908d2eSPascal PAILLET-LME static const struct regmap_access_table stpmic1_readable_table = {
4951908d2eSPascal PAILLET-LME .yes_ranges = stpmic1_readable_ranges,
5051908d2eSPascal PAILLET-LME .n_yes_ranges = ARRAY_SIZE(stpmic1_readable_ranges),
5151908d2eSPascal PAILLET-LME };
5251908d2eSPascal PAILLET-LME
5351908d2eSPascal PAILLET-LME static const struct regmap_access_table stpmic1_writeable_table = {
5451908d2eSPascal PAILLET-LME .yes_ranges = stpmic1_writeable_ranges,
5551908d2eSPascal PAILLET-LME .n_yes_ranges = ARRAY_SIZE(stpmic1_writeable_ranges),
5651908d2eSPascal PAILLET-LME };
5751908d2eSPascal PAILLET-LME
5851908d2eSPascal PAILLET-LME static const struct regmap_access_table stpmic1_volatile_table = {
5951908d2eSPascal PAILLET-LME .yes_ranges = stpmic1_volatile_ranges,
6051908d2eSPascal PAILLET-LME .n_yes_ranges = ARRAY_SIZE(stpmic1_volatile_ranges),
6151908d2eSPascal PAILLET-LME };
6251908d2eSPascal PAILLET-LME
630c09e712SYueHaibing static const struct regmap_config stpmic1_regmap_config = {
6451908d2eSPascal PAILLET-LME .reg_bits = 8,
6551908d2eSPascal PAILLET-LME .val_bits = 8,
66*12edc9a8SBo Liu .cache_type = REGCACHE_MAPLE,
6751908d2eSPascal PAILLET-LME .max_register = PMIC_MAX_REGISTER_ADDRESS,
6851908d2eSPascal PAILLET-LME .rd_table = &stpmic1_readable_table,
6951908d2eSPascal PAILLET-LME .wr_table = &stpmic1_writeable_table,
7051908d2eSPascal PAILLET-LME .volatile_table = &stpmic1_volatile_table,
7151908d2eSPascal PAILLET-LME };
7251908d2eSPascal PAILLET-LME
7351908d2eSPascal PAILLET-LME static const struct regmap_irq stpmic1_irqs[] = {
7451908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_PONKEY_F, 0, 0x01),
7551908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_PONKEY_R, 0, 0x02),
7651908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_WAKEUP_F, 0, 0x04),
7751908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_WAKEUP_R, 0, 0x08),
7851908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_VBUS_OTG_F, 0, 0x10),
7951908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_VBUS_OTG_R, 0, 0x20),
8051908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_SWOUT_F, 0, 0x40),
8151908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_SWOUT_R, 0, 0x80),
8251908d2eSPascal PAILLET-LME
8351908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_CURLIM_BUCK1, 1, 0x01),
8451908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_CURLIM_BUCK2, 1, 0x02),
8551908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_CURLIM_BUCK3, 1, 0x04),
8651908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_CURLIM_BUCK4, 1, 0x08),
8751908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_OCP_OTG, 1, 0x10),
8851908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_OCP_SWOUT, 1, 0x20),
8951908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_OCP_BOOST, 1, 0x40),
9051908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_OVP_BOOST, 1, 0x80),
9151908d2eSPascal PAILLET-LME
9251908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_CURLIM_LDO1, 2, 0x01),
9351908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_CURLIM_LDO2, 2, 0x02),
9451908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_CURLIM_LDO3, 2, 0x04),
9551908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_CURLIM_LDO4, 2, 0x08),
9651908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_CURLIM_LDO5, 2, 0x10),
9751908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_CURLIM_LDO6, 2, 0x20),
9851908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_SHORT_SWOTG, 2, 0x40),
9951908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_SHORT_SWOUT, 2, 0x80),
10051908d2eSPascal PAILLET-LME
10151908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_TWARN_F, 3, 0x01),
10251908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_TWARN_R, 3, 0x02),
10351908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_VINLOW_F, 3, 0x04),
10451908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_VINLOW_R, 3, 0x08),
10551908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_SWIN_F, 3, 0x40),
10651908d2eSPascal PAILLET-LME REGMAP_IRQ_REG(IT_SWIN_R, 3, 0x80),
10751908d2eSPascal PAILLET-LME };
10851908d2eSPascal PAILLET-LME
10951908d2eSPascal PAILLET-LME static const struct regmap_irq_chip stpmic1_regmap_irq_chip = {
11051908d2eSPascal PAILLET-LME .name = "pmic_irq",
11151908d2eSPascal PAILLET-LME .status_base = INT_PENDING_R1,
112c79e3873SAidan MacDonald .mask_base = INT_SET_MASK_R1,
113c79e3873SAidan MacDonald .unmask_base = INT_CLEAR_MASK_R1,
114c79e3873SAidan MacDonald .mask_unmask_non_inverted = true,
11551908d2eSPascal PAILLET-LME .ack_base = INT_CLEAR_R1,
11651908d2eSPascal PAILLET-LME .num_regs = STPMIC1_PMIC_NUM_IRQ_REGS,
11751908d2eSPascal PAILLET-LME .irqs = stpmic1_irqs,
11851908d2eSPascal PAILLET-LME .num_irqs = ARRAY_SIZE(stpmic1_irqs),
11951908d2eSPascal PAILLET-LME };
12051908d2eSPascal PAILLET-LME
stpmic1_power_off(struct sys_off_data * data)1216e9df38fSSean Nyekjaer static int stpmic1_power_off(struct sys_off_data *data)
1226e9df38fSSean Nyekjaer {
1236e9df38fSSean Nyekjaer struct stpmic1 *ddata = data->cb_data;
1246e9df38fSSean Nyekjaer
1256e9df38fSSean Nyekjaer regmap_update_bits(ddata->regmap, MAIN_CR,
1266e9df38fSSean Nyekjaer SOFTWARE_SWITCH_OFF, SOFTWARE_SWITCH_OFF);
1276e9df38fSSean Nyekjaer
1286e9df38fSSean Nyekjaer return NOTIFY_DONE;
1296e9df38fSSean Nyekjaer }
1306e9df38fSSean Nyekjaer
stpmic1_probe(struct i2c_client * i2c)13139cabdc8SUwe Kleine-König static int stpmic1_probe(struct i2c_client *i2c)
13251908d2eSPascal PAILLET-LME {
13351908d2eSPascal PAILLET-LME struct stpmic1 *ddata;
13451908d2eSPascal PAILLET-LME struct device *dev = &i2c->dev;
13551908d2eSPascal PAILLET-LME int ret;
13651908d2eSPascal PAILLET-LME struct device_node *np = dev->of_node;
13751908d2eSPascal PAILLET-LME u32 reg;
13851908d2eSPascal PAILLET-LME
13951908d2eSPascal PAILLET-LME ddata = devm_kzalloc(dev, sizeof(struct stpmic1), GFP_KERNEL);
14051908d2eSPascal PAILLET-LME if (!ddata)
14151908d2eSPascal PAILLET-LME return -ENOMEM;
14251908d2eSPascal PAILLET-LME
14351908d2eSPascal PAILLET-LME i2c_set_clientdata(i2c, ddata);
14451908d2eSPascal PAILLET-LME ddata->dev = dev;
14551908d2eSPascal PAILLET-LME
14651908d2eSPascal PAILLET-LME ddata->regmap = devm_regmap_init_i2c(i2c, &stpmic1_regmap_config);
14751908d2eSPascal PAILLET-LME if (IS_ERR(ddata->regmap))
14851908d2eSPascal PAILLET-LME return PTR_ERR(ddata->regmap);
14951908d2eSPascal PAILLET-LME
15051908d2eSPascal PAILLET-LME ddata->irq = of_irq_get(np, STPMIC1_MAIN_IRQ);
15151908d2eSPascal PAILLET-LME if (ddata->irq < 0) {
15251908d2eSPascal PAILLET-LME dev_err(dev, "Failed to get main IRQ: %d\n", ddata->irq);
15351908d2eSPascal PAILLET-LME return ddata->irq;
15451908d2eSPascal PAILLET-LME }
15551908d2eSPascal PAILLET-LME
15651908d2eSPascal PAILLET-LME ret = regmap_read(ddata->regmap, VERSION_SR, ®);
15751908d2eSPascal PAILLET-LME if (ret) {
15851908d2eSPascal PAILLET-LME dev_err(dev, "Unable to read PMIC version\n");
15951908d2eSPascal PAILLET-LME return ret;
16051908d2eSPascal PAILLET-LME }
16151908d2eSPascal PAILLET-LME dev_info(dev, "PMIC Chip Version: 0x%x\n", reg);
16251908d2eSPascal PAILLET-LME
16351908d2eSPascal PAILLET-LME /* Initialize PMIC IRQ Chip & associated IRQ domains */
16451908d2eSPascal PAILLET-LME ret = devm_regmap_add_irq_chip(dev, ddata->regmap, ddata->irq,
16551908d2eSPascal PAILLET-LME IRQF_ONESHOT | IRQF_SHARED,
16651908d2eSPascal PAILLET-LME 0, &stpmic1_regmap_irq_chip,
16751908d2eSPascal PAILLET-LME &ddata->irq_data);
16851908d2eSPascal PAILLET-LME if (ret) {
16951908d2eSPascal PAILLET-LME dev_err(dev, "IRQ Chip registration failed: %d\n", ret);
17051908d2eSPascal PAILLET-LME return ret;
17151908d2eSPascal PAILLET-LME }
17251908d2eSPascal PAILLET-LME
1736e9df38fSSean Nyekjaer ret = devm_register_sys_off_handler(ddata->dev,
1746e9df38fSSean Nyekjaer SYS_OFF_MODE_POWER_OFF,
1756e9df38fSSean Nyekjaer SYS_OFF_PRIO_DEFAULT,
1766e9df38fSSean Nyekjaer stpmic1_power_off,
1776e9df38fSSean Nyekjaer ddata);
1786e9df38fSSean Nyekjaer if (ret) {
1796e9df38fSSean Nyekjaer dev_err(ddata->dev, "failed to register sys-off handler: %d\n", ret);
1806e9df38fSSean Nyekjaer return ret;
1816e9df38fSSean Nyekjaer }
1826e9df38fSSean Nyekjaer
18351908d2eSPascal PAILLET-LME return devm_of_platform_populate(dev);
18451908d2eSPascal PAILLET-LME }
18551908d2eSPascal PAILLET-LME
stpmic1_suspend(struct device * dev)18651908d2eSPascal PAILLET-LME static int stpmic1_suspend(struct device *dev)
18751908d2eSPascal PAILLET-LME {
18851908d2eSPascal PAILLET-LME struct i2c_client *i2c = to_i2c_client(dev);
18951908d2eSPascal PAILLET-LME struct stpmic1 *pmic_dev = i2c_get_clientdata(i2c);
19051908d2eSPascal PAILLET-LME
19151908d2eSPascal PAILLET-LME disable_irq(pmic_dev->irq);
19251908d2eSPascal PAILLET-LME
19351908d2eSPascal PAILLET-LME return 0;
19451908d2eSPascal PAILLET-LME }
19551908d2eSPascal PAILLET-LME
stpmic1_resume(struct device * dev)19651908d2eSPascal PAILLET-LME static int stpmic1_resume(struct device *dev)
19751908d2eSPascal PAILLET-LME {
19851908d2eSPascal PAILLET-LME struct i2c_client *i2c = to_i2c_client(dev);
19951908d2eSPascal PAILLET-LME struct stpmic1 *pmic_dev = i2c_get_clientdata(i2c);
20051908d2eSPascal PAILLET-LME int ret;
20151908d2eSPascal PAILLET-LME
20251908d2eSPascal PAILLET-LME ret = regcache_sync(pmic_dev->regmap);
20351908d2eSPascal PAILLET-LME if (ret)
20451908d2eSPascal PAILLET-LME return ret;
20551908d2eSPascal PAILLET-LME
20651908d2eSPascal PAILLET-LME enable_irq(pmic_dev->irq);
20751908d2eSPascal PAILLET-LME
20851908d2eSPascal PAILLET-LME return 0;
20951908d2eSPascal PAILLET-LME }
21051908d2eSPascal PAILLET-LME
211e4b9a17cSPaul Cercueil static DEFINE_SIMPLE_DEV_PM_OPS(stpmic1_pm, stpmic1_suspend, stpmic1_resume);
21251908d2eSPascal PAILLET-LME
21351908d2eSPascal PAILLET-LME static const struct of_device_id stpmic1_of_match[] = {
21451908d2eSPascal PAILLET-LME { .compatible = "st,stpmic1", },
21551908d2eSPascal PAILLET-LME {},
21651908d2eSPascal PAILLET-LME };
21751908d2eSPascal PAILLET-LME MODULE_DEVICE_TABLE(of, stpmic1_of_match);
21851908d2eSPascal PAILLET-LME
21951908d2eSPascal PAILLET-LME static struct i2c_driver stpmic1_driver = {
22051908d2eSPascal PAILLET-LME .driver = {
22151908d2eSPascal PAILLET-LME .name = "stpmic1",
2229425f72aSZhu Wang .of_match_table = stpmic1_of_match,
223e4b9a17cSPaul Cercueil .pm = pm_sleep_ptr(&stpmic1_pm),
22451908d2eSPascal PAILLET-LME },
2259816d859SUwe Kleine-König .probe = stpmic1_probe,
22651908d2eSPascal PAILLET-LME };
22751908d2eSPascal PAILLET-LME
22851908d2eSPascal PAILLET-LME module_i2c_driver(stpmic1_driver);
22951908d2eSPascal PAILLET-LME
23051908d2eSPascal PAILLET-LME MODULE_DESCRIPTION("STPMIC1 PMIC Driver");
23151908d2eSPascal PAILLET-LME MODULE_AUTHOR("Pascal Paillet <p.paillet@st.com>");
23251908d2eSPascal PAILLET-LME MODULE_LICENSE("GPL v2");
233