1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics 2016 4 * Author: Benjamin Gaignard <benjamin.gaignard@st.com> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/mfd/stm32-timers.h> 9 #include <linux/module.h> 10 #include <linux/of_platform.h> 11 #include <linux/platform_device.h> 12 #include <linux/property.h> 13 #include <linux/reset.h> 14 15 #define STM32_TIMERS_MAX_REGISTERS 0x3fc 16 17 /* DIER register DMA enable bits */ 18 static const u32 stm32_timers_dier_dmaen[STM32_TIMERS_MAX_DMAS] = { 19 TIM_DIER_CC1DE, 20 TIM_DIER_CC2DE, 21 TIM_DIER_CC3DE, 22 TIM_DIER_CC4DE, 23 TIM_DIER_UIE, 24 TIM_DIER_TDE, 25 TIM_DIER_COMDE 26 }; 27 28 static void stm32_timers_dma_done(void *p) 29 { 30 struct stm32_timers_dma *dma = p; 31 struct dma_tx_state state; 32 enum dma_status status; 33 34 status = dmaengine_tx_status(dma->chan, dma->chan->cookie, &state); 35 if (status == DMA_COMPLETE) 36 complete(&dma->completion); 37 } 38 39 /** 40 * stm32_timers_dma_burst_read - Read from timers registers using DMA. 41 * 42 * Read from STM32 timers registers using DMA on a single event. 43 * @dev: reference to stm32_timers MFD device 44 * @buf: DMA'able destination buffer 45 * @id: stm32_timers_dmas event identifier (ch[1..4], up, trig or com) 46 * @reg: registers start offset for DMA to read from (like CCRx for capture) 47 * @num_reg: number of registers to read upon each DMA request, starting @reg. 48 * @bursts: number of bursts to read (e.g. like two for pwm period capture) 49 * @tmo_ms: timeout (milliseconds) 50 */ 51 int stm32_timers_dma_burst_read(struct device *dev, u32 *buf, 52 enum stm32_timers_dmas id, u32 reg, 53 unsigned int num_reg, unsigned int bursts, 54 unsigned long tmo_ms) 55 { 56 struct stm32_timers *ddata = dev_get_drvdata(dev); 57 unsigned long timeout = msecs_to_jiffies(tmo_ms); 58 struct regmap *regmap = ddata->regmap; 59 struct stm32_timers_dma *dma = &ddata->dma; 60 size_t len = num_reg * bursts * sizeof(u32); 61 struct dma_async_tx_descriptor *desc; 62 struct dma_slave_config config; 63 dma_cookie_t cookie; 64 dma_addr_t dma_buf; 65 u32 dbl, dba; 66 long err; 67 int ret; 68 69 /* Sanity check */ 70 if (id < STM32_TIMERS_DMA_CH1 || id >= STM32_TIMERS_MAX_DMAS) 71 return -EINVAL; 72 73 if (!num_reg || !bursts || reg > STM32_TIMERS_MAX_REGISTERS || 74 (reg + num_reg * sizeof(u32)) > STM32_TIMERS_MAX_REGISTERS) 75 return -EINVAL; 76 77 if (!dma->chans[id]) 78 return -ENODEV; 79 mutex_lock(&dma->lock); 80 81 /* Select DMA channel in use */ 82 dma->chan = dma->chans[id]; 83 dma_buf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE); 84 if (dma_mapping_error(dev, dma_buf)) { 85 ret = -ENOMEM; 86 goto unlock; 87 } 88 89 /* Prepare DMA read from timer registers, using DMA burst mode */ 90 memset(&config, 0, sizeof(config)); 91 config.src_addr = (dma_addr_t)dma->phys_base + TIM_DMAR; 92 config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 93 ret = dmaengine_slave_config(dma->chan, &config); 94 if (ret) 95 goto unmap; 96 97 desc = dmaengine_prep_slave_single(dma->chan, dma_buf, len, 98 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 99 if (!desc) { 100 ret = -EBUSY; 101 goto unmap; 102 } 103 104 desc->callback = stm32_timers_dma_done; 105 desc->callback_param = dma; 106 cookie = dmaengine_submit(desc); 107 ret = dma_submit_error(cookie); 108 if (ret) 109 goto dma_term; 110 111 reinit_completion(&dma->completion); 112 dma_async_issue_pending(dma->chan); 113 114 /* Setup and enable timer DMA burst mode */ 115 dbl = FIELD_PREP(TIM_DCR_DBL, bursts - 1); 116 dba = FIELD_PREP(TIM_DCR_DBA, reg >> 2); 117 ret = regmap_write(regmap, TIM_DCR, dbl | dba); 118 if (ret) 119 goto dma_term; 120 121 /* Clear pending flags before enabling DMA request */ 122 ret = regmap_write(regmap, TIM_SR, 0); 123 if (ret) 124 goto dcr_clr; 125 126 ret = regmap_update_bits(regmap, TIM_DIER, stm32_timers_dier_dmaen[id], 127 stm32_timers_dier_dmaen[id]); 128 if (ret) 129 goto dcr_clr; 130 131 err = wait_for_completion_interruptible_timeout(&dma->completion, 132 timeout); 133 if (err == 0) 134 ret = -ETIMEDOUT; 135 else if (err < 0) 136 ret = err; 137 138 regmap_update_bits(regmap, TIM_DIER, stm32_timers_dier_dmaen[id], 0); 139 regmap_write(regmap, TIM_SR, 0); 140 dcr_clr: 141 regmap_write(regmap, TIM_DCR, 0); 142 dma_term: 143 dmaengine_terminate_all(dma->chan); 144 unmap: 145 dma_unmap_single(dev, dma_buf, len, DMA_FROM_DEVICE); 146 unlock: 147 dma->chan = NULL; 148 mutex_unlock(&dma->lock); 149 150 return ret; 151 } 152 EXPORT_SYMBOL_GPL(stm32_timers_dma_burst_read); 153 154 static const struct regmap_config stm32_timers_regmap_cfg = { 155 .reg_bits = 32, 156 .val_bits = 32, 157 .reg_stride = sizeof(u32), 158 .max_register = STM32_TIMERS_MAX_REGISTERS, 159 }; 160 161 static void stm32_timers_get_arr_size(struct stm32_timers *ddata) 162 { 163 u32 arr; 164 165 /* Backup ARR to restore it after getting the maximum value */ 166 regmap_read(ddata->regmap, TIM_ARR, &arr); 167 168 /* 169 * Only the available bits will be written so when readback 170 * we get the maximum value of auto reload register 171 */ 172 regmap_write(ddata->regmap, TIM_ARR, ~0L); 173 regmap_read(ddata->regmap, TIM_ARR, &ddata->max_arr); 174 regmap_write(ddata->regmap, TIM_ARR, arr); 175 } 176 177 static int stm32_timers_probe_hwcfgr(struct device *dev, struct stm32_timers *ddata) 178 { 179 u32 val; 180 181 ddata->ipidr = (uintptr_t)device_get_match_data(dev); 182 if (!ddata->ipidr) { 183 /* Fallback to legacy method for probing counter width */ 184 stm32_timers_get_arr_size(ddata); 185 return 0; 186 } 187 188 regmap_read(ddata->regmap, TIM_IPIDR, &val); 189 if (val != ddata->ipidr) { 190 dev_err(dev, "Unsupported device detected: %u\n", val); 191 return -EINVAL; 192 } 193 194 regmap_read(ddata->regmap, TIM_HWCFGR2, &val); 195 196 /* Counter width in bits, max reload value is BIT(width) - 1 */ 197 ddata->max_arr = BIT(FIELD_GET(TIM_HWCFGR2_CNT_WIDTH, val)) - 1; 198 199 return 0; 200 } 201 202 static int stm32_timers_dma_probe(struct device *dev, 203 struct stm32_timers *ddata) 204 { 205 int i; 206 int ret = 0; 207 char name[4]; 208 209 init_completion(&ddata->dma.completion); 210 mutex_init(&ddata->dma.lock); 211 212 /* Optional DMA support: get valid DMA channel(s) or NULL */ 213 for (i = STM32_TIMERS_DMA_CH1; i <= STM32_TIMERS_DMA_CH4; i++) { 214 snprintf(name, ARRAY_SIZE(name), "ch%1d", i + 1); 215 ddata->dma.chans[i] = dma_request_chan(dev, name); 216 } 217 ddata->dma.chans[STM32_TIMERS_DMA_UP] = dma_request_chan(dev, "up"); 218 ddata->dma.chans[STM32_TIMERS_DMA_TRIG] = dma_request_chan(dev, "trig"); 219 ddata->dma.chans[STM32_TIMERS_DMA_COM] = dma_request_chan(dev, "com"); 220 221 for (i = STM32_TIMERS_DMA_CH1; i < STM32_TIMERS_MAX_DMAS; i++) { 222 if (IS_ERR(ddata->dma.chans[i])) { 223 /* Save the first error code to return */ 224 if (PTR_ERR(ddata->dma.chans[i]) != -ENODEV && !ret) 225 ret = PTR_ERR(ddata->dma.chans[i]); 226 227 ddata->dma.chans[i] = NULL; 228 } 229 } 230 231 return ret; 232 } 233 234 static void stm32_timers_dma_remove(struct device *dev, 235 struct stm32_timers *ddata) 236 { 237 int i; 238 239 for (i = STM32_TIMERS_DMA_CH1; i < STM32_TIMERS_MAX_DMAS; i++) 240 if (ddata->dma.chans[i]) 241 dma_release_channel(ddata->dma.chans[i]); 242 } 243 244 static const char * const stm32_timers_irq_name[STM32_TIMERS_MAX_IRQS] = { 245 "brk", "up", "trg-com", "cc" 246 }; 247 248 static int stm32_timers_irq_probe(struct platform_device *pdev, 249 struct stm32_timers *ddata) 250 { 251 int i, ret; 252 253 /* 254 * STM32 Timer may have either: 255 * - a unique global interrupt line 256 * - four dedicated interrupt lines that may be handled separately. 257 * Optionally get them here, to be used by child devices. 258 */ 259 ret = platform_get_irq_byname_optional(pdev, "global"); 260 if (ret < 0 && ret != -ENXIO) { 261 return ret; 262 } else if (ret != -ENXIO) { 263 ddata->irq[STM32_TIMERS_IRQ_GLOBAL_BRK] = ret; 264 ddata->nr_irqs = 1; 265 return 0; 266 } 267 268 for (i = 0; i < STM32_TIMERS_MAX_IRQS; i++) { 269 ret = platform_get_irq_byname_optional(pdev, stm32_timers_irq_name[i]); 270 if (ret < 0 && ret != -ENXIO) { 271 return ret; 272 } else if (ret != -ENXIO) { 273 ddata->irq[i] = ret; 274 ddata->nr_irqs++; 275 } 276 } 277 278 if (ddata->nr_irqs && ddata->nr_irqs != STM32_TIMERS_MAX_IRQS) { 279 dev_err(&pdev->dev, "Invalid number of IRQs %d\n", ddata->nr_irqs); 280 return -EINVAL; 281 } 282 283 return 0; 284 } 285 286 static int stm32_timers_probe(struct platform_device *pdev) 287 { 288 struct device *dev = &pdev->dev; 289 struct stm32_timers *ddata; 290 struct resource *res; 291 void __iomem *mmio; 292 int ret; 293 294 ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL); 295 if (!ddata) 296 return -ENOMEM; 297 298 mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 299 if (IS_ERR(mmio)) 300 return PTR_ERR(mmio); 301 302 /* Timer physical addr for DMA */ 303 ddata->dma.phys_base = res->start; 304 305 ddata->regmap = devm_regmap_init_mmio_clk(dev, "int", mmio, 306 &stm32_timers_regmap_cfg); 307 if (IS_ERR(ddata->regmap)) 308 return PTR_ERR(ddata->regmap); 309 310 ddata->clk = devm_clk_get(dev, NULL); 311 if (IS_ERR(ddata->clk)) 312 return PTR_ERR(ddata->clk); 313 314 ret = stm32_timers_probe_hwcfgr(dev, ddata); 315 if (ret) 316 return ret; 317 318 ret = stm32_timers_irq_probe(pdev, ddata); 319 if (ret) 320 return ret; 321 322 ret = stm32_timers_dma_probe(dev, ddata); 323 if (ret) { 324 stm32_timers_dma_remove(dev, ddata); 325 return ret; 326 } 327 328 platform_set_drvdata(pdev, ddata); 329 330 ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); 331 if (ret) 332 stm32_timers_dma_remove(dev, ddata); 333 334 return ret; 335 } 336 337 static void stm32_timers_remove(struct platform_device *pdev) 338 { 339 struct stm32_timers *ddata = platform_get_drvdata(pdev); 340 341 /* 342 * Don't use devm_ here: enfore of_platform_depopulate() happens before 343 * DMA are released, to avoid race on DMA. 344 */ 345 of_platform_depopulate(&pdev->dev); 346 stm32_timers_dma_remove(&pdev->dev, ddata); 347 } 348 349 static const struct of_device_id stm32_timers_of_match[] = { 350 { .compatible = "st,stm32-timers", }, 351 { .compatible = "st,stm32mp25-timers", .data = (void *)STM32MP25_TIM_IPIDR }, 352 { /* end node */ }, 353 }; 354 MODULE_DEVICE_TABLE(of, stm32_timers_of_match); 355 356 static struct platform_driver stm32_timers_driver = { 357 .probe = stm32_timers_probe, 358 .remove = stm32_timers_remove, 359 .driver = { 360 .name = "stm32-timers", 361 .of_match_table = stm32_timers_of_match, 362 }, 363 }; 364 module_platform_driver(stm32_timers_driver); 365 366 MODULE_DESCRIPTION("STMicroelectronics STM32 Timers"); 367 MODULE_LICENSE("GPL v2"); 368