1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2009-2013, The Linux Foundation. All rights reserved. 3 * Copyright (c) 2010, Google Inc. 4 * 5 * Original authors: Code Aurora Forum 6 * 7 * Author: Dima Zavin <dima@android.com> 8 * - Largely rewritten from original to not be an i2c driver. 9 */ 10 11 #define pr_fmt(fmt) "%s: " fmt, __func__ 12 13 #include <linux/delay.h> 14 #include <linux/err.h> 15 #include <linux/io.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_platform.h> 20 #include <linux/platform_device.h> 21 #include <linux/slab.h> 22 #include <linux/ssbi.h> 23 24 /* SSBI 2.0 controller registers */ 25 #define SSBI2_CMD 0x0008 26 #define SSBI2_RD 0x0010 27 #define SSBI2_STATUS 0x0014 28 #define SSBI2_MODE2 0x001C 29 30 /* SSBI_CMD fields */ 31 #define SSBI_CMD_RDWRN (1 << 24) 32 33 /* SSBI_STATUS fields */ 34 #define SSBI_STATUS_RD_READY (1 << 2) 35 #define SSBI_STATUS_READY (1 << 1) 36 #define SSBI_STATUS_MCHN_BUSY (1 << 0) 37 38 /* SSBI_MODE2 fields */ 39 #define SSBI_MODE2_REG_ADDR_15_8_SHFT 0x04 40 #define SSBI_MODE2_REG_ADDR_15_8_MASK (0x7f << SSBI_MODE2_REG_ADDR_15_8_SHFT) 41 42 #define SET_SSBI_MODE2_REG_ADDR_15_8(MD, AD) \ 43 (((MD) & 0x0F) | ((((AD) >> 8) << SSBI_MODE2_REG_ADDR_15_8_SHFT) & \ 44 SSBI_MODE2_REG_ADDR_15_8_MASK)) 45 46 /* SSBI PMIC Arbiter command registers */ 47 #define SSBI_PA_CMD 0x0000 48 #define SSBI_PA_RD_STATUS 0x0004 49 50 /* SSBI_PA_CMD fields */ 51 #define SSBI_PA_CMD_RDWRN (1 << 24) 52 #define SSBI_PA_CMD_ADDR_MASK 0x7fff /* REG_ADDR_7_0, REG_ADDR_8_14*/ 53 54 /* SSBI_PA_RD_STATUS fields */ 55 #define SSBI_PA_RD_STATUS_TRANS_DONE (1 << 27) 56 #define SSBI_PA_RD_STATUS_TRANS_DENIED (1 << 26) 57 58 #define SSBI_TIMEOUT_US 100 59 60 enum ssbi_controller_type { 61 MSM_SBI_CTRL_SSBI = 0, 62 MSM_SBI_CTRL_SSBI2, 63 MSM_SBI_CTRL_PMIC_ARBITER, 64 }; 65 66 struct ssbi { 67 void __iomem *base; 68 spinlock_t lock; 69 enum ssbi_controller_type controller_type; 70 int (*read)(struct ssbi *, u16 addr, u8 *buf, int len); 71 int (*write)(struct ssbi *, u16 addr, const u8 *buf, int len); 72 }; 73 74 static inline u32 ssbi_readl(struct ssbi *ssbi, u32 reg) 75 { 76 return readl(ssbi->base + reg); 77 } 78 79 static inline void ssbi_writel(struct ssbi *ssbi, u32 val, u32 reg) 80 { 81 writel(val, ssbi->base + reg); 82 } 83 84 /* 85 * Via private exchange with one of the original authors, the hardware 86 * should generally finish a transaction in about 5us. The worst 87 * case, is when using the arbiter and both other CPUs have just 88 * started trying to use the SSBI bus will result in a time of about 89 * 20us. It should never take longer than this. 90 * 91 * As such, this wait merely spins, with a udelay. 92 */ 93 static int ssbi_wait_mask(struct ssbi *ssbi, u32 set_mask, u32 clr_mask) 94 { 95 u32 timeout = SSBI_TIMEOUT_US; 96 u32 val; 97 98 while (timeout--) { 99 val = ssbi_readl(ssbi, SSBI2_STATUS); 100 if (((val & set_mask) == set_mask) && ((val & clr_mask) == 0)) 101 return 0; 102 udelay(1); 103 } 104 105 return -ETIMEDOUT; 106 } 107 108 static int 109 ssbi_read_bytes(struct ssbi *ssbi, u16 addr, u8 *buf, int len) 110 { 111 u32 cmd = SSBI_CMD_RDWRN | ((addr & 0xff) << 16); 112 int ret = 0; 113 114 if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) { 115 u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2); 116 mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr); 117 ssbi_writel(ssbi, mode2, SSBI2_MODE2); 118 } 119 120 while (len) { 121 ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0); 122 if (ret) 123 goto err; 124 125 ssbi_writel(ssbi, cmd, SSBI2_CMD); 126 ret = ssbi_wait_mask(ssbi, SSBI_STATUS_RD_READY, 0); 127 if (ret) 128 goto err; 129 *buf++ = ssbi_readl(ssbi, SSBI2_RD) & 0xff; 130 len--; 131 } 132 133 err: 134 return ret; 135 } 136 137 static int 138 ssbi_write_bytes(struct ssbi *ssbi, u16 addr, const u8 *buf, int len) 139 { 140 int ret = 0; 141 142 if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) { 143 u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2); 144 mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr); 145 ssbi_writel(ssbi, mode2, SSBI2_MODE2); 146 } 147 148 while (len) { 149 ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0); 150 if (ret) 151 goto err; 152 153 ssbi_writel(ssbi, ((addr & 0xff) << 16) | *buf, SSBI2_CMD); 154 ret = ssbi_wait_mask(ssbi, 0, SSBI_STATUS_MCHN_BUSY); 155 if (ret) 156 goto err; 157 buf++; 158 len--; 159 } 160 161 err: 162 return ret; 163 } 164 165 /* 166 * See ssbi_wait_mask for an explanation of the time and the 167 * busywait. 168 */ 169 static inline int 170 ssbi_pa_transfer(struct ssbi *ssbi, u32 cmd, u8 *data) 171 { 172 u32 timeout = SSBI_TIMEOUT_US; 173 u32 rd_status = 0; 174 175 ssbi_writel(ssbi, cmd, SSBI_PA_CMD); 176 177 while (timeout--) { 178 rd_status = ssbi_readl(ssbi, SSBI_PA_RD_STATUS); 179 180 if (rd_status & SSBI_PA_RD_STATUS_TRANS_DENIED) 181 return -EPERM; 182 183 if (rd_status & SSBI_PA_RD_STATUS_TRANS_DONE) { 184 if (data) 185 *data = rd_status & 0xff; 186 return 0; 187 } 188 udelay(1); 189 } 190 191 return -ETIMEDOUT; 192 } 193 194 static int 195 ssbi_pa_read_bytes(struct ssbi *ssbi, u16 addr, u8 *buf, int len) 196 { 197 u32 cmd; 198 int ret = 0; 199 200 cmd = SSBI_PA_CMD_RDWRN | (addr & SSBI_PA_CMD_ADDR_MASK) << 8; 201 202 while (len) { 203 ret = ssbi_pa_transfer(ssbi, cmd, buf); 204 if (ret) 205 goto err; 206 buf++; 207 len--; 208 } 209 210 err: 211 return ret; 212 } 213 214 static int 215 ssbi_pa_write_bytes(struct ssbi *ssbi, u16 addr, const u8 *buf, int len) 216 { 217 u32 cmd; 218 int ret = 0; 219 220 while (len) { 221 cmd = (addr & SSBI_PA_CMD_ADDR_MASK) << 8 | *buf; 222 ret = ssbi_pa_transfer(ssbi, cmd, NULL); 223 if (ret) 224 goto err; 225 buf++; 226 len--; 227 } 228 229 err: 230 return ret; 231 } 232 233 int ssbi_read(struct device *dev, u16 addr, u8 *buf, int len) 234 { 235 struct ssbi *ssbi = dev_get_drvdata(dev); 236 unsigned long flags; 237 int ret; 238 239 spin_lock_irqsave(&ssbi->lock, flags); 240 ret = ssbi->read(ssbi, addr, buf, len); 241 spin_unlock_irqrestore(&ssbi->lock, flags); 242 243 return ret; 244 } 245 EXPORT_SYMBOL_GPL(ssbi_read); 246 247 int ssbi_write(struct device *dev, u16 addr, const u8 *buf, int len) 248 { 249 struct ssbi *ssbi = dev_get_drvdata(dev); 250 unsigned long flags; 251 int ret; 252 253 spin_lock_irqsave(&ssbi->lock, flags); 254 ret = ssbi->write(ssbi, addr, buf, len); 255 spin_unlock_irqrestore(&ssbi->lock, flags); 256 257 return ret; 258 } 259 EXPORT_SYMBOL_GPL(ssbi_write); 260 261 static int ssbi_probe(struct platform_device *pdev) 262 { 263 struct device_node *np = pdev->dev.of_node; 264 struct ssbi *ssbi; 265 const char *type; 266 267 ssbi = devm_kzalloc(&pdev->dev, sizeof(*ssbi), GFP_KERNEL); 268 if (!ssbi) 269 return -ENOMEM; 270 271 ssbi->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 272 if (IS_ERR(ssbi->base)) 273 return PTR_ERR(ssbi->base); 274 275 platform_set_drvdata(pdev, ssbi); 276 277 type = of_get_property(np, "qcom,controller-type", NULL); 278 if (type == NULL) { 279 dev_err(&pdev->dev, "Missing qcom,controller-type property\n"); 280 return -EINVAL; 281 } 282 dev_info(&pdev->dev, "SSBI controller type: '%s'\n", type); 283 if (strcmp(type, "ssbi") == 0) 284 ssbi->controller_type = MSM_SBI_CTRL_SSBI; 285 else if (strcmp(type, "ssbi2") == 0) 286 ssbi->controller_type = MSM_SBI_CTRL_SSBI2; 287 else if (strcmp(type, "pmic-arbiter") == 0) 288 ssbi->controller_type = MSM_SBI_CTRL_PMIC_ARBITER; 289 else { 290 dev_err(&pdev->dev, "Unknown qcom,controller-type\n"); 291 return -EINVAL; 292 } 293 294 if (ssbi->controller_type == MSM_SBI_CTRL_PMIC_ARBITER) { 295 ssbi->read = ssbi_pa_read_bytes; 296 ssbi->write = ssbi_pa_write_bytes; 297 } else { 298 ssbi->read = ssbi_read_bytes; 299 ssbi->write = ssbi_write_bytes; 300 } 301 302 spin_lock_init(&ssbi->lock); 303 304 return devm_of_platform_populate(&pdev->dev); 305 } 306 307 static const struct of_device_id ssbi_match_table[] = { 308 { .compatible = "qcom,ssbi" }, 309 {} 310 }; 311 MODULE_DEVICE_TABLE(of, ssbi_match_table); 312 313 static struct platform_driver ssbi_driver = { 314 .probe = ssbi_probe, 315 .driver = { 316 .name = "ssbi", 317 .of_match_table = ssbi_match_table, 318 }, 319 }; 320 module_platform_driver(ssbi_driver); 321 322 MODULE_LICENSE("GPL v2"); 323 MODULE_VERSION("1.0"); 324 MODULE_ALIAS("platform:ssbi"); 325 MODULE_AUTHOR("Dima Zavin <dima@android.com>"); 326