1 // SPDX-License-Identifier: GPL-2.0-only 2 /* linux/drivers/mfd/sm501.c 3 * 4 * Copyright (C) 2006 Simtec Electronics 5 * Ben Dooks <ben@simtec.co.uk> 6 * Vincent Sanders <vince@simtec.co.uk> 7 * 8 * SM501 MFD driver 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/delay.h> 14 #include <linux/init.h> 15 #include <linux/list.h> 16 #include <linux/device.h> 17 #include <linux/platform_device.h> 18 #include <linux/pci.h> 19 #include <linux/platform_data/i2c-gpio.h> 20 #include <linux/gpio/driver.h> 21 #include <linux/gpio/machine.h> 22 #include <linux/slab.h> 23 24 #include <linux/sm501.h> 25 #include <linux/sm501-regs.h> 26 #include <linux/serial_8250.h> 27 28 #include <linux/io.h> 29 30 struct sm501_device { 31 struct list_head list; 32 struct platform_device pdev; 33 }; 34 35 struct sm501_gpio; 36 37 #ifdef CONFIG_MFD_SM501_GPIO 38 #include <linux/gpio.h> 39 40 struct sm501_gpio_chip { 41 struct gpio_chip gpio; 42 struct sm501_gpio *ourgpio; /* to get back to parent. */ 43 void __iomem *regbase; 44 void __iomem *control; /* address of control reg. */ 45 }; 46 47 struct sm501_gpio { 48 struct sm501_gpio_chip low; 49 struct sm501_gpio_chip high; 50 spinlock_t lock; 51 52 unsigned int registered : 1; 53 void __iomem *regs; 54 struct resource *regs_res; 55 }; 56 #else 57 struct sm501_gpio { 58 /* no gpio support, empty definition for sm501_devdata. */ 59 }; 60 #endif 61 62 struct sm501_devdata { 63 spinlock_t reg_lock; 64 struct mutex clock_lock; 65 struct list_head devices; 66 struct sm501_gpio gpio; 67 68 struct device *dev; 69 struct resource *io_res; 70 struct resource *mem_res; 71 struct resource *regs_claim; 72 struct sm501_platdata *platdata; 73 74 75 unsigned int in_suspend; 76 unsigned long pm_misc; 77 78 int unit_power[20]; 79 unsigned int pdev_id; 80 unsigned int irq; 81 void __iomem *regs; 82 unsigned int rev; 83 }; 84 85 86 #define MHZ (1000 * 1000) 87 88 #ifdef DEBUG 89 static const unsigned int div_tab[] = { 90 [0] = 1, 91 [1] = 2, 92 [2] = 4, 93 [3] = 8, 94 [4] = 16, 95 [5] = 32, 96 [6] = 64, 97 [7] = 128, 98 [8] = 3, 99 [9] = 6, 100 [10] = 12, 101 [11] = 24, 102 [12] = 48, 103 [13] = 96, 104 [14] = 192, 105 [15] = 384, 106 [16] = 5, 107 [17] = 10, 108 [18] = 20, 109 [19] = 40, 110 [20] = 80, 111 [21] = 160, 112 [22] = 320, 113 [23] = 604, 114 }; 115 116 static unsigned long decode_div(unsigned long pll2, unsigned long val, 117 unsigned int lshft, unsigned int selbit, 118 unsigned long mask) 119 { 120 if (val & selbit) 121 pll2 = 288 * MHZ; 122 123 return pll2 / div_tab[(val >> lshft) & mask]; 124 } 125 126 #define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x) 127 128 /* sm501_dump_clk 129 * 130 * Print out the current clock configuration for the device 131 */ 132 133 static void sm501_dump_clk(struct sm501_devdata *sm) 134 { 135 unsigned long misct = smc501_readl(sm->regs + SM501_MISC_TIMING); 136 unsigned long pm0 = smc501_readl(sm->regs + SM501_POWER_MODE_0_CLOCK); 137 unsigned long pm1 = smc501_readl(sm->regs + SM501_POWER_MODE_1_CLOCK); 138 unsigned long pmc = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); 139 unsigned long sdclk0, sdclk1; 140 unsigned long pll2 = 0; 141 142 switch (misct & 0x30) { 143 case 0x00: 144 pll2 = 336 * MHZ; 145 break; 146 case 0x10: 147 pll2 = 288 * MHZ; 148 break; 149 case 0x20: 150 pll2 = 240 * MHZ; 151 break; 152 case 0x30: 153 pll2 = 192 * MHZ; 154 break; 155 } 156 157 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; 158 sdclk0 /= div_tab[((misct >> 8) & 0xf)]; 159 160 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; 161 sdclk1 /= div_tab[((misct >> 16) & 0xf)]; 162 163 dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n", 164 misct, pm0, pm1); 165 166 dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n", 167 fmt_freq(pll2), sdclk0, sdclk1); 168 169 dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1); 170 171 dev_dbg(sm->dev, "PM0[%c]: " 172 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), " 173 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n", 174 (pmc & 3 ) == 0 ? '*' : '-', 175 fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)), 176 fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)), 177 fmt_freq(decode_div(pll2, pm0, 8, 1<<12, 15)), 178 fmt_freq(decode_div(pll2, pm0, 0, 1<<4, 15))); 179 180 dev_dbg(sm->dev, "PM1[%c]: " 181 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), " 182 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n", 183 (pmc & 3 ) == 1 ? '*' : '-', 184 fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)), 185 fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)), 186 fmt_freq(decode_div(pll2, pm1, 8, 1<<12, 15)), 187 fmt_freq(decode_div(pll2, pm1, 0, 1<<4, 15))); 188 } 189 190 static void sm501_dump_regs(struct sm501_devdata *sm) 191 { 192 void __iomem *regs = sm->regs; 193 194 dev_info(sm->dev, "System Control %08x\n", 195 smc501_readl(regs + SM501_SYSTEM_CONTROL)); 196 dev_info(sm->dev, "Misc Control %08x\n", 197 smc501_readl(regs + SM501_MISC_CONTROL)); 198 dev_info(sm->dev, "GPIO Control Low %08x\n", 199 smc501_readl(regs + SM501_GPIO31_0_CONTROL)); 200 dev_info(sm->dev, "GPIO Control Hi %08x\n", 201 smc501_readl(regs + SM501_GPIO63_32_CONTROL)); 202 dev_info(sm->dev, "DRAM Control %08x\n", 203 smc501_readl(regs + SM501_DRAM_CONTROL)); 204 dev_info(sm->dev, "Arbitration Ctrl %08x\n", 205 smc501_readl(regs + SM501_ARBTRTN_CONTROL)); 206 dev_info(sm->dev, "Misc Timing %08x\n", 207 smc501_readl(regs + SM501_MISC_TIMING)); 208 } 209 210 static void sm501_dump_gate(struct sm501_devdata *sm) 211 { 212 dev_info(sm->dev, "CurrentGate %08x\n", 213 smc501_readl(sm->regs + SM501_CURRENT_GATE)); 214 dev_info(sm->dev, "CurrentClock %08x\n", 215 smc501_readl(sm->regs + SM501_CURRENT_CLOCK)); 216 dev_info(sm->dev, "PowerModeControl %08x\n", 217 smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL)); 218 } 219 220 #else 221 static inline void sm501_dump_gate(struct sm501_devdata *sm) { } 222 static inline void sm501_dump_regs(struct sm501_devdata *sm) { } 223 static inline void sm501_dump_clk(struct sm501_devdata *sm) { } 224 #endif 225 226 /* sm501_sync_regs 227 * 228 * ensure the 229 */ 230 231 static void sm501_sync_regs(struct sm501_devdata *sm) 232 { 233 smc501_readl(sm->regs); 234 } 235 236 static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay) 237 { 238 /* during suspend/resume, we are currently not allowed to sleep, 239 * so change to using mdelay() instead of msleep() if we 240 * are in one of these paths */ 241 242 if (sm->in_suspend) 243 mdelay(delay); 244 else 245 msleep(delay); 246 } 247 248 /* sm501_misc_control 249 * 250 * alters the miscellaneous control parameters 251 */ 252 253 int sm501_misc_control(struct device *dev, 254 unsigned long set, unsigned long clear) 255 { 256 struct sm501_devdata *sm = dev_get_drvdata(dev); 257 unsigned long misc; 258 unsigned long save; 259 unsigned long to; 260 261 spin_lock_irqsave(&sm->reg_lock, save); 262 263 misc = smc501_readl(sm->regs + SM501_MISC_CONTROL); 264 to = (misc & ~clear) | set; 265 266 if (to != misc) { 267 smc501_writel(to, sm->regs + SM501_MISC_CONTROL); 268 sm501_sync_regs(sm); 269 270 dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc); 271 } 272 273 spin_unlock_irqrestore(&sm->reg_lock, save); 274 return to; 275 } 276 277 EXPORT_SYMBOL_GPL(sm501_misc_control); 278 279 /* sm501_modify_reg 280 * 281 * Modify a register in the SM501 which may be shared with other 282 * drivers. 283 */ 284 285 unsigned long sm501_modify_reg(struct device *dev, 286 unsigned long reg, 287 unsigned long set, 288 unsigned long clear) 289 { 290 struct sm501_devdata *sm = dev_get_drvdata(dev); 291 unsigned long data; 292 unsigned long save; 293 294 spin_lock_irqsave(&sm->reg_lock, save); 295 296 data = smc501_readl(sm->regs + reg); 297 data |= set; 298 data &= ~clear; 299 300 smc501_writel(data, sm->regs + reg); 301 sm501_sync_regs(sm); 302 303 spin_unlock_irqrestore(&sm->reg_lock, save); 304 305 return data; 306 } 307 308 EXPORT_SYMBOL_GPL(sm501_modify_reg); 309 310 /* sm501_unit_power 311 * 312 * alters the power active gate to set specific units on or off 313 */ 314 315 int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to) 316 { 317 struct sm501_devdata *sm = dev_get_drvdata(dev); 318 unsigned long mode; 319 unsigned long gate; 320 unsigned long clock; 321 322 mutex_lock(&sm->clock_lock); 323 324 mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); 325 gate = smc501_readl(sm->regs + SM501_CURRENT_GATE); 326 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK); 327 328 mode &= 3; /* get current power mode */ 329 330 if (unit >= ARRAY_SIZE(sm->unit_power)) { 331 dev_err(dev, "%s: bad unit %d\n", __func__, unit); 332 goto already; 333 } 334 335 dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit, 336 sm->unit_power[unit], to); 337 338 if (to == 0 && sm->unit_power[unit] == 0) { 339 dev_err(sm->dev, "unit %d is already shutdown\n", unit); 340 goto already; 341 } 342 343 sm->unit_power[unit] += to ? 1 : -1; 344 to = sm->unit_power[unit] ? 1 : 0; 345 346 if (to) { 347 if (gate & (1 << unit)) 348 goto already; 349 gate |= (1 << unit); 350 } else { 351 if (!(gate & (1 << unit))) 352 goto already; 353 gate &= ~(1 << unit); 354 } 355 356 switch (mode) { 357 case 1: 358 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE); 359 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK); 360 mode = 0; 361 break; 362 case 2: 363 case 0: 364 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE); 365 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK); 366 mode = 1; 367 break; 368 369 default: 370 gate = -1; 371 goto already; 372 } 373 374 smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL); 375 sm501_sync_regs(sm); 376 377 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n", 378 gate, clock, mode); 379 380 sm501_mdelay(sm, 16); 381 382 already: 383 mutex_unlock(&sm->clock_lock); 384 return gate; 385 } 386 387 EXPORT_SYMBOL_GPL(sm501_unit_power); 388 389 /* clock value structure. */ 390 struct sm501_clock { 391 unsigned long mclk; 392 int divider; 393 int shift; 394 unsigned int m, n, k; 395 }; 396 397 /* sm501_calc_clock 398 * 399 * Calculates the nearest discrete clock frequency that 400 * can be achieved with the specified input clock. 401 * the maximum divisor is 3 or 5 402 */ 403 404 static int sm501_calc_clock(unsigned long freq, 405 struct sm501_clock *clock, 406 int max_div, 407 unsigned long mclk, 408 long *best_diff) 409 { 410 int ret = 0; 411 int divider; 412 int shift; 413 long diff; 414 415 /* try dividers 1 and 3 for CRT and for panel, 416 try divider 5 for panel only.*/ 417 418 for (divider = 1; divider <= max_div; divider += 2) { 419 /* try all 8 shift values.*/ 420 for (shift = 0; shift < 8; shift++) { 421 /* Calculate difference to requested clock */ 422 diff = DIV_ROUND_CLOSEST(mclk, divider << shift) - freq; 423 if (diff < 0) 424 diff = -diff; 425 426 /* If it is less than the current, use it */ 427 if (diff < *best_diff) { 428 *best_diff = diff; 429 430 clock->mclk = mclk; 431 clock->divider = divider; 432 clock->shift = shift; 433 ret = 1; 434 } 435 } 436 } 437 438 return ret; 439 } 440 441 /* sm501_calc_pll 442 * 443 * Calculates the nearest discrete clock frequency that can be 444 * achieved using the programmable PLL. 445 * the maximum divisor is 3 or 5 446 */ 447 448 static unsigned long sm501_calc_pll(unsigned long freq, 449 struct sm501_clock *clock, 450 int max_div) 451 { 452 unsigned long mclk; 453 unsigned int m, n, k; 454 long best_diff = 999999999; 455 456 /* 457 * The SM502 datasheet doesn't specify the min/max values for M and N. 458 * N = 1 at least doesn't work in practice. 459 */ 460 for (m = 2; m <= 255; m++) { 461 for (n = 2; n <= 127; n++) { 462 for (k = 0; k <= 1; k++) { 463 mclk = (24000000UL * m / n) >> k; 464 465 if (sm501_calc_clock(freq, clock, max_div, 466 mclk, &best_diff)) { 467 clock->m = m; 468 clock->n = n; 469 clock->k = k; 470 } 471 } 472 } 473 } 474 475 /* Return best clock. */ 476 return clock->mclk / (clock->divider << clock->shift); 477 } 478 479 /* sm501_select_clock 480 * 481 * Calculates the nearest discrete clock frequency that can be 482 * achieved using the 288MHz and 336MHz PLLs. 483 * the maximum divisor is 3 or 5 484 */ 485 486 static unsigned long sm501_select_clock(unsigned long freq, 487 struct sm501_clock *clock, 488 int max_div) 489 { 490 unsigned long mclk; 491 long best_diff = 999999999; 492 493 /* Try 288MHz and 336MHz clocks. */ 494 for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) { 495 sm501_calc_clock(freq, clock, max_div, mclk, &best_diff); 496 } 497 498 /* Return best clock. */ 499 return clock->mclk / (clock->divider << clock->shift); 500 } 501 502 /* sm501_set_clock 503 * 504 * set one of the four clock sources to the closest available frequency to 505 * the one specified 506 */ 507 508 unsigned long sm501_set_clock(struct device *dev, 509 int clksrc, 510 unsigned long req_freq) 511 { 512 struct sm501_devdata *sm = dev_get_drvdata(dev); 513 unsigned long mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); 514 unsigned long gate = smc501_readl(sm->regs + SM501_CURRENT_GATE); 515 unsigned long clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK); 516 unsigned int pll_reg = 0; 517 unsigned long sm501_freq; /* the actual frequency achieved */ 518 u64 reg; 519 520 struct sm501_clock to; 521 522 /* find achivable discrete frequency and setup register value 523 * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK 524 * has an extra bit for the divider */ 525 526 switch (clksrc) { 527 case SM501_CLOCK_P2XCLK: 528 /* This clock is divided in half so to achieve the 529 * requested frequency the value must be multiplied by 530 * 2. This clock also has an additional pre divisor */ 531 532 if (sm->rev >= 0xC0) { 533 /* SM502 -> use the programmable PLL */ 534 sm501_freq = (sm501_calc_pll(2 * req_freq, 535 &to, 5) / 2); 536 reg = to.shift & 0x07;/* bottom 3 bits are shift */ 537 if (to.divider == 3) 538 reg |= 0x08; /* /3 divider required */ 539 else if (to.divider == 5) 540 reg |= 0x10; /* /5 divider required */ 541 reg |= 0x40; /* select the programmable PLL */ 542 pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m; 543 } else { 544 sm501_freq = (sm501_select_clock(2 * req_freq, 545 &to, 5) / 2); 546 reg = to.shift & 0x07;/* bottom 3 bits are shift */ 547 if (to.divider == 3) 548 reg |= 0x08; /* /3 divider required */ 549 else if (to.divider == 5) 550 reg |= 0x10; /* /5 divider required */ 551 if (to.mclk != 288000000) 552 reg |= 0x20; /* which mclk pll is source */ 553 } 554 break; 555 556 case SM501_CLOCK_V2XCLK: 557 /* This clock is divided in half so to achieve the 558 * requested frequency the value must be multiplied by 2. */ 559 560 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2); 561 reg=to.shift & 0x07; /* bottom 3 bits are shift */ 562 if (to.divider == 3) 563 reg |= 0x08; /* /3 divider required */ 564 if (to.mclk != 288000000) 565 reg |= 0x10; /* which mclk pll is source */ 566 break; 567 568 case SM501_CLOCK_MCLK: 569 case SM501_CLOCK_M1XCLK: 570 /* These clocks are the same and not further divided */ 571 572 sm501_freq = sm501_select_clock( req_freq, &to, 3); 573 reg=to.shift & 0x07; /* bottom 3 bits are shift */ 574 if (to.divider == 3) 575 reg |= 0x08; /* /3 divider required */ 576 if (to.mclk != 288000000) 577 reg |= 0x10; /* which mclk pll is source */ 578 break; 579 580 default: 581 return 0; /* this is bad */ 582 } 583 584 mutex_lock(&sm->clock_lock); 585 586 mode = smc501_readl(sm->regs + SM501_POWER_MODE_CONTROL); 587 gate = smc501_readl(sm->regs + SM501_CURRENT_GATE); 588 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK); 589 590 clock = clock & ~(0xFF << clksrc); 591 clock |= reg<<clksrc; 592 593 mode &= 3; /* find current mode */ 594 595 switch (mode) { 596 case 1: 597 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE); 598 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK); 599 mode = 0; 600 break; 601 case 2: 602 case 0: 603 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE); 604 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK); 605 mode = 1; 606 break; 607 608 default: 609 mutex_unlock(&sm->clock_lock); 610 return -1; 611 } 612 613 smc501_writel(mode, sm->regs + SM501_POWER_MODE_CONTROL); 614 615 if (pll_reg) 616 smc501_writel(pll_reg, 617 sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL); 618 619 sm501_sync_regs(sm); 620 621 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n", 622 gate, clock, mode); 623 624 sm501_mdelay(sm, 16); 625 mutex_unlock(&sm->clock_lock); 626 627 sm501_dump_clk(sm); 628 629 return sm501_freq; 630 } 631 632 EXPORT_SYMBOL_GPL(sm501_set_clock); 633 634 static struct sm501_device *to_sm_device(struct platform_device *pdev) 635 { 636 return container_of(pdev, struct sm501_device, pdev); 637 } 638 639 /* sm501_device_release 640 * 641 * A release function for the platform devices we create to allow us to 642 * free any items we allocated 643 */ 644 645 static void sm501_device_release(struct device *dev) 646 { 647 kfree(to_sm_device(to_platform_device(dev))); 648 } 649 650 /* sm501_create_subdev 651 * 652 * Create a skeleton platform device with resources for passing to a 653 * sub-driver 654 */ 655 656 static struct platform_device * 657 sm501_create_subdev(struct sm501_devdata *sm, char *name, 658 unsigned int res_count, unsigned int platform_data_size) 659 { 660 struct sm501_device *smdev; 661 662 smdev = kzalloc(sizeof(struct sm501_device) + 663 (sizeof(struct resource) * res_count) + 664 platform_data_size, GFP_KERNEL); 665 if (!smdev) 666 return NULL; 667 668 smdev->pdev.dev.release = sm501_device_release; 669 670 smdev->pdev.name = name; 671 smdev->pdev.id = sm->pdev_id; 672 smdev->pdev.dev.parent = sm->dev; 673 smdev->pdev.dev.coherent_dma_mask = 0xffffffff; 674 675 if (res_count) { 676 smdev->pdev.resource = (struct resource *)(smdev+1); 677 smdev->pdev.num_resources = res_count; 678 } 679 if (platform_data_size) 680 smdev->pdev.dev.platform_data = (void *)(smdev+1); 681 682 return &smdev->pdev; 683 } 684 685 /* sm501_register_device 686 * 687 * Register a platform device created with sm501_create_subdev() 688 */ 689 690 static int sm501_register_device(struct sm501_devdata *sm, 691 struct platform_device *pdev) 692 { 693 struct sm501_device *smdev = to_sm_device(pdev); 694 int ptr; 695 int ret; 696 697 for (ptr = 0; ptr < pdev->num_resources; ptr++) { 698 printk(KERN_DEBUG "%s[%d] %pR\n", 699 pdev->name, ptr, &pdev->resource[ptr]); 700 } 701 702 ret = platform_device_register(pdev); 703 704 if (ret >= 0) { 705 dev_dbg(sm->dev, "registered %s\n", pdev->name); 706 list_add_tail(&smdev->list, &sm->devices); 707 } else { 708 dev_err(sm->dev, "error registering %s (%d)\n", 709 pdev->name, ret); 710 platform_device_put(pdev); 711 } 712 713 return ret; 714 } 715 716 /* sm501_create_subio 717 * 718 * Fill in an IO resource for a sub device 719 */ 720 721 static void sm501_create_subio(struct sm501_devdata *sm, 722 struct resource *res, 723 resource_size_t offs, 724 resource_size_t size) 725 { 726 res->flags = IORESOURCE_MEM; 727 res->parent = sm->io_res; 728 res->start = sm->io_res->start + offs; 729 res->end = res->start + size - 1; 730 } 731 732 /* sm501_create_mem 733 * 734 * Fill in an MEM resource for a sub device 735 */ 736 737 static void sm501_create_mem(struct sm501_devdata *sm, 738 struct resource *res, 739 resource_size_t *offs, 740 resource_size_t size) 741 { 742 *offs -= size; /* adjust memory size */ 743 744 res->flags = IORESOURCE_MEM; 745 res->parent = sm->mem_res; 746 res->start = sm->mem_res->start + *offs; 747 res->end = res->start + size - 1; 748 } 749 750 /* sm501_create_irq 751 * 752 * Fill in an IRQ resource for a sub device 753 */ 754 755 static void sm501_create_irq(struct sm501_devdata *sm, 756 struct resource *res) 757 { 758 res->flags = IORESOURCE_IRQ; 759 res->parent = NULL; 760 res->start = res->end = sm->irq; 761 } 762 763 static int sm501_register_usbhost(struct sm501_devdata *sm, 764 resource_size_t *mem_avail) 765 { 766 struct platform_device *pdev; 767 768 pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0); 769 if (!pdev) 770 return -ENOMEM; 771 772 sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000); 773 sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024); 774 sm501_create_irq(sm, &pdev->resource[2]); 775 776 return sm501_register_device(sm, pdev); 777 } 778 779 static void sm501_setup_uart_data(struct sm501_devdata *sm, 780 struct plat_serial8250_port *uart_data, 781 unsigned int offset) 782 { 783 uart_data->membase = sm->regs + offset; 784 uart_data->mapbase = sm->io_res->start + offset; 785 uart_data->iotype = UPIO_MEM; 786 uart_data->irq = sm->irq; 787 uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ; 788 uart_data->regshift = 2; 789 uart_data->uartclk = (9600 * 16); 790 } 791 792 static int sm501_register_uart(struct sm501_devdata *sm, int devices) 793 { 794 struct platform_device *pdev; 795 struct plat_serial8250_port *uart_data; 796 797 pdev = sm501_create_subdev(sm, "serial8250", 0, 798 sizeof(struct plat_serial8250_port) * 3); 799 if (!pdev) 800 return -ENOMEM; 801 802 uart_data = dev_get_platdata(&pdev->dev); 803 804 if (devices & SM501_USE_UART0) { 805 sm501_setup_uart_data(sm, uart_data++, 0x30000); 806 sm501_unit_power(sm->dev, SM501_GATE_UART0, 1); 807 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0); 808 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0); 809 } 810 if (devices & SM501_USE_UART1) { 811 sm501_setup_uart_data(sm, uart_data++, 0x30020); 812 sm501_unit_power(sm->dev, SM501_GATE_UART1, 1); 813 sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0); 814 sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0); 815 } 816 817 pdev->id = PLAT8250_DEV_SM501; 818 819 return sm501_register_device(sm, pdev); 820 } 821 822 static int sm501_register_display(struct sm501_devdata *sm, 823 resource_size_t *mem_avail) 824 { 825 struct platform_device *pdev; 826 827 pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0); 828 if (!pdev) 829 return -ENOMEM; 830 831 sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000); 832 sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000); 833 sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail); 834 sm501_create_irq(sm, &pdev->resource[3]); 835 836 return sm501_register_device(sm, pdev); 837 } 838 839 #ifdef CONFIG_MFD_SM501_GPIO 840 841 static inline struct sm501_devdata *sm501_gpio_to_dev(struct sm501_gpio *gpio) 842 { 843 return container_of(gpio, struct sm501_devdata, gpio); 844 } 845 846 static int sm501_gpio_get(struct gpio_chip *chip, unsigned offset) 847 848 { 849 struct sm501_gpio_chip *smgpio = gpiochip_get_data(chip); 850 unsigned long result; 851 852 result = smc501_readl(smgpio->regbase + SM501_GPIO_DATA_LOW); 853 result >>= offset; 854 855 return result & 1UL; 856 } 857 858 static void sm501_gpio_ensure_gpio(struct sm501_gpio_chip *smchip, 859 unsigned long bit) 860 { 861 unsigned long ctrl; 862 863 /* check and modify if this pin is not set as gpio. */ 864 865 if (smc501_readl(smchip->control) & bit) { 866 dev_info(sm501_gpio_to_dev(smchip->ourgpio)->dev, 867 "changing mode of gpio, bit %08lx\n", bit); 868 869 ctrl = smc501_readl(smchip->control); 870 ctrl &= ~bit; 871 smc501_writel(ctrl, smchip->control); 872 873 sm501_sync_regs(sm501_gpio_to_dev(smchip->ourgpio)); 874 } 875 } 876 877 static int sm501_gpio_set(struct gpio_chip *chip, unsigned int offset, 878 int value) 879 880 { 881 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip); 882 struct sm501_gpio *smgpio = smchip->ourgpio; 883 unsigned long bit = BIT(offset); 884 void __iomem *regs = smchip->regbase; 885 unsigned long save; 886 unsigned long val; 887 888 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n", 889 __func__, chip, offset); 890 891 spin_lock_irqsave(&smgpio->lock, save); 892 893 val = smc501_readl(regs + SM501_GPIO_DATA_LOW) & ~bit; 894 if (value) 895 val |= bit; 896 smc501_writel(val, regs); 897 898 sm501_sync_regs(sm501_gpio_to_dev(smgpio)); 899 sm501_gpio_ensure_gpio(smchip, bit); 900 901 spin_unlock_irqrestore(&smgpio->lock, save); 902 903 return 0; 904 } 905 906 static int sm501_gpio_input(struct gpio_chip *chip, unsigned offset) 907 { 908 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip); 909 struct sm501_gpio *smgpio = smchip->ourgpio; 910 void __iomem *regs = smchip->regbase; 911 unsigned long bit = BIT(offset); 912 unsigned long save; 913 unsigned long ddr; 914 915 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d)\n", 916 __func__, chip, offset); 917 918 spin_lock_irqsave(&smgpio->lock, save); 919 920 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW); 921 smc501_writel(ddr & ~bit, regs + SM501_GPIO_DDR_LOW); 922 923 sm501_sync_regs(sm501_gpio_to_dev(smgpio)); 924 sm501_gpio_ensure_gpio(smchip, bit); 925 926 spin_unlock_irqrestore(&smgpio->lock, save); 927 928 return 0; 929 } 930 931 static int sm501_gpio_output(struct gpio_chip *chip, 932 unsigned offset, int value) 933 { 934 struct sm501_gpio_chip *smchip = gpiochip_get_data(chip); 935 struct sm501_gpio *smgpio = smchip->ourgpio; 936 unsigned long bit = BIT(offset); 937 void __iomem *regs = smchip->regbase; 938 unsigned long save; 939 unsigned long val; 940 unsigned long ddr; 941 942 dev_dbg(sm501_gpio_to_dev(smgpio)->dev, "%s(%p,%d,%d)\n", 943 __func__, chip, offset, value); 944 945 spin_lock_irqsave(&smgpio->lock, save); 946 947 val = smc501_readl(regs + SM501_GPIO_DATA_LOW); 948 if (value) 949 val |= bit; 950 else 951 val &= ~bit; 952 smc501_writel(val, regs); 953 954 ddr = smc501_readl(regs + SM501_GPIO_DDR_LOW); 955 smc501_writel(ddr | bit, regs + SM501_GPIO_DDR_LOW); 956 957 sm501_sync_regs(sm501_gpio_to_dev(smgpio)); 958 smc501_writel(val, regs + SM501_GPIO_DATA_LOW); 959 960 sm501_sync_regs(sm501_gpio_to_dev(smgpio)); 961 spin_unlock_irqrestore(&smgpio->lock, save); 962 963 return 0; 964 } 965 966 static const struct gpio_chip gpio_chip_template = { 967 .ngpio = 32, 968 .direction_input = sm501_gpio_input, 969 .direction_output = sm501_gpio_output, 970 .set = sm501_gpio_set, 971 .get = sm501_gpio_get, 972 }; 973 974 static int sm501_gpio_register_chip(struct sm501_devdata *sm, 975 struct sm501_gpio *gpio, 976 struct sm501_gpio_chip *chip) 977 { 978 struct sm501_platdata *pdata = sm->platdata; 979 struct gpio_chip *gchip = &chip->gpio; 980 int base = pdata->gpio_base; 981 982 chip->gpio = gpio_chip_template; 983 984 if (chip == &gpio->high) { 985 if (base > 0) 986 base += 32; 987 chip->regbase = gpio->regs + SM501_GPIO_DATA_HIGH; 988 chip->control = sm->regs + SM501_GPIO63_32_CONTROL; 989 gchip->label = "SM501-HIGH"; 990 } else { 991 chip->regbase = gpio->regs + SM501_GPIO_DATA_LOW; 992 chip->control = sm->regs + SM501_GPIO31_0_CONTROL; 993 gchip->label = "SM501-LOW"; 994 } 995 996 gchip->base = base; 997 chip->ourgpio = gpio; 998 999 return gpiochip_add_data(gchip, chip); 1000 } 1001 1002 static int sm501_register_gpio(struct sm501_devdata *sm) 1003 { 1004 struct sm501_gpio *gpio = &sm->gpio; 1005 resource_size_t iobase = sm->io_res->start + SM501_GPIO; 1006 int ret; 1007 1008 dev_dbg(sm->dev, "registering gpio block %08llx\n", 1009 (unsigned long long)iobase); 1010 1011 spin_lock_init(&gpio->lock); 1012 1013 gpio->regs_res = request_mem_region(iobase, 0x20, "sm501-gpio"); 1014 if (!gpio->regs_res) { 1015 dev_err(sm->dev, "gpio: failed to request region\n"); 1016 return -ENXIO; 1017 } 1018 1019 gpio->regs = ioremap(iobase, 0x20); 1020 if (!gpio->regs) { 1021 dev_err(sm->dev, "gpio: failed to remap registers\n"); 1022 ret = -ENXIO; 1023 goto err_claimed; 1024 } 1025 1026 /* Register both our chips. */ 1027 1028 ret = sm501_gpio_register_chip(sm, gpio, &gpio->low); 1029 if (ret) { 1030 dev_err(sm->dev, "failed to add low chip\n"); 1031 goto err_mapped; 1032 } 1033 1034 ret = sm501_gpio_register_chip(sm, gpio, &gpio->high); 1035 if (ret) { 1036 dev_err(sm->dev, "failed to add high chip\n"); 1037 goto err_low_chip; 1038 } 1039 1040 gpio->registered = 1; 1041 1042 return 0; 1043 1044 err_low_chip: 1045 gpiochip_remove(&gpio->low.gpio); 1046 1047 err_mapped: 1048 iounmap(gpio->regs); 1049 1050 err_claimed: 1051 release_mem_region(iobase, 0x20); 1052 1053 return ret; 1054 } 1055 1056 static void sm501_gpio_remove(struct sm501_devdata *sm) 1057 { 1058 struct sm501_gpio *gpio = &sm->gpio; 1059 resource_size_t iobase = sm->io_res->start + SM501_GPIO; 1060 1061 if (!sm->gpio.registered) 1062 return; 1063 1064 gpiochip_remove(&gpio->low.gpio); 1065 gpiochip_remove(&gpio->high.gpio); 1066 1067 iounmap(gpio->regs); 1068 release_mem_region(iobase, 0x20); 1069 } 1070 1071 static inline int sm501_gpio_isregistered(struct sm501_devdata *sm) 1072 { 1073 return sm->gpio.registered; 1074 } 1075 #else 1076 static inline int sm501_register_gpio(struct sm501_devdata *sm) 1077 { 1078 return 0; 1079 } 1080 1081 static inline void sm501_gpio_remove(struct sm501_devdata *sm) 1082 { 1083 } 1084 1085 static inline int sm501_gpio_isregistered(struct sm501_devdata *sm) 1086 { 1087 return 0; 1088 } 1089 #endif 1090 1091 static int sm501_register_gpio_i2c_instance(struct sm501_devdata *sm, 1092 struct sm501_platdata_gpio_i2c *iic) 1093 { 1094 struct i2c_gpio_platform_data *icd; 1095 struct platform_device *pdev; 1096 struct gpiod_lookup_table *lookup; 1097 1098 pdev = sm501_create_subdev(sm, "i2c-gpio", 0, 1099 sizeof(struct i2c_gpio_platform_data)); 1100 if (!pdev) 1101 return -ENOMEM; 1102 1103 /* Create a gpiod lookup using gpiochip-local offsets */ 1104 lookup = devm_kzalloc(&pdev->dev, struct_size(lookup, table, 3), 1105 GFP_KERNEL); 1106 if (!lookup) 1107 return -ENOMEM; 1108 1109 lookup->dev_id = "i2c-gpio"; 1110 lookup->table[0] = (struct gpiod_lookup) 1111 GPIO_LOOKUP_IDX(iic->pin_sda < 32 ? "SM501-LOW" : "SM501-HIGH", 1112 iic->pin_sda % 32, NULL, 0, 1113 GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN); 1114 lookup->table[1] = (struct gpiod_lookup) 1115 GPIO_LOOKUP_IDX(iic->pin_scl < 32 ? "SM501-LOW" : "SM501-HIGH", 1116 iic->pin_scl % 32, NULL, 1, 1117 GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN); 1118 gpiod_add_lookup_table(lookup); 1119 1120 icd = dev_get_platdata(&pdev->dev); 1121 icd->timeout = iic->timeout; 1122 icd->udelay = iic->udelay; 1123 1124 /* note, we can't use either of the pin numbers, as the i2c-gpio 1125 * driver uses the platform.id field to generate the bus number 1126 * to register with the i2c core; The i2c core doesn't have enough 1127 * entries to deal with anything we currently use. 1128 */ 1129 1130 pdev->id = iic->bus_num; 1131 1132 dev_info(sm->dev, "registering i2c-%d: sda=%d, scl=%d\n", 1133 iic->bus_num, 1134 iic->pin_sda, iic->pin_scl); 1135 1136 return sm501_register_device(sm, pdev); 1137 } 1138 1139 static int sm501_register_gpio_i2c(struct sm501_devdata *sm, 1140 struct sm501_platdata *pdata) 1141 { 1142 struct sm501_platdata_gpio_i2c *iic = pdata->gpio_i2c; 1143 int index; 1144 int ret; 1145 1146 for (index = 0; index < pdata->gpio_i2c_nr; index++, iic++) { 1147 ret = sm501_register_gpio_i2c_instance(sm, iic); 1148 if (ret < 0) 1149 return ret; 1150 } 1151 1152 return 0; 1153 } 1154 1155 /* dbg_regs_show 1156 * 1157 * Debug attribute to attach to parent device to show core registers 1158 */ 1159 1160 static ssize_t dbg_regs_show(struct device *dev, 1161 struct device_attribute *attr, char *buff) 1162 { 1163 struct sm501_devdata *sm = dev_get_drvdata(dev) ; 1164 unsigned int reg; 1165 char *ptr = buff; 1166 int ret; 1167 1168 for (reg = 0x00; reg < 0x70; reg += 4) { 1169 ret = sprintf(ptr, "%08x = %08x\n", 1170 reg, smc501_readl(sm->regs + reg)); 1171 ptr += ret; 1172 } 1173 1174 return ptr - buff; 1175 } 1176 1177 1178 static DEVICE_ATTR_RO(dbg_regs); 1179 1180 /* sm501_init_reg 1181 * 1182 * Helper function for the init code to setup a register 1183 * 1184 * clear the bits which are set in r->mask, and then set 1185 * the bits set in r->set. 1186 */ 1187 1188 static inline void sm501_init_reg(struct sm501_devdata *sm, 1189 unsigned long reg, 1190 struct sm501_reg_init *r) 1191 { 1192 unsigned long tmp; 1193 1194 tmp = smc501_readl(sm->regs + reg); 1195 tmp &= ~r->mask; 1196 tmp |= r->set; 1197 smc501_writel(tmp, sm->regs + reg); 1198 } 1199 1200 /* sm501_init_regs 1201 * 1202 * Setup core register values 1203 */ 1204 1205 static void sm501_init_regs(struct sm501_devdata *sm, 1206 struct sm501_initdata *init) 1207 { 1208 sm501_misc_control(sm->dev, 1209 init->misc_control.set, 1210 init->misc_control.mask); 1211 1212 sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing); 1213 sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low); 1214 sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high); 1215 1216 if (init->m1xclk) { 1217 dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk); 1218 sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk); 1219 } 1220 1221 if (init->mclk) { 1222 dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk); 1223 sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk); 1224 } 1225 1226 } 1227 1228 /* Check the PLL sources for the M1CLK and M1XCLK 1229 * 1230 * If the M1CLK and M1XCLKs are not sourced from the same PLL, then 1231 * there is a risk (see errata AB-5) that the SM501 will cease proper 1232 * function. If this happens, then it is likely the SM501 will 1233 * hang the system. 1234 */ 1235 1236 static int sm501_check_clocks(struct sm501_devdata *sm) 1237 { 1238 unsigned long pwrmode = smc501_readl(sm->regs + SM501_CURRENT_CLOCK); 1239 unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC); 1240 unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC); 1241 1242 return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0)); 1243 } 1244 1245 static unsigned int sm501_mem_local[] = { 1246 [0] = 4*1024*1024, 1247 [1] = 8*1024*1024, 1248 [2] = 16*1024*1024, 1249 [3] = 32*1024*1024, 1250 [4] = 64*1024*1024, 1251 [5] = 2*1024*1024, 1252 }; 1253 1254 /* sm501_init_dev 1255 * 1256 * Common init code for an SM501 1257 */ 1258 1259 static int sm501_init_dev(struct sm501_devdata *sm) 1260 { 1261 struct sm501_initdata *idata; 1262 struct sm501_platdata *pdata; 1263 resource_size_t mem_avail; 1264 unsigned long dramctrl; 1265 unsigned long devid; 1266 int ret; 1267 1268 mutex_init(&sm->clock_lock); 1269 spin_lock_init(&sm->reg_lock); 1270 1271 INIT_LIST_HEAD(&sm->devices); 1272 1273 devid = smc501_readl(sm->regs + SM501_DEVICEID); 1274 1275 if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) { 1276 dev_err(sm->dev, "incorrect device id %08lx\n", devid); 1277 return -EINVAL; 1278 } 1279 1280 /* disable irqs */ 1281 smc501_writel(0, sm->regs + SM501_IRQ_MASK); 1282 1283 dramctrl = smc501_readl(sm->regs + SM501_DRAM_CONTROL); 1284 mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7]; 1285 1286 dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n", 1287 sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq); 1288 1289 sm->rev = devid & SM501_DEVICEID_REVMASK; 1290 1291 sm501_dump_gate(sm); 1292 1293 ret = device_create_file(sm->dev, &dev_attr_dbg_regs); 1294 if (ret) 1295 dev_err(sm->dev, "failed to create debug regs file\n"); 1296 1297 sm501_dump_clk(sm); 1298 1299 /* check to see if we have some device initialisation */ 1300 1301 pdata = sm->platdata; 1302 idata = pdata ? pdata->init : NULL; 1303 1304 if (idata) { 1305 sm501_init_regs(sm, idata); 1306 1307 if (idata->devices & SM501_USE_USB_HOST) 1308 sm501_register_usbhost(sm, &mem_avail); 1309 if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1)) 1310 sm501_register_uart(sm, idata->devices); 1311 if (idata->devices & SM501_USE_GPIO) 1312 sm501_register_gpio(sm); 1313 } 1314 1315 if (pdata && pdata->gpio_i2c && pdata->gpio_i2c_nr > 0) { 1316 if (!sm501_gpio_isregistered(sm)) 1317 dev_err(sm->dev, "no gpio available for i2c gpio.\n"); 1318 else 1319 sm501_register_gpio_i2c(sm, pdata); 1320 } 1321 1322 ret = sm501_check_clocks(sm); 1323 if (ret) { 1324 dev_err(sm->dev, "M1X and M clocks sourced from different " 1325 "PLLs\n"); 1326 return -EINVAL; 1327 } 1328 1329 /* always create a framebuffer */ 1330 sm501_register_display(sm, &mem_avail); 1331 1332 return 0; 1333 } 1334 1335 static int sm501_plat_probe(struct platform_device *dev) 1336 { 1337 struct sm501_devdata *sm; 1338 int ret; 1339 1340 sm = kzalloc_obj(*sm); 1341 if (!sm) { 1342 ret = -ENOMEM; 1343 goto err1; 1344 } 1345 1346 sm->dev = &dev->dev; 1347 sm->pdev_id = dev->id; 1348 sm->platdata = dev_get_platdata(&dev->dev); 1349 1350 ret = platform_get_irq(dev, 0); 1351 if (ret < 0) 1352 goto err_res; 1353 sm->irq = ret; 1354 1355 sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1); 1356 sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0); 1357 if (!sm->io_res || !sm->mem_res) { 1358 dev_err(&dev->dev, "failed to get IO resource\n"); 1359 ret = -ENOENT; 1360 goto err_res; 1361 } 1362 1363 sm->regs_claim = request_mem_region(sm->io_res->start, 1364 0x100, "sm501"); 1365 if (!sm->regs_claim) { 1366 dev_err(&dev->dev, "cannot claim registers\n"); 1367 ret = -EBUSY; 1368 goto err_res; 1369 } 1370 1371 platform_set_drvdata(dev, sm); 1372 1373 sm->regs = ioremap(sm->io_res->start, resource_size(sm->io_res)); 1374 if (!sm->regs) { 1375 dev_err(&dev->dev, "cannot remap registers\n"); 1376 ret = -EIO; 1377 goto err_claim; 1378 } 1379 1380 ret = sm501_init_dev(sm); 1381 if (ret) 1382 goto err_unmap; 1383 1384 return 0; 1385 1386 err_unmap: 1387 iounmap(sm->regs); 1388 err_claim: 1389 release_mem_region(sm->io_res->start, 0x100); 1390 err_res: 1391 kfree(sm); 1392 err1: 1393 return ret; 1394 1395 } 1396 1397 /* power management support */ 1398 1399 static void sm501_set_power(struct sm501_devdata *sm, int on) 1400 { 1401 struct sm501_platdata *pd = sm->platdata; 1402 1403 if (!pd) 1404 return; 1405 1406 if (pd->get_power) { 1407 if (pd->get_power(sm->dev) == on) { 1408 dev_dbg(sm->dev, "is already %d\n", on); 1409 return; 1410 } 1411 } 1412 1413 if (pd->set_power) { 1414 dev_dbg(sm->dev, "setting power to %d\n", on); 1415 1416 pd->set_power(sm->dev, on); 1417 sm501_mdelay(sm, 10); 1418 } 1419 } 1420 1421 static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state) 1422 { 1423 struct sm501_devdata *sm = platform_get_drvdata(pdev); 1424 1425 sm->in_suspend = 1; 1426 sm->pm_misc = smc501_readl(sm->regs + SM501_MISC_CONTROL); 1427 1428 sm501_dump_regs(sm); 1429 1430 if (sm->platdata) { 1431 if (sm->platdata->flags & SM501_FLAG_SUSPEND_OFF) 1432 sm501_set_power(sm, 0); 1433 } 1434 1435 return 0; 1436 } 1437 1438 static int sm501_plat_resume(struct platform_device *pdev) 1439 { 1440 struct sm501_devdata *sm = platform_get_drvdata(pdev); 1441 1442 sm501_set_power(sm, 1); 1443 1444 sm501_dump_regs(sm); 1445 sm501_dump_gate(sm); 1446 sm501_dump_clk(sm); 1447 1448 /* check to see if we are in the same state as when suspended */ 1449 1450 if (smc501_readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) { 1451 dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n"); 1452 smc501_writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL); 1453 1454 /* our suspend causes the controller state to change, 1455 * either by something attempting setup, power loss, 1456 * or an external reset event on power change */ 1457 1458 if (sm->platdata && sm->platdata->init) { 1459 sm501_init_regs(sm, sm->platdata->init); 1460 } 1461 } 1462 1463 /* dump our state from resume */ 1464 1465 sm501_dump_regs(sm); 1466 sm501_dump_clk(sm); 1467 1468 sm->in_suspend = 0; 1469 1470 return 0; 1471 } 1472 1473 /* Initialisation data for PCI devices */ 1474 1475 static struct sm501_initdata sm501_pci_initdata = { 1476 .gpio_high = { 1477 .set = 0x3F000000, /* 24bit panel */ 1478 .mask = 0x0, 1479 }, 1480 .misc_timing = { 1481 .set = 0x010100, /* SDRAM timing */ 1482 .mask = 0x1F1F00, 1483 }, 1484 .misc_control = { 1485 .set = SM501_MISC_PNL_24BIT, 1486 .mask = 0, 1487 }, 1488 1489 .devices = SM501_USE_ALL, 1490 1491 /* Errata AB-3 says that 72MHz is the fastest available 1492 * for 33MHZ PCI with proper bus-mastering operation */ 1493 1494 .mclk = 72 * MHZ, 1495 .m1xclk = 144 * MHZ, 1496 }; 1497 1498 static struct sm501_platdata_fbsub sm501_pdata_fbsub = { 1499 .flags = (SM501FB_FLAG_USE_INIT_MODE | 1500 SM501FB_FLAG_USE_HWCURSOR | 1501 SM501FB_FLAG_USE_HWACCEL | 1502 SM501FB_FLAG_DISABLE_AT_EXIT), 1503 }; 1504 1505 static struct sm501_platdata_fb sm501_fb_pdata = { 1506 .fb_route = SM501_FB_OWN, 1507 .fb_crt = &sm501_pdata_fbsub, 1508 .fb_pnl = &sm501_pdata_fbsub, 1509 }; 1510 1511 static struct sm501_platdata sm501_pci_platdata = { 1512 .init = &sm501_pci_initdata, 1513 .fb = &sm501_fb_pdata, 1514 .gpio_base = -1, 1515 }; 1516 1517 static int sm501_pci_probe(struct pci_dev *dev, 1518 const struct pci_device_id *id) 1519 { 1520 struct sm501_devdata *sm; 1521 int err; 1522 1523 sm = kzalloc_obj(*sm); 1524 if (!sm) { 1525 err = -ENOMEM; 1526 goto err1; 1527 } 1528 1529 /* set a default set of platform data */ 1530 dev->dev.platform_data = sm->platdata = &sm501_pci_platdata; 1531 1532 /* set a hopefully unique id for our child platform devices */ 1533 sm->pdev_id = 32 + dev->devfn; 1534 1535 pci_set_drvdata(dev, sm); 1536 1537 err = pci_enable_device(dev); 1538 if (err) { 1539 dev_err(&dev->dev, "cannot enable device\n"); 1540 goto err2; 1541 } 1542 1543 sm->dev = &dev->dev; 1544 sm->irq = dev->irq; 1545 1546 #ifdef __BIG_ENDIAN 1547 /* if the system is big-endian, we most probably have a 1548 * translation in the IO layer making the PCI bus little endian 1549 * so make the framebuffer swapped pixels */ 1550 1551 sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN; 1552 #endif 1553 1554 /* check our resources */ 1555 1556 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) { 1557 dev_err(&dev->dev, "region #0 is not memory?\n"); 1558 err = -EINVAL; 1559 goto err3; 1560 } 1561 1562 if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) { 1563 dev_err(&dev->dev, "region #1 is not memory?\n"); 1564 err = -EINVAL; 1565 goto err3; 1566 } 1567 1568 /* make our resources ready for sharing */ 1569 1570 sm->io_res = &dev->resource[1]; 1571 sm->mem_res = &dev->resource[0]; 1572 1573 sm->regs_claim = request_mem_region(sm->io_res->start, 1574 0x100, "sm501"); 1575 if (!sm->regs_claim) { 1576 dev_err(&dev->dev, "cannot claim registers\n"); 1577 err= -EBUSY; 1578 goto err3; 1579 } 1580 1581 sm->regs = pci_ioremap_bar(dev, 1); 1582 if (!sm->regs) { 1583 dev_err(&dev->dev, "cannot remap registers\n"); 1584 err = -EIO; 1585 goto err4; 1586 } 1587 1588 sm501_init_dev(sm); 1589 return 0; 1590 1591 err4: 1592 release_mem_region(sm->io_res->start, 0x100); 1593 err3: 1594 pci_disable_device(dev); 1595 err2: 1596 kfree(sm); 1597 err1: 1598 return err; 1599 } 1600 1601 static void sm501_remove_sub(struct sm501_devdata *sm, 1602 struct sm501_device *smdev) 1603 { 1604 list_del(&smdev->list); 1605 platform_device_unregister(&smdev->pdev); 1606 } 1607 1608 static void sm501_dev_remove(struct sm501_devdata *sm) 1609 { 1610 struct sm501_device *smdev, *tmp; 1611 1612 list_for_each_entry_safe(smdev, tmp, &sm->devices, list) 1613 sm501_remove_sub(sm, smdev); 1614 1615 device_remove_file(sm->dev, &dev_attr_dbg_regs); 1616 1617 sm501_gpio_remove(sm); 1618 } 1619 1620 static void sm501_pci_remove(struct pci_dev *dev) 1621 { 1622 struct sm501_devdata *sm = pci_get_drvdata(dev); 1623 1624 sm501_dev_remove(sm); 1625 iounmap(sm->regs); 1626 1627 release_mem_region(sm->io_res->start, 0x100); 1628 1629 pci_disable_device(dev); 1630 } 1631 1632 static void sm501_plat_remove(struct platform_device *dev) 1633 { 1634 struct sm501_devdata *sm = platform_get_drvdata(dev); 1635 1636 sm501_dev_remove(sm); 1637 iounmap(sm->regs); 1638 1639 release_mem_region(sm->io_res->start, 0x100); 1640 } 1641 1642 static const struct pci_device_id sm501_pci_tbl[] = { 1643 { PCI_DEVICE(0x126f, 0x0501) }, 1644 { }, 1645 }; 1646 1647 MODULE_DEVICE_TABLE(pci, sm501_pci_tbl); 1648 1649 static struct pci_driver sm501_pci_driver = { 1650 .name = "sm501", 1651 .id_table = sm501_pci_tbl, 1652 .probe = sm501_pci_probe, 1653 .remove = sm501_pci_remove, 1654 }; 1655 1656 MODULE_ALIAS("platform:sm501"); 1657 1658 static const struct of_device_id of_sm501_match_tbl[] = { 1659 { .compatible = "smi,sm501", }, 1660 { /* end */ } 1661 }; 1662 MODULE_DEVICE_TABLE(of, of_sm501_match_tbl); 1663 1664 static struct platform_driver sm501_plat_driver = { 1665 .driver = { 1666 .name = "sm501", 1667 .of_match_table = of_sm501_match_tbl, 1668 }, 1669 .probe = sm501_plat_probe, 1670 .remove = sm501_plat_remove, 1671 .suspend = pm_sleep_ptr(sm501_plat_suspend), 1672 .resume = pm_sleep_ptr(sm501_plat_resume), 1673 }; 1674 1675 static int __init sm501_base_init(void) 1676 { 1677 int ret; 1678 1679 ret = platform_driver_register(&sm501_plat_driver); 1680 if (ret < 0) 1681 return ret; 1682 1683 return pci_register_driver(&sm501_pci_driver); 1684 } 1685 1686 static void __exit sm501_base_exit(void) 1687 { 1688 platform_driver_unregister(&sm501_plat_driver); 1689 pci_unregister_driver(&sm501_pci_driver); 1690 } 1691 1692 module_init(sm501_base_init); 1693 module_exit(sm501_base_exit); 1694 1695 MODULE_DESCRIPTION("SM501 Core Driver"); 1696 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders"); 1697 MODULE_LICENSE("GPL v2"); 1698