1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Copyright (c) 2011-2014 Samsung Electronics Co., Ltd 4 // http://www.samsung.com 5 6 #include <linux/array_size.h> 7 #include <linux/build_bug.h> 8 #include <linux/dev_printk.h> 9 #include <linux/interrupt.h> 10 #include <linux/irq.h> 11 #include <linux/mfd/samsung/core.h> 12 #include <linux/mfd/samsung/irq.h> 13 #include <linux/mfd/samsung/s2mpg10.h> 14 #include <linux/mfd/samsung/s2mpg11.h> 15 #include <linux/mfd/samsung/s2mps11.h> 16 #include <linux/mfd/samsung/s2mps14.h> 17 #include <linux/mfd/samsung/s2mpu02.h> 18 #include <linux/mfd/samsung/s2mpu05.h> 19 #include <linux/mfd/samsung/s2mu005.h> 20 #include <linux/mfd/samsung/s5m8767.h> 21 #include <linux/regmap.h> 22 #include "sec-core.h" 23 24 static const struct regmap_irq s2mpg10_irqs[] = { 25 REGMAP_IRQ_REG(S2MPG10_COMMON_IRQ_PMIC, 0, S2MPG10_COMMON_INT_SRC_PMIC), 26 /* No documentation or other reference for remaining bits */ 27 REGMAP_IRQ_REG(S2MPG10_COMMON_IRQ_UNUSED, 0, GENMASK(7, 1)), 28 }; 29 30 static const struct regmap_irq s2mpg10_pmic_irqs[] = { 31 REGMAP_IRQ_REG(S2MPG10_IRQ_PWRONF, 0, S2MPG10_IRQ_PWRONF_MASK), 32 REGMAP_IRQ_REG(S2MPG10_IRQ_PWRONR, 0, S2MPG10_IRQ_PWRONR_MASK), 33 REGMAP_IRQ_REG(S2MPG10_IRQ_JIGONBF, 0, S2MPG10_IRQ_JIGONBF_MASK), 34 REGMAP_IRQ_REG(S2MPG10_IRQ_JIGONBR, 0, S2MPG10_IRQ_JIGONBR_MASK), 35 REGMAP_IRQ_REG(S2MPG10_IRQ_ACOKBF, 0, S2MPG10_IRQ_ACOKBF_MASK), 36 REGMAP_IRQ_REG(S2MPG10_IRQ_ACOKBR, 0, S2MPG10_IRQ_ACOKBR_MASK), 37 REGMAP_IRQ_REG(S2MPG10_IRQ_PWRON1S, 0, S2MPG10_IRQ_PWRON1S_MASK), 38 REGMAP_IRQ_REG(S2MPG10_IRQ_MRB, 0, S2MPG10_IRQ_MRB_MASK), 39 40 REGMAP_IRQ_REG(S2MPG10_IRQ_RTC60S, 1, S2MPG10_IRQ_RTC60S_MASK), 41 REGMAP_IRQ_REG(S2MPG10_IRQ_RTCA1, 1, S2MPG10_IRQ_RTCA1_MASK), 42 REGMAP_IRQ_REG(S2MPG10_IRQ_RTCA0, 1, S2MPG10_IRQ_RTCA0_MASK), 43 REGMAP_IRQ_REG(S2MPG10_IRQ_RTC1S, 1, S2MPG10_IRQ_RTC1S_MASK), 44 REGMAP_IRQ_REG(S2MPG10_IRQ_WTSR_COLDRST, 1, S2MPG10_IRQ_WTSR_COLDRST_MASK), 45 REGMAP_IRQ_REG(S2MPG10_IRQ_WTSR, 1, S2MPG10_IRQ_WTSR_MASK), 46 REGMAP_IRQ_REG(S2MPG10_IRQ_WRST, 1, S2MPG10_IRQ_WRST_MASK), 47 REGMAP_IRQ_REG(S2MPG10_IRQ_SMPL, 1, S2MPG10_IRQ_SMPL_MASK), 48 49 REGMAP_IRQ_REG(S2MPG10_IRQ_120C, 2, S2MPG10_IRQ_INT120C_MASK), 50 REGMAP_IRQ_REG(S2MPG10_IRQ_140C, 2, S2MPG10_IRQ_INT140C_MASK), 51 REGMAP_IRQ_REG(S2MPG10_IRQ_TSD, 2, S2MPG10_IRQ_TSD_MASK), 52 REGMAP_IRQ_REG(S2MPG10_IRQ_PIF_TIMEOUT1, 2, S2MPG10_IRQ_PIF_TIMEOUT1_MASK), 53 REGMAP_IRQ_REG(S2MPG10_IRQ_PIF_TIMEOUT2, 2, S2MPG10_IRQ_PIF_TIMEOUT2_MASK), 54 REGMAP_IRQ_REG(S2MPG10_IRQ_SPD_PARITY_ERR, 2, S2MPG10_IRQ_SPD_PARITY_ERR_MASK), 55 REGMAP_IRQ_REG(S2MPG10_IRQ_SPD_ABNORMAL_STOP, 2, S2MPG10_IRQ_SPD_ABNORMAL_STOP_MASK), 56 REGMAP_IRQ_REG(S2MPG10_IRQ_PMETER_OVERF, 2, S2MPG10_IRQ_PMETER_OVERF_MASK), 57 58 REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B1M, 3, S2MPG10_IRQ_OCP_B1M_MASK), 59 REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B2M, 3, S2MPG10_IRQ_OCP_B2M_MASK), 60 REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B3M, 3, S2MPG10_IRQ_OCP_B3M_MASK), 61 REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B4M, 3, S2MPG10_IRQ_OCP_B4M_MASK), 62 REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B5M, 3, S2MPG10_IRQ_OCP_B5M_MASK), 63 REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B6M, 3, S2MPG10_IRQ_OCP_B6M_MASK), 64 REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B7M, 3, S2MPG10_IRQ_OCP_B7M_MASK), 65 REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B8M, 3, S2MPG10_IRQ_OCP_B8M_MASK), 66 67 REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B9M, 4, S2MPG10_IRQ_OCP_B9M_MASK), 68 REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B10M, 4, S2MPG10_IRQ_OCP_B10M_MASK), 69 REGMAP_IRQ_REG(S2MPG10_IRQ_WLWP_ACC, 4, S2MPG10_IRQ_WLWP_ACC_MASK), 70 REGMAP_IRQ_REG(S2MPG10_IRQ_SMPL_TIMEOUT, 4, S2MPG10_IRQ_SMPL_TIMEOUT_MASK), 71 REGMAP_IRQ_REG(S2MPG10_IRQ_WTSR_TIMEOUT, 4, S2MPG10_IRQ_WTSR_TIMEOUT_MASK), 72 REGMAP_IRQ_REG(S2MPG10_IRQ_SPD_SRP_PKT_RST, 4, S2MPG10_IRQ_SPD_SRP_PKT_RST_MASK), 73 74 REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH0, 5, S2MPG10_IRQ_PWR_WARN_CH0_MASK), 75 REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH1, 5, S2MPG10_IRQ_PWR_WARN_CH1_MASK), 76 REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH2, 5, S2MPG10_IRQ_PWR_WARN_CH2_MASK), 77 REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH3, 5, S2MPG10_IRQ_PWR_WARN_CH3_MASK), 78 REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH4, 5, S2MPG10_IRQ_PWR_WARN_CH4_MASK), 79 REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH5, 5, S2MPG10_IRQ_PWR_WARN_CH5_MASK), 80 REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH6, 5, S2MPG10_IRQ_PWR_WARN_CH6_MASK), 81 REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH7, 5, S2MPG10_IRQ_PWR_WARN_CH7_MASK), 82 }; 83 84 static const struct regmap_irq s2mpg11_irqs[] = { 85 REGMAP_IRQ_REG(S2MPG11_COMMON_IRQ_PMIC, 0, S2MPG11_COMMON_INT_SRC_PMIC), 86 /* No documentation or other reference for remaining bits */ 87 REGMAP_IRQ_REG(S2MPG11_COMMON_IRQ_UNUSED, 0, GENMASK(7, 1)), 88 }; 89 90 static const struct regmap_irq s2mpg11_pmic_irqs[] = { 91 REGMAP_IRQ_REG(S2MPG11_IRQ_PWRONF, 0, S2MPG11_IRQ_PWRONF_MASK), 92 REGMAP_IRQ_REG(S2MPG11_IRQ_PWRONR, 0, S2MPG11_IRQ_PWRONR_MASK), 93 REGMAP_IRQ_REG(S2MPG11_IRQ_PIF_TIMEOUT_MIF, 0, S2MPG11_IRQ_PIF_TIMEOUT_MIF_MASK), 94 REGMAP_IRQ_REG(S2MPG11_IRQ_PIF_TIMEOUTS, 0, S2MPG11_IRQ_PIF_TIMEOUTS_MASK), 95 REGMAP_IRQ_REG(S2MPG11_IRQ_WTSR, 0, S2MPG11_IRQ_WTSR_MASK), 96 REGMAP_IRQ_REG(S2MPG11_IRQ_SPD_ABNORMAL_STOP, 0, S2MPG11_IRQ_SPD_ABNORMAL_STOP_MASK), 97 REGMAP_IRQ_REG(S2MPG11_IRQ_SPD_PARITY_ERR, 0, S2MPG11_IRQ_SPD_PARITY_ERR_MASK), 98 99 REGMAP_IRQ_REG(S2MPG11_IRQ_140C, 1, S2MPG11_IRQ_INT140C_MASK), 100 REGMAP_IRQ_REG(S2MPG11_IRQ_120C, 1, S2MPG11_IRQ_INT120C_MASK), 101 REGMAP_IRQ_REG(S2MPG11_IRQ_TSD, 1, S2MPG11_IRQ_TSD_MASK), 102 REGMAP_IRQ_REG(S2MPG11_IRQ_WRST, 1, S2MPG11_IRQ_WRST_MASK), 103 REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_CYCLE_DONE, 1, S2MPG11_IRQ_NTC_CYCLE_DONE_MASK), 104 REGMAP_IRQ_REG(S2MPG11_IRQ_PMETER_OVERF, 1, S2MPG11_IRQ_PMETER_OVERF_MASK), 105 106 REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B1S, 2, S2MPG11_IRQ_OCP_B1S_MASK), 107 REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B2S, 2, S2MPG11_IRQ_OCP_B2S_MASK), 108 REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B3S, 2, S2MPG11_IRQ_OCP_B3S_MASK), 109 REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B4S, 2, S2MPG11_IRQ_OCP_B4S_MASK), 110 REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B5S, 2, S2MPG11_IRQ_OCP_B5S_MASK), 111 REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B6S, 2, S2MPG11_IRQ_OCP_B6S_MASK), 112 REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B7S, 2, S2MPG11_IRQ_OCP_B7S_MASK), 113 REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B8S, 2, S2MPG11_IRQ_OCP_B8S_MASK), 114 115 REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B9S, 3, S2MPG11_IRQ_OCP_B9S_MASK), 116 REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B10S, 3, S2MPG11_IRQ_OCP_B10S_MASK), 117 REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_BDS, 3, S2MPG11_IRQ_OCP_BDS_MASK), 118 REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_BAS, 3, S2MPG11_IRQ_OCP_BAS_MASK), 119 REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_BBS, 3, S2MPG11_IRQ_OCP_BBS_MASK), 120 REGMAP_IRQ_REG(S2MPG11_IRQ_WLWP_ACC, 3, S2MPG11_IRQ_WLWP_ACC_MASK), 121 REGMAP_IRQ_REG(S2MPG11_IRQ_SPD_SRP_PKT_RST, 3, S2MPG11_IRQ_SPD_SRP_PKT_RST_MASK), 122 123 REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH0, 4, S2MPG11_IRQ_PWR_WARN_CH0_MASK), 124 REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH1, 4, S2MPG11_IRQ_PWR_WARN_CH1_MASK), 125 REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH2, 4, S2MPG11_IRQ_PWR_WARN_CH2_MASK), 126 REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH3, 4, S2MPG11_IRQ_PWR_WARN_CH3_MASK), 127 REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH4, 4, S2MPG11_IRQ_PWR_WARN_CH4_MASK), 128 REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH5, 4, S2MPG11_IRQ_PWR_WARN_CH5_MASK), 129 REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH6, 4, S2MPG11_IRQ_PWR_WARN_CH6_MASK), 130 REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH7, 4, S2MPG11_IRQ_PWR_WARN_CH7_MASK), 131 132 REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH0, 5, S2MPG11_IRQ_NTC_WARN_CH0_MASK), 133 REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH1, 5, S2MPG11_IRQ_NTC_WARN_CH1_MASK), 134 REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH2, 5, S2MPG11_IRQ_NTC_WARN_CH2_MASK), 135 REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH3, 5, S2MPG11_IRQ_NTC_WARN_CH3_MASK), 136 REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH4, 5, S2MPG11_IRQ_NTC_WARN_CH4_MASK), 137 REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH5, 5, S2MPG11_IRQ_NTC_WARN_CH5_MASK), 138 REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH6, 5, S2MPG11_IRQ_NTC_WARN_CH6_MASK), 139 REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH7, 5, S2MPG11_IRQ_NTC_WARN_CH7_MASK), 140 }; 141 142 static const struct regmap_irq s2mps11_irqs[] = { 143 REGMAP_IRQ_REG(S2MPS11_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK), 144 REGMAP_IRQ_REG(S2MPS11_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK), 145 REGMAP_IRQ_REG(S2MPS11_IRQ_JIGONBF, 0, S2MPS11_IRQ_JIGONBF_MASK), 146 REGMAP_IRQ_REG(S2MPS11_IRQ_JIGONBR, 0, S2MPS11_IRQ_JIGONBR_MASK), 147 REGMAP_IRQ_REG(S2MPS11_IRQ_ACOKBF, 0, S2MPS11_IRQ_ACOKBF_MASK), 148 REGMAP_IRQ_REG(S2MPS11_IRQ_ACOKBR, 0, S2MPS11_IRQ_ACOKBR_MASK), 149 REGMAP_IRQ_REG(S2MPS11_IRQ_PWRON1S, 0, S2MPS11_IRQ_PWRON1S_MASK), 150 REGMAP_IRQ_REG(S2MPS11_IRQ_MRB, 0, S2MPS11_IRQ_MRB_MASK), 151 152 REGMAP_IRQ_REG(S2MPS11_IRQ_RTC60S, 1, S2MPS11_IRQ_RTC60S_MASK), 153 REGMAP_IRQ_REG(S2MPS11_IRQ_RTCA1, 1, S2MPS11_IRQ_RTCA1_MASK), 154 REGMAP_IRQ_REG(S2MPS11_IRQ_RTCA0, 1, S2MPS11_IRQ_RTCA0_MASK), 155 REGMAP_IRQ_REG(S2MPS11_IRQ_SMPL, 1, S2MPS11_IRQ_SMPL_MASK), 156 REGMAP_IRQ_REG(S2MPS11_IRQ_RTC1S, 1, S2MPS11_IRQ_RTC1S_MASK), 157 REGMAP_IRQ_REG(S2MPS11_IRQ_WTSR, 1, S2MPS11_IRQ_WTSR_MASK), 158 159 REGMAP_IRQ_REG(S2MPS11_IRQ_INT120C, 2, S2MPS11_IRQ_INT120C_MASK), 160 REGMAP_IRQ_REG(S2MPS11_IRQ_INT140C, 2, S2MPS11_IRQ_INT140C_MASK), 161 }; 162 163 static const struct regmap_irq s2mps14_irqs[] = { 164 REGMAP_IRQ_REG(S2MPS14_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK), 165 REGMAP_IRQ_REG(S2MPS14_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK), 166 REGMAP_IRQ_REG(S2MPS14_IRQ_JIGONBF, 0, S2MPS11_IRQ_JIGONBF_MASK), 167 REGMAP_IRQ_REG(S2MPS14_IRQ_JIGONBR, 0, S2MPS11_IRQ_JIGONBR_MASK), 168 REGMAP_IRQ_REG(S2MPS14_IRQ_ACOKBF, 0, S2MPS11_IRQ_ACOKBF_MASK), 169 REGMAP_IRQ_REG(S2MPS14_IRQ_ACOKBR, 0, S2MPS11_IRQ_ACOKBR_MASK), 170 REGMAP_IRQ_REG(S2MPS14_IRQ_PWRON1S, 0, S2MPS11_IRQ_PWRON1S_MASK), 171 REGMAP_IRQ_REG(S2MPS14_IRQ_MRB, 0, S2MPS11_IRQ_MRB_MASK), 172 173 REGMAP_IRQ_REG(S2MPS14_IRQ_RTC60S, 1, S2MPS11_IRQ_RTC60S_MASK), 174 REGMAP_IRQ_REG(S2MPS14_IRQ_RTCA1, 1, S2MPS11_IRQ_RTCA1_MASK), 175 REGMAP_IRQ_REG(S2MPS14_IRQ_RTCA0, 1, S2MPS11_IRQ_RTCA0_MASK), 176 REGMAP_IRQ_REG(S2MPS14_IRQ_SMPL, 1, S2MPS11_IRQ_SMPL_MASK), 177 REGMAP_IRQ_REG(S2MPS14_IRQ_RTC1S, 1, S2MPS11_IRQ_RTC1S_MASK), 178 REGMAP_IRQ_REG(S2MPS14_IRQ_WTSR, 1, S2MPS11_IRQ_WTSR_MASK), 179 180 REGMAP_IRQ_REG(S2MPS14_IRQ_INT120C, 2, S2MPS11_IRQ_INT120C_MASK), 181 REGMAP_IRQ_REG(S2MPS14_IRQ_INT140C, 2, S2MPS11_IRQ_INT140C_MASK), 182 REGMAP_IRQ_REG(S2MPS14_IRQ_TSD, 2, S2MPS14_IRQ_TSD_MASK), 183 }; 184 185 static const struct regmap_irq s2mpu02_irqs[] = { 186 REGMAP_IRQ_REG(S2MPU02_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK), 187 REGMAP_IRQ_REG(S2MPU02_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK), 188 REGMAP_IRQ_REG(S2MPU02_IRQ_JIGONBF, 0, S2MPS11_IRQ_JIGONBF_MASK), 189 REGMAP_IRQ_REG(S2MPU02_IRQ_JIGONBR, 0, S2MPS11_IRQ_JIGONBR_MASK), 190 REGMAP_IRQ_REG(S2MPU02_IRQ_ACOKBF, 0, S2MPS11_IRQ_ACOKBF_MASK), 191 REGMAP_IRQ_REG(S2MPU02_IRQ_ACOKBR, 0, S2MPS11_IRQ_ACOKBR_MASK), 192 REGMAP_IRQ_REG(S2MPU02_IRQ_PWRON1S, 0, S2MPS11_IRQ_PWRON1S_MASK), 193 REGMAP_IRQ_REG(S2MPU02_IRQ_MRB, 0, S2MPS11_IRQ_MRB_MASK), 194 195 REGMAP_IRQ_REG(S2MPU02_IRQ_RTC60S, 1, S2MPS11_IRQ_RTC60S_MASK), 196 REGMAP_IRQ_REG(S2MPU02_IRQ_RTCA1, 1, S2MPS11_IRQ_RTCA1_MASK), 197 REGMAP_IRQ_REG(S2MPU02_IRQ_RTCA0, 1, S2MPS11_IRQ_RTCA0_MASK), 198 REGMAP_IRQ_REG(S2MPU02_IRQ_SMPL, 1, S2MPS11_IRQ_SMPL_MASK), 199 REGMAP_IRQ_REG(S2MPU02_IRQ_RTC1S, 1, S2MPS11_IRQ_RTC1S_MASK), 200 REGMAP_IRQ_REG(S2MPU02_IRQ_WTSR, 1, S2MPS11_IRQ_WTSR_MASK), 201 202 REGMAP_IRQ_REG(S2MPU02_IRQ_INT120C, 2, S2MPS11_IRQ_INT120C_MASK), 203 REGMAP_IRQ_REG(S2MPU02_IRQ_INT140C, 2, S2MPS11_IRQ_INT140C_MASK), 204 REGMAP_IRQ_REG(S2MPU02_IRQ_TSD, 2, S2MPS14_IRQ_TSD_MASK), 205 }; 206 207 static const struct regmap_irq s2mpu05_irqs[] = { 208 REGMAP_IRQ_REG(S2MPU05_IRQ_PWRONF, 0, S2MPU05_IRQ_PWRONF_MASK), 209 REGMAP_IRQ_REG(S2MPU05_IRQ_PWRONR, 0, S2MPU05_IRQ_PWRONR_MASK), 210 REGMAP_IRQ_REG(S2MPU05_IRQ_JIGONBF, 0, S2MPU05_IRQ_JIGONBF_MASK), 211 REGMAP_IRQ_REG(S2MPU05_IRQ_JIGONBR, 0, S2MPU05_IRQ_JIGONBR_MASK), 212 REGMAP_IRQ_REG(S2MPU05_IRQ_ACOKF, 0, S2MPU05_IRQ_ACOKF_MASK), 213 REGMAP_IRQ_REG(S2MPU05_IRQ_ACOKR, 0, S2MPU05_IRQ_ACOKR_MASK), 214 REGMAP_IRQ_REG(S2MPU05_IRQ_PWRON1S, 0, S2MPU05_IRQ_PWRON1S_MASK), 215 REGMAP_IRQ_REG(S2MPU05_IRQ_MRB, 0, S2MPU05_IRQ_MRB_MASK), 216 REGMAP_IRQ_REG(S2MPU05_IRQ_RTC60S, 1, S2MPU05_IRQ_RTC60S_MASK), 217 REGMAP_IRQ_REG(S2MPU05_IRQ_RTCA1, 1, S2MPU05_IRQ_RTCA1_MASK), 218 REGMAP_IRQ_REG(S2MPU05_IRQ_RTCA0, 1, S2MPU05_IRQ_RTCA0_MASK), 219 REGMAP_IRQ_REG(S2MPU05_IRQ_SMPL, 1, S2MPU05_IRQ_SMPL_MASK), 220 REGMAP_IRQ_REG(S2MPU05_IRQ_RTC1S, 1, S2MPU05_IRQ_RTC1S_MASK), 221 REGMAP_IRQ_REG(S2MPU05_IRQ_WTSR, 1, S2MPU05_IRQ_WTSR_MASK), 222 REGMAP_IRQ_REG(S2MPU05_IRQ_INT120C, 2, S2MPU05_IRQ_INT120C_MASK), 223 REGMAP_IRQ_REG(S2MPU05_IRQ_INT140C, 2, S2MPU05_IRQ_INT140C_MASK), 224 REGMAP_IRQ_REG(S2MPU05_IRQ_TSD, 2, S2MPU05_IRQ_TSD_MASK), 225 }; 226 227 static const struct regmap_irq s2mu005_irqs[] = { 228 REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_DETBAT, 0, S2MU005_IRQ_CHGR_DETBAT_MASK), 229 REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_BAT, 0, S2MU005_IRQ_CHGR_BAT_MASK), 230 REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_IVR, 0, S2MU005_IRQ_CHGR_IVR_MASK), 231 REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_EVENT, 0, S2MU005_IRQ_CHGR_EVENT_MASK), 232 REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_CHG, 0, S2MU005_IRQ_CHGR_CHG_MASK), 233 REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_VMID, 0, S2MU005_IRQ_CHGR_VMID_MASK), 234 REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_WCIN, 0, S2MU005_IRQ_CHGR_WCIN_MASK), 235 REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_VBUS, 0, S2MU005_IRQ_CHGR_VBUS_MASK), 236 237 REGMAP_IRQ_REG(S2MU005_IRQ_FLED_LBPROT, 1, S2MU005_IRQ_FLED_LBPROT_MASK), 238 REGMAP_IRQ_REG(S2MU005_IRQ_FLED_OPENCH2, 1, S2MU005_IRQ_FLED_OPENCH2_MASK), 239 REGMAP_IRQ_REG(S2MU005_IRQ_FLED_OPENCH1, 1, S2MU005_IRQ_FLED_OPENCH1_MASK), 240 REGMAP_IRQ_REG(S2MU005_IRQ_FLED_SHORTCH2, 1, S2MU005_IRQ_FLED_SHORTCH2_MASK), 241 REGMAP_IRQ_REG(S2MU005_IRQ_FLED_SHORTCH1, 1, S2MU005_IRQ_FLED_SHORTCH1_MASK), 242 243 REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_ATTACH, 2, S2MU005_IRQ_MUIC_ATTACH_MASK), 244 REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_DETACH, 2, S2MU005_IRQ_MUIC_DETACH_MASK), 245 REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_KP, 2, S2MU005_IRQ_MUIC_KP_MASK), 246 REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_LKP, 2, S2MU005_IRQ_MUIC_LKP_MASK), 247 REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_LKR, 2, S2MU005_IRQ_MUIC_LKR_MASK), 248 REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_RIDCHG, 2, S2MU005_IRQ_MUIC_RIDCHG_MASK), 249 250 REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_VBUSON, 3, S2MU005_IRQ_MUIC_VBUSON_MASK), 251 REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_RSVD, 3, S2MU005_IRQ_MUIC_RSVD_MASK), 252 REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_ADC, 3, S2MU005_IRQ_MUIC_ADC_MASK), 253 REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_STUCK, 3, S2MU005_IRQ_MUIC_STUCK_MASK), 254 REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_STUCKRCV, 3, S2MU005_IRQ_MUIC_STUCKRCV_MASK), 255 REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_MHDL, 3, S2MU005_IRQ_MUIC_MHDL_MASK), 256 REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_AVCHG, 3, S2MU005_IRQ_MUIC_AVCHG_MASK), 257 REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_VBUSOFF, 3, S2MU005_IRQ_MUIC_VBUSOFF_MASK), 258 }; 259 260 static unsigned int s2mu005_irq_get_reg(struct regmap_irq_chip_data *data, 261 unsigned int base, int index) 262 { 263 const unsigned int irqf_regs[] = { 264 S2MU005_REG_CHGR_INT1, 265 S2MU005_REG_FLED_INT1, 266 S2MU005_REG_MUIC_INT1, 267 S2MU005_REG_MUIC_INT2, 268 }; 269 const unsigned int mask_regs[] = { 270 S2MU005_REG_CHGR_INT1M, 271 S2MU005_REG_FLED_INT1M, 272 S2MU005_REG_MUIC_INT1M, 273 S2MU005_REG_MUIC_INT2M, 274 }; 275 276 switch (base) { 277 case S2MU005_REG_CHGR_INT1: 278 return irqf_regs[index]; 279 case S2MU005_REG_CHGR_INT1M: 280 return mask_regs[index]; 281 } 282 283 return base; 284 } 285 286 static const struct regmap_irq s5m8767_irqs[] = { 287 REGMAP_IRQ_REG(S5M8767_IRQ_PWRR, 0, S5M8767_IRQ_PWRR_MASK), 288 REGMAP_IRQ_REG(S5M8767_IRQ_PWRF, 0, S5M8767_IRQ_PWRF_MASK), 289 REGMAP_IRQ_REG(S5M8767_IRQ_PWR1S, 0, S5M8767_IRQ_PWR1S_MASK), 290 REGMAP_IRQ_REG(S5M8767_IRQ_JIGR, 0, S5M8767_IRQ_JIGR_MASK), 291 REGMAP_IRQ_REG(S5M8767_IRQ_JIGF, 0, S5M8767_IRQ_JIGF_MASK), 292 REGMAP_IRQ_REG(S5M8767_IRQ_LOWBAT2, 0, S5M8767_IRQ_LOWBAT2_MASK), 293 REGMAP_IRQ_REG(S5M8767_IRQ_LOWBAT1, 0, S5M8767_IRQ_LOWBAT1_MASK), 294 295 REGMAP_IRQ_REG(S5M8767_IRQ_MRB, 1, S5M8767_IRQ_MRB_MASK), 296 REGMAP_IRQ_REG(S5M8767_IRQ_DVSOK2, 1, S5M8767_IRQ_DVSOK2_MASK), 297 REGMAP_IRQ_REG(S5M8767_IRQ_DVSOK3, 1, S5M8767_IRQ_DVSOK3_MASK), 298 REGMAP_IRQ_REG(S5M8767_IRQ_DVSOK4, 1, S5M8767_IRQ_DVSOK4_MASK), 299 300 REGMAP_IRQ_REG(S5M8767_IRQ_RTC60S, 2, S5M8767_IRQ_RTC60S_MASK), 301 REGMAP_IRQ_REG(S5M8767_IRQ_RTCA1, 2, S5M8767_IRQ_RTCA1_MASK), 302 REGMAP_IRQ_REG(S5M8767_IRQ_RTCA2, 2, S5M8767_IRQ_RTCA2_MASK), 303 REGMAP_IRQ_REG(S5M8767_IRQ_SMPL, 2, S5M8767_IRQ_SMPL_MASK), 304 REGMAP_IRQ_REG(S5M8767_IRQ_RTC1S, 2, S5M8767_IRQ_RTC1S_MASK), 305 REGMAP_IRQ_REG(S5M8767_IRQ_WTSR, 2, S5M8767_IRQ_WTSR_MASK), 306 }; 307 308 /* All S2MPG1x interrupt sources are read-only and don't require clearing */ 309 static const struct regmap_irq_chip s2mpg10_irq_chip = { 310 .name = "s2mpg10", 311 .status_base = S2MPG10_COMMON_INT, 312 .mask_base = S2MPG10_COMMON_INT_MASK, 313 .num_regs = 1, 314 .irqs = s2mpg10_irqs, 315 .num_irqs = ARRAY_SIZE(s2mpg10_irqs), 316 }; 317 318 static const struct regmap_irq_chip s2mpg10_irq_chip_pmic = { 319 .name = "s2mpg10-pmic", 320 .domain_suffix = "pmic", 321 .status_base = S2MPG10_PMIC_INT1, 322 .mask_base = S2MPG10_PMIC_INT1M, 323 .num_regs = 6, 324 .irqs = s2mpg10_pmic_irqs, 325 .num_irqs = ARRAY_SIZE(s2mpg10_pmic_irqs), 326 }; 327 328 static const struct regmap_irq_chip s2mpg11_irq_chip = { 329 .name = "s2mpg11", 330 .status_base = S2MPG11_COMMON_INT, 331 .mask_base = S2MPG11_COMMON_INT_MASK, 332 .num_regs = 1, 333 .irqs = s2mpg11_irqs, 334 .num_irqs = ARRAY_SIZE(s2mpg11_irqs), 335 }; 336 337 static const struct regmap_irq_chip s2mpg11_irq_chip_pmic = { 338 .name = "s2mpg11-pmic", 339 .domain_suffix = "pmic", 340 .status_base = S2MPG11_PMIC_INT1, 341 .mask_base = S2MPG11_PMIC_INT1M, 342 .num_regs = 6, 343 .irqs = s2mpg11_pmic_irqs, 344 .num_irqs = ARRAY_SIZE(s2mpg11_pmic_irqs), 345 }; 346 347 static const struct regmap_irq_chip s2mps11_irq_chip = { 348 .name = "s2mps11", 349 .irqs = s2mps11_irqs, 350 .num_irqs = ARRAY_SIZE(s2mps11_irqs), 351 .num_regs = 3, 352 .status_base = S2MPS11_REG_INT1, 353 .mask_base = S2MPS11_REG_INT1M, 354 .ack_base = S2MPS11_REG_INT1, 355 }; 356 357 #define S2MPS1X_IRQ_CHIP_COMMON_DATA \ 358 .irqs = s2mps14_irqs, \ 359 .num_irqs = ARRAY_SIZE(s2mps14_irqs), \ 360 .num_regs = 3, \ 361 .status_base = S2MPS14_REG_INT1, \ 362 .mask_base = S2MPS14_REG_INT1M, \ 363 .ack_base = S2MPS14_REG_INT1 \ 364 365 static const struct regmap_irq_chip s2mps13_irq_chip = { 366 .name = "s2mps13", 367 S2MPS1X_IRQ_CHIP_COMMON_DATA, 368 }; 369 370 static const struct regmap_irq_chip s2mps14_irq_chip = { 371 .name = "s2mps14", 372 S2MPS1X_IRQ_CHIP_COMMON_DATA, 373 }; 374 375 static const struct regmap_irq_chip s2mps15_irq_chip = { 376 .name = "s2mps15", 377 S2MPS1X_IRQ_CHIP_COMMON_DATA, 378 }; 379 380 static const struct regmap_irq_chip s2mpu02_irq_chip = { 381 .name = "s2mpu02", 382 .irqs = s2mpu02_irqs, 383 .num_irqs = ARRAY_SIZE(s2mpu02_irqs), 384 .num_regs = 3, 385 .status_base = S2MPU02_REG_INT1, 386 .mask_base = S2MPU02_REG_INT1M, 387 .ack_base = S2MPU02_REG_INT1, 388 }; 389 390 static const struct regmap_irq_chip s2mpu05_irq_chip = { 391 .name = "s2mpu05", 392 .irqs = s2mpu05_irqs, 393 .num_irqs = ARRAY_SIZE(s2mpu05_irqs), 394 .num_regs = 3, 395 .status_base = S2MPU05_REG_INT1, 396 .mask_base = S2MPU05_REG_INT1M, 397 .ack_base = S2MPU05_REG_INT1, 398 }; 399 400 static const struct regmap_irq_chip s2mu005_irq_chip = { 401 .name = "s2mu005", 402 .irqs = s2mu005_irqs, 403 .num_irqs = ARRAY_SIZE(s2mu005_irqs), 404 .num_regs = 4, 405 .status_base = S2MU005_REG_CHGR_INT1, 406 .mask_base = S2MU005_REG_CHGR_INT1M, 407 .get_irq_reg = s2mu005_irq_get_reg, 408 }; 409 410 static const struct regmap_irq_chip s5m8767_irq_chip = { 411 .name = "s5m8767", 412 .irqs = s5m8767_irqs, 413 .num_irqs = ARRAY_SIZE(s5m8767_irqs), 414 .num_regs = 3, 415 .status_base = S5M8767_REG_INT1, 416 .mask_base = S5M8767_REG_INT1M, 417 .ack_base = S5M8767_REG_INT1, 418 }; 419 420 static struct regmap_irq_chip_data * 421 s2mpg1x_add_chained_pmic(struct sec_pmic_dev *sec_pmic, int pirq, 422 struct regmap_irq_chip_data *parent, const struct regmap_irq_chip *chip) 423 { 424 struct device *dev = sec_pmic->dev; 425 struct regmap_irq_chip_data *data; 426 int irq, ret; 427 428 irq = regmap_irq_get_virq(parent, pirq); 429 if (irq < 0) 430 return dev_err_ptr_probe(dev, irq, "Failed to get parent vIRQ(%d) for chip %s\n", 431 pirq, chip->name); 432 433 ret = devm_regmap_add_irq_chip(dev, sec_pmic->regmap_pmic, irq, 434 IRQF_ONESHOT | IRQF_SHARED, 0, chip, &data); 435 if (ret) 436 return dev_err_ptr_probe(dev, ret, "Failed to add %s IRQ chip\n", chip->name); 437 438 return data; 439 } 440 441 static struct regmap_irq_chip_data *sec_irq_init_s2mpg1x(struct sec_pmic_dev *sec_pmic) 442 { 443 const struct regmap_irq_chip *irq_chip, *chained_irq_chip; 444 struct regmap_irq_chip_data *irq_data; 445 struct regmap *regmap_common; 446 int chained_pirq; 447 int ret; 448 449 switch (sec_pmic->device_type) { 450 case S2MPG10: 451 irq_chip = &s2mpg10_irq_chip; 452 chained_irq_chip = &s2mpg10_irq_chip_pmic; 453 chained_pirq = S2MPG10_COMMON_IRQ_PMIC; 454 break; 455 case S2MPG11: 456 irq_chip = &s2mpg11_irq_chip; 457 chained_irq_chip = &s2mpg11_irq_chip_pmic; 458 chained_pirq = S2MPG11_COMMON_IRQ_PMIC; 459 break; 460 default: 461 return dev_err_ptr_probe(sec_pmic->dev, -EINVAL, "Unsupported device type %d\n", 462 sec_pmic->device_type); 463 } 464 465 regmap_common = dev_get_regmap(sec_pmic->dev, "common"); 466 if (!regmap_common) 467 return dev_err_ptr_probe(sec_pmic->dev, -EINVAL, "No 'common' regmap %d\n", 468 sec_pmic->device_type); 469 470 ret = devm_regmap_add_irq_chip(sec_pmic->dev, regmap_common, sec_pmic->irq, IRQF_ONESHOT, 0, 471 irq_chip, &irq_data); 472 if (ret) 473 return dev_err_ptr_probe(sec_pmic->dev, ret, "Failed to add %s IRQ chip\n", 474 irq_chip->name); 475 476 return s2mpg1x_add_chained_pmic(sec_pmic, chained_pirq, irq_data, chained_irq_chip); 477 } 478 479 struct regmap_irq_chip_data *sec_irq_init(struct sec_pmic_dev *sec_pmic) 480 { 481 struct regmap_irq_chip_data *sec_irq_chip_data; 482 const struct regmap_irq_chip *sec_irq_chip; 483 int ret; 484 485 switch (sec_pmic->device_type) { 486 case S5M8767X: 487 sec_irq_chip = &s5m8767_irq_chip; 488 break; 489 case S2DOS05: 490 return NULL; 491 case S2MPA01: 492 sec_irq_chip = &s2mps14_irq_chip; 493 break; 494 case S2MPG10: 495 case S2MPG11: 496 return sec_irq_init_s2mpg1x(sec_pmic); 497 case S2MPS11X: 498 sec_irq_chip = &s2mps11_irq_chip; 499 break; 500 case S2MPS13X: 501 sec_irq_chip = &s2mps13_irq_chip; 502 break; 503 case S2MPS14X: 504 sec_irq_chip = &s2mps14_irq_chip; 505 break; 506 case S2MPS15X: 507 sec_irq_chip = &s2mps15_irq_chip; 508 break; 509 case S2MPU02: 510 sec_irq_chip = &s2mpu02_irq_chip; 511 break; 512 case S2MPU05: 513 sec_irq_chip = &s2mpu05_irq_chip; 514 break; 515 case S2MU005: 516 sec_irq_chip = &s2mu005_irq_chip; 517 break; 518 default: 519 return dev_err_ptr_probe(sec_pmic->dev, -EINVAL, "Unsupported device type %d\n", 520 sec_pmic->device_type); 521 } 522 523 if (!sec_pmic->irq) { 524 dev_warn(sec_pmic->dev, 525 "No interrupt specified, no interrupts\n"); 526 return NULL; 527 } 528 529 ret = devm_regmap_add_irq_chip(sec_pmic->dev, sec_pmic->regmap_pmic, 530 sec_pmic->irq, IRQF_ONESHOT, 531 0, sec_irq_chip, &sec_irq_chip_data); 532 if (ret) 533 return dev_err_ptr_probe(sec_pmic->dev, ret, "Failed to add %s IRQ chip\n", 534 sec_irq_chip->name); 535 536 return sec_irq_chip_data; 537 } 538