1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Copyright (c) 2011-2014 Samsung Electronics Co., Ltd 4 // http://www.samsung.com 5 6 #include <linux/array_size.h> 7 #include <linux/build_bug.h> 8 #include <linux/dev_printk.h> 9 #include <linux/interrupt.h> 10 #include <linux/irq.h> 11 #include <linux/mfd/samsung/core.h> 12 #include <linux/mfd/samsung/irq.h> 13 #include <linux/mfd/samsung/s2mpg10.h> 14 #include <linux/mfd/samsung/s2mpg11.h> 15 #include <linux/mfd/samsung/s2mps11.h> 16 #include <linux/mfd/samsung/s2mps14.h> 17 #include <linux/mfd/samsung/s2mpu02.h> 18 #include <linux/mfd/samsung/s2mpu05.h> 19 #include <linux/mfd/samsung/s5m8767.h> 20 #include <linux/regmap.h> 21 #include "sec-core.h" 22 23 static const struct regmap_irq s2mpg10_irqs[] = { 24 REGMAP_IRQ_REG(S2MPG10_COMMON_IRQ_PMIC, 0, S2MPG10_COMMON_INT_SRC_PMIC), 25 /* No documentation or other reference for remaining bits */ 26 REGMAP_IRQ_REG(S2MPG10_COMMON_IRQ_UNUSED, 0, GENMASK(7, 1)), 27 }; 28 29 static const struct regmap_irq s2mpg10_pmic_irqs[] = { 30 REGMAP_IRQ_REG(S2MPG10_IRQ_PWRONF, 0, S2MPG10_IRQ_PWRONF_MASK), 31 REGMAP_IRQ_REG(S2MPG10_IRQ_PWRONR, 0, S2MPG10_IRQ_PWRONR_MASK), 32 REGMAP_IRQ_REG(S2MPG10_IRQ_JIGONBF, 0, S2MPG10_IRQ_JIGONBF_MASK), 33 REGMAP_IRQ_REG(S2MPG10_IRQ_JIGONBR, 0, S2MPG10_IRQ_JIGONBR_MASK), 34 REGMAP_IRQ_REG(S2MPG10_IRQ_ACOKBF, 0, S2MPG10_IRQ_ACOKBF_MASK), 35 REGMAP_IRQ_REG(S2MPG10_IRQ_ACOKBR, 0, S2MPG10_IRQ_ACOKBR_MASK), 36 REGMAP_IRQ_REG(S2MPG10_IRQ_PWRON1S, 0, S2MPG10_IRQ_PWRON1S_MASK), 37 REGMAP_IRQ_REG(S2MPG10_IRQ_MRB, 0, S2MPG10_IRQ_MRB_MASK), 38 39 REGMAP_IRQ_REG(S2MPG10_IRQ_RTC60S, 1, S2MPG10_IRQ_RTC60S_MASK), 40 REGMAP_IRQ_REG(S2MPG10_IRQ_RTCA1, 1, S2MPG10_IRQ_RTCA1_MASK), 41 REGMAP_IRQ_REG(S2MPG10_IRQ_RTCA0, 1, S2MPG10_IRQ_RTCA0_MASK), 42 REGMAP_IRQ_REG(S2MPG10_IRQ_RTC1S, 1, S2MPG10_IRQ_RTC1S_MASK), 43 REGMAP_IRQ_REG(S2MPG10_IRQ_WTSR_COLDRST, 1, S2MPG10_IRQ_WTSR_COLDRST_MASK), 44 REGMAP_IRQ_REG(S2MPG10_IRQ_WTSR, 1, S2MPG10_IRQ_WTSR_MASK), 45 REGMAP_IRQ_REG(S2MPG10_IRQ_WRST, 1, S2MPG10_IRQ_WRST_MASK), 46 REGMAP_IRQ_REG(S2MPG10_IRQ_SMPL, 1, S2MPG10_IRQ_SMPL_MASK), 47 48 REGMAP_IRQ_REG(S2MPG10_IRQ_120C, 2, S2MPG10_IRQ_INT120C_MASK), 49 REGMAP_IRQ_REG(S2MPG10_IRQ_140C, 2, S2MPG10_IRQ_INT140C_MASK), 50 REGMAP_IRQ_REG(S2MPG10_IRQ_TSD, 2, S2MPG10_IRQ_TSD_MASK), 51 REGMAP_IRQ_REG(S2MPG10_IRQ_PIF_TIMEOUT1, 2, S2MPG10_IRQ_PIF_TIMEOUT1_MASK), 52 REGMAP_IRQ_REG(S2MPG10_IRQ_PIF_TIMEOUT2, 2, S2MPG10_IRQ_PIF_TIMEOUT2_MASK), 53 REGMAP_IRQ_REG(S2MPG10_IRQ_SPD_PARITY_ERR, 2, S2MPG10_IRQ_SPD_PARITY_ERR_MASK), 54 REGMAP_IRQ_REG(S2MPG10_IRQ_SPD_ABNORMAL_STOP, 2, S2MPG10_IRQ_SPD_ABNORMAL_STOP_MASK), 55 REGMAP_IRQ_REG(S2MPG10_IRQ_PMETER_OVERF, 2, S2MPG10_IRQ_PMETER_OVERF_MASK), 56 57 REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B1M, 3, S2MPG10_IRQ_OCP_B1M_MASK), 58 REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B2M, 3, S2MPG10_IRQ_OCP_B2M_MASK), 59 REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B3M, 3, S2MPG10_IRQ_OCP_B3M_MASK), 60 REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B4M, 3, S2MPG10_IRQ_OCP_B4M_MASK), 61 REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B5M, 3, S2MPG10_IRQ_OCP_B5M_MASK), 62 REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B6M, 3, S2MPG10_IRQ_OCP_B6M_MASK), 63 REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B7M, 3, S2MPG10_IRQ_OCP_B7M_MASK), 64 REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B8M, 3, S2MPG10_IRQ_OCP_B8M_MASK), 65 66 REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B9M, 4, S2MPG10_IRQ_OCP_B9M_MASK), 67 REGMAP_IRQ_REG(S2MPG10_IRQ_OCP_B10M, 4, S2MPG10_IRQ_OCP_B10M_MASK), 68 REGMAP_IRQ_REG(S2MPG10_IRQ_WLWP_ACC, 4, S2MPG10_IRQ_WLWP_ACC_MASK), 69 REGMAP_IRQ_REG(S2MPG10_IRQ_SMPL_TIMEOUT, 4, S2MPG10_IRQ_SMPL_TIMEOUT_MASK), 70 REGMAP_IRQ_REG(S2MPG10_IRQ_WTSR_TIMEOUT, 4, S2MPG10_IRQ_WTSR_TIMEOUT_MASK), 71 REGMAP_IRQ_REG(S2MPG10_IRQ_SPD_SRP_PKT_RST, 4, S2MPG10_IRQ_SPD_SRP_PKT_RST_MASK), 72 73 REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH0, 5, S2MPG10_IRQ_PWR_WARN_CH0_MASK), 74 REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH1, 5, S2MPG10_IRQ_PWR_WARN_CH1_MASK), 75 REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH2, 5, S2MPG10_IRQ_PWR_WARN_CH2_MASK), 76 REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH3, 5, S2MPG10_IRQ_PWR_WARN_CH3_MASK), 77 REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH4, 5, S2MPG10_IRQ_PWR_WARN_CH4_MASK), 78 REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH5, 5, S2MPG10_IRQ_PWR_WARN_CH5_MASK), 79 REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH6, 5, S2MPG10_IRQ_PWR_WARN_CH6_MASK), 80 REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH7, 5, S2MPG10_IRQ_PWR_WARN_CH7_MASK), 81 }; 82 83 static const struct regmap_irq s2mpg11_irqs[] = { 84 REGMAP_IRQ_REG(S2MPG11_COMMON_IRQ_PMIC, 0, S2MPG11_COMMON_INT_SRC_PMIC), 85 /* No documentation or other reference for remaining bits */ 86 REGMAP_IRQ_REG(S2MPG11_COMMON_IRQ_UNUSED, 0, GENMASK(7, 1)), 87 }; 88 89 static const struct regmap_irq s2mpg11_pmic_irqs[] = { 90 REGMAP_IRQ_REG(S2MPG11_IRQ_PWRONF, 0, S2MPG11_IRQ_PWRONF_MASK), 91 REGMAP_IRQ_REG(S2MPG11_IRQ_PWRONR, 0, S2MPG11_IRQ_PWRONR_MASK), 92 REGMAP_IRQ_REG(S2MPG11_IRQ_PIF_TIMEOUT_MIF, 0, S2MPG11_IRQ_PIF_TIMEOUT_MIF_MASK), 93 REGMAP_IRQ_REG(S2MPG11_IRQ_PIF_TIMEOUTS, 0, S2MPG11_IRQ_PIF_TIMEOUTS_MASK), 94 REGMAP_IRQ_REG(S2MPG11_IRQ_WTSR, 0, S2MPG11_IRQ_WTSR_MASK), 95 REGMAP_IRQ_REG(S2MPG11_IRQ_SPD_ABNORMAL_STOP, 0, S2MPG11_IRQ_SPD_ABNORMAL_STOP_MASK), 96 REGMAP_IRQ_REG(S2MPG11_IRQ_SPD_PARITY_ERR, 0, S2MPG11_IRQ_SPD_PARITY_ERR_MASK), 97 98 REGMAP_IRQ_REG(S2MPG11_IRQ_140C, 1, S2MPG11_IRQ_INT140C_MASK), 99 REGMAP_IRQ_REG(S2MPG11_IRQ_120C, 1, S2MPG11_IRQ_INT120C_MASK), 100 REGMAP_IRQ_REG(S2MPG11_IRQ_TSD, 1, S2MPG11_IRQ_TSD_MASK), 101 REGMAP_IRQ_REG(S2MPG11_IRQ_WRST, 1, S2MPG11_IRQ_WRST_MASK), 102 REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_CYCLE_DONE, 1, S2MPG11_IRQ_NTC_CYCLE_DONE_MASK), 103 REGMAP_IRQ_REG(S2MPG11_IRQ_PMETER_OVERF, 1, S2MPG11_IRQ_PMETER_OVERF_MASK), 104 105 REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B1S, 2, S2MPG11_IRQ_OCP_B1S_MASK), 106 REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B2S, 2, S2MPG11_IRQ_OCP_B2S_MASK), 107 REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B3S, 2, S2MPG11_IRQ_OCP_B3S_MASK), 108 REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B4S, 2, S2MPG11_IRQ_OCP_B4S_MASK), 109 REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B5S, 2, S2MPG11_IRQ_OCP_B5S_MASK), 110 REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B6S, 2, S2MPG11_IRQ_OCP_B6S_MASK), 111 REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B7S, 2, S2MPG11_IRQ_OCP_B7S_MASK), 112 REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B8S, 2, S2MPG11_IRQ_OCP_B8S_MASK), 113 114 REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B9S, 3, S2MPG11_IRQ_OCP_B9S_MASK), 115 REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B10S, 3, S2MPG11_IRQ_OCP_B10S_MASK), 116 REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_BDS, 3, S2MPG11_IRQ_OCP_BDS_MASK), 117 REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_BAS, 3, S2MPG11_IRQ_OCP_BAS_MASK), 118 REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_BBS, 3, S2MPG11_IRQ_OCP_BBS_MASK), 119 REGMAP_IRQ_REG(S2MPG11_IRQ_WLWP_ACC, 3, S2MPG11_IRQ_WLWP_ACC_MASK), 120 REGMAP_IRQ_REG(S2MPG11_IRQ_SPD_SRP_PKT_RST, 3, S2MPG11_IRQ_SPD_SRP_PKT_RST_MASK), 121 122 REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH0, 4, S2MPG11_IRQ_PWR_WARN_CH0_MASK), 123 REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH1, 4, S2MPG11_IRQ_PWR_WARN_CH1_MASK), 124 REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH2, 4, S2MPG11_IRQ_PWR_WARN_CH2_MASK), 125 REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH3, 4, S2MPG11_IRQ_PWR_WARN_CH3_MASK), 126 REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH4, 4, S2MPG11_IRQ_PWR_WARN_CH4_MASK), 127 REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH5, 4, S2MPG11_IRQ_PWR_WARN_CH5_MASK), 128 REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH6, 4, S2MPG11_IRQ_PWR_WARN_CH6_MASK), 129 REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH7, 4, S2MPG11_IRQ_PWR_WARN_CH7_MASK), 130 131 REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH0, 5, S2MPG11_IRQ_NTC_WARN_CH0_MASK), 132 REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH1, 5, S2MPG11_IRQ_NTC_WARN_CH1_MASK), 133 REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH2, 5, S2MPG11_IRQ_NTC_WARN_CH2_MASK), 134 REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH3, 5, S2MPG11_IRQ_NTC_WARN_CH3_MASK), 135 REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH4, 5, S2MPG11_IRQ_NTC_WARN_CH4_MASK), 136 REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH5, 5, S2MPG11_IRQ_NTC_WARN_CH5_MASK), 137 REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH6, 5, S2MPG11_IRQ_NTC_WARN_CH6_MASK), 138 REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH7, 5, S2MPG11_IRQ_NTC_WARN_CH7_MASK), 139 }; 140 141 static const struct regmap_irq s2mps11_irqs[] = { 142 REGMAP_IRQ_REG(S2MPS11_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK), 143 REGMAP_IRQ_REG(S2MPS11_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK), 144 REGMAP_IRQ_REG(S2MPS11_IRQ_JIGONBF, 0, S2MPS11_IRQ_JIGONBF_MASK), 145 REGMAP_IRQ_REG(S2MPS11_IRQ_JIGONBR, 0, S2MPS11_IRQ_JIGONBR_MASK), 146 REGMAP_IRQ_REG(S2MPS11_IRQ_ACOKBF, 0, S2MPS11_IRQ_ACOKBF_MASK), 147 REGMAP_IRQ_REG(S2MPS11_IRQ_ACOKBR, 0, S2MPS11_IRQ_ACOKBR_MASK), 148 REGMAP_IRQ_REG(S2MPS11_IRQ_PWRON1S, 0, S2MPS11_IRQ_PWRON1S_MASK), 149 REGMAP_IRQ_REG(S2MPS11_IRQ_MRB, 0, S2MPS11_IRQ_MRB_MASK), 150 151 REGMAP_IRQ_REG(S2MPS11_IRQ_RTC60S, 1, S2MPS11_IRQ_RTC60S_MASK), 152 REGMAP_IRQ_REG(S2MPS11_IRQ_RTCA1, 1, S2MPS11_IRQ_RTCA1_MASK), 153 REGMAP_IRQ_REG(S2MPS11_IRQ_RTCA0, 1, S2MPS11_IRQ_RTCA0_MASK), 154 REGMAP_IRQ_REG(S2MPS11_IRQ_SMPL, 1, S2MPS11_IRQ_SMPL_MASK), 155 REGMAP_IRQ_REG(S2MPS11_IRQ_RTC1S, 1, S2MPS11_IRQ_RTC1S_MASK), 156 REGMAP_IRQ_REG(S2MPS11_IRQ_WTSR, 1, S2MPS11_IRQ_WTSR_MASK), 157 158 REGMAP_IRQ_REG(S2MPS11_IRQ_INT120C, 2, S2MPS11_IRQ_INT120C_MASK), 159 REGMAP_IRQ_REG(S2MPS11_IRQ_INT140C, 2, S2MPS11_IRQ_INT140C_MASK), 160 }; 161 162 static const struct regmap_irq s2mps14_irqs[] = { 163 REGMAP_IRQ_REG(S2MPS14_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK), 164 REGMAP_IRQ_REG(S2MPS14_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK), 165 REGMAP_IRQ_REG(S2MPS14_IRQ_JIGONBF, 0, S2MPS11_IRQ_JIGONBF_MASK), 166 REGMAP_IRQ_REG(S2MPS14_IRQ_JIGONBR, 0, S2MPS11_IRQ_JIGONBR_MASK), 167 REGMAP_IRQ_REG(S2MPS14_IRQ_ACOKBF, 0, S2MPS11_IRQ_ACOKBF_MASK), 168 REGMAP_IRQ_REG(S2MPS14_IRQ_ACOKBR, 0, S2MPS11_IRQ_ACOKBR_MASK), 169 REGMAP_IRQ_REG(S2MPS14_IRQ_PWRON1S, 0, S2MPS11_IRQ_PWRON1S_MASK), 170 REGMAP_IRQ_REG(S2MPS14_IRQ_MRB, 0, S2MPS11_IRQ_MRB_MASK), 171 172 REGMAP_IRQ_REG(S2MPS14_IRQ_RTC60S, 1, S2MPS11_IRQ_RTC60S_MASK), 173 REGMAP_IRQ_REG(S2MPS14_IRQ_RTCA1, 1, S2MPS11_IRQ_RTCA1_MASK), 174 REGMAP_IRQ_REG(S2MPS14_IRQ_RTCA0, 1, S2MPS11_IRQ_RTCA0_MASK), 175 REGMAP_IRQ_REG(S2MPS14_IRQ_SMPL, 1, S2MPS11_IRQ_SMPL_MASK), 176 REGMAP_IRQ_REG(S2MPS14_IRQ_RTC1S, 1, S2MPS11_IRQ_RTC1S_MASK), 177 REGMAP_IRQ_REG(S2MPS14_IRQ_WTSR, 1, S2MPS11_IRQ_WTSR_MASK), 178 179 REGMAP_IRQ_REG(S2MPS14_IRQ_INT120C, 2, S2MPS11_IRQ_INT120C_MASK), 180 REGMAP_IRQ_REG(S2MPS14_IRQ_INT140C, 2, S2MPS11_IRQ_INT140C_MASK), 181 REGMAP_IRQ_REG(S2MPS14_IRQ_TSD, 2, S2MPS14_IRQ_TSD_MASK), 182 }; 183 184 static const struct regmap_irq s2mpu02_irqs[] = { 185 REGMAP_IRQ_REG(S2MPU02_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK), 186 REGMAP_IRQ_REG(S2MPU02_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK), 187 REGMAP_IRQ_REG(S2MPU02_IRQ_JIGONBF, 0, S2MPS11_IRQ_JIGONBF_MASK), 188 REGMAP_IRQ_REG(S2MPU02_IRQ_JIGONBR, 0, S2MPS11_IRQ_JIGONBR_MASK), 189 REGMAP_IRQ_REG(S2MPU02_IRQ_ACOKBF, 0, S2MPS11_IRQ_ACOKBF_MASK), 190 REGMAP_IRQ_REG(S2MPU02_IRQ_ACOKBR, 0, S2MPS11_IRQ_ACOKBR_MASK), 191 REGMAP_IRQ_REG(S2MPU02_IRQ_PWRON1S, 0, S2MPS11_IRQ_PWRON1S_MASK), 192 REGMAP_IRQ_REG(S2MPU02_IRQ_MRB, 0, S2MPS11_IRQ_MRB_MASK), 193 194 REGMAP_IRQ_REG(S2MPU02_IRQ_RTC60S, 1, S2MPS11_IRQ_RTC60S_MASK), 195 REGMAP_IRQ_REG(S2MPU02_IRQ_RTCA1, 1, S2MPS11_IRQ_RTCA1_MASK), 196 REGMAP_IRQ_REG(S2MPU02_IRQ_RTCA0, 1, S2MPS11_IRQ_RTCA0_MASK), 197 REGMAP_IRQ_REG(S2MPU02_IRQ_SMPL, 1, S2MPS11_IRQ_SMPL_MASK), 198 REGMAP_IRQ_REG(S2MPU02_IRQ_RTC1S, 1, S2MPS11_IRQ_RTC1S_MASK), 199 REGMAP_IRQ_REG(S2MPU02_IRQ_WTSR, 1, S2MPS11_IRQ_WTSR_MASK), 200 201 REGMAP_IRQ_REG(S2MPU02_IRQ_INT120C, 2, S2MPS11_IRQ_INT120C_MASK), 202 REGMAP_IRQ_REG(S2MPU02_IRQ_INT140C, 2, S2MPS11_IRQ_INT140C_MASK), 203 REGMAP_IRQ_REG(S2MPU02_IRQ_TSD, 2, S2MPS14_IRQ_TSD_MASK), 204 }; 205 206 static const struct regmap_irq s2mpu05_irqs[] = { 207 REGMAP_IRQ_REG(S2MPU05_IRQ_PWRONF, 0, S2MPU05_IRQ_PWRONF_MASK), 208 REGMAP_IRQ_REG(S2MPU05_IRQ_PWRONR, 0, S2MPU05_IRQ_PWRONR_MASK), 209 REGMAP_IRQ_REG(S2MPU05_IRQ_JIGONBF, 0, S2MPU05_IRQ_JIGONBF_MASK), 210 REGMAP_IRQ_REG(S2MPU05_IRQ_JIGONBR, 0, S2MPU05_IRQ_JIGONBR_MASK), 211 REGMAP_IRQ_REG(S2MPU05_IRQ_ACOKF, 0, S2MPU05_IRQ_ACOKF_MASK), 212 REGMAP_IRQ_REG(S2MPU05_IRQ_ACOKR, 0, S2MPU05_IRQ_ACOKR_MASK), 213 REGMAP_IRQ_REG(S2MPU05_IRQ_PWRON1S, 0, S2MPU05_IRQ_PWRON1S_MASK), 214 REGMAP_IRQ_REG(S2MPU05_IRQ_MRB, 0, S2MPU05_IRQ_MRB_MASK), 215 REGMAP_IRQ_REG(S2MPU05_IRQ_RTC60S, 1, S2MPU05_IRQ_RTC60S_MASK), 216 REGMAP_IRQ_REG(S2MPU05_IRQ_RTCA1, 1, S2MPU05_IRQ_RTCA1_MASK), 217 REGMAP_IRQ_REG(S2MPU05_IRQ_RTCA0, 1, S2MPU05_IRQ_RTCA0_MASK), 218 REGMAP_IRQ_REG(S2MPU05_IRQ_SMPL, 1, S2MPU05_IRQ_SMPL_MASK), 219 REGMAP_IRQ_REG(S2MPU05_IRQ_RTC1S, 1, S2MPU05_IRQ_RTC1S_MASK), 220 REGMAP_IRQ_REG(S2MPU05_IRQ_WTSR, 1, S2MPU05_IRQ_WTSR_MASK), 221 REGMAP_IRQ_REG(S2MPU05_IRQ_INT120C, 2, S2MPU05_IRQ_INT120C_MASK), 222 REGMAP_IRQ_REG(S2MPU05_IRQ_INT140C, 2, S2MPU05_IRQ_INT140C_MASK), 223 REGMAP_IRQ_REG(S2MPU05_IRQ_TSD, 2, S2MPU05_IRQ_TSD_MASK), 224 }; 225 226 static const struct regmap_irq s5m8767_irqs[] = { 227 REGMAP_IRQ_REG(S5M8767_IRQ_PWRR, 0, S5M8767_IRQ_PWRR_MASK), 228 REGMAP_IRQ_REG(S5M8767_IRQ_PWRF, 0, S5M8767_IRQ_PWRF_MASK), 229 REGMAP_IRQ_REG(S5M8767_IRQ_PWR1S, 0, S5M8767_IRQ_PWR1S_MASK), 230 REGMAP_IRQ_REG(S5M8767_IRQ_JIGR, 0, S5M8767_IRQ_JIGR_MASK), 231 REGMAP_IRQ_REG(S5M8767_IRQ_JIGF, 0, S5M8767_IRQ_JIGF_MASK), 232 REGMAP_IRQ_REG(S5M8767_IRQ_LOWBAT2, 0, S5M8767_IRQ_LOWBAT2_MASK), 233 REGMAP_IRQ_REG(S5M8767_IRQ_LOWBAT1, 0, S5M8767_IRQ_LOWBAT1_MASK), 234 235 REGMAP_IRQ_REG(S5M8767_IRQ_MRB, 1, S5M8767_IRQ_MRB_MASK), 236 REGMAP_IRQ_REG(S5M8767_IRQ_DVSOK2, 1, S5M8767_IRQ_DVSOK2_MASK), 237 REGMAP_IRQ_REG(S5M8767_IRQ_DVSOK3, 1, S5M8767_IRQ_DVSOK3_MASK), 238 REGMAP_IRQ_REG(S5M8767_IRQ_DVSOK4, 1, S5M8767_IRQ_DVSOK4_MASK), 239 240 REGMAP_IRQ_REG(S5M8767_IRQ_RTC60S, 2, S5M8767_IRQ_RTC60S_MASK), 241 REGMAP_IRQ_REG(S5M8767_IRQ_RTCA1, 2, S5M8767_IRQ_RTCA1_MASK), 242 REGMAP_IRQ_REG(S5M8767_IRQ_RTCA2, 2, S5M8767_IRQ_RTCA2_MASK), 243 REGMAP_IRQ_REG(S5M8767_IRQ_SMPL, 2, S5M8767_IRQ_SMPL_MASK), 244 REGMAP_IRQ_REG(S5M8767_IRQ_RTC1S, 2, S5M8767_IRQ_RTC1S_MASK), 245 REGMAP_IRQ_REG(S5M8767_IRQ_WTSR, 2, S5M8767_IRQ_WTSR_MASK), 246 }; 247 248 /* All S2MPG1x interrupt sources are read-only and don't require clearing */ 249 static const struct regmap_irq_chip s2mpg10_irq_chip = { 250 .name = "s2mpg10", 251 .status_base = S2MPG10_COMMON_INT, 252 .mask_base = S2MPG10_COMMON_INT_MASK, 253 .num_regs = 1, 254 .irqs = s2mpg10_irqs, 255 .num_irqs = ARRAY_SIZE(s2mpg10_irqs), 256 }; 257 258 static const struct regmap_irq_chip s2mpg10_irq_chip_pmic = { 259 .name = "s2mpg10-pmic", 260 .status_base = S2MPG10_PMIC_INT1, 261 .mask_base = S2MPG10_PMIC_INT1M, 262 .num_regs = 6, 263 .irqs = s2mpg10_pmic_irqs, 264 .num_irqs = ARRAY_SIZE(s2mpg10_pmic_irqs), 265 }; 266 267 static const struct regmap_irq_chip s2mpg11_irq_chip = { 268 .name = "s2mpg11", 269 .status_base = S2MPG11_COMMON_INT, 270 .mask_base = S2MPG11_COMMON_INT_MASK, 271 .num_regs = 1, 272 .irqs = s2mpg11_irqs, 273 .num_irqs = ARRAY_SIZE(s2mpg11_irqs), 274 }; 275 276 static const struct regmap_irq_chip s2mpg11_irq_chip_pmic = { 277 .name = "s2mpg11-pmic", 278 .domain_suffix = "pmic", 279 .status_base = S2MPG11_PMIC_INT1, 280 .mask_base = S2MPG11_PMIC_INT1M, 281 .num_regs = 6, 282 .irqs = s2mpg11_pmic_irqs, 283 .num_irqs = ARRAY_SIZE(s2mpg11_pmic_irqs), 284 }; 285 286 static const struct regmap_irq_chip s2mps11_irq_chip = { 287 .name = "s2mps11", 288 .irqs = s2mps11_irqs, 289 .num_irqs = ARRAY_SIZE(s2mps11_irqs), 290 .num_regs = 3, 291 .status_base = S2MPS11_REG_INT1, 292 .mask_base = S2MPS11_REG_INT1M, 293 .ack_base = S2MPS11_REG_INT1, 294 }; 295 296 #define S2MPS1X_IRQ_CHIP_COMMON_DATA \ 297 .irqs = s2mps14_irqs, \ 298 .num_irqs = ARRAY_SIZE(s2mps14_irqs), \ 299 .num_regs = 3, \ 300 .status_base = S2MPS14_REG_INT1, \ 301 .mask_base = S2MPS14_REG_INT1M, \ 302 .ack_base = S2MPS14_REG_INT1 \ 303 304 static const struct regmap_irq_chip s2mps13_irq_chip = { 305 .name = "s2mps13", 306 S2MPS1X_IRQ_CHIP_COMMON_DATA, 307 }; 308 309 static const struct regmap_irq_chip s2mps14_irq_chip = { 310 .name = "s2mps14", 311 S2MPS1X_IRQ_CHIP_COMMON_DATA, 312 }; 313 314 static const struct regmap_irq_chip s2mps15_irq_chip = { 315 .name = "s2mps15", 316 S2MPS1X_IRQ_CHIP_COMMON_DATA, 317 }; 318 319 static const struct regmap_irq_chip s2mpu02_irq_chip = { 320 .name = "s2mpu02", 321 .irqs = s2mpu02_irqs, 322 .num_irqs = ARRAY_SIZE(s2mpu02_irqs), 323 .num_regs = 3, 324 .status_base = S2MPU02_REG_INT1, 325 .mask_base = S2MPU02_REG_INT1M, 326 .ack_base = S2MPU02_REG_INT1, 327 }; 328 329 static const struct regmap_irq_chip s2mpu05_irq_chip = { 330 .name = "s2mpu05", 331 .irqs = s2mpu05_irqs, 332 .num_irqs = ARRAY_SIZE(s2mpu05_irqs), 333 .num_regs = 3, 334 .status_base = S2MPU05_REG_INT1, 335 .mask_base = S2MPU05_REG_INT1M, 336 .ack_base = S2MPU05_REG_INT1, 337 }; 338 339 static const struct regmap_irq_chip s5m8767_irq_chip = { 340 .name = "s5m8767", 341 .irqs = s5m8767_irqs, 342 .num_irqs = ARRAY_SIZE(s5m8767_irqs), 343 .num_regs = 3, 344 .status_base = S5M8767_REG_INT1, 345 .mask_base = S5M8767_REG_INT1M, 346 .ack_base = S5M8767_REG_INT1, 347 }; 348 349 static struct regmap_irq_chip_data * 350 s2mpg1x_add_chained_pmic(struct sec_pmic_dev *sec_pmic, int pirq, 351 struct regmap_irq_chip_data *parent, const struct regmap_irq_chip *chip) 352 { 353 struct device *dev = sec_pmic->dev; 354 struct regmap_irq_chip_data *data; 355 int irq, ret; 356 357 irq = regmap_irq_get_virq(parent, pirq); 358 if (irq < 0) 359 return dev_err_ptr_probe(dev, irq, "Failed to get parent vIRQ(%d) for chip %s\n", 360 pirq, chip->name); 361 362 ret = devm_regmap_add_irq_chip(dev, sec_pmic->regmap_pmic, irq, 363 IRQF_ONESHOT | IRQF_SHARED, 0, chip, &data); 364 if (ret) 365 return dev_err_ptr_probe(dev, ret, "Failed to add %s IRQ chip\n", chip->name); 366 367 return data; 368 } 369 370 static struct regmap_irq_chip_data *sec_irq_init_s2mpg1x(struct sec_pmic_dev *sec_pmic) 371 { 372 const struct regmap_irq_chip *irq_chip, *chained_irq_chip; 373 struct regmap_irq_chip_data *irq_data; 374 struct regmap *regmap_common; 375 int chained_pirq; 376 int ret; 377 378 switch (sec_pmic->device_type) { 379 case S2MPG10: 380 irq_chip = &s2mpg10_irq_chip; 381 chained_irq_chip = &s2mpg10_irq_chip_pmic; 382 chained_pirq = S2MPG10_COMMON_IRQ_PMIC; 383 break; 384 case S2MPG11: 385 irq_chip = &s2mpg11_irq_chip; 386 chained_irq_chip = &s2mpg11_irq_chip_pmic; 387 chained_pirq = S2MPG11_COMMON_IRQ_PMIC; 388 break; 389 default: 390 return dev_err_ptr_probe(sec_pmic->dev, -EINVAL, "Unsupported device type %d\n", 391 sec_pmic->device_type); 392 } 393 394 regmap_common = dev_get_regmap(sec_pmic->dev, "common"); 395 if (!regmap_common) 396 return dev_err_ptr_probe(sec_pmic->dev, -EINVAL, "No 'common' regmap %d\n", 397 sec_pmic->device_type); 398 399 ret = devm_regmap_add_irq_chip(sec_pmic->dev, regmap_common, sec_pmic->irq, IRQF_ONESHOT, 0, 400 irq_chip, &irq_data); 401 if (ret) 402 return dev_err_ptr_probe(sec_pmic->dev, ret, "Failed to add %s IRQ chip\n", 403 irq_chip->name); 404 405 return s2mpg1x_add_chained_pmic(sec_pmic, chained_pirq, irq_data, chained_irq_chip); 406 } 407 408 struct regmap_irq_chip_data *sec_irq_init(struct sec_pmic_dev *sec_pmic) 409 { 410 struct regmap_irq_chip_data *sec_irq_chip_data; 411 const struct regmap_irq_chip *sec_irq_chip; 412 int ret; 413 414 switch (sec_pmic->device_type) { 415 case S5M8767X: 416 sec_irq_chip = &s5m8767_irq_chip; 417 break; 418 case S2DOS05: 419 return NULL; 420 case S2MPA01: 421 sec_irq_chip = &s2mps14_irq_chip; 422 break; 423 case S2MPG10: 424 case S2MPG11: 425 return sec_irq_init_s2mpg1x(sec_pmic); 426 case S2MPS11X: 427 sec_irq_chip = &s2mps11_irq_chip; 428 break; 429 case S2MPS13X: 430 sec_irq_chip = &s2mps13_irq_chip; 431 break; 432 case S2MPS14X: 433 sec_irq_chip = &s2mps14_irq_chip; 434 break; 435 case S2MPS15X: 436 sec_irq_chip = &s2mps15_irq_chip; 437 break; 438 case S2MPU02: 439 sec_irq_chip = &s2mpu02_irq_chip; 440 break; 441 case S2MPU05: 442 sec_irq_chip = &s2mpu05_irq_chip; 443 break; 444 default: 445 return dev_err_ptr_probe(sec_pmic->dev, -EINVAL, "Unsupported device type %d\n", 446 sec_pmic->device_type); 447 } 448 449 if (!sec_pmic->irq) { 450 dev_warn(sec_pmic->dev, 451 "No interrupt specified, no interrupts\n"); 452 return NULL; 453 } 454 455 ret = devm_regmap_add_irq_chip(sec_pmic->dev, sec_pmic->regmap_pmic, 456 sec_pmic->irq, IRQF_ONESHOT, 457 0, sec_irq_chip, &sec_irq_chip_data); 458 if (ret) 459 return dev_err_ptr_probe(sec_pmic->dev, ret, "Failed to add %s IRQ chip\n", 460 sec_irq_chip->name); 461 462 return sec_irq_chip_data; 463 } 464