1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2024 ROHM Semiconductors 4 * 5 * ROHM BD96801 PMIC driver 6 * 7 * This version of the "BD86801 scalable PMIC"'s driver supports only very 8 * basic set of the PMIC features. 9 * Most notably, there is no support for the configurations which should 10 * be done when the PMIC is in STBY mode. 11 * 12 * Being able to reliably do the configurations like changing the 13 * regulator safety limits (like limits for the over/under -voltages, over 14 * current, thermal protection) would require the configuring driver to be 15 * synchronized with entity causing the PMIC state transitions. Eg, one 16 * should be able to ensure the PMIC is in STBY state when the 17 * configurations are applied to the hardware. How and when the PMIC state 18 * transitions are to be done is likely to be very system specific, as will 19 * be the need to configure these safety limits. Hence it's not simple to 20 * come up with a generic solution. 21 * 22 * Users who require the STBY state configurations can have a look at the 23 * original RFC: 24 * https://lore.kernel.org/all/cover.1712920132.git.mazziesaccount@gmail.com/ 25 * which implements some of the safety limit configurations - but leaves the 26 * state change handling and synchronization to be implemented. 27 * 28 * It would be great to hear (and receive a patch!) if you implement the 29 * STBY configuration support or a proper fix in your downstream driver ;) 30 */ 31 32 #include <linux/i2c.h> 33 #include <linux/interrupt.h> 34 #include <linux/mfd/core.h> 35 #include <linux/module.h> 36 #include <linux/property.h> 37 #include <linux/regmap.h> 38 #include <linux/types.h> 39 40 #include <linux/mfd/rohm-bd96801.h> 41 #include <linux/mfd/rohm-generic.h> 42 43 static const struct resource regulator_errb_irqs[] = { 44 DEFINE_RES_IRQ_NAMED(BD96801_OTP_ERR_STAT, "bd96801-otp-err"), 45 DEFINE_RES_IRQ_NAMED(BD96801_DBIST_ERR_STAT, "bd96801-dbist-err"), 46 DEFINE_RES_IRQ_NAMED(BD96801_EEP_ERR_STAT, "bd96801-eep-err"), 47 DEFINE_RES_IRQ_NAMED(BD96801_ABIST_ERR_STAT, "bd96801-abist-err"), 48 DEFINE_RES_IRQ_NAMED(BD96801_PRSTB_ERR_STAT, "bd96801-prstb-err"), 49 DEFINE_RES_IRQ_NAMED(BD96801_DRMOS1_ERR_STAT, "bd96801-drmoserr1"), 50 DEFINE_RES_IRQ_NAMED(BD96801_DRMOS2_ERR_STAT, "bd96801-drmoserr2"), 51 DEFINE_RES_IRQ_NAMED(BD96801_SLAVE_ERR_STAT, "bd96801-slave-err"), 52 DEFINE_RES_IRQ_NAMED(BD96801_VREF_ERR_STAT, "bd96801-vref-err"), 53 DEFINE_RES_IRQ_NAMED(BD96801_TSD_ERR_STAT, "bd96801-tsd"), 54 DEFINE_RES_IRQ_NAMED(BD96801_UVLO_ERR_STAT, "bd96801-uvlo-err"), 55 DEFINE_RES_IRQ_NAMED(BD96801_OVLO_ERR_STAT, "bd96801-ovlo-err"), 56 DEFINE_RES_IRQ_NAMED(BD96801_OSC_ERR_STAT, "bd96801-osc-err"), 57 DEFINE_RES_IRQ_NAMED(BD96801_PON_ERR_STAT, "bd96801-pon-err"), 58 DEFINE_RES_IRQ_NAMED(BD96801_POFF_ERR_STAT, "bd96801-poff-err"), 59 DEFINE_RES_IRQ_NAMED(BD96801_CMD_SHDN_ERR_STAT, "bd96801-cmd-shdn-err"), 60 61 DEFINE_RES_IRQ_NAMED(BD96801_INT_PRSTB_WDT_ERR, "bd96801-prstb-wdt-err"), 62 DEFINE_RES_IRQ_NAMED(BD96801_INT_CHIP_IF_ERR, "bd96801-chip-if-err"), 63 DEFINE_RES_IRQ_NAMED(BD96801_INT_SHDN_ERR_STAT, "bd96801-int-shdn-err"), 64 65 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_PVIN_ERR_STAT, "bd96801-buck1-pvin-err"), 66 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OVP_ERR_STAT, "bd96801-buck1-ovp-err"), 67 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_UVP_ERR_STAT, "bd96801-buck1-uvp-err"), 68 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_SHDN_ERR_STAT, "bd96801-buck1-shdn-err"), 69 70 DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_PVIN_ERR_STAT, "bd96801-buck2-pvin-err"), 71 DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OVP_ERR_STAT, "bd96801-buck2-ovp-err"), 72 DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_UVP_ERR_STAT, "bd96801-buck2-uvp-err"), 73 DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_SHDN_ERR_STAT, "bd96801-buck2-shdn-err"), 74 75 DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_PVIN_ERR_STAT, "bd96801-buck3-pvin-err"), 76 DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OVP_ERR_STAT, "bd96801-buck3-ovp-err"), 77 DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_UVP_ERR_STAT, "bd96801-buck3-uvp-err"), 78 DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_SHDN_ERR_STAT, "bd96801-buck3-shdn-err"), 79 80 DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_PVIN_ERR_STAT, "bd96801-buck4-pvin-err"), 81 DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OVP_ERR_STAT, "bd96801-buck4-ovp-err"), 82 DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_UVP_ERR_STAT, "bd96801-buck4-uvp-err"), 83 DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_SHDN_ERR_STAT, "bd96801-buck4-shdn-err"), 84 85 DEFINE_RES_IRQ_NAMED(BD96801_LDO5_PVIN_ERR_STAT, "bd96801-ldo5-pvin-err"), 86 DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OVP_ERR_STAT, "bd96801-ldo5-ovp-err"), 87 DEFINE_RES_IRQ_NAMED(BD96801_LDO5_UVP_ERR_STAT, "bd96801-ldo5-uvp-err"), 88 DEFINE_RES_IRQ_NAMED(BD96801_LDO5_SHDN_ERR_STAT, "bd96801-ldo5-shdn-err"), 89 90 DEFINE_RES_IRQ_NAMED(BD96801_LDO6_PVIN_ERR_STAT, "bd96801-ldo6-pvin-err"), 91 DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OVP_ERR_STAT, "bd96801-ldo6-ovp-err"), 92 DEFINE_RES_IRQ_NAMED(BD96801_LDO6_UVP_ERR_STAT, "bd96801-ldo6-uvp-err"), 93 DEFINE_RES_IRQ_NAMED(BD96801_LDO6_SHDN_ERR_STAT, "bd96801-ldo6-shdn-err"), 94 95 DEFINE_RES_IRQ_NAMED(BD96801_LDO7_PVIN_ERR_STAT, "bd96801-ldo7-pvin-err"), 96 DEFINE_RES_IRQ_NAMED(BD96801_LDO7_OVP_ERR_STAT, "bd96801-ldo7-ovp-err"), 97 DEFINE_RES_IRQ_NAMED(BD96801_LDO7_UVP_ERR_STAT, "bd96801-ldo7-uvp-err"), 98 DEFINE_RES_IRQ_NAMED(BD96801_LDO7_SHDN_ERR_STAT, "bd96801-ldo7-shdn-err"), 99 }; 100 101 static const struct resource regulator_intb_irqs[] = { 102 DEFINE_RES_IRQ_NAMED(BD96801_TW_STAT, "bd96801-core-thermal"), 103 104 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPH_STAT, "bd96801-buck1-overcurr-h"), 105 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPL_STAT, "bd96801-buck1-overcurr-l"), 106 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OCPN_STAT, "bd96801-buck1-overcurr-n"), 107 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_OVD_STAT, "bd96801-buck1-overvolt"), 108 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_UVD_STAT, "bd96801-buck1-undervolt"), 109 DEFINE_RES_IRQ_NAMED(BD96801_BUCK1_TW_CH_STAT, "bd96801-buck1-thermal"), 110 111 DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPH_STAT, "bd96801-buck2-overcurr-h"), 112 DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPL_STAT, "bd96801-buck2-overcurr-l"), 113 DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OCPN_STAT, "bd96801-buck2-overcurr-n"), 114 DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_OVD_STAT, "bd96801-buck2-overvolt"), 115 DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_UVD_STAT, "bd96801-buck2-undervolt"), 116 DEFINE_RES_IRQ_NAMED(BD96801_BUCK2_TW_CH_STAT, "bd96801-buck2-thermal"), 117 118 DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPH_STAT, "bd96801-buck3-overcurr-h"), 119 DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPL_STAT, "bd96801-buck3-overcurr-l"), 120 DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OCPN_STAT, "bd96801-buck3-overcurr-n"), 121 DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_OVD_STAT, "bd96801-buck3-overvolt"), 122 DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_UVD_STAT, "bd96801-buck3-undervolt"), 123 DEFINE_RES_IRQ_NAMED(BD96801_BUCK3_TW_CH_STAT, "bd96801-buck3-thermal"), 124 125 DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPH_STAT, "bd96801-buck4-overcurr-h"), 126 DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPL_STAT, "bd96801-buck4-overcurr-l"), 127 DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OCPN_STAT, "bd96801-buck4-overcurr-n"), 128 DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_OVD_STAT, "bd96801-buck4-overvolt"), 129 DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_UVD_STAT, "bd96801-buck4-undervolt"), 130 DEFINE_RES_IRQ_NAMED(BD96801_BUCK4_TW_CH_STAT, "bd96801-buck4-thermal"), 131 132 DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OCPH_STAT, "bd96801-ldo5-overcurr"), 133 DEFINE_RES_IRQ_NAMED(BD96801_LDO5_OVD_STAT, "bd96801-ldo5-overvolt"), 134 DEFINE_RES_IRQ_NAMED(BD96801_LDO5_UVD_STAT, "bd96801-ldo5-undervolt"), 135 136 DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OCPH_STAT, "bd96801-ldo6-overcurr"), 137 DEFINE_RES_IRQ_NAMED(BD96801_LDO6_OVD_STAT, "bd96801-ldo6-overvolt"), 138 DEFINE_RES_IRQ_NAMED(BD96801_LDO6_UVD_STAT, "bd96801-ldo6-undervolt"), 139 140 DEFINE_RES_IRQ_NAMED(BD96801_LDO7_OCPH_STAT, "bd96801-ldo7-overcurr"), 141 DEFINE_RES_IRQ_NAMED(BD96801_LDO7_OVD_STAT, "bd96801-ldo7-overvolt"), 142 DEFINE_RES_IRQ_NAMED(BD96801_LDO7_UVD_STAT, "bd96801-ldo7-undervolt"), 143 }; 144 145 enum { 146 WDG_CELL = 0, 147 REGULATOR_CELL, 148 }; 149 150 static struct mfd_cell bd96801_cells[] = { 151 [WDG_CELL] = { .name = "bd96801-wdt", }, 152 [REGULATOR_CELL] = { .name = "bd96801-regulator", }, 153 }; 154 155 static const struct regmap_range bd96801_volatile_ranges[] = { 156 /* Status registers */ 157 regmap_reg_range(BD96801_REG_WD_FEED, BD96801_REG_WD_FAILCOUNT), 158 regmap_reg_range(BD96801_REG_WD_ASK, BD96801_REG_WD_ASK), 159 regmap_reg_range(BD96801_REG_WD_STATUS, BD96801_REG_WD_STATUS), 160 regmap_reg_range(BD96801_REG_PMIC_STATE, BD96801_REG_INT_LDO7_INTB), 161 /* Registers which do not update value unless PMIC is in STBY */ 162 regmap_reg_range(BD96801_REG_SSCG_CTRL, BD96801_REG_SHD_INTB), 163 regmap_reg_range(BD96801_REG_BUCK_OVP, BD96801_REG_BOOT_OVERTIME), 164 /* 165 * LDO control registers have single bit (LDO MODE) which does not 166 * change when we write it unless PMIC is in STBY. It's safer to not 167 * cache it. 168 */ 169 regmap_reg_range(BD96801_LDO5_VOL_LVL_REG, BD96801_LDO7_VOL_LVL_REG), 170 }; 171 172 static const struct regmap_access_table volatile_regs = { 173 .yes_ranges = bd96801_volatile_ranges, 174 .n_yes_ranges = ARRAY_SIZE(bd96801_volatile_ranges), 175 }; 176 177 /* 178 * For ERRB we need main register bit mapping as bit(0) indicates active IRQ 179 * in one of the first 3 sub IRQ registers, For INTB we can use default 1 to 1 180 * mapping. 181 */ 182 static unsigned int bit0_offsets[] = {0, 1, 2}; /* System stat, 3 registers */ 183 static unsigned int bit1_offsets[] = {3}; /* Buck 1 stat */ 184 static unsigned int bit2_offsets[] = {4}; /* Buck 2 stat */ 185 static unsigned int bit3_offsets[] = {5}; /* Buck 3 stat */ 186 static unsigned int bit4_offsets[] = {6}; /* Buck 4 stat */ 187 static unsigned int bit5_offsets[] = {7}; /* LDO 5 stat */ 188 static unsigned int bit6_offsets[] = {8}; /* LDO 6 stat */ 189 static unsigned int bit7_offsets[] = {9}; /* LDO 7 stat */ 190 191 static const struct regmap_irq_sub_irq_map errb_sub_irq_offsets[] = { 192 REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets), 193 REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets), 194 REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets), 195 REGMAP_IRQ_MAIN_REG_OFFSET(bit3_offsets), 196 REGMAP_IRQ_MAIN_REG_OFFSET(bit4_offsets), 197 REGMAP_IRQ_MAIN_REG_OFFSET(bit5_offsets), 198 REGMAP_IRQ_MAIN_REG_OFFSET(bit6_offsets), 199 REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets), 200 }; 201 202 static const struct regmap_irq bd96801_errb_irqs[] = { 203 /* Reg 0x52 Fatal ERRB1 */ 204 REGMAP_IRQ_REG(BD96801_OTP_ERR_STAT, 0, BD96801_OTP_ERR_MASK), 205 REGMAP_IRQ_REG(BD96801_DBIST_ERR_STAT, 0, BD96801_DBIST_ERR_MASK), 206 REGMAP_IRQ_REG(BD96801_EEP_ERR_STAT, 0, BD96801_EEP_ERR_MASK), 207 REGMAP_IRQ_REG(BD96801_ABIST_ERR_STAT, 0, BD96801_ABIST_ERR_MASK), 208 REGMAP_IRQ_REG(BD96801_PRSTB_ERR_STAT, 0, BD96801_PRSTB_ERR_MASK), 209 REGMAP_IRQ_REG(BD96801_DRMOS1_ERR_STAT, 0, BD96801_DRMOS1_ERR_MASK), 210 REGMAP_IRQ_REG(BD96801_DRMOS2_ERR_STAT, 0, BD96801_DRMOS2_ERR_MASK), 211 REGMAP_IRQ_REG(BD96801_SLAVE_ERR_STAT, 0, BD96801_SLAVE_ERR_MASK), 212 /* 0x53 Fatal ERRB2 */ 213 REGMAP_IRQ_REG(BD96801_VREF_ERR_STAT, 1, BD96801_VREF_ERR_MASK), 214 REGMAP_IRQ_REG(BD96801_TSD_ERR_STAT, 1, BD96801_TSD_ERR_MASK), 215 REGMAP_IRQ_REG(BD96801_UVLO_ERR_STAT, 1, BD96801_UVLO_ERR_MASK), 216 REGMAP_IRQ_REG(BD96801_OVLO_ERR_STAT, 1, BD96801_OVLO_ERR_MASK), 217 REGMAP_IRQ_REG(BD96801_OSC_ERR_STAT, 1, BD96801_OSC_ERR_MASK), 218 REGMAP_IRQ_REG(BD96801_PON_ERR_STAT, 1, BD96801_PON_ERR_MASK), 219 REGMAP_IRQ_REG(BD96801_POFF_ERR_STAT, 1, BD96801_POFF_ERR_MASK), 220 REGMAP_IRQ_REG(BD96801_CMD_SHDN_ERR_STAT, 1, BD96801_CMD_SHDN_ERR_MASK), 221 /* 0x54 Fatal INTB shadowed to ERRB */ 222 REGMAP_IRQ_REG(BD96801_INT_PRSTB_WDT_ERR, 2, BD96801_INT_PRSTB_WDT_ERR_MASK), 223 REGMAP_IRQ_REG(BD96801_INT_CHIP_IF_ERR, 2, BD96801_INT_CHIP_IF_ERR_MASK), 224 REGMAP_IRQ_REG(BD96801_INT_SHDN_ERR_STAT, 2, BD96801_INT_SHDN_ERR_MASK), 225 /* Reg 0x55 BUCK1 ERR IRQs */ 226 REGMAP_IRQ_REG(BD96801_BUCK1_PVIN_ERR_STAT, 3, BD96801_OUT_PVIN_ERR_MASK), 227 REGMAP_IRQ_REG(BD96801_BUCK1_OVP_ERR_STAT, 3, BD96801_OUT_OVP_ERR_MASK), 228 REGMAP_IRQ_REG(BD96801_BUCK1_UVP_ERR_STAT, 3, BD96801_OUT_UVP_ERR_MASK), 229 REGMAP_IRQ_REG(BD96801_BUCK1_SHDN_ERR_STAT, 3, BD96801_OUT_SHDN_ERR_MASK), 230 /* Reg 0x56 BUCK2 ERR IRQs */ 231 REGMAP_IRQ_REG(BD96801_BUCK2_PVIN_ERR_STAT, 4, BD96801_OUT_PVIN_ERR_MASK), 232 REGMAP_IRQ_REG(BD96801_BUCK2_OVP_ERR_STAT, 4, BD96801_OUT_OVP_ERR_MASK), 233 REGMAP_IRQ_REG(BD96801_BUCK2_UVP_ERR_STAT, 4, BD96801_OUT_UVP_ERR_MASK), 234 REGMAP_IRQ_REG(BD96801_BUCK2_SHDN_ERR_STAT, 4, BD96801_OUT_SHDN_ERR_MASK), 235 /* Reg 0x57 BUCK3 ERR IRQs */ 236 REGMAP_IRQ_REG(BD96801_BUCK3_PVIN_ERR_STAT, 5, BD96801_OUT_PVIN_ERR_MASK), 237 REGMAP_IRQ_REG(BD96801_BUCK3_OVP_ERR_STAT, 5, BD96801_OUT_OVP_ERR_MASK), 238 REGMAP_IRQ_REG(BD96801_BUCK3_UVP_ERR_STAT, 5, BD96801_OUT_UVP_ERR_MASK), 239 REGMAP_IRQ_REG(BD96801_BUCK3_SHDN_ERR_STAT, 5, BD96801_OUT_SHDN_ERR_MASK), 240 /* Reg 0x58 BUCK4 ERR IRQs */ 241 REGMAP_IRQ_REG(BD96801_BUCK4_PVIN_ERR_STAT, 6, BD96801_OUT_PVIN_ERR_MASK), 242 REGMAP_IRQ_REG(BD96801_BUCK4_OVP_ERR_STAT, 6, BD96801_OUT_OVP_ERR_MASK), 243 REGMAP_IRQ_REG(BD96801_BUCK4_UVP_ERR_STAT, 6, BD96801_OUT_UVP_ERR_MASK), 244 REGMAP_IRQ_REG(BD96801_BUCK4_SHDN_ERR_STAT, 6, BD96801_OUT_SHDN_ERR_MASK), 245 /* Reg 0x59 LDO5 ERR IRQs */ 246 REGMAP_IRQ_REG(BD96801_LDO5_PVIN_ERR_STAT, 7, BD96801_OUT_PVIN_ERR_MASK), 247 REGMAP_IRQ_REG(BD96801_LDO5_OVP_ERR_STAT, 7, BD96801_OUT_OVP_ERR_MASK), 248 REGMAP_IRQ_REG(BD96801_LDO5_UVP_ERR_STAT, 7, BD96801_OUT_UVP_ERR_MASK), 249 REGMAP_IRQ_REG(BD96801_LDO5_SHDN_ERR_STAT, 7, BD96801_OUT_SHDN_ERR_MASK), 250 /* Reg 0x5a LDO6 ERR IRQs */ 251 REGMAP_IRQ_REG(BD96801_LDO6_PVIN_ERR_STAT, 8, BD96801_OUT_PVIN_ERR_MASK), 252 REGMAP_IRQ_REG(BD96801_LDO6_OVP_ERR_STAT, 8, BD96801_OUT_OVP_ERR_MASK), 253 REGMAP_IRQ_REG(BD96801_LDO6_UVP_ERR_STAT, 8, BD96801_OUT_UVP_ERR_MASK), 254 REGMAP_IRQ_REG(BD96801_LDO6_SHDN_ERR_STAT, 8, BD96801_OUT_SHDN_ERR_MASK), 255 /* Reg 0x5b LDO7 ERR IRQs */ 256 REGMAP_IRQ_REG(BD96801_LDO7_PVIN_ERR_STAT, 9, BD96801_OUT_PVIN_ERR_MASK), 257 REGMAP_IRQ_REG(BD96801_LDO7_OVP_ERR_STAT, 9, BD96801_OUT_OVP_ERR_MASK), 258 REGMAP_IRQ_REG(BD96801_LDO7_UVP_ERR_STAT, 9, BD96801_OUT_UVP_ERR_MASK), 259 REGMAP_IRQ_REG(BD96801_LDO7_SHDN_ERR_STAT, 9, BD96801_OUT_SHDN_ERR_MASK), 260 }; 261 262 static const struct regmap_irq bd96801_intb_irqs[] = { 263 /* STATUS SYSTEM INTB */ 264 REGMAP_IRQ_REG(BD96801_TW_STAT, 0, BD96801_TW_STAT_MASK), 265 REGMAP_IRQ_REG(BD96801_WDT_ERR_STAT, 0, BD96801_WDT_ERR_STAT_MASK), 266 REGMAP_IRQ_REG(BD96801_I2C_ERR_STAT, 0, BD96801_I2C_ERR_STAT_MASK), 267 REGMAP_IRQ_REG(BD96801_CHIP_IF_ERR_STAT, 0, BD96801_CHIP_IF_ERR_STAT_MASK), 268 /* STATUS BUCK1 INTB */ 269 REGMAP_IRQ_REG(BD96801_BUCK1_OCPH_STAT, 1, BD96801_BUCK_OCPH_STAT_MASK), 270 REGMAP_IRQ_REG(BD96801_BUCK1_OCPL_STAT, 1, BD96801_BUCK_OCPL_STAT_MASK), 271 REGMAP_IRQ_REG(BD96801_BUCK1_OCPN_STAT, 1, BD96801_BUCK_OCPN_STAT_MASK), 272 REGMAP_IRQ_REG(BD96801_BUCK1_OVD_STAT, 1, BD96801_BUCK_OVD_STAT_MASK), 273 REGMAP_IRQ_REG(BD96801_BUCK1_UVD_STAT, 1, BD96801_BUCK_UVD_STAT_MASK), 274 REGMAP_IRQ_REG(BD96801_BUCK1_TW_CH_STAT, 1, BD96801_BUCK_TW_CH_STAT_MASK), 275 /* BUCK 2 INTB */ 276 REGMAP_IRQ_REG(BD96801_BUCK2_OCPH_STAT, 2, BD96801_BUCK_OCPH_STAT_MASK), 277 REGMAP_IRQ_REG(BD96801_BUCK2_OCPL_STAT, 2, BD96801_BUCK_OCPL_STAT_MASK), 278 REGMAP_IRQ_REG(BD96801_BUCK2_OCPN_STAT, 2, BD96801_BUCK_OCPN_STAT_MASK), 279 REGMAP_IRQ_REG(BD96801_BUCK2_OVD_STAT, 2, BD96801_BUCK_OVD_STAT_MASK), 280 REGMAP_IRQ_REG(BD96801_BUCK2_UVD_STAT, 2, BD96801_BUCK_UVD_STAT_MASK), 281 REGMAP_IRQ_REG(BD96801_BUCK2_TW_CH_STAT, 2, BD96801_BUCK_TW_CH_STAT_MASK), 282 /* BUCK 3 INTB */ 283 REGMAP_IRQ_REG(BD96801_BUCK3_OCPH_STAT, 3, BD96801_BUCK_OCPH_STAT_MASK), 284 REGMAP_IRQ_REG(BD96801_BUCK3_OCPL_STAT, 3, BD96801_BUCK_OCPL_STAT_MASK), 285 REGMAP_IRQ_REG(BD96801_BUCK3_OCPN_STAT, 3, BD96801_BUCK_OCPN_STAT_MASK), 286 REGMAP_IRQ_REG(BD96801_BUCK3_OVD_STAT, 3, BD96801_BUCK_OVD_STAT_MASK), 287 REGMAP_IRQ_REG(BD96801_BUCK3_UVD_STAT, 3, BD96801_BUCK_UVD_STAT_MASK), 288 REGMAP_IRQ_REG(BD96801_BUCK3_TW_CH_STAT, 3, BD96801_BUCK_TW_CH_STAT_MASK), 289 /* BUCK 4 INTB */ 290 REGMAP_IRQ_REG(BD96801_BUCK4_OCPH_STAT, 4, BD96801_BUCK_OCPH_STAT_MASK), 291 REGMAP_IRQ_REG(BD96801_BUCK4_OCPL_STAT, 4, BD96801_BUCK_OCPL_STAT_MASK), 292 REGMAP_IRQ_REG(BD96801_BUCK4_OCPN_STAT, 4, BD96801_BUCK_OCPN_STAT_MASK), 293 REGMAP_IRQ_REG(BD96801_BUCK4_OVD_STAT, 4, BD96801_BUCK_OVD_STAT_MASK), 294 REGMAP_IRQ_REG(BD96801_BUCK4_UVD_STAT, 4, BD96801_BUCK_UVD_STAT_MASK), 295 REGMAP_IRQ_REG(BD96801_BUCK4_TW_CH_STAT, 4, BD96801_BUCK_TW_CH_STAT_MASK), 296 /* LDO5 INTB */ 297 REGMAP_IRQ_REG(BD96801_LDO5_OCPH_STAT, 5, BD96801_LDO_OCPH_STAT_MASK), 298 REGMAP_IRQ_REG(BD96801_LDO5_OVD_STAT, 5, BD96801_LDO_OVD_STAT_MASK), 299 REGMAP_IRQ_REG(BD96801_LDO5_UVD_STAT, 5, BD96801_LDO_UVD_STAT_MASK), 300 /* LDO6 INTB */ 301 REGMAP_IRQ_REG(BD96801_LDO6_OCPH_STAT, 6, BD96801_LDO_OCPH_STAT_MASK), 302 REGMAP_IRQ_REG(BD96801_LDO6_OVD_STAT, 6, BD96801_LDO_OVD_STAT_MASK), 303 REGMAP_IRQ_REG(BD96801_LDO6_UVD_STAT, 6, BD96801_LDO_UVD_STAT_MASK), 304 /* LDO7 INTB */ 305 REGMAP_IRQ_REG(BD96801_LDO7_OCPH_STAT, 7, BD96801_LDO_OCPH_STAT_MASK), 306 REGMAP_IRQ_REG(BD96801_LDO7_OVD_STAT, 7, BD96801_LDO_OVD_STAT_MASK), 307 REGMAP_IRQ_REG(BD96801_LDO7_UVD_STAT, 7, BD96801_LDO_UVD_STAT_MASK), 308 }; 309 310 static const struct regmap_irq_chip bd96801_irq_chip_errb = { 311 .name = "bd96801-irq-errb", 312 .domain_suffix = "errb", 313 .main_status = BD96801_REG_INT_MAIN, 314 .num_main_regs = 1, 315 .irqs = &bd96801_errb_irqs[0], 316 .num_irqs = ARRAY_SIZE(bd96801_errb_irqs), 317 .status_base = BD96801_REG_INT_SYS_ERRB1, 318 .mask_base = BD96801_REG_MASK_SYS_ERRB, 319 .ack_base = BD96801_REG_INT_SYS_ERRB1, 320 .init_ack_masked = true, 321 .num_regs = 10, 322 .irq_reg_stride = 1, 323 .sub_reg_offsets = &errb_sub_irq_offsets[0], 324 }; 325 326 static const struct regmap_irq_chip bd96801_irq_chip_intb = { 327 .name = "bd96801-irq-intb", 328 .domain_suffix = "intb", 329 .main_status = BD96801_REG_INT_MAIN, 330 .num_main_regs = 1, 331 .irqs = &bd96801_intb_irqs[0], 332 .num_irqs = ARRAY_SIZE(bd96801_intb_irqs), 333 .status_base = BD96801_REG_INT_SYS_INTB, 334 .mask_base = BD96801_REG_MASK_SYS_INTB, 335 .ack_base = BD96801_REG_INT_SYS_INTB, 336 .init_ack_masked = true, 337 .num_regs = 8, 338 .irq_reg_stride = 1, 339 }; 340 341 static const struct regmap_config bd96801_regmap_config = { 342 .reg_bits = 8, 343 .val_bits = 8, 344 .volatile_table = &volatile_regs, 345 .cache_type = REGCACHE_MAPLE, 346 }; 347 348 static int bd96801_i2c_probe(struct i2c_client *i2c) 349 { 350 struct regmap_irq_chip_data *intb_irq_data, *errb_irq_data; 351 struct irq_domain *intb_domain, *errb_domain; 352 const struct fwnode_handle *fwnode; 353 struct resource *regulator_res; 354 struct resource wdg_irq; 355 struct regmap *regmap; 356 int intb_irq, errb_irq, num_intb, num_errb = 0; 357 int num_regu_irqs, wdg_irq_no; 358 int i, ret; 359 360 fwnode = dev_fwnode(&i2c->dev); 361 if (!fwnode) 362 return dev_err_probe(&i2c->dev, -EINVAL, "Failed to find fwnode\n"); 363 364 intb_irq = fwnode_irq_get_byname(fwnode, "intb"); 365 if (intb_irq < 0) 366 return dev_err_probe(&i2c->dev, intb_irq, "INTB IRQ not configured\n"); 367 368 num_intb = ARRAY_SIZE(regulator_intb_irqs); 369 370 /* ERRB may be omitted if processor is powered by the PMIC */ 371 errb_irq = fwnode_irq_get_byname(fwnode, "errb"); 372 if (errb_irq < 0) 373 errb_irq = 0; 374 375 if (errb_irq) 376 num_errb = ARRAY_SIZE(regulator_errb_irqs); 377 378 num_regu_irqs = num_intb + num_errb; 379 380 regulator_res = devm_kcalloc(&i2c->dev, num_regu_irqs, 381 sizeof(*regulator_res), GFP_KERNEL); 382 if (!regulator_res) 383 return -ENOMEM; 384 385 regmap = devm_regmap_init_i2c(i2c, &bd96801_regmap_config); 386 if (IS_ERR(regmap)) 387 return dev_err_probe(&i2c->dev, PTR_ERR(regmap), 388 "Regmap initialization failed\n"); 389 390 ret = regmap_write(regmap, BD96801_LOCK_REG, BD96801_UNLOCK); 391 if (ret) 392 return dev_err_probe(&i2c->dev, ret, "Failed to unlock PMIC\n"); 393 394 ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, intb_irq, 395 IRQF_ONESHOT, 0, &bd96801_irq_chip_intb, 396 &intb_irq_data); 397 if (ret) 398 return dev_err_probe(&i2c->dev, ret, "Failed to add INTB IRQ chip\n"); 399 400 intb_domain = regmap_irq_get_domain(intb_irq_data); 401 402 /* 403 * MFD core code is built to handle only one IRQ domain. BD96801 404 * has two domains so we do IRQ mapping here and provide the 405 * already mapped IRQ numbers to sub-devices. 406 */ 407 for (i = 0; i < num_intb; i++) { 408 struct resource *res = ®ulator_res[i]; 409 410 *res = regulator_intb_irqs[i]; 411 res->start = res->end = irq_create_mapping(intb_domain, 412 res->start); 413 } 414 415 wdg_irq_no = irq_create_mapping(intb_domain, BD96801_WDT_ERR_STAT); 416 wdg_irq = DEFINE_RES_IRQ_NAMED(wdg_irq_no, "bd96801-wdg"); 417 bd96801_cells[WDG_CELL].resources = &wdg_irq; 418 bd96801_cells[WDG_CELL].num_resources = 1; 419 420 if (!num_errb) 421 goto skip_errb; 422 423 ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, errb_irq, IRQF_ONESHOT, 424 0, &bd96801_irq_chip_errb, &errb_irq_data); 425 if (ret) 426 return dev_err_probe(&i2c->dev, ret, 427 "Failed to add ERRB IRQ chip\n"); 428 429 errb_domain = regmap_irq_get_domain(errb_irq_data); 430 431 for (i = 0; i < num_errb; i++) { 432 struct resource *res = ®ulator_res[num_intb + i]; 433 434 *res = regulator_errb_irqs[i]; 435 res->start = res->end = irq_create_mapping(errb_domain, res->start); 436 } 437 438 skip_errb: 439 bd96801_cells[REGULATOR_CELL].resources = regulator_res; 440 bd96801_cells[REGULATOR_CELL].num_resources = num_regu_irqs; 441 442 ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, bd96801_cells, 443 ARRAY_SIZE(bd96801_cells), NULL, 0, NULL); 444 if (ret) 445 dev_err_probe(&i2c->dev, ret, "Failed to create subdevices\n"); 446 447 return ret; 448 } 449 450 static const struct of_device_id bd96801_of_match[] = { 451 { .compatible = "rohm,bd96801", }, 452 { } 453 }; 454 MODULE_DEVICE_TABLE(of, bd96801_of_match); 455 456 static struct i2c_driver bd96801_i2c_driver = { 457 .driver = { 458 .name = "rohm-bd96801", 459 .of_match_table = bd96801_of_match, 460 }, 461 .probe = bd96801_i2c_probe, 462 }; 463 464 static int __init bd96801_i2c_init(void) 465 { 466 return i2c_add_driver(&bd96801_i2c_driver); 467 } 468 469 /* Initialise early so consumer devices can complete system boot */ 470 subsys_initcall(bd96801_i2c_init); 471 472 static void __exit bd96801_i2c_exit(void) 473 { 474 i2c_del_driver(&bd96801_i2c_driver); 475 } 476 module_exit(bd96801_i2c_exit); 477 478 MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>"); 479 MODULE_DESCRIPTION("ROHM BD96801 Power Management IC driver"); 480 MODULE_LICENSE("GPL"); 481