1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2019 ROHM Semiconductors 4 * 5 * ROHM BD718[15/28/79] and BD72720 PMIC driver 6 */ 7 8 #include <linux/gpio_keys.h> 9 #include <linux/i2c.h> 10 #include <linux/input.h> 11 #include <linux/interrupt.h> 12 #include <linux/ioport.h> 13 #include <linux/irq.h> 14 #include <linux/mfd/core.h> 15 #include <linux/mfd/rohm-bd71815.h> 16 #include <linux/mfd/rohm-bd71828.h> 17 #include <linux/mfd/rohm-bd72720.h> 18 #include <linux/mfd/rohm-generic.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/regmap.h> 22 #include <linux/types.h> 23 24 #define BD72720_TYPED_IRQ_REG(_irq, _stat_offset, _mask, _type_offset) \ 25 [_irq] = { \ 26 .reg_offset = (_stat_offset), \ 27 .mask = (_mask), \ 28 { \ 29 .type_reg_offset = (_type_offset), \ 30 .type_reg_mask = BD72720_GPIO_IRQ_TYPE_MASK, \ 31 .type_rising_val = BD72720_GPIO_IRQ_TYPE_RISING, \ 32 .type_falling_val = BD72720_GPIO_IRQ_TYPE_FALLING, \ 33 .type_level_low_val = BD72720_GPIO_IRQ_TYPE_LOW, \ 34 .type_level_high_val = BD72720_GPIO_IRQ_TYPE_HIGH, \ 35 .types_supported = IRQ_TYPE_EDGE_BOTH | \ 36 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW, \ 37 }, \ 38 } 39 40 static struct gpio_keys_button button = { 41 .code = KEY_POWER, 42 .gpio = -1, 43 .type = EV_KEY, 44 }; 45 46 static const struct gpio_keys_platform_data bd71828_powerkey_data = { 47 .buttons = &button, 48 .nbuttons = 1, 49 .name = "bd71828-pwrkey", 50 }; 51 52 static const struct resource bd71815_rtc_irqs[] = { 53 DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC0, "bd70528-rtc-alm-0"), 54 DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC1, "bd70528-rtc-alm-1"), 55 DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC2, "bd70528-rtc-alm-2"), 56 }; 57 58 static const struct resource bd71828_rtc_irqs[] = { 59 DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC0, "bd70528-rtc-alm-0"), 60 DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC1, "bd70528-rtc-alm-1"), 61 DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC2, "bd70528-rtc-alm-2"), 62 }; 63 64 static const struct resource bd72720_rtc_irqs[] = { 65 DEFINE_RES_IRQ_NAMED(BD72720_INT_RTC0, "bd70528-rtc-alm-0"), 66 DEFINE_RES_IRQ_NAMED(BD72720_INT_RTC1, "bd70528-rtc-alm-1"), 67 DEFINE_RES_IRQ_NAMED(BD72720_INT_RTC2, "bd70528-rtc-alm-2"), 68 }; 69 70 static const struct resource bd71815_power_irqs[] = { 71 DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_RMV, "bd71815-dcin-rmv"), 72 DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_OUT, "bd71815-dcin-clps-out"), 73 DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_IN, "bd71815-dcin-clps-in"), 74 DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_RES, "bd71815-dcin-ovp-res"), 75 DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_DET, "bd71815-dcin-ovp-det"), 76 DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_MON_RES, "bd71815-dcin-mon-res"), 77 DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_MON_DET, "bd71815-dcin-mon-det"), 78 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_UV_RES, "bd71815-vsys-uv-res"), 79 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_UV_DET, "bd71815-vsys-uv-det"), 80 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_RES, "bd71815-vsys-low-res"), 81 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_DET, "bd71815-vsys-low-det"), 82 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_RES, "bd71815-vsys-mon-res"), 83 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_DET, "bd71815-vsys-mon-det"), 84 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TEMP, "bd71815-chg-wdg-temp"), 85 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TIME, "bd71815-chg-wdg"), 86 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RECHARGE_RES, "bd71815-rechg-res"), 87 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RECHARGE_DET, "bd71815-rechg-det"), 88 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RANGED_TEMP_TRANSITION, "bd71815-ranged-temp-transit"), 89 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_STATE_TRANSITION, "bd71815-chg-state-change"), 90 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_TEMP_NORMAL, "bd71815-bat-temp-normal"), 91 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_TEMP_ERANGE, "bd71815-bat-temp-erange"), 92 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_REMOVED, "bd71815-bat-rmv"), 93 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_DETECTED, "bd71815-bat-det"), 94 DEFINE_RES_IRQ_NAMED(BD71815_INT_THERM_REMOVED, "bd71815-therm-rmv"), 95 DEFINE_RES_IRQ_NAMED(BD71815_INT_THERM_DETECTED, "bd71815-therm-det"), 96 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_DEAD, "bd71815-bat-dead"), 97 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_SHORTC_RES, "bd71815-bat-short-res"), 98 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_SHORTC_DET, "bd71815-bat-short-det"), 99 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_LOW_VOLT_RES, "bd71815-bat-low-res"), 100 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_LOW_VOLT_DET, "bd71815-bat-low-det"), 101 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_VOLT_RES, "bd71815-bat-over-res"), 102 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_VOLT_DET, "bd71815-bat-over-det"), 103 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_MON_RES, "bd71815-bat-mon-res"), 104 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_MON_DET, "bd71815-bat-mon-det"), 105 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON1, "bd71815-bat-cc-mon1"), 106 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON2, "bd71815-bat-cc-mon2"), 107 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON3, "bd71815-bat-cc-mon3"), 108 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_1_RES, "bd71815-bat-oc1-res"), 109 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_1_DET, "bd71815-bat-oc1-det"), 110 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_2_RES, "bd71815-bat-oc2-res"), 111 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_2_DET, "bd71815-bat-oc2-det"), 112 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_RES, "bd71815-bat-oc3-res"), 113 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_DET, "bd71815-bat-oc3-det"), 114 DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_RES, "bd71815-temp-bat-low-res"), 115 DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_DET, "bd71815-temp-bat-low-det"), 116 DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_RES, "bd71815-temp-bat-hi-res"), 117 DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_DET, "bd71815-temp-bat-hi-det"), 118 }; 119 120 static const struct mfd_cell bd71815_mfd_cells[] = { 121 { .name = "bd71815-pmic", }, 122 { .name = "bd71815-clk", }, 123 { .name = "bd71815-gpo", }, 124 { 125 .name = "bd71815-power", 126 .num_resources = ARRAY_SIZE(bd71815_power_irqs), 127 .resources = &bd71815_power_irqs[0], 128 }, 129 { 130 .name = "bd71815-rtc", 131 .num_resources = ARRAY_SIZE(bd71815_rtc_irqs), 132 .resources = &bd71815_rtc_irqs[0], 133 }, 134 }; 135 136 static const struct resource bd71828_power_irqs[] = { 137 DEFINE_RES_IRQ_NAMED(BD71828_INT_CHG_TOPOFF_TO_DONE, 138 "bd71828-chg-done"), 139 DEFINE_RES_IRQ_NAMED(BD71828_INT_DCIN_DET, "bd71828-pwr-dcin-in"), 140 DEFINE_RES_IRQ_NAMED(BD71828_INT_DCIN_RMV, "bd71828-pwr-dcin-out"), 141 DEFINE_RES_IRQ_NAMED(BD71828_INT_BAT_LOW_VOLT_RES, 142 "bd71828-vbat-normal"), 143 DEFINE_RES_IRQ_NAMED(BD71828_INT_BAT_LOW_VOLT_DET, "bd71828-vbat-low"), 144 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_HI_DET, "bd71828-btemp-hi"), 145 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_HI_RES, "bd71828-btemp-cool"), 146 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_LOW_DET, "bd71828-btemp-lo"), 147 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_LOW_RES, 148 "bd71828-btemp-warm"), 149 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_VF_DET, 150 "bd71828-temp-hi"), 151 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_VF_RES, 152 "bd71828-temp-norm"), 153 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_125_DET, 154 "bd71828-temp-125-over"), 155 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_125_RES, 156 "bd71828-temp-125-under"), 157 }; 158 159 static struct mfd_cell bd71828_mfd_cells[] = { 160 { .name = "bd71828-pmic", }, 161 { .name = "bd71828-gpio", }, 162 { .name = "bd71828-led", .of_compatible = "rohm,bd71828-leds" }, 163 /* 164 * We use BD71837 driver to drive the clock block. Only differences to 165 * BD70528 clock gate are the register address and mask. 166 */ 167 { .name = "bd71828-clk", }, 168 { 169 .name = "bd71828-power", 170 .resources = bd71828_power_irqs, 171 .num_resources = ARRAY_SIZE(bd71828_power_irqs), 172 }, { 173 .name = "bd71828-rtc", 174 .resources = bd71828_rtc_irqs, 175 .num_resources = ARRAY_SIZE(bd71828_rtc_irqs), 176 }, { 177 .name = "gpio-keys", 178 .platform_data = &bd71828_powerkey_data, 179 .pdata_size = sizeof(bd71828_powerkey_data), 180 }, 181 }; 182 183 static const struct resource bd72720_power_irqs[] = { 184 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_RMV, "bd72720_int_vbus_rmv"), 185 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_DET, "bd72720_int_vbus_det"), 186 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_MON_RES, "bd72720_int_vbus_mon_res"), 187 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_MON_DET, "bd72720_int_vbus_mon_det"), 188 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_MON_RES, "bd72720_int_vsys_mon_res"), 189 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_MON_DET, "bd72720_int_vsys_mon_det"), 190 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_UV_RES, "bd72720_int_vsys_uv_res"), 191 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_UV_DET, "bd72720_int_vsys_uv_det"), 192 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_LO_RES, "bd72720_int_vsys_lo_res"), 193 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_LO_DET, "bd72720_int_vsys_lo_det"), 194 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_OV_RES, "bd72720_int_vsys_ov_res"), 195 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_OV_DET, "bd72720_int_vsys_ov_det"), 196 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_ILIM, "bd72720_int_bat_ilim"), 197 DEFINE_RES_IRQ_NAMED(BD72720_INT_CHG_DONE, "bd72720_int_chg_done"), 198 DEFINE_RES_IRQ_NAMED(BD72720_INT_EXTEMP_TOUT, "bd72720_int_extemp_tout"), 199 DEFINE_RES_IRQ_NAMED(BD72720_INT_CHG_WDT_EXP, "bd72720_int_chg_wdt_exp"), 200 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_MNT_OUT, "bd72720_int_bat_mnt_out"), 201 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_MNT_IN, "bd72720_int_bat_mnt_in"), 202 DEFINE_RES_IRQ_NAMED(BD72720_INT_CHG_TRNS, "bd72720_int_chg_trns"), 203 204 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_MON_RES, "bd72720_int_vbat_mon_res"), 205 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_MON_DET, "bd72720_int_vbat_mon_det"), 206 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_SHT_RES, "bd72720_int_vbat_sht_res"), 207 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_SHT_DET, "bd72720_int_vbat_sht_det"), 208 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_LO_RES, "bd72720_int_vbat_lo_res"), 209 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_LO_DET, "bd72720_int_vbat_lo_det"), 210 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_OV_RES, "bd72720_int_vbat_ov_res"), 211 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_OV_DET, "bd72720_int_vbat_ov_det"), 212 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_RMV, "bd72720_int_bat_rmv"), 213 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_DET, "bd72720_int_bat_det"), 214 DEFINE_RES_IRQ_NAMED(BD72720_INT_DBAT_DET, "bd72720_int_dbat_det"), 215 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_TEMP_TRNS, "bd72720_int_bat_temp_trns"), 216 DEFINE_RES_IRQ_NAMED(BD72720_INT_LOBTMP_RES, "bd72720_int_lobtmp_res"), 217 DEFINE_RES_IRQ_NAMED(BD72720_INT_LOBTMP_DET, "bd72720_int_lobtmp_det"), 218 DEFINE_RES_IRQ_NAMED(BD72720_INT_OVBTMP_RES, "bd72720_int_ovbtmp_res"), 219 DEFINE_RES_IRQ_NAMED(BD72720_INT_OVBTMP_DET, "bd72720_int_ovbtmp_det"), 220 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR1_RES, "bd72720_int_ocur1_res"), 221 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR1_DET, "bd72720_int_ocur1_det"), 222 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR2_RES, "bd72720_int_ocur2_res"), 223 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR2_DET, "bd72720_int_ocur2_det"), 224 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR3_RES, "bd72720_int_ocur3_res"), 225 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR3_DET, "bd72720_int_ocur3_det"), 226 DEFINE_RES_IRQ_NAMED(BD72720_INT_CC_MON1_DET, "bd72720_int_cc_mon1_det"), 227 DEFINE_RES_IRQ_NAMED(BD72720_INT_CC_MON2_DET, "bd72720_int_cc_mon2_det"), 228 DEFINE_RES_IRQ_NAMED(BD72720_INT_CC_MON3_DET, "bd72720_int_cc_mon3_det"), 229 }; 230 231 static const struct mfd_cell bd72720_mfd_cells[] = { 232 { .name = "bd72720-pmic", }, 233 { .name = "bd72720-gpio", }, 234 { .name = "bd72720-led", }, 235 { .name = "bd72720-clk", }, 236 { 237 .name = "bd72720-power", 238 .resources = bd72720_power_irqs, 239 .num_resources = ARRAY_SIZE(bd72720_power_irqs), 240 }, { 241 .name = "bd72720-rtc", 242 .resources = bd72720_rtc_irqs, 243 .num_resources = ARRAY_SIZE(bd72720_rtc_irqs), 244 }, { 245 .name = "gpio-keys", 246 .platform_data = &bd71828_powerkey_data, 247 .pdata_size = sizeof(bd71828_powerkey_data), 248 }, 249 }; 250 251 static const struct regmap_range bd71815_volatile_ranges[] = { 252 regmap_reg_range(BD71815_REG_SEC, BD71815_REG_YEAR), 253 regmap_reg_range(BD71815_REG_CONF, BD71815_REG_BAT_TEMP), 254 regmap_reg_range(BD71815_REG_VM_IBAT_U, BD71815_REG_CC_CTRL), 255 regmap_reg_range(BD71815_REG_CC_STAT, BD71815_REG_CC_CURCD_L), 256 regmap_reg_range(BD71815_REG_VM_BTMP_MON, BD71815_REG_VM_BTMP_MON), 257 regmap_reg_range(BD71815_REG_INT_STAT, BD71815_REG_INT_UPDATE), 258 regmap_reg_range(BD71815_REG_VM_VSYS_U, BD71815_REG_REX_CTRL_1), 259 regmap_reg_range(BD71815_REG_FULL_CCNTD_3, BD71815_REG_CCNTD_CHG_2), 260 }; 261 262 static const struct regmap_range bd71828_volatile_ranges[] = { 263 regmap_reg_range(BD71828_REG_PS_CTRL_1, BD71828_REG_PS_CTRL_1), 264 regmap_reg_range(BD71828_REG_PS_CTRL_3, BD71828_REG_PS_CTRL_3), 265 regmap_reg_range(BD71828_REG_RTC_SEC, BD71828_REG_RTC_YEAR), 266 /* 267 * For now make all charger registers volatile because many 268 * needs to be and because the charger block is not that 269 * performance critical. 270 */ 271 regmap_reg_range(BD71828_REG_CHG_STATE, BD71828_REG_CHG_FULL), 272 regmap_reg_range(BD71828_REG_INT_MAIN, BD71828_REG_IO_STAT), 273 }; 274 275 static const struct regmap_range bd72720_volatile_ranges_4b[] = { 276 regmap_reg_range(BD72720_REG_RESETSRC_1, BD72720_REG_RESETSRC_2), 277 regmap_reg_range(BD72720_REG_POWER_STATE, BD72720_REG_POWER_STATE), 278 /* The state indicator bit changes when new state is reached */ 279 regmap_reg_range(BD72720_REG_PS_CTRL_1, BD72720_REG_PS_CTRL_1), 280 regmap_reg_range(BD72720_REG_RCVNUM, BD72720_REG_RCVNUM), 281 regmap_reg_range(BD72720_REG_CONF, BD72720_REG_HALL_STAT), 282 regmap_reg_range(BD72720_REG_RTC_SEC, BD72720_REG_RTC_YEAR), 283 regmap_reg_range(BD72720_REG_INT_LVL1_STAT, BD72720_REG_INT_ETC2_SRC), 284 }; 285 286 static const struct regmap_range bd72720_precious_ranges_4b[] = { 287 regmap_reg_range(BD72720_REG_INT_LVL1_STAT, BD72720_REG_INT_ETC2_STAT), 288 }; 289 290 /* 291 * The BD72720 is an odd beast in that it contains two separate sets of 292 * registers, both starting from address 0x0. The twist is that these "pages" 293 * are behind different I2C slave addresses. Most of the registers are behind 294 * a slave address 0x4b, which will be used as the "main" address for this 295 * device. 296 * 297 * Most of the charger related registers are located behind slave address 0x4c. 298 * It is tempting to push the dealing with the charger registers and the extra 299 * 0x4c device in power-supply driver - but perhaps it's better for the sake of 300 * the cleaner re-use to deal with setting up all of the regmaps here. 301 * Furthermore, the LED stuff may need access to both of these devices. 302 * 303 * Instead of providing one of the regmaps to sub-devices in MFD platform data, 304 * we create one more 'wrapper regmap' with custom read/write operations. These 305 * custom accessors will select which of the 'real' regmaps to use, based on 306 * the register address. 307 * 308 * The register addresses are 8-bit, so we add offset 0x100 to the addresses 309 * behind the secondary slave 0x4c. The 'wrapper' regmap can then detect the 310 * correct slave address based on the register address and call regmap_write() 311 * and regmap_read() using correct 'real' regmap. This way the registers of 312 * both of the slaves can be accessed using one 'wrapper' regmap. 313 * 314 * NOTE: The added offsets mean that the defined addresses for slave 0x4c must 315 * be used through the 'wrapper' regmap because the offset must be stripped 316 * from the register addresses. The 0x4b can be accessed both indirectly using 317 * the 'wrapper' regmap, and directly using the 'real' regmap. 318 */ 319 #define BD72720_SECONDARY_I2C_SLAVE 0x4c 320 #define BD72720_SECONDARY_I2C_REG_OFFSET 0x100 321 322 struct bd72720_regmaps { 323 struct regmap *map1_4b; 324 struct regmap *map2_4c; 325 }; 326 327 /* Translate the slave 0x4c wrapper register address to a real one */ 328 #define BD72720_REG_UNWRAP(reg) ((reg) - BD72720_SECONDARY_I2C_REG_OFFSET) 329 330 /* Ranges given to 'real' 0x4c regmap must use unwrapped addresses. */ 331 #define BD72720_UNWRAP_REG_RANGE(startreg, endreg) \ 332 regmap_reg_range(BD72720_REG_UNWRAP(startreg), BD72720_REG_UNWRAP(endreg)) 333 334 static const struct regmap_range bd72720_volatile_ranges_4c[] = { 335 /* Status information */ 336 BD72720_UNWRAP_REG_RANGE(BD72720_REG_CHG_STATE, BD72720_REG_CHG_EN), 337 /* 338 * Under certain circumstances, write to some bits may be 339 * ignored 340 */ 341 BD72720_UNWRAP_REG_RANGE(BD72720_REG_CHG_CTRL, BD72720_REG_CHG_CTRL), 342 /* 343 * TODO: Ensure this is used to advertise state, not (only?) to 344 * control it. 345 */ 346 BD72720_UNWRAP_REG_RANGE(BD72720_REG_VSYS_STATE_STAT, BD72720_REG_VSYS_STATE_STAT), 347 /* Measured data */ 348 BD72720_UNWRAP_REG_RANGE(BD72720_REG_VM_VBAT_U, BD72720_REG_VM_VF_L), 349 /* Self clearing bits */ 350 BD72720_UNWRAP_REG_RANGE(BD72720_REG_VM_VSYS_SA_MINMAX_CTRL, 351 BD72720_REG_VM_VSYS_SA_MINMAX_CTRL), 352 /* Counters, self clearing bits */ 353 BD72720_UNWRAP_REG_RANGE(BD72720_REG_CC_CURCD_U, BD72720_REG_CC_CTRL), 354 /* Self clearing bits */ 355 BD72720_UNWRAP_REG_RANGE(BD72720_REG_CC_CCNTD_CTRL, BD72720_REG_CC_CCNTD_CTRL), 356 /* Self clearing bits */ 357 BD72720_UNWRAP_REG_RANGE(BD72720_REG_IMPCHK_CTRL, BD72720_REG_IMPCHK_CTRL), 358 }; 359 360 static const struct regmap_access_table bd71815_volatile_regs = { 361 .yes_ranges = &bd71815_volatile_ranges[0], 362 .n_yes_ranges = ARRAY_SIZE(bd71815_volatile_ranges), 363 }; 364 365 static const struct regmap_access_table bd71828_volatile_regs = { 366 .yes_ranges = &bd71828_volatile_ranges[0], 367 .n_yes_ranges = ARRAY_SIZE(bd71828_volatile_ranges), 368 }; 369 370 static const struct regmap_access_table bd72720_volatile_regs_4b = { 371 .yes_ranges = &bd72720_volatile_ranges_4b[0], 372 .n_yes_ranges = ARRAY_SIZE(bd72720_volatile_ranges_4b), 373 }; 374 375 static const struct regmap_access_table bd72720_precious_regs_4b = { 376 .yes_ranges = &bd72720_precious_ranges_4b[0], 377 .n_yes_ranges = ARRAY_SIZE(bd72720_precious_ranges_4b), 378 }; 379 380 static const struct regmap_access_table bd72720_volatile_regs_4c = { 381 .yes_ranges = &bd72720_volatile_ranges_4c[0], 382 .n_yes_ranges = ARRAY_SIZE(bd72720_volatile_ranges_4c), 383 }; 384 385 static const struct regmap_config bd71815_regmap = { 386 .reg_bits = 8, 387 .val_bits = 8, 388 .volatile_table = &bd71815_volatile_regs, 389 .max_register = BD71815_MAX_REGISTER - 1, 390 .cache_type = REGCACHE_MAPLE, 391 }; 392 393 static const struct regmap_config bd71828_regmap = { 394 .reg_bits = 8, 395 .val_bits = 8, 396 .volatile_table = &bd71828_volatile_regs, 397 .max_register = BD71828_MAX_REGISTER, 398 .cache_type = REGCACHE_MAPLE, 399 }; 400 401 static int regmap_write_wrapper(void *context, unsigned int reg, unsigned int val) 402 { 403 struct bd72720_regmaps *maps = context; 404 405 if (reg < BD72720_SECONDARY_I2C_REG_OFFSET) 406 return regmap_write(maps->map1_4b, reg, val); 407 408 reg = BD72720_REG_UNWRAP(reg); 409 410 return regmap_write(maps->map2_4c, reg, val); 411 } 412 413 static int regmap_read_wrapper(void *context, unsigned int reg, unsigned int *val) 414 { 415 struct bd72720_regmaps *maps = context; 416 417 if (reg < BD72720_SECONDARY_I2C_REG_OFFSET) 418 return regmap_read(maps->map1_4b, reg, val); 419 420 reg = BD72720_REG_UNWRAP(reg); 421 422 return regmap_read(maps->map2_4c, reg, val); 423 } 424 425 static const struct regmap_config bd72720_wrapper_map_config = { 426 .name = "wrap-map", 427 .reg_bits = 9, 428 .val_bits = 8, 429 .max_register = BD72720_REG_IMPCHK_CTRL, 430 /* 431 * We don't want to duplicate caches. It would be a bit faster to 432 * have the cache in this 'wrapper regmap', and not in the 'real 433 * regmaps' bd72720_regmap_4b and bd72720_regmap_4c below. This would 434 * require all the subdevices to use the wrapper-map in order to be 435 * able to benefit from the cache. 436 * Currently most of the sub-devices use only the same slave-address 437 * as this MFD driver. Now, because we don't add the offset to the 438 * registers belonging to this slave, those devices can use either the 439 * wrapper map, or the bd72720_regmap_4b directly. This means majority 440 * of our sub devices don't need to care which regmap they get using 441 * the dev_get_regmap(). This unifies the code between the BD72720 and 442 * those variants which don't have this 'multiple slave addresses' 443 * -hassle. 444 * So, for a small performance penalty, we simplify the code for the 445 * sub-devices by having the caches in the wrapped regmaps and not here. 446 */ 447 .cache_type = REGCACHE_NONE, 448 .reg_write = regmap_write_wrapper, 449 .reg_read = regmap_read_wrapper, 450 }; 451 452 static const struct regmap_config bd72720_regmap_4b = { 453 .reg_bits = 8, 454 .val_bits = 8, 455 .volatile_table = &bd72720_volatile_regs_4b, 456 .precious_table = &bd72720_precious_regs_4b, 457 .max_register = BD72720_REG_INT_ETC2_SRC, 458 .cache_type = REGCACHE_MAPLE, 459 }; 460 461 static const struct regmap_config bd72720_regmap_4c = { 462 .reg_bits = 8, 463 .val_bits = 8, 464 .volatile_table = &bd72720_volatile_regs_4c, 465 .max_register = BD72720_REG_UNWRAP(BD72720_REG_IMPCHK_CTRL), 466 .cache_type = REGCACHE_MAPLE, 467 }; 468 469 /* 470 * Mapping of main IRQ register bits to sub-IRQ register offsets so that we can 471 * access corect sub-IRQ registers based on bits that are set in main IRQ 472 * register. BD71815 and BD71828 have same sub-register-block offests, the 473 * BD72720 has a different one. 474 */ 475 476 static unsigned int bit0_offsets[] = {11}; /* RTC IRQ */ 477 static unsigned int bit1_offsets[] = {10}; /* TEMP IRQ */ 478 static unsigned int bit2_offsets[] = {6, 7, 8, 9}; /* BAT MON IRQ */ 479 static unsigned int bit3_offsets[] = {5}; /* BAT IRQ */ 480 static unsigned int bit4_offsets[] = {4}; /* CHG IRQ */ 481 static unsigned int bit5_offsets[] = {3}; /* VSYS IRQ */ 482 static unsigned int bit6_offsets[] = {1, 2}; /* DCIN IRQ */ 483 static unsigned int bit7_offsets[] = {0}; /* BUCK IRQ */ 484 485 static unsigned int bd72720_bit0_offsets[] = {0, 1}; /* PS1 and PS2 */ 486 static unsigned int bd72720_bit1_offsets[] = {2, 3}; /* DVS1 and DVS2 */ 487 static unsigned int bd72720_bit2_offsets[] = {4}; /* VBUS */ 488 static unsigned int bd72720_bit3_offsets[] = {5}; /* VSYS */ 489 static unsigned int bd72720_bit4_offsets[] = {6}; /* CHG */ 490 static unsigned int bd72720_bit5_offsets[] = {7, 8}; /* BAT1 and BAT2 */ 491 static unsigned int bd72720_bit6_offsets[] = {9}; /* IBAT */ 492 static unsigned int bd72720_bit7_offsets[] = {10, 11}; /* ETC1 and ETC2 */ 493 494 static const struct regmap_irq_sub_irq_map bd718xx_sub_irq_offsets[] = { 495 REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets), 496 REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets), 497 REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets), 498 REGMAP_IRQ_MAIN_REG_OFFSET(bit3_offsets), 499 REGMAP_IRQ_MAIN_REG_OFFSET(bit4_offsets), 500 REGMAP_IRQ_MAIN_REG_OFFSET(bit5_offsets), 501 REGMAP_IRQ_MAIN_REG_OFFSET(bit6_offsets), 502 REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets), 503 }; 504 505 static const struct regmap_irq_sub_irq_map bd72720_sub_irq_offsets[] = { 506 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit0_offsets), 507 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit1_offsets), 508 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit2_offsets), 509 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit3_offsets), 510 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit4_offsets), 511 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit5_offsets), 512 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit6_offsets), 513 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit7_offsets), 514 }; 515 516 static const struct regmap_irq bd71815_irqs[] = { 517 REGMAP_IRQ_REG(BD71815_INT_BUCK1_OCP, 0, BD71815_INT_BUCK1_OCP_MASK), 518 REGMAP_IRQ_REG(BD71815_INT_BUCK2_OCP, 0, BD71815_INT_BUCK2_OCP_MASK), 519 REGMAP_IRQ_REG(BD71815_INT_BUCK3_OCP, 0, BD71815_INT_BUCK3_OCP_MASK), 520 REGMAP_IRQ_REG(BD71815_INT_BUCK4_OCP, 0, BD71815_INT_BUCK4_OCP_MASK), 521 REGMAP_IRQ_REG(BD71815_INT_BUCK5_OCP, 0, BD71815_INT_BUCK5_OCP_MASK), 522 REGMAP_IRQ_REG(BD71815_INT_LED_OVP, 0, BD71815_INT_LED_OVP_MASK), 523 REGMAP_IRQ_REG(BD71815_INT_LED_OCP, 0, BD71815_INT_LED_OCP_MASK), 524 REGMAP_IRQ_REG(BD71815_INT_LED_SCP, 0, BD71815_INT_LED_SCP_MASK), 525 /* DCIN1 interrupts */ 526 REGMAP_IRQ_REG(BD71815_INT_DCIN_RMV, 1, BD71815_INT_DCIN_RMV_MASK), 527 REGMAP_IRQ_REG(BD71815_INT_CLPS_OUT, 1, BD71815_INT_CLPS_OUT_MASK), 528 REGMAP_IRQ_REG(BD71815_INT_CLPS_IN, 1, BD71815_INT_CLPS_IN_MASK), 529 REGMAP_IRQ_REG(BD71815_INT_DCIN_OVP_RES, 1, BD71815_INT_DCIN_OVP_RES_MASK), 530 REGMAP_IRQ_REG(BD71815_INT_DCIN_OVP_DET, 1, BD71815_INT_DCIN_OVP_DET_MASK), 531 /* DCIN2 interrupts */ 532 REGMAP_IRQ_REG(BD71815_INT_DCIN_MON_RES, 2, BD71815_INT_DCIN_MON_RES_MASK), 533 REGMAP_IRQ_REG(BD71815_INT_DCIN_MON_DET, 2, BD71815_INT_DCIN_MON_DET_MASK), 534 REGMAP_IRQ_REG(BD71815_INT_WDOG, 2, BD71815_INT_WDOG_MASK), 535 /* Vsys */ 536 REGMAP_IRQ_REG(BD71815_INT_VSYS_UV_RES, 3, BD71815_INT_VSYS_UV_RES_MASK), 537 REGMAP_IRQ_REG(BD71815_INT_VSYS_UV_DET, 3, BD71815_INT_VSYS_UV_DET_MASK), 538 REGMAP_IRQ_REG(BD71815_INT_VSYS_LOW_RES, 3, BD71815_INT_VSYS_LOW_RES_MASK), 539 REGMAP_IRQ_REG(BD71815_INT_VSYS_LOW_DET, 3, BD71815_INT_VSYS_LOW_DET_MASK), 540 REGMAP_IRQ_REG(BD71815_INT_VSYS_MON_RES, 3, BD71815_INT_VSYS_MON_RES_MASK), 541 REGMAP_IRQ_REG(BD71815_INT_VSYS_MON_DET, 3, BD71815_INT_VSYS_MON_DET_MASK), 542 /* Charger */ 543 REGMAP_IRQ_REG(BD71815_INT_CHG_WDG_TEMP, 4, BD71815_INT_CHG_WDG_TEMP_MASK), 544 REGMAP_IRQ_REG(BD71815_INT_CHG_WDG_TIME, 4, BD71815_INT_CHG_WDG_TIME_MASK), 545 REGMAP_IRQ_REG(BD71815_INT_CHG_RECHARGE_RES, 4, BD71815_INT_CHG_RECHARGE_RES_MASK), 546 REGMAP_IRQ_REG(BD71815_INT_CHG_RECHARGE_DET, 4, BD71815_INT_CHG_RECHARGE_DET_MASK), 547 REGMAP_IRQ_REG(BD71815_INT_CHG_RANGED_TEMP_TRANSITION, 4, 548 BD71815_INT_CHG_RANGED_TEMP_TRANSITION_MASK), 549 REGMAP_IRQ_REG(BD71815_INT_CHG_STATE_TRANSITION, 4, BD71815_INT_CHG_STATE_TRANSITION_MASK), 550 /* Battery */ 551 REGMAP_IRQ_REG(BD71815_INT_BAT_TEMP_NORMAL, 5, BD71815_INT_BAT_TEMP_NORMAL_MASK), 552 REGMAP_IRQ_REG(BD71815_INT_BAT_TEMP_ERANGE, 5, BD71815_INT_BAT_TEMP_ERANGE_MASK), 553 REGMAP_IRQ_REG(BD71815_INT_BAT_REMOVED, 5, BD71815_INT_BAT_REMOVED_MASK), 554 REGMAP_IRQ_REG(BD71815_INT_BAT_DETECTED, 5, BD71815_INT_BAT_DETECTED_MASK), 555 REGMAP_IRQ_REG(BD71815_INT_THERM_REMOVED, 5, BD71815_INT_THERM_REMOVED_MASK), 556 REGMAP_IRQ_REG(BD71815_INT_THERM_DETECTED, 5, BD71815_INT_THERM_DETECTED_MASK), 557 /* Battery Mon 1 */ 558 REGMAP_IRQ_REG(BD71815_INT_BAT_DEAD, 6, BD71815_INT_BAT_DEAD_MASK), 559 REGMAP_IRQ_REG(BD71815_INT_BAT_SHORTC_RES, 6, BD71815_INT_BAT_SHORTC_RES_MASK), 560 REGMAP_IRQ_REG(BD71815_INT_BAT_SHORTC_DET, 6, BD71815_INT_BAT_SHORTC_DET_MASK), 561 REGMAP_IRQ_REG(BD71815_INT_BAT_LOW_VOLT_RES, 6, BD71815_INT_BAT_LOW_VOLT_RES_MASK), 562 REGMAP_IRQ_REG(BD71815_INT_BAT_LOW_VOLT_DET, 6, BD71815_INT_BAT_LOW_VOLT_DET_MASK), 563 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_VOLT_RES, 6, BD71815_INT_BAT_OVER_VOLT_RES_MASK), 564 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_VOLT_DET, 6, BD71815_INT_BAT_OVER_VOLT_DET_MASK), 565 /* Battery Mon 2 */ 566 REGMAP_IRQ_REG(BD71815_INT_BAT_MON_RES, 7, BD71815_INT_BAT_MON_RES_MASK), 567 REGMAP_IRQ_REG(BD71815_INT_BAT_MON_DET, 7, BD71815_INT_BAT_MON_DET_MASK), 568 /* Battery Mon 3 (Coulomb counter) */ 569 REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON1, 8, BD71815_INT_BAT_CC_MON1_MASK), 570 REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON2, 8, BD71815_INT_BAT_CC_MON2_MASK), 571 REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON3, 8, BD71815_INT_BAT_CC_MON3_MASK), 572 /* Battery Mon 4 */ 573 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_1_RES, 9, BD71815_INT_BAT_OVER_CURR_1_RES_MASK), 574 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_1_DET, 9, BD71815_INT_BAT_OVER_CURR_1_DET_MASK), 575 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_2_RES, 9, BD71815_INT_BAT_OVER_CURR_2_RES_MASK), 576 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_2_DET, 9, BD71815_INT_BAT_OVER_CURR_2_DET_MASK), 577 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_3_RES, 9, BD71815_INT_BAT_OVER_CURR_3_RES_MASK), 578 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_3_DET, 9, BD71815_INT_BAT_OVER_CURR_3_DET_MASK), 579 /* Temperature */ 580 REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_LOW_RES, 10, BD71815_INT_TEMP_BAT_LOW_RES_MASK), 581 REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_LOW_DET, 10, BD71815_INT_TEMP_BAT_LOW_DET_MASK), 582 REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_HI_RES, 10, BD71815_INT_TEMP_BAT_HI_RES_MASK), 583 REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_HI_DET, 10, BD71815_INT_TEMP_BAT_HI_DET_MASK), 584 REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_125_RES, 10, 585 BD71815_INT_TEMP_CHIP_OVER_125_RES_MASK), 586 REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_125_DET, 10, 587 BD71815_INT_TEMP_CHIP_OVER_125_DET_MASK), 588 REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_VF_RES, 10, 589 BD71815_INT_TEMP_CHIP_OVER_VF_RES_MASK), 590 REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_VF_DET, 10, 591 BD71815_INT_TEMP_CHIP_OVER_VF_DET_MASK), 592 /* RTC Alarm */ 593 REGMAP_IRQ_REG(BD71815_INT_RTC0, 11, BD71815_INT_RTC0_MASK), 594 REGMAP_IRQ_REG(BD71815_INT_RTC1, 11, BD71815_INT_RTC1_MASK), 595 REGMAP_IRQ_REG(BD71815_INT_RTC2, 11, BD71815_INT_RTC2_MASK), 596 }; 597 598 static const struct regmap_irq bd71828_irqs[] = { 599 REGMAP_IRQ_REG(BD71828_INT_BUCK1_OCP, 0, BD71828_INT_BUCK1_OCP_MASK), 600 REGMAP_IRQ_REG(BD71828_INT_BUCK2_OCP, 0, BD71828_INT_BUCK2_OCP_MASK), 601 REGMAP_IRQ_REG(BD71828_INT_BUCK3_OCP, 0, BD71828_INT_BUCK3_OCP_MASK), 602 REGMAP_IRQ_REG(BD71828_INT_BUCK4_OCP, 0, BD71828_INT_BUCK4_OCP_MASK), 603 REGMAP_IRQ_REG(BD71828_INT_BUCK5_OCP, 0, BD71828_INT_BUCK5_OCP_MASK), 604 REGMAP_IRQ_REG(BD71828_INT_BUCK6_OCP, 0, BD71828_INT_BUCK6_OCP_MASK), 605 REGMAP_IRQ_REG(BD71828_INT_BUCK7_OCP, 0, BD71828_INT_BUCK7_OCP_MASK), 606 REGMAP_IRQ_REG(BD71828_INT_PGFAULT, 0, BD71828_INT_PGFAULT_MASK), 607 /* DCIN1 interrupts */ 608 REGMAP_IRQ_REG(BD71828_INT_DCIN_DET, 1, BD71828_INT_DCIN_DET_MASK), 609 REGMAP_IRQ_REG(BD71828_INT_DCIN_RMV, 1, BD71828_INT_DCIN_RMV_MASK), 610 REGMAP_IRQ_REG(BD71828_INT_CLPS_OUT, 1, BD71828_INT_CLPS_OUT_MASK), 611 REGMAP_IRQ_REG(BD71828_INT_CLPS_IN, 1, BD71828_INT_CLPS_IN_MASK), 612 /* DCIN2 interrupts */ 613 REGMAP_IRQ_REG(BD71828_INT_DCIN_MON_RES, 2, BD71828_INT_DCIN_MON_RES_MASK), 614 REGMAP_IRQ_REG(BD71828_INT_DCIN_MON_DET, 2, BD71828_INT_DCIN_MON_DET_MASK), 615 REGMAP_IRQ_REG(BD71828_INT_LONGPUSH, 2, BD71828_INT_LONGPUSH_MASK), 616 REGMAP_IRQ_REG(BD71828_INT_MIDPUSH, 2, BD71828_INT_MIDPUSH_MASK), 617 REGMAP_IRQ_REG(BD71828_INT_SHORTPUSH, 2, BD71828_INT_SHORTPUSH_MASK), 618 REGMAP_IRQ_REG(BD71828_INT_PUSH, 2, BD71828_INT_PUSH_MASK), 619 REGMAP_IRQ_REG(BD71828_INT_WDOG, 2, BD71828_INT_WDOG_MASK), 620 REGMAP_IRQ_REG(BD71828_INT_SWRESET, 2, BD71828_INT_SWRESET_MASK), 621 /* Vsys */ 622 REGMAP_IRQ_REG(BD71828_INT_VSYS_UV_RES, 3, BD71828_INT_VSYS_UV_RES_MASK), 623 REGMAP_IRQ_REG(BD71828_INT_VSYS_UV_DET, 3, BD71828_INT_VSYS_UV_DET_MASK), 624 REGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_RES, 3, BD71828_INT_VSYS_LOW_RES_MASK), 625 REGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_DET, 3, BD71828_INT_VSYS_LOW_DET_MASK), 626 REGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_IN, 3, BD71828_INT_VSYS_HALL_IN_MASK), 627 REGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_TOGGLE, 3, BD71828_INT_VSYS_HALL_TOGGLE_MASK), 628 REGMAP_IRQ_REG(BD71828_INT_VSYS_MON_RES, 3, BD71828_INT_VSYS_MON_RES_MASK), 629 REGMAP_IRQ_REG(BD71828_INT_VSYS_MON_DET, 3, BD71828_INT_VSYS_MON_DET_MASK), 630 /* Charger */ 631 REGMAP_IRQ_REG(BD71828_INT_CHG_DCIN_ILIM, 4, BD71828_INT_CHG_DCIN_ILIM_MASK), 632 REGMAP_IRQ_REG(BD71828_INT_CHG_TOPOFF_TO_DONE, 4, BD71828_INT_CHG_TOPOFF_TO_DONE_MASK), 633 REGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TEMP, 4, BD71828_INT_CHG_WDG_TEMP_MASK), 634 REGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TIME, 4, BD71828_INT_CHG_WDG_TIME_MASK), 635 REGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_RES, 4, BD71828_INT_CHG_RECHARGE_RES_MASK), 636 REGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_DET, 4, BD71828_INT_CHG_RECHARGE_DET_MASK), 637 REGMAP_IRQ_REG(BD71828_INT_CHG_RANGED_TEMP_TRANSITION, 4, 638 BD71828_INT_CHG_RANGED_TEMP_TRANSITION_MASK), 639 REGMAP_IRQ_REG(BD71828_INT_CHG_STATE_TRANSITION, 4, BD71828_INT_CHG_STATE_TRANSITION_MASK), 640 /* Battery */ 641 REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_NORMAL, 5, BD71828_INT_BAT_TEMP_NORMAL_MASK), 642 REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_ERANGE, 5, BD71828_INT_BAT_TEMP_ERANGE_MASK), 643 REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_WARN, 5, BD71828_INT_BAT_TEMP_WARN_MASK), 644 REGMAP_IRQ_REG(BD71828_INT_BAT_REMOVED, 5, BD71828_INT_BAT_REMOVED_MASK), 645 REGMAP_IRQ_REG(BD71828_INT_BAT_DETECTED, 5, BD71828_INT_BAT_DETECTED_MASK), 646 REGMAP_IRQ_REG(BD71828_INT_THERM_REMOVED, 5, BD71828_INT_THERM_REMOVED_MASK), 647 REGMAP_IRQ_REG(BD71828_INT_THERM_DETECTED, 5, BD71828_INT_THERM_DETECTED_MASK), 648 /* Battery Mon 1 */ 649 REGMAP_IRQ_REG(BD71828_INT_BAT_DEAD, 6, BD71828_INT_BAT_DEAD_MASK), 650 REGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_RES, 6, BD71828_INT_BAT_SHORTC_RES_MASK), 651 REGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_DET, 6, BD71828_INT_BAT_SHORTC_DET_MASK), 652 REGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_RES, 6, BD71828_INT_BAT_LOW_VOLT_RES_MASK), 653 REGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_DET, 6, BD71828_INT_BAT_LOW_VOLT_DET_MASK), 654 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_RES, 6, BD71828_INT_BAT_OVER_VOLT_RES_MASK), 655 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_DET, 6, BD71828_INT_BAT_OVER_VOLT_DET_MASK), 656 /* Battery Mon 2 */ 657 REGMAP_IRQ_REG(BD71828_INT_BAT_MON_RES, 7, BD71828_INT_BAT_MON_RES_MASK), 658 REGMAP_IRQ_REG(BD71828_INT_BAT_MON_DET, 7, BD71828_INT_BAT_MON_DET_MASK), 659 /* Battery Mon 3 (Coulomb counter) */ 660 REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON1, 8, BD71828_INT_BAT_CC_MON1_MASK), 661 REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON2, 8, BD71828_INT_BAT_CC_MON2_MASK), 662 REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON3, 8, BD71828_INT_BAT_CC_MON3_MASK), 663 /* Battery Mon 4 */ 664 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_RES, 9, BD71828_INT_BAT_OVER_CURR_1_RES_MASK), 665 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_DET, 9, BD71828_INT_BAT_OVER_CURR_1_DET_MASK), 666 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_RES, 9, BD71828_INT_BAT_OVER_CURR_2_RES_MASK), 667 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_DET, 9, BD71828_INT_BAT_OVER_CURR_2_DET_MASK), 668 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_RES, 9, BD71828_INT_BAT_OVER_CURR_3_RES_MASK), 669 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_DET, 9, BD71828_INT_BAT_OVER_CURR_3_DET_MASK), 670 /* Temperature */ 671 REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_RES, 10, BD71828_INT_TEMP_BAT_LOW_RES_MASK), 672 REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_DET, 10, BD71828_INT_TEMP_BAT_LOW_DET_MASK), 673 REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_RES, 10, BD71828_INT_TEMP_BAT_HI_RES_MASK), 674 REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_DET, 10, BD71828_INT_TEMP_BAT_HI_DET_MASK), 675 REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_125_RES, 10, 676 BD71828_INT_TEMP_CHIP_OVER_125_RES_MASK), 677 REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_125_DET, 10, 678 BD71828_INT_TEMP_CHIP_OVER_125_DET_MASK), 679 REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_VF_DET, 10, 680 BD71828_INT_TEMP_CHIP_OVER_VF_DET_MASK), 681 REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_VF_RES, 10, 682 BD71828_INT_TEMP_CHIP_OVER_VF_RES_MASK), 683 /* RTC Alarm */ 684 REGMAP_IRQ_REG(BD71828_INT_RTC0, 11, BD71828_INT_RTC0_MASK), 685 REGMAP_IRQ_REG(BD71828_INT_RTC1, 11, BD71828_INT_RTC1_MASK), 686 REGMAP_IRQ_REG(BD71828_INT_RTC2, 11, BD71828_INT_RTC2_MASK), 687 }; 688 689 static const struct regmap_irq bd72720_irqs[] = { 690 REGMAP_IRQ_REG(BD72720_INT_LONGPUSH, 0, BD72720_INT_LONGPUSH_MASK), 691 REGMAP_IRQ_REG(BD72720_INT_MIDPUSH, 0, BD72720_INT_MIDPUSH_MASK), 692 REGMAP_IRQ_REG(BD72720_INT_SHORTPUSH, 0, BD72720_INT_SHORTPUSH_MASK), 693 REGMAP_IRQ_REG(BD72720_INT_PUSH, 0, BD72720_INT_PUSH_MASK), 694 REGMAP_IRQ_REG(BD72720_INT_HALL_DET, 0, BD72720_INT_HALL_DET_MASK), 695 REGMAP_IRQ_REG(BD72720_INT_HALL_TGL, 0, BD72720_INT_HALL_TGL_MASK), 696 REGMAP_IRQ_REG(BD72720_INT_WDOG, 0, BD72720_INT_WDOG_MASK), 697 REGMAP_IRQ_REG(BD72720_INT_SWRESET, 0, BD72720_INT_SWRESET_MASK), 698 REGMAP_IRQ_REG(BD72720_INT_SEQ_DONE, 1, BD72720_INT_SEQ_DONE_MASK), 699 REGMAP_IRQ_REG(BD72720_INT_PGFAULT, 1, BD72720_INT_PGFAULT_MASK), 700 REGMAP_IRQ_REG(BD72720_INT_BUCK1_DVS, 2, BD72720_INT_BUCK1_DVS_MASK), 701 REGMAP_IRQ_REG(BD72720_INT_BUCK2_DVS, 2, BD72720_INT_BUCK2_DVS_MASK), 702 REGMAP_IRQ_REG(BD72720_INT_BUCK3_DVS, 2, BD72720_INT_BUCK3_DVS_MASK), 703 REGMAP_IRQ_REG(BD72720_INT_BUCK4_DVS, 2, BD72720_INT_BUCK4_DVS_MASK), 704 REGMAP_IRQ_REG(BD72720_INT_BUCK5_DVS, 2, BD72720_INT_BUCK5_DVS_MASK), 705 REGMAP_IRQ_REG(BD72720_INT_BUCK6_DVS, 2, BD72720_INT_BUCK6_DVS_MASK), 706 REGMAP_IRQ_REG(BD72720_INT_BUCK7_DVS, 2, BD72720_INT_BUCK7_DVS_MASK), 707 REGMAP_IRQ_REG(BD72720_INT_BUCK8_DVS, 2, BD72720_INT_BUCK8_DVS_MASK), 708 REGMAP_IRQ_REG(BD72720_INT_BUCK9_DVS, 3, BD72720_INT_BUCK9_DVS_MASK), 709 REGMAP_IRQ_REG(BD72720_INT_BUCK10_DVS, 3, BD72720_INT_BUCK10_DVS_MASK), 710 REGMAP_IRQ_REG(BD72720_INT_LDO1_DVS, 3, BD72720_INT_LDO1_DVS_MASK), 711 REGMAP_IRQ_REG(BD72720_INT_LDO2_DVS, 3, BD72720_INT_LDO2_DVS_MASK), 712 REGMAP_IRQ_REG(BD72720_INT_LDO3_DVS, 3, BD72720_INT_LDO3_DVS_MASK), 713 REGMAP_IRQ_REG(BD72720_INT_LDO4_DVS, 3, BD72720_INT_LDO4_DVS_MASK), 714 715 REGMAP_IRQ_REG(BD72720_INT_VBUS_RMV, 4, BD72720_INT_VBUS_RMV_MASK), 716 REGMAP_IRQ_REG(BD72720_INT_VBUS_DET, 4, BD72720_INT_VBUS_DET_MASK), 717 REGMAP_IRQ_REG(BD72720_INT_VBUS_MON_RES, 4, BD72720_INT_VBUS_MON_RES_MASK), 718 REGMAP_IRQ_REG(BD72720_INT_VBUS_MON_DET, 4, BD72720_INT_VBUS_MON_DET_MASK), 719 REGMAP_IRQ_REG(BD72720_INT_VSYS_MON_RES, 5, BD72720_INT_VSYS_MON_RES_MASK), 720 REGMAP_IRQ_REG(BD72720_INT_VSYS_MON_DET, 5, BD72720_INT_VSYS_MON_DET_MASK), 721 REGMAP_IRQ_REG(BD72720_INT_VSYS_UV_RES, 5, BD72720_INT_VSYS_UV_RES_MASK), 722 REGMAP_IRQ_REG(BD72720_INT_VSYS_UV_DET, 5, BD72720_INT_VSYS_UV_DET_MASK), 723 REGMAP_IRQ_REG(BD72720_INT_VSYS_LO_RES, 5, BD72720_INT_VSYS_LO_RES_MASK), 724 REGMAP_IRQ_REG(BD72720_INT_VSYS_LO_DET, 5, BD72720_INT_VSYS_LO_DET_MASK), 725 REGMAP_IRQ_REG(BD72720_INT_VSYS_OV_RES, 5, BD72720_INT_VSYS_OV_RES_MASK), 726 REGMAP_IRQ_REG(BD72720_INT_VSYS_OV_DET, 5, BD72720_INT_VSYS_OV_DET_MASK), 727 REGMAP_IRQ_REG(BD72720_INT_BAT_ILIM, 6, BD72720_INT_BAT_ILIM_MASK), 728 REGMAP_IRQ_REG(BD72720_INT_CHG_DONE, 6, BD72720_INT_CHG_DONE_MASK), 729 REGMAP_IRQ_REG(BD72720_INT_EXTEMP_TOUT, 6, BD72720_INT_EXTEMP_TOUT_MASK), 730 REGMAP_IRQ_REG(BD72720_INT_CHG_WDT_EXP, 6, BD72720_INT_CHG_WDT_EXP_MASK), 731 REGMAP_IRQ_REG(BD72720_INT_BAT_MNT_OUT, 6, BD72720_INT_BAT_MNT_OUT_MASK), 732 REGMAP_IRQ_REG(BD72720_INT_BAT_MNT_IN, 6, BD72720_INT_BAT_MNT_IN_MASK), 733 REGMAP_IRQ_REG(BD72720_INT_CHG_TRNS, 6, BD72720_INT_CHG_TRNS_MASK), 734 735 REGMAP_IRQ_REG(BD72720_INT_VBAT_MON_RES, 7, BD72720_INT_VBAT_MON_RES_MASK), 736 REGMAP_IRQ_REG(BD72720_INT_VBAT_MON_DET, 7, BD72720_INT_VBAT_MON_DET_MASK), 737 REGMAP_IRQ_REG(BD72720_INT_VBAT_SHT_RES, 7, BD72720_INT_VBAT_SHT_RES_MASK), 738 REGMAP_IRQ_REG(BD72720_INT_VBAT_SHT_DET, 7, BD72720_INT_VBAT_SHT_DET_MASK), 739 REGMAP_IRQ_REG(BD72720_INT_VBAT_LO_RES, 7, BD72720_INT_VBAT_LO_RES_MASK), 740 REGMAP_IRQ_REG(BD72720_INT_VBAT_LO_DET, 7, BD72720_INT_VBAT_LO_DET_MASK), 741 REGMAP_IRQ_REG(BD72720_INT_VBAT_OV_RES, 7, BD72720_INT_VBAT_OV_RES_MASK), 742 REGMAP_IRQ_REG(BD72720_INT_VBAT_OV_DET, 7, BD72720_INT_VBAT_OV_DET_MASK), 743 REGMAP_IRQ_REG(BD72720_INT_BAT_RMV, 8, BD72720_INT_BAT_RMV_MASK), 744 REGMAP_IRQ_REG(BD72720_INT_BAT_DET, 8, BD72720_INT_BAT_DET_MASK), 745 REGMAP_IRQ_REG(BD72720_INT_DBAT_DET, 8, BD72720_INT_DBAT_DET_MASK), 746 REGMAP_IRQ_REG(BD72720_INT_BAT_TEMP_TRNS, 8, BD72720_INT_BAT_TEMP_TRNS_MASK), 747 REGMAP_IRQ_REG(BD72720_INT_LOBTMP_RES, 8, BD72720_INT_LOBTMP_RES_MASK), 748 REGMAP_IRQ_REG(BD72720_INT_LOBTMP_DET, 8, BD72720_INT_LOBTMP_DET_MASK), 749 REGMAP_IRQ_REG(BD72720_INT_OVBTMP_RES, 8, BD72720_INT_OVBTMP_RES_MASK), 750 REGMAP_IRQ_REG(BD72720_INT_OVBTMP_DET, 8, BD72720_INT_OVBTMP_DET_MASK), 751 REGMAP_IRQ_REG(BD72720_INT_OCUR1_RES, 9, BD72720_INT_OCUR1_RES_MASK), 752 REGMAP_IRQ_REG(BD72720_INT_OCUR1_DET, 9, BD72720_INT_OCUR1_DET_MASK), 753 REGMAP_IRQ_REG(BD72720_INT_OCUR2_RES, 9, BD72720_INT_OCUR2_RES_MASK), 754 REGMAP_IRQ_REG(BD72720_INT_OCUR2_DET, 9, BD72720_INT_OCUR2_DET_MASK), 755 REGMAP_IRQ_REG(BD72720_INT_OCUR3_RES, 9, BD72720_INT_OCUR3_RES_MASK), 756 REGMAP_IRQ_REG(BD72720_INT_OCUR3_DET, 9, BD72720_INT_OCUR3_DET_MASK), 757 REGMAP_IRQ_REG(BD72720_INT_CC_MON1_DET, 10, BD72720_INT_CC_MON1_DET_MASK), 758 REGMAP_IRQ_REG(BD72720_INT_CC_MON2_DET, 10, BD72720_INT_CC_MON2_DET_MASK), 759 REGMAP_IRQ_REG(BD72720_INT_CC_MON3_DET, 10, BD72720_INT_CC_MON3_DET_MASK), 760 /* 761 * The GPIO1_IN and GPIO2_IN IRQs are generated from the PMIC's GPIO1 and GPIO2 762 * pins. Eg, they may be wired to other devices which can then use the PMIC as 763 * an interrupt controller. The GPIO1 and GPIO2 can have the IRQ type 764 * specified. All of the types (falling, rising, and both edges as well as low 765 * and high levels) are supported. 766 */ 767 BD72720_TYPED_IRQ_REG(BD72720_INT_GPIO1_IN, 10, BD72720_INT_GPIO1_IN_MASK, 0), 768 BD72720_TYPED_IRQ_REG(BD72720_INT_GPIO2_IN, 10, BD72720_INT_GPIO2_IN_MASK, 1), 769 REGMAP_IRQ_REG(BD72720_INT_VF125_RES, 11, BD72720_INT_VF125_RES_MASK), 770 REGMAP_IRQ_REG(BD72720_INT_VF125_DET, 11, BD72720_INT_VF125_DET_MASK), 771 REGMAP_IRQ_REG(BD72720_INT_VF_RES, 11, BD72720_INT_VF_RES_MASK), 772 REGMAP_IRQ_REG(BD72720_INT_VF_DET, 11, BD72720_INT_VF_DET_MASK), 773 REGMAP_IRQ_REG(BD72720_INT_RTC0, 11, BD72720_INT_RTC0_MASK), 774 REGMAP_IRQ_REG(BD72720_INT_RTC1, 11, BD72720_INT_RTC1_MASK), 775 REGMAP_IRQ_REG(BD72720_INT_RTC2, 11, BD72720_INT_RTC2_MASK), 776 }; 777 778 static int bd72720_set_type_config(unsigned int **buf, unsigned int type, 779 const struct regmap_irq *irq_data, 780 int idx, void *irq_drv_data) 781 { 782 const struct regmap_irq_type *t = &irq_data->type; 783 784 /* 785 * The regmap IRQ ecpects IRQ_TYPE_EDGE_BOTH to be written to register 786 * as logical OR of the type_falling_val and type_rising_val. This is 787 * not how the BD72720 implements this configuration, hence we need 788 * to handle this specific case separately. 789 */ 790 if (type == IRQ_TYPE_EDGE_BOTH) { 791 buf[0][idx] &= ~t->type_reg_mask; 792 buf[0][idx] |= BD72720_GPIO_IRQ_TYPE_BOTH; 793 794 return 0; 795 } 796 797 return regmap_irq_set_type_config_simple(buf, type, irq_data, idx, irq_drv_data); 798 } 799 800 static const struct regmap_irq_chip bd71828_irq_chip = { 801 .name = "bd71828_irq", 802 .main_status = BD71828_REG_INT_MAIN, 803 .irqs = &bd71828_irqs[0], 804 .num_irqs = ARRAY_SIZE(bd71828_irqs), 805 .status_base = BD71828_REG_INT_BUCK, 806 .unmask_base = BD71828_REG_INT_MASK_BUCK, 807 .ack_base = BD71828_REG_INT_BUCK, 808 .init_ack_masked = true, 809 .num_regs = 12, 810 .num_main_regs = 1, 811 .sub_reg_offsets = &bd718xx_sub_irq_offsets[0], 812 .num_main_status_bits = 8, 813 .irq_reg_stride = 1, 814 }; 815 816 static const struct regmap_irq_chip bd71815_irq_chip = { 817 .name = "bd71815_irq", 818 .main_status = BD71815_REG_INT_STAT, 819 .irqs = &bd71815_irqs[0], 820 .num_irqs = ARRAY_SIZE(bd71815_irqs), 821 .status_base = BD71815_REG_INT_STAT_01, 822 .unmask_base = BD71815_REG_INT_EN_01, 823 .ack_base = BD71815_REG_INT_STAT_01, 824 .init_ack_masked = true, 825 .num_regs = 12, 826 .num_main_regs = 1, 827 .sub_reg_offsets = &bd718xx_sub_irq_offsets[0], 828 .num_main_status_bits = 8, 829 .irq_reg_stride = 1, 830 }; 831 832 static const unsigned int bd72720_irq_type_base[] = { BD72720_REG_GPIO1_CTRL }; 833 834 static const struct regmap_irq_chip bd72720_irq_chip = { 835 .name = "bd72720_irq", 836 .main_status = BD72720_REG_INT_LVL1_STAT, 837 .irqs = &bd72720_irqs[0], 838 .num_irqs = ARRAY_SIZE(bd72720_irqs), 839 .status_base = BD72720_REG_INT_PS1_STAT, 840 .unmask_base = BD72720_REG_INT_PS1_EN, 841 .config_base = &bd72720_irq_type_base[0], 842 .num_config_bases = 1, 843 .num_config_regs = 2, 844 .set_type_config = bd72720_set_type_config, 845 .ack_base = BD72720_REG_INT_PS1_STAT, 846 .init_ack_masked = true, 847 .num_regs = 12, 848 .num_main_regs = 1, 849 .sub_reg_offsets = &bd72720_sub_irq_offsets[0], 850 .num_main_status_bits = 8, 851 .irq_reg_stride = 1, 852 }; 853 854 static int set_clk_mode(struct device *dev, struct regmap *regmap, 855 int clkmode_reg) 856 { 857 int ret; 858 unsigned int open_drain; 859 860 ret = of_property_read_u32(dev->of_node, "rohm,clkout-open-drain", &open_drain); 861 if (ret) { 862 if (ret == -EINVAL) 863 return 0; 864 return ret; 865 } 866 if (open_drain > 1) { 867 dev_err(dev, "bad clk32kout mode configuration"); 868 return -EINVAL; 869 } 870 871 if (open_drain) 872 return regmap_update_bits(regmap, clkmode_reg, OUT32K_MODE, 873 OUT32K_MODE_OPEN_DRAIN); 874 875 return regmap_update_bits(regmap, clkmode_reg, OUT32K_MODE, 876 OUT32K_MODE_CMOS); 877 } 878 879 static struct i2c_client *bd71828_dev; 880 static void bd71828_power_off(void) 881 { 882 while (true) { 883 s32 val; 884 885 /* We are not allowed to sleep, so do not use regmap involving mutexes here. */ 886 val = i2c_smbus_read_byte_data(bd71828_dev, BD71828_REG_PS_CTRL_1); 887 if (val >= 0) 888 i2c_smbus_write_byte_data(bd71828_dev, 889 BD71828_REG_PS_CTRL_1, 890 BD71828_MASK_STATE_HBNT | (u8)val); 891 mdelay(500); 892 } 893 } 894 895 static void bd71828_remove_poweroff(void *data) 896 { 897 pm_power_off = NULL; 898 } 899 900 static struct regmap *bd72720_do_regmaps(struct i2c_client *i2c) 901 { 902 struct bd72720_regmaps *maps; 903 struct i2c_client *secondary_i2c; 904 905 secondary_i2c = devm_i2c_new_dummy_device(&i2c->dev, i2c->adapter, 906 BD72720_SECONDARY_I2C_SLAVE); 907 if (IS_ERR(secondary_i2c)) { 908 dev_err_probe(&i2c->dev, PTR_ERR(secondary_i2c), "Failed to get secondary I2C\n"); 909 910 return ERR_CAST(secondary_i2c); 911 } 912 913 maps = devm_kzalloc(&i2c->dev, sizeof(*maps), GFP_KERNEL); 914 if (!maps) 915 return ERR_PTR(-ENOMEM); 916 917 maps->map1_4b = devm_regmap_init_i2c(i2c, &bd72720_regmap_4b); 918 if (IS_ERR(maps->map1_4b)) 919 return maps->map1_4b; 920 921 maps->map2_4c = devm_regmap_init_i2c(secondary_i2c, &bd72720_regmap_4c); 922 if (IS_ERR(maps->map2_4c)) 923 return maps->map2_4c; 924 925 return devm_regmap_init(&i2c->dev, NULL, maps, &bd72720_wrapper_map_config); 926 } 927 928 static int bd71828_i2c_probe(struct i2c_client *i2c) 929 { 930 struct regmap_irq_chip_data *irq_data; 931 int ret; 932 struct regmap *regmap = NULL; 933 const struct regmap_config *regmap_config; 934 const struct regmap_irq_chip *irqchip; 935 unsigned int chip_type; 936 const struct mfd_cell *mfd; 937 int cells; 938 int button_irq; 939 int clkmode_reg; 940 int main_lvl_mask_reg = 0, main_lvl_val = 0; 941 942 if (!i2c->irq) { 943 dev_err(&i2c->dev, "No IRQ configured\n"); 944 return -EINVAL; 945 } 946 947 chip_type = (unsigned int)(uintptr_t) 948 of_device_get_match_data(&i2c->dev); 949 switch (chip_type) { 950 case ROHM_CHIP_TYPE_BD71828: 951 mfd = bd71828_mfd_cells; 952 cells = ARRAY_SIZE(bd71828_mfd_cells); 953 regmap_config = &bd71828_regmap; 954 irqchip = &bd71828_irq_chip; 955 clkmode_reg = BD71828_REG_OUT32K; 956 button_irq = BD71828_INT_SHORTPUSH; 957 break; 958 case ROHM_CHIP_TYPE_BD71815: 959 mfd = bd71815_mfd_cells; 960 cells = ARRAY_SIZE(bd71815_mfd_cells); 961 regmap_config = &bd71815_regmap; 962 irqchip = &bd71815_irq_chip; 963 clkmode_reg = BD71815_REG_OUT32K; 964 /* 965 * If BD71817 support is needed we should be able to handle it 966 * with proper DT configs + BD71815 drivers + power-button. 967 * BD71815 data-sheet does not list the power-button IRQ so we 968 * don't use it. 969 */ 970 button_irq = 0; 971 break; 972 case ROHM_CHIP_TYPE_BD72720: 973 { 974 mfd = bd72720_mfd_cells; 975 cells = ARRAY_SIZE(bd72720_mfd_cells); 976 977 regmap = bd72720_do_regmaps(i2c); 978 if (IS_ERR(regmap)) 979 return dev_err_probe(&i2c->dev, PTR_ERR(regmap), 980 "Failed to initialize Regmap\n"); 981 982 irqchip = &bd72720_irq_chip; 983 clkmode_reg = BD72720_REG_OUT32K; 984 button_irq = BD72720_INT_SHORTPUSH; 985 main_lvl_mask_reg = BD72720_REG_INT_LVL1_EN; 986 main_lvl_val = BD72720_MASK_LVL1_EN_ALL; 987 break; 988 } 989 default: 990 dev_err(&i2c->dev, "Unknown device type"); 991 return -EINVAL; 992 } 993 994 if (!regmap) { 995 regmap = devm_regmap_init_i2c(i2c, regmap_config); 996 if (IS_ERR(regmap)) 997 return dev_err_probe(&i2c->dev, PTR_ERR(regmap), 998 "Failed to initialize Regmap\n"); 999 } 1000 1001 ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, i2c->irq, 1002 IRQF_ONESHOT, 0, irqchip, &irq_data); 1003 if (ret) 1004 return dev_err_probe(&i2c->dev, ret, 1005 "Failed to add IRQ chip\n"); 1006 1007 dev_dbg(&i2c->dev, "Registered %d IRQs for chip\n", 1008 irqchip->num_irqs); 1009 1010 /* 1011 * On some ICs the main IRQ register has corresponding mask register. 1012 * This is not handled by the regmap IRQ. Let's enable all the main 1013 * level IRQs here. Further writes to the main level MASK is not 1014 * needed because masking is handled by the per IRQ 2.nd level MASK 1015 * registers. 2.nd level masks are handled by the regmap IRQ. 1016 */ 1017 if (main_lvl_mask_reg) { 1018 ret = regmap_write(regmap, main_lvl_mask_reg, main_lvl_val); 1019 if (ret) { 1020 return dev_err_probe(&i2c->dev, ret, 1021 "Failed to enable main level IRQs\n"); 1022 } 1023 } 1024 if (button_irq) { 1025 ret = regmap_irq_get_virq(irq_data, button_irq); 1026 if (ret < 0) 1027 return dev_err_probe(&i2c->dev, ret, 1028 "Failed to get the power-key IRQ\n"); 1029 1030 button.irq = ret; 1031 } 1032 1033 ret = set_clk_mode(&i2c->dev, regmap, clkmode_reg); 1034 if (ret) 1035 return ret; 1036 1037 ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, mfd, cells, 1038 NULL, 0, regmap_irq_get_domain(irq_data)); 1039 if (ret) 1040 return dev_err_probe(&i2c->dev, ret, "Failed to create subdevices\n"); 1041 1042 if (of_device_is_system_power_controller(i2c->dev.of_node) && 1043 chip_type == ROHM_CHIP_TYPE_BD71828) { 1044 if (!pm_power_off) { 1045 bd71828_dev = i2c; 1046 pm_power_off = bd71828_power_off; 1047 ret = devm_add_action_or_reset(&i2c->dev, 1048 bd71828_remove_poweroff, 1049 NULL); 1050 } else { 1051 dev_warn(&i2c->dev, "Poweroff callback already assigned\n"); 1052 } 1053 } 1054 1055 return ret; 1056 } 1057 1058 static const struct of_device_id bd71828_of_match[] = { 1059 { 1060 .compatible = "rohm,bd71828", 1061 .data = (void *)ROHM_CHIP_TYPE_BD71828, 1062 }, { 1063 .compatible = "rohm,bd71815", 1064 .data = (void *)ROHM_CHIP_TYPE_BD71815, 1065 }, { 1066 .compatible = "rohm,bd72720", 1067 .data = (void *)ROHM_CHIP_TYPE_BD72720, 1068 }, 1069 { }, 1070 }; 1071 MODULE_DEVICE_TABLE(of, bd71828_of_match); 1072 1073 static struct i2c_driver bd71828_drv = { 1074 .driver = { 1075 .name = "rohm-bd71828", 1076 .of_match_table = bd71828_of_match, 1077 }, 1078 .probe = bd71828_i2c_probe, 1079 }; 1080 module_i2c_driver(bd71828_drv); 1081 1082 MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>"); 1083 MODULE_DESCRIPTION("ROHM BD71828 Power Management IC driver"); 1084 MODULE_LICENSE("GPL"); 1085