1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2019 ROHM Semiconductors 4 * 5 * ROHM BD718[15/28/79] and BD72720 PMIC driver 6 */ 7 8 #include <linux/gpio_keys.h> 9 #include <linux/i2c.h> 10 #include <linux/input.h> 11 #include <linux/interrupt.h> 12 #include <linux/ioport.h> 13 #include <linux/irq.h> 14 #include <linux/mfd/core.h> 15 #include <linux/mfd/rohm-bd71815.h> 16 #include <linux/mfd/rohm-bd71828.h> 17 #include <linux/mfd/rohm-bd72720.h> 18 #include <linux/mfd/rohm-generic.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/regmap.h> 22 #include <linux/types.h> 23 24 #define BD72720_TYPED_IRQ_REG(_irq, _stat_offset, _mask, _type_offset) \ 25 [_irq] = { \ 26 .reg_offset = (_stat_offset), \ 27 .mask = (_mask), \ 28 { \ 29 .type_reg_offset = (_type_offset), \ 30 .type_reg_mask = BD72720_GPIO_IRQ_TYPE_MASK, \ 31 .type_rising_val = BD72720_GPIO_IRQ_TYPE_RISING, \ 32 .type_falling_val = BD72720_GPIO_IRQ_TYPE_FALLING, \ 33 .type_level_low_val = BD72720_GPIO_IRQ_TYPE_LOW, \ 34 .type_level_high_val = BD72720_GPIO_IRQ_TYPE_HIGH, \ 35 .types_supported = IRQ_TYPE_EDGE_BOTH | \ 36 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW, \ 37 }, \ 38 } 39 40 static struct gpio_keys_button button = { 41 .code = KEY_POWER, 42 .gpio = -1, 43 .type = EV_KEY, 44 .wakeup = 1, 45 }; 46 47 static const struct gpio_keys_platform_data bd71828_powerkey_data = { 48 .buttons = &button, 49 .nbuttons = 1, 50 .name = "bd71828-pwrkey", 51 }; 52 53 static const struct resource bd71815_rtc_irqs[] = { 54 DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC0, "bd70528-rtc-alm-0"), 55 DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC1, "bd70528-rtc-alm-1"), 56 DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC2, "bd70528-rtc-alm-2"), 57 }; 58 59 static const struct resource bd71828_rtc_irqs[] = { 60 DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC0, "bd70528-rtc-alm-0"), 61 DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC1, "bd70528-rtc-alm-1"), 62 DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC2, "bd70528-rtc-alm-2"), 63 }; 64 65 static const struct resource bd72720_rtc_irqs[] = { 66 DEFINE_RES_IRQ_NAMED(BD72720_INT_RTC0, "bd70528-rtc-alm-0"), 67 DEFINE_RES_IRQ_NAMED(BD72720_INT_RTC1, "bd70528-rtc-alm-1"), 68 DEFINE_RES_IRQ_NAMED(BD72720_INT_RTC2, "bd70528-rtc-alm-2"), 69 }; 70 71 static const struct resource bd71815_power_irqs[] = { 72 DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_RMV, "bd71815-dcin-rmv"), 73 DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_OUT, "bd71815-dcin-clps-out"), 74 DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_IN, "bd71815-dcin-clps-in"), 75 DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_RES, "bd71815-dcin-ovp-res"), 76 DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_DET, "bd71815-dcin-ovp-det"), 77 DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_MON_RES, "bd71815-dcin-mon-res"), 78 DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_MON_DET, "bd71815-dcin-mon-det"), 79 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_UV_RES, "bd71815-vsys-uv-res"), 80 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_UV_DET, "bd71815-vsys-uv-det"), 81 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_RES, "bd71815-vsys-low-res"), 82 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_DET, "bd71815-vsys-low-det"), 83 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_RES, "bd71815-vsys-mon-res"), 84 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_DET, "bd71815-vsys-mon-det"), 85 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TEMP, "bd71815-chg-wdg-temp"), 86 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TIME, "bd71815-chg-wdg"), 87 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RECHARGE_RES, "bd71815-rechg-res"), 88 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RECHARGE_DET, "bd71815-rechg-det"), 89 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RANGED_TEMP_TRANSITION, "bd71815-ranged-temp-transit"), 90 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_STATE_TRANSITION, "bd71815-chg-state-change"), 91 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_TEMP_NORMAL, "bd71815-bat-temp-normal"), 92 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_TEMP_ERANGE, "bd71815-bat-temp-erange"), 93 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_REMOVED, "bd71815-bat-rmv"), 94 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_DETECTED, "bd71815-bat-det"), 95 DEFINE_RES_IRQ_NAMED(BD71815_INT_THERM_REMOVED, "bd71815-therm-rmv"), 96 DEFINE_RES_IRQ_NAMED(BD71815_INT_THERM_DETECTED, "bd71815-therm-det"), 97 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_DEAD, "bd71815-bat-dead"), 98 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_SHORTC_RES, "bd71815-bat-short-res"), 99 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_SHORTC_DET, "bd71815-bat-short-det"), 100 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_LOW_VOLT_RES, "bd71815-bat-low-res"), 101 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_LOW_VOLT_DET, "bd71815-bat-low-det"), 102 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_VOLT_RES, "bd71815-bat-over-res"), 103 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_VOLT_DET, "bd71815-bat-over-det"), 104 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_MON_RES, "bd71815-bat-mon-res"), 105 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_MON_DET, "bd71815-bat-mon-det"), 106 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON1, "bd71815-bat-cc-mon1"), 107 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON2, "bd71815-bat-cc-mon2"), 108 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON3, "bd71815-bat-cc-mon3"), 109 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_1_RES, "bd71815-bat-oc1-res"), 110 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_1_DET, "bd71815-bat-oc1-det"), 111 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_2_RES, "bd71815-bat-oc2-res"), 112 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_2_DET, "bd71815-bat-oc2-det"), 113 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_RES, "bd71815-bat-oc3-res"), 114 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_DET, "bd71815-bat-oc3-det"), 115 DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_RES, "bd71815-temp-bat-low-res"), 116 DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_DET, "bd71815-temp-bat-low-det"), 117 DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_RES, "bd71815-temp-bat-hi-res"), 118 DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_DET, "bd71815-temp-bat-hi-det"), 119 }; 120 121 static const struct mfd_cell bd71815_mfd_cells[] = { 122 { .name = "bd71815-pmic", }, 123 { .name = "bd71815-clk", }, 124 { .name = "bd71815-gpo", }, 125 { 126 .name = "bd71815-power", 127 .num_resources = ARRAY_SIZE(bd71815_power_irqs), 128 .resources = &bd71815_power_irqs[0], 129 }, 130 { 131 .name = "bd71815-rtc", 132 .num_resources = ARRAY_SIZE(bd71815_rtc_irqs), 133 .resources = &bd71815_rtc_irqs[0], 134 }, 135 }; 136 137 static const struct resource bd71828_power_irqs[] = { 138 DEFINE_RES_IRQ_NAMED(BD71828_INT_CHG_TOPOFF_TO_DONE, 139 "bd71828-chg-done"), 140 DEFINE_RES_IRQ_NAMED(BD71828_INT_DCIN_DET, "bd71828-pwr-dcin-in"), 141 DEFINE_RES_IRQ_NAMED(BD71828_INT_DCIN_RMV, "bd71828-pwr-dcin-out"), 142 DEFINE_RES_IRQ_NAMED(BD71828_INT_BAT_LOW_VOLT_RES, 143 "bd71828-vbat-normal"), 144 DEFINE_RES_IRQ_NAMED(BD71828_INT_BAT_LOW_VOLT_DET, "bd71828-vbat-low"), 145 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_HI_DET, "bd71828-btemp-hi"), 146 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_HI_RES, "bd71828-btemp-cool"), 147 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_LOW_DET, "bd71828-btemp-lo"), 148 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_LOW_RES, 149 "bd71828-btemp-warm"), 150 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_VF_DET, 151 "bd71828-temp-hi"), 152 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_VF_RES, 153 "bd71828-temp-norm"), 154 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_125_DET, 155 "bd71828-temp-125-over"), 156 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_125_RES, 157 "bd71828-temp-125-under"), 158 }; 159 160 static struct mfd_cell bd71828_mfd_cells[] = { 161 { .name = "bd71828-pmic", }, 162 { .name = "bd71828-gpio", }, 163 { .name = "bd71828-led", .of_compatible = "rohm,bd71828-leds" }, 164 /* 165 * We use BD71837 driver to drive the clock block. Only differences to 166 * BD70528 clock gate are the register address and mask. 167 */ 168 { .name = "bd71828-clk", }, 169 { 170 .name = "bd71828-power", 171 .resources = bd71828_power_irqs, 172 .num_resources = ARRAY_SIZE(bd71828_power_irqs), 173 }, { 174 .name = "bd71828-rtc", 175 .resources = bd71828_rtc_irqs, 176 .num_resources = ARRAY_SIZE(bd71828_rtc_irqs), 177 }, { 178 .name = "gpio-keys", 179 .platform_data = &bd71828_powerkey_data, 180 .pdata_size = sizeof(bd71828_powerkey_data), 181 }, 182 }; 183 184 static const struct resource bd72720_power_irqs[] = { 185 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_RMV, "bd72720_int_vbus_rmv"), 186 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_DET, "bd72720_int_vbus_det"), 187 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_MON_RES, "bd72720_int_vbus_mon_res"), 188 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_MON_DET, "bd72720_int_vbus_mon_det"), 189 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_MON_RES, "bd72720_int_vsys_mon_res"), 190 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_MON_DET, "bd72720_int_vsys_mon_det"), 191 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_UV_RES, "bd72720_int_vsys_uv_res"), 192 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_UV_DET, "bd72720_int_vsys_uv_det"), 193 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_LO_RES, "bd72720_int_vsys_lo_res"), 194 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_LO_DET, "bd72720_int_vsys_lo_det"), 195 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_OV_RES, "bd72720_int_vsys_ov_res"), 196 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_OV_DET, "bd72720_int_vsys_ov_det"), 197 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_ILIM, "bd72720_int_bat_ilim"), 198 DEFINE_RES_IRQ_NAMED(BD72720_INT_CHG_DONE, "bd72720_int_chg_done"), 199 DEFINE_RES_IRQ_NAMED(BD72720_INT_EXTEMP_TOUT, "bd72720_int_extemp_tout"), 200 DEFINE_RES_IRQ_NAMED(BD72720_INT_CHG_WDT_EXP, "bd72720_int_chg_wdt_exp"), 201 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_MNT_OUT, "bd72720_int_bat_mnt_out"), 202 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_MNT_IN, "bd72720_int_bat_mnt_in"), 203 DEFINE_RES_IRQ_NAMED(BD72720_INT_CHG_TRNS, "bd72720_int_chg_trns"), 204 205 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_MON_RES, "bd72720_int_vbat_mon_res"), 206 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_MON_DET, "bd72720_int_vbat_mon_det"), 207 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_SHT_RES, "bd72720_int_vbat_sht_res"), 208 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_SHT_DET, "bd72720_int_vbat_sht_det"), 209 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_LO_RES, "bd72720_int_vbat_lo_res"), 210 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_LO_DET, "bd72720_int_vbat_lo_det"), 211 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_OV_RES, "bd72720_int_vbat_ov_res"), 212 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_OV_DET, "bd72720_int_vbat_ov_det"), 213 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_RMV, "bd72720_int_bat_rmv"), 214 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_DET, "bd72720_int_bat_det"), 215 DEFINE_RES_IRQ_NAMED(BD72720_INT_DBAT_DET, "bd72720_int_dbat_det"), 216 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_TEMP_TRNS, "bd72720_int_bat_temp_trns"), 217 DEFINE_RES_IRQ_NAMED(BD72720_INT_LOBTMP_RES, "bd72720_int_lobtmp_res"), 218 DEFINE_RES_IRQ_NAMED(BD72720_INT_LOBTMP_DET, "bd72720_int_lobtmp_det"), 219 DEFINE_RES_IRQ_NAMED(BD72720_INT_OVBTMP_RES, "bd72720_int_ovbtmp_res"), 220 DEFINE_RES_IRQ_NAMED(BD72720_INT_OVBTMP_DET, "bd72720_int_ovbtmp_det"), 221 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR1_RES, "bd72720_int_ocur1_res"), 222 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR1_DET, "bd72720_int_ocur1_det"), 223 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR2_RES, "bd72720_int_ocur2_res"), 224 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR2_DET, "bd72720_int_ocur2_det"), 225 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR3_RES, "bd72720_int_ocur3_res"), 226 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR3_DET, "bd72720_int_ocur3_det"), 227 DEFINE_RES_IRQ_NAMED(BD72720_INT_CC_MON1_DET, "bd72720_int_cc_mon1_det"), 228 DEFINE_RES_IRQ_NAMED(BD72720_INT_CC_MON2_DET, "bd72720_int_cc_mon2_det"), 229 DEFINE_RES_IRQ_NAMED(BD72720_INT_CC_MON3_DET, "bd72720_int_cc_mon3_det"), 230 }; 231 232 static const struct mfd_cell bd72720_mfd_cells[] = { 233 { .name = "bd72720-pmic", }, 234 { .name = "bd72720-gpio", }, 235 { .name = "bd72720-led", }, 236 { .name = "bd72720-clk", }, 237 { 238 .name = "bd72720-power", 239 .resources = bd72720_power_irqs, 240 .num_resources = ARRAY_SIZE(bd72720_power_irqs), 241 }, { 242 .name = "bd72720-rtc", 243 .resources = bd72720_rtc_irqs, 244 .num_resources = ARRAY_SIZE(bd72720_rtc_irqs), 245 }, { 246 .name = "gpio-keys", 247 .platform_data = &bd71828_powerkey_data, 248 .pdata_size = sizeof(bd71828_powerkey_data), 249 }, 250 }; 251 252 static const struct regmap_range bd71815_volatile_ranges[] = { 253 regmap_reg_range(BD71815_REG_SEC, BD71815_REG_YEAR), 254 regmap_reg_range(BD71815_REG_CONF, BD71815_REG_BAT_TEMP), 255 regmap_reg_range(BD71815_REG_VM_IBAT_U, BD71815_REG_CC_CTRL), 256 regmap_reg_range(BD71815_REG_CC_STAT, BD71815_REG_CC_CURCD_L), 257 regmap_reg_range(BD71815_REG_VM_BTMP_MON, BD71815_REG_VM_BTMP_MON), 258 regmap_reg_range(BD71815_REG_INT_STAT, BD71815_REG_INT_UPDATE), 259 regmap_reg_range(BD71815_REG_VM_VSYS_U, BD71815_REG_REX_CTRL_1), 260 regmap_reg_range(BD71815_REG_FULL_CCNTD_3, BD71815_REG_CCNTD_CHG_2), 261 }; 262 263 static const struct regmap_range bd71828_volatile_ranges[] = { 264 regmap_reg_range(BD71828_REG_PS_CTRL_1, BD71828_REG_PS_CTRL_1), 265 regmap_reg_range(BD71828_REG_PS_CTRL_3, BD71828_REG_PS_CTRL_3), 266 regmap_reg_range(BD71828_REG_RTC_SEC, BD71828_REG_RTC_YEAR), 267 /* 268 * For now make all charger registers volatile because many 269 * needs to be and because the charger block is not that 270 * performance critical. 271 */ 272 regmap_reg_range(BD71828_REG_CHG_STATE, BD71828_REG_CHG_FULL), 273 regmap_reg_range(BD71828_REG_INT_MAIN, BD71828_REG_IO_STAT), 274 }; 275 276 static const struct regmap_range bd72720_volatile_ranges_4b[] = { 277 regmap_reg_range(BD72720_REG_RESETSRC_1, BD72720_REG_RESETSRC_2), 278 regmap_reg_range(BD72720_REG_POWER_STATE, BD72720_REG_POWER_STATE), 279 /* The state indicator bit changes when new state is reached */ 280 regmap_reg_range(BD72720_REG_PS_CTRL_1, BD72720_REG_PS_CTRL_1), 281 regmap_reg_range(BD72720_REG_RCVNUM, BD72720_REG_RCVNUM), 282 regmap_reg_range(BD72720_REG_CONF, BD72720_REG_HALL_STAT), 283 regmap_reg_range(BD72720_REG_RTC_SEC, BD72720_REG_RTC_YEAR), 284 regmap_reg_range(BD72720_REG_INT_LVL1_STAT, BD72720_REG_INT_ETC2_SRC), 285 }; 286 287 static const struct regmap_range bd72720_precious_ranges_4b[] = { 288 regmap_reg_range(BD72720_REG_INT_LVL1_STAT, BD72720_REG_INT_ETC2_STAT), 289 }; 290 291 /* 292 * The BD72720 is an odd beast in that it contains two separate sets of 293 * registers, both starting from address 0x0. The twist is that these "pages" 294 * are behind different I2C slave addresses. Most of the registers are behind 295 * a slave address 0x4b, which will be used as the "main" address for this 296 * device. 297 * 298 * Most of the charger related registers are located behind slave address 0x4c. 299 * It is tempting to push the dealing with the charger registers and the extra 300 * 0x4c device in power-supply driver - but perhaps it's better for the sake of 301 * the cleaner re-use to deal with setting up all of the regmaps here. 302 * Furthermore, the LED stuff may need access to both of these devices. 303 * 304 * Instead of providing one of the regmaps to sub-devices in MFD platform data, 305 * we create one more 'wrapper regmap' with custom read/write operations. These 306 * custom accessors will select which of the 'real' regmaps to use, based on 307 * the register address. 308 * 309 * The register addresses are 8-bit, so we add offset 0x100 to the addresses 310 * behind the secondary slave 0x4c. The 'wrapper' regmap can then detect the 311 * correct slave address based on the register address and call regmap_write() 312 * and regmap_read() using correct 'real' regmap. This way the registers of 313 * both of the slaves can be accessed using one 'wrapper' regmap. 314 * 315 * NOTE: The added offsets mean that the defined addresses for slave 0x4c must 316 * be used through the 'wrapper' regmap because the offset must be stripped 317 * from the register addresses. The 0x4b can be accessed both indirectly using 318 * the 'wrapper' regmap, and directly using the 'real' regmap. 319 */ 320 #define BD72720_SECONDARY_I2C_SLAVE 0x4c 321 #define BD72720_SECONDARY_I2C_REG_OFFSET 0x100 322 323 struct bd72720_regmaps { 324 struct regmap *map1_4b; 325 struct regmap *map2_4c; 326 }; 327 328 /* Translate the slave 0x4c wrapper register address to a real one */ 329 #define BD72720_REG_UNWRAP(reg) ((reg) - BD72720_SECONDARY_I2C_REG_OFFSET) 330 331 /* Ranges given to 'real' 0x4c regmap must use unwrapped addresses. */ 332 #define BD72720_UNWRAP_REG_RANGE(startreg, endreg) \ 333 regmap_reg_range(BD72720_REG_UNWRAP(startreg), BD72720_REG_UNWRAP(endreg)) 334 335 static const struct regmap_range bd72720_volatile_ranges_4c[] = { 336 /* Status information */ 337 BD72720_UNWRAP_REG_RANGE(BD72720_REG_CHG_STATE, BD72720_REG_CHG_EN), 338 /* 339 * Under certain circumstances, write to some bits may be 340 * ignored 341 */ 342 BD72720_UNWRAP_REG_RANGE(BD72720_REG_CHG_CTRL, BD72720_REG_CHG_CTRL), 343 /* 344 * TODO: Ensure this is used to advertise state, not (only?) to 345 * control it. 346 */ 347 BD72720_UNWRAP_REG_RANGE(BD72720_REG_VSYS_STATE_STAT, BD72720_REG_VSYS_STATE_STAT), 348 /* Measured data */ 349 BD72720_UNWRAP_REG_RANGE(BD72720_REG_VM_VBAT_U, BD72720_REG_VM_VF_L), 350 /* Self clearing bits */ 351 BD72720_UNWRAP_REG_RANGE(BD72720_REG_VM_VSYS_SA_MINMAX_CTRL, 352 BD72720_REG_VM_VSYS_SA_MINMAX_CTRL), 353 /* Counters, self clearing bits */ 354 BD72720_UNWRAP_REG_RANGE(BD72720_REG_CC_CURCD_U, BD72720_REG_CC_CTRL), 355 /* Self clearing bits */ 356 BD72720_UNWRAP_REG_RANGE(BD72720_REG_CC_CCNTD_CTRL, BD72720_REG_CC_CCNTD_CTRL), 357 /* Self clearing bits */ 358 BD72720_UNWRAP_REG_RANGE(BD72720_REG_IMPCHK_CTRL, BD72720_REG_IMPCHK_CTRL), 359 }; 360 361 static const struct regmap_access_table bd71815_volatile_regs = { 362 .yes_ranges = &bd71815_volatile_ranges[0], 363 .n_yes_ranges = ARRAY_SIZE(bd71815_volatile_ranges), 364 }; 365 366 static const struct regmap_access_table bd71828_volatile_regs = { 367 .yes_ranges = &bd71828_volatile_ranges[0], 368 .n_yes_ranges = ARRAY_SIZE(bd71828_volatile_ranges), 369 }; 370 371 static const struct regmap_access_table bd72720_volatile_regs_4b = { 372 .yes_ranges = &bd72720_volatile_ranges_4b[0], 373 .n_yes_ranges = ARRAY_SIZE(bd72720_volatile_ranges_4b), 374 }; 375 376 static const struct regmap_access_table bd72720_precious_regs_4b = { 377 .yes_ranges = &bd72720_precious_ranges_4b[0], 378 .n_yes_ranges = ARRAY_SIZE(bd72720_precious_ranges_4b), 379 }; 380 381 static const struct regmap_access_table bd72720_volatile_regs_4c = { 382 .yes_ranges = &bd72720_volatile_ranges_4c[0], 383 .n_yes_ranges = ARRAY_SIZE(bd72720_volatile_ranges_4c), 384 }; 385 386 static const struct regmap_config bd71815_regmap = { 387 .reg_bits = 8, 388 .val_bits = 8, 389 .volatile_table = &bd71815_volatile_regs, 390 .max_register = BD71815_MAX_REGISTER - 1, 391 .cache_type = REGCACHE_MAPLE, 392 }; 393 394 static const struct regmap_config bd71828_regmap = { 395 .reg_bits = 8, 396 .val_bits = 8, 397 .volatile_table = &bd71828_volatile_regs, 398 .max_register = BD71828_MAX_REGISTER, 399 .cache_type = REGCACHE_MAPLE, 400 }; 401 402 static int regmap_write_wrapper(void *context, unsigned int reg, unsigned int val) 403 { 404 struct bd72720_regmaps *maps = context; 405 406 if (reg < BD72720_SECONDARY_I2C_REG_OFFSET) 407 return regmap_write(maps->map1_4b, reg, val); 408 409 reg = BD72720_REG_UNWRAP(reg); 410 411 return regmap_write(maps->map2_4c, reg, val); 412 } 413 414 static int regmap_read_wrapper(void *context, unsigned int reg, unsigned int *val) 415 { 416 struct bd72720_regmaps *maps = context; 417 418 if (reg < BD72720_SECONDARY_I2C_REG_OFFSET) 419 return regmap_read(maps->map1_4b, reg, val); 420 421 reg = BD72720_REG_UNWRAP(reg); 422 423 return regmap_read(maps->map2_4c, reg, val); 424 } 425 426 static const struct regmap_config bd72720_wrapper_map_config = { 427 .name = "wrap-map", 428 .reg_bits = 9, 429 .val_bits = 8, 430 .max_register = BD72720_REG_IMPCHK_CTRL, 431 /* 432 * We don't want to duplicate caches. It would be a bit faster to 433 * have the cache in this 'wrapper regmap', and not in the 'real 434 * regmaps' bd72720_regmap_4b and bd72720_regmap_4c below. This would 435 * require all the subdevices to use the wrapper-map in order to be 436 * able to benefit from the cache. 437 * Currently most of the sub-devices use only the same slave-address 438 * as this MFD driver. Now, because we don't add the offset to the 439 * registers belonging to this slave, those devices can use either the 440 * wrapper map, or the bd72720_regmap_4b directly. This means majority 441 * of our sub devices don't need to care which regmap they get using 442 * the dev_get_regmap(). This unifies the code between the BD72720 and 443 * those variants which don't have this 'multiple slave addresses' 444 * -hassle. 445 * So, for a small performance penalty, we simplify the code for the 446 * sub-devices by having the caches in the wrapped regmaps and not here. 447 */ 448 .cache_type = REGCACHE_NONE, 449 .reg_write = regmap_write_wrapper, 450 .reg_read = regmap_read_wrapper, 451 }; 452 453 static const struct regmap_config bd72720_regmap_4b = { 454 .reg_bits = 8, 455 .val_bits = 8, 456 .volatile_table = &bd72720_volatile_regs_4b, 457 .precious_table = &bd72720_precious_regs_4b, 458 .max_register = BD72720_REG_INT_ETC2_SRC, 459 .cache_type = REGCACHE_MAPLE, 460 }; 461 462 static const struct regmap_config bd72720_regmap_4c = { 463 .reg_bits = 8, 464 .val_bits = 8, 465 .volatile_table = &bd72720_volatile_regs_4c, 466 .max_register = BD72720_REG_UNWRAP(BD72720_REG_IMPCHK_CTRL), 467 .cache_type = REGCACHE_MAPLE, 468 }; 469 470 /* 471 * Mapping of main IRQ register bits to sub-IRQ register offsets so that we can 472 * access corect sub-IRQ registers based on bits that are set in main IRQ 473 * register. BD71815 and BD71828 have same sub-register-block offests, the 474 * BD72720 has a different one. 475 */ 476 477 static unsigned int bit0_offsets[] = {11}; /* RTC IRQ */ 478 static unsigned int bit1_offsets[] = {10}; /* TEMP IRQ */ 479 static unsigned int bit2_offsets[] = {6, 7, 8, 9}; /* BAT MON IRQ */ 480 static unsigned int bit3_offsets[] = {5}; /* BAT IRQ */ 481 static unsigned int bit4_offsets[] = {4}; /* CHG IRQ */ 482 static unsigned int bit5_offsets[] = {3}; /* VSYS IRQ */ 483 static unsigned int bit6_offsets[] = {1, 2}; /* DCIN IRQ */ 484 static unsigned int bit7_offsets[] = {0}; /* BUCK IRQ */ 485 486 static unsigned int bd72720_bit0_offsets[] = {0, 1}; /* PS1 and PS2 */ 487 static unsigned int bd72720_bit1_offsets[] = {2, 3}; /* DVS1 and DVS2 */ 488 static unsigned int bd72720_bit2_offsets[] = {4}; /* VBUS */ 489 static unsigned int bd72720_bit3_offsets[] = {5}; /* VSYS */ 490 static unsigned int bd72720_bit4_offsets[] = {6}; /* CHG */ 491 static unsigned int bd72720_bit5_offsets[] = {7, 8}; /* BAT1 and BAT2 */ 492 static unsigned int bd72720_bit6_offsets[] = {9}; /* IBAT */ 493 static unsigned int bd72720_bit7_offsets[] = {10, 11}; /* ETC1 and ETC2 */ 494 495 static const struct regmap_irq_sub_irq_map bd718xx_sub_irq_offsets[] = { 496 REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets), 497 REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets), 498 REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets), 499 REGMAP_IRQ_MAIN_REG_OFFSET(bit3_offsets), 500 REGMAP_IRQ_MAIN_REG_OFFSET(bit4_offsets), 501 REGMAP_IRQ_MAIN_REG_OFFSET(bit5_offsets), 502 REGMAP_IRQ_MAIN_REG_OFFSET(bit6_offsets), 503 REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets), 504 }; 505 506 static const struct regmap_irq_sub_irq_map bd72720_sub_irq_offsets[] = { 507 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit0_offsets), 508 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit1_offsets), 509 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit2_offsets), 510 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit3_offsets), 511 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit4_offsets), 512 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit5_offsets), 513 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit6_offsets), 514 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit7_offsets), 515 }; 516 517 static const struct regmap_irq bd71815_irqs[] = { 518 REGMAP_IRQ_REG(BD71815_INT_BUCK1_OCP, 0, BD71815_INT_BUCK1_OCP_MASK), 519 REGMAP_IRQ_REG(BD71815_INT_BUCK2_OCP, 0, BD71815_INT_BUCK2_OCP_MASK), 520 REGMAP_IRQ_REG(BD71815_INT_BUCK3_OCP, 0, BD71815_INT_BUCK3_OCP_MASK), 521 REGMAP_IRQ_REG(BD71815_INT_BUCK4_OCP, 0, BD71815_INT_BUCK4_OCP_MASK), 522 REGMAP_IRQ_REG(BD71815_INT_BUCK5_OCP, 0, BD71815_INT_BUCK5_OCP_MASK), 523 REGMAP_IRQ_REG(BD71815_INT_LED_OVP, 0, BD71815_INT_LED_OVP_MASK), 524 REGMAP_IRQ_REG(BD71815_INT_LED_OCP, 0, BD71815_INT_LED_OCP_MASK), 525 REGMAP_IRQ_REG(BD71815_INT_LED_SCP, 0, BD71815_INT_LED_SCP_MASK), 526 /* DCIN1 interrupts */ 527 REGMAP_IRQ_REG(BD71815_INT_DCIN_RMV, 1, BD71815_INT_DCIN_RMV_MASK), 528 REGMAP_IRQ_REG(BD71815_INT_CLPS_OUT, 1, BD71815_INT_CLPS_OUT_MASK), 529 REGMAP_IRQ_REG(BD71815_INT_CLPS_IN, 1, BD71815_INT_CLPS_IN_MASK), 530 REGMAP_IRQ_REG(BD71815_INT_DCIN_OVP_RES, 1, BD71815_INT_DCIN_OVP_RES_MASK), 531 REGMAP_IRQ_REG(BD71815_INT_DCIN_OVP_DET, 1, BD71815_INT_DCIN_OVP_DET_MASK), 532 /* DCIN2 interrupts */ 533 REGMAP_IRQ_REG(BD71815_INT_DCIN_MON_RES, 2, BD71815_INT_DCIN_MON_RES_MASK), 534 REGMAP_IRQ_REG(BD71815_INT_DCIN_MON_DET, 2, BD71815_INT_DCIN_MON_DET_MASK), 535 REGMAP_IRQ_REG(BD71815_INT_WDOG, 2, BD71815_INT_WDOG_MASK), 536 /* Vsys */ 537 REGMAP_IRQ_REG(BD71815_INT_VSYS_UV_RES, 3, BD71815_INT_VSYS_UV_RES_MASK), 538 REGMAP_IRQ_REG(BD71815_INT_VSYS_UV_DET, 3, BD71815_INT_VSYS_UV_DET_MASK), 539 REGMAP_IRQ_REG(BD71815_INT_VSYS_LOW_RES, 3, BD71815_INT_VSYS_LOW_RES_MASK), 540 REGMAP_IRQ_REG(BD71815_INT_VSYS_LOW_DET, 3, BD71815_INT_VSYS_LOW_DET_MASK), 541 REGMAP_IRQ_REG(BD71815_INT_VSYS_MON_RES, 3, BD71815_INT_VSYS_MON_RES_MASK), 542 REGMAP_IRQ_REG(BD71815_INT_VSYS_MON_DET, 3, BD71815_INT_VSYS_MON_DET_MASK), 543 /* Charger */ 544 REGMAP_IRQ_REG(BD71815_INT_CHG_WDG_TEMP, 4, BD71815_INT_CHG_WDG_TEMP_MASK), 545 REGMAP_IRQ_REG(BD71815_INT_CHG_WDG_TIME, 4, BD71815_INT_CHG_WDG_TIME_MASK), 546 REGMAP_IRQ_REG(BD71815_INT_CHG_RECHARGE_RES, 4, BD71815_INT_CHG_RECHARGE_RES_MASK), 547 REGMAP_IRQ_REG(BD71815_INT_CHG_RECHARGE_DET, 4, BD71815_INT_CHG_RECHARGE_DET_MASK), 548 REGMAP_IRQ_REG(BD71815_INT_CHG_RANGED_TEMP_TRANSITION, 4, 549 BD71815_INT_CHG_RANGED_TEMP_TRANSITION_MASK), 550 REGMAP_IRQ_REG(BD71815_INT_CHG_STATE_TRANSITION, 4, BD71815_INT_CHG_STATE_TRANSITION_MASK), 551 /* Battery */ 552 REGMAP_IRQ_REG(BD71815_INT_BAT_TEMP_NORMAL, 5, BD71815_INT_BAT_TEMP_NORMAL_MASK), 553 REGMAP_IRQ_REG(BD71815_INT_BAT_TEMP_ERANGE, 5, BD71815_INT_BAT_TEMP_ERANGE_MASK), 554 REGMAP_IRQ_REG(BD71815_INT_BAT_REMOVED, 5, BD71815_INT_BAT_REMOVED_MASK), 555 REGMAP_IRQ_REG(BD71815_INT_BAT_DETECTED, 5, BD71815_INT_BAT_DETECTED_MASK), 556 REGMAP_IRQ_REG(BD71815_INT_THERM_REMOVED, 5, BD71815_INT_THERM_REMOVED_MASK), 557 REGMAP_IRQ_REG(BD71815_INT_THERM_DETECTED, 5, BD71815_INT_THERM_DETECTED_MASK), 558 /* Battery Mon 1 */ 559 REGMAP_IRQ_REG(BD71815_INT_BAT_DEAD, 6, BD71815_INT_BAT_DEAD_MASK), 560 REGMAP_IRQ_REG(BD71815_INT_BAT_SHORTC_RES, 6, BD71815_INT_BAT_SHORTC_RES_MASK), 561 REGMAP_IRQ_REG(BD71815_INT_BAT_SHORTC_DET, 6, BD71815_INT_BAT_SHORTC_DET_MASK), 562 REGMAP_IRQ_REG(BD71815_INT_BAT_LOW_VOLT_RES, 6, BD71815_INT_BAT_LOW_VOLT_RES_MASK), 563 REGMAP_IRQ_REG(BD71815_INT_BAT_LOW_VOLT_DET, 6, BD71815_INT_BAT_LOW_VOLT_DET_MASK), 564 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_VOLT_RES, 6, BD71815_INT_BAT_OVER_VOLT_RES_MASK), 565 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_VOLT_DET, 6, BD71815_INT_BAT_OVER_VOLT_DET_MASK), 566 /* Battery Mon 2 */ 567 REGMAP_IRQ_REG(BD71815_INT_BAT_MON_RES, 7, BD71815_INT_BAT_MON_RES_MASK), 568 REGMAP_IRQ_REG(BD71815_INT_BAT_MON_DET, 7, BD71815_INT_BAT_MON_DET_MASK), 569 /* Battery Mon 3 (Coulomb counter) */ 570 REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON1, 8, BD71815_INT_BAT_CC_MON1_MASK), 571 REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON2, 8, BD71815_INT_BAT_CC_MON2_MASK), 572 REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON3, 8, BD71815_INT_BAT_CC_MON3_MASK), 573 /* Battery Mon 4 */ 574 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_1_RES, 9, BD71815_INT_BAT_OVER_CURR_1_RES_MASK), 575 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_1_DET, 9, BD71815_INT_BAT_OVER_CURR_1_DET_MASK), 576 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_2_RES, 9, BD71815_INT_BAT_OVER_CURR_2_RES_MASK), 577 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_2_DET, 9, BD71815_INT_BAT_OVER_CURR_2_DET_MASK), 578 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_3_RES, 9, BD71815_INT_BAT_OVER_CURR_3_RES_MASK), 579 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_3_DET, 9, BD71815_INT_BAT_OVER_CURR_3_DET_MASK), 580 /* Temperature */ 581 REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_LOW_RES, 10, BD71815_INT_TEMP_BAT_LOW_RES_MASK), 582 REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_LOW_DET, 10, BD71815_INT_TEMP_BAT_LOW_DET_MASK), 583 REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_HI_RES, 10, BD71815_INT_TEMP_BAT_HI_RES_MASK), 584 REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_HI_DET, 10, BD71815_INT_TEMP_BAT_HI_DET_MASK), 585 REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_125_RES, 10, 586 BD71815_INT_TEMP_CHIP_OVER_125_RES_MASK), 587 REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_125_DET, 10, 588 BD71815_INT_TEMP_CHIP_OVER_125_DET_MASK), 589 REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_VF_RES, 10, 590 BD71815_INT_TEMP_CHIP_OVER_VF_RES_MASK), 591 REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_VF_DET, 10, 592 BD71815_INT_TEMP_CHIP_OVER_VF_DET_MASK), 593 /* RTC Alarm */ 594 REGMAP_IRQ_REG(BD71815_INT_RTC0, 11, BD71815_INT_RTC0_MASK), 595 REGMAP_IRQ_REG(BD71815_INT_RTC1, 11, BD71815_INT_RTC1_MASK), 596 REGMAP_IRQ_REG(BD71815_INT_RTC2, 11, BD71815_INT_RTC2_MASK), 597 }; 598 599 static const struct regmap_irq bd71828_irqs[] = { 600 REGMAP_IRQ_REG(BD71828_INT_BUCK1_OCP, 0, BD71828_INT_BUCK1_OCP_MASK), 601 REGMAP_IRQ_REG(BD71828_INT_BUCK2_OCP, 0, BD71828_INT_BUCK2_OCP_MASK), 602 REGMAP_IRQ_REG(BD71828_INT_BUCK3_OCP, 0, BD71828_INT_BUCK3_OCP_MASK), 603 REGMAP_IRQ_REG(BD71828_INT_BUCK4_OCP, 0, BD71828_INT_BUCK4_OCP_MASK), 604 REGMAP_IRQ_REG(BD71828_INT_BUCK5_OCP, 0, BD71828_INT_BUCK5_OCP_MASK), 605 REGMAP_IRQ_REG(BD71828_INT_BUCK6_OCP, 0, BD71828_INT_BUCK6_OCP_MASK), 606 REGMAP_IRQ_REG(BD71828_INT_BUCK7_OCP, 0, BD71828_INT_BUCK7_OCP_MASK), 607 REGMAP_IRQ_REG(BD71828_INT_PGFAULT, 0, BD71828_INT_PGFAULT_MASK), 608 /* DCIN1 interrupts */ 609 REGMAP_IRQ_REG(BD71828_INT_DCIN_DET, 1, BD71828_INT_DCIN_DET_MASK), 610 REGMAP_IRQ_REG(BD71828_INT_DCIN_RMV, 1, BD71828_INT_DCIN_RMV_MASK), 611 REGMAP_IRQ_REG(BD71828_INT_CLPS_OUT, 1, BD71828_INT_CLPS_OUT_MASK), 612 REGMAP_IRQ_REG(BD71828_INT_CLPS_IN, 1, BD71828_INT_CLPS_IN_MASK), 613 /* DCIN2 interrupts */ 614 REGMAP_IRQ_REG(BD71828_INT_DCIN_MON_RES, 2, BD71828_INT_DCIN_MON_RES_MASK), 615 REGMAP_IRQ_REG(BD71828_INT_DCIN_MON_DET, 2, BD71828_INT_DCIN_MON_DET_MASK), 616 REGMAP_IRQ_REG(BD71828_INT_LONGPUSH, 2, BD71828_INT_LONGPUSH_MASK), 617 REGMAP_IRQ_REG(BD71828_INT_MIDPUSH, 2, BD71828_INT_MIDPUSH_MASK), 618 REGMAP_IRQ_REG(BD71828_INT_SHORTPUSH, 2, BD71828_INT_SHORTPUSH_MASK), 619 REGMAP_IRQ_REG(BD71828_INT_PUSH, 2, BD71828_INT_PUSH_MASK), 620 REGMAP_IRQ_REG(BD71828_INT_WDOG, 2, BD71828_INT_WDOG_MASK), 621 REGMAP_IRQ_REG(BD71828_INT_SWRESET, 2, BD71828_INT_SWRESET_MASK), 622 /* Vsys */ 623 REGMAP_IRQ_REG(BD71828_INT_VSYS_UV_RES, 3, BD71828_INT_VSYS_UV_RES_MASK), 624 REGMAP_IRQ_REG(BD71828_INT_VSYS_UV_DET, 3, BD71828_INT_VSYS_UV_DET_MASK), 625 REGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_RES, 3, BD71828_INT_VSYS_LOW_RES_MASK), 626 REGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_DET, 3, BD71828_INT_VSYS_LOW_DET_MASK), 627 REGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_IN, 3, BD71828_INT_VSYS_HALL_IN_MASK), 628 REGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_TOGGLE, 3, BD71828_INT_VSYS_HALL_TOGGLE_MASK), 629 REGMAP_IRQ_REG(BD71828_INT_VSYS_MON_RES, 3, BD71828_INT_VSYS_MON_RES_MASK), 630 REGMAP_IRQ_REG(BD71828_INT_VSYS_MON_DET, 3, BD71828_INT_VSYS_MON_DET_MASK), 631 /* Charger */ 632 REGMAP_IRQ_REG(BD71828_INT_CHG_DCIN_ILIM, 4, BD71828_INT_CHG_DCIN_ILIM_MASK), 633 REGMAP_IRQ_REG(BD71828_INT_CHG_TOPOFF_TO_DONE, 4, BD71828_INT_CHG_TOPOFF_TO_DONE_MASK), 634 REGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TEMP, 4, BD71828_INT_CHG_WDG_TEMP_MASK), 635 REGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TIME, 4, BD71828_INT_CHG_WDG_TIME_MASK), 636 REGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_RES, 4, BD71828_INT_CHG_RECHARGE_RES_MASK), 637 REGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_DET, 4, BD71828_INT_CHG_RECHARGE_DET_MASK), 638 REGMAP_IRQ_REG(BD71828_INT_CHG_RANGED_TEMP_TRANSITION, 4, 639 BD71828_INT_CHG_RANGED_TEMP_TRANSITION_MASK), 640 REGMAP_IRQ_REG(BD71828_INT_CHG_STATE_TRANSITION, 4, BD71828_INT_CHG_STATE_TRANSITION_MASK), 641 /* Battery */ 642 REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_NORMAL, 5, BD71828_INT_BAT_TEMP_NORMAL_MASK), 643 REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_ERANGE, 5, BD71828_INT_BAT_TEMP_ERANGE_MASK), 644 REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_WARN, 5, BD71828_INT_BAT_TEMP_WARN_MASK), 645 REGMAP_IRQ_REG(BD71828_INT_BAT_REMOVED, 5, BD71828_INT_BAT_REMOVED_MASK), 646 REGMAP_IRQ_REG(BD71828_INT_BAT_DETECTED, 5, BD71828_INT_BAT_DETECTED_MASK), 647 REGMAP_IRQ_REG(BD71828_INT_THERM_REMOVED, 5, BD71828_INT_THERM_REMOVED_MASK), 648 REGMAP_IRQ_REG(BD71828_INT_THERM_DETECTED, 5, BD71828_INT_THERM_DETECTED_MASK), 649 /* Battery Mon 1 */ 650 REGMAP_IRQ_REG(BD71828_INT_BAT_DEAD, 6, BD71828_INT_BAT_DEAD_MASK), 651 REGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_RES, 6, BD71828_INT_BAT_SHORTC_RES_MASK), 652 REGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_DET, 6, BD71828_INT_BAT_SHORTC_DET_MASK), 653 REGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_RES, 6, BD71828_INT_BAT_LOW_VOLT_RES_MASK), 654 REGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_DET, 6, BD71828_INT_BAT_LOW_VOLT_DET_MASK), 655 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_RES, 6, BD71828_INT_BAT_OVER_VOLT_RES_MASK), 656 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_DET, 6, BD71828_INT_BAT_OVER_VOLT_DET_MASK), 657 /* Battery Mon 2 */ 658 REGMAP_IRQ_REG(BD71828_INT_BAT_MON_RES, 7, BD71828_INT_BAT_MON_RES_MASK), 659 REGMAP_IRQ_REG(BD71828_INT_BAT_MON_DET, 7, BD71828_INT_BAT_MON_DET_MASK), 660 /* Battery Mon 3 (Coulomb counter) */ 661 REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON1, 8, BD71828_INT_BAT_CC_MON1_MASK), 662 REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON2, 8, BD71828_INT_BAT_CC_MON2_MASK), 663 REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON3, 8, BD71828_INT_BAT_CC_MON3_MASK), 664 /* Battery Mon 4 */ 665 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_RES, 9, BD71828_INT_BAT_OVER_CURR_1_RES_MASK), 666 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_DET, 9, BD71828_INT_BAT_OVER_CURR_1_DET_MASK), 667 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_RES, 9, BD71828_INT_BAT_OVER_CURR_2_RES_MASK), 668 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_DET, 9, BD71828_INT_BAT_OVER_CURR_2_DET_MASK), 669 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_RES, 9, BD71828_INT_BAT_OVER_CURR_3_RES_MASK), 670 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_DET, 9, BD71828_INT_BAT_OVER_CURR_3_DET_MASK), 671 /* Temperature */ 672 REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_RES, 10, BD71828_INT_TEMP_BAT_LOW_RES_MASK), 673 REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_DET, 10, BD71828_INT_TEMP_BAT_LOW_DET_MASK), 674 REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_RES, 10, BD71828_INT_TEMP_BAT_HI_RES_MASK), 675 REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_DET, 10, BD71828_INT_TEMP_BAT_HI_DET_MASK), 676 REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_125_RES, 10, 677 BD71828_INT_TEMP_CHIP_OVER_125_RES_MASK), 678 REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_125_DET, 10, 679 BD71828_INT_TEMP_CHIP_OVER_125_DET_MASK), 680 REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_VF_DET, 10, 681 BD71828_INT_TEMP_CHIP_OVER_VF_DET_MASK), 682 REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_VF_RES, 10, 683 BD71828_INT_TEMP_CHIP_OVER_VF_RES_MASK), 684 /* RTC Alarm */ 685 REGMAP_IRQ_REG(BD71828_INT_RTC0, 11, BD71828_INT_RTC0_MASK), 686 REGMAP_IRQ_REG(BD71828_INT_RTC1, 11, BD71828_INT_RTC1_MASK), 687 REGMAP_IRQ_REG(BD71828_INT_RTC2, 11, BD71828_INT_RTC2_MASK), 688 }; 689 690 static const struct regmap_irq bd72720_irqs[] = { 691 REGMAP_IRQ_REG(BD72720_INT_LONGPUSH, 0, BD72720_INT_LONGPUSH_MASK), 692 REGMAP_IRQ_REG(BD72720_INT_MIDPUSH, 0, BD72720_INT_MIDPUSH_MASK), 693 REGMAP_IRQ_REG(BD72720_INT_SHORTPUSH, 0, BD72720_INT_SHORTPUSH_MASK), 694 REGMAP_IRQ_REG(BD72720_INT_PUSH, 0, BD72720_INT_PUSH_MASK), 695 REGMAP_IRQ_REG(BD72720_INT_HALL_DET, 0, BD72720_INT_HALL_DET_MASK), 696 REGMAP_IRQ_REG(BD72720_INT_HALL_TGL, 0, BD72720_INT_HALL_TGL_MASK), 697 REGMAP_IRQ_REG(BD72720_INT_WDOG, 0, BD72720_INT_WDOG_MASK), 698 REGMAP_IRQ_REG(BD72720_INT_SWRESET, 0, BD72720_INT_SWRESET_MASK), 699 REGMAP_IRQ_REG(BD72720_INT_SEQ_DONE, 1, BD72720_INT_SEQ_DONE_MASK), 700 REGMAP_IRQ_REG(BD72720_INT_PGFAULT, 1, BD72720_INT_PGFAULT_MASK), 701 REGMAP_IRQ_REG(BD72720_INT_BUCK1_DVS, 2, BD72720_INT_BUCK1_DVS_MASK), 702 REGMAP_IRQ_REG(BD72720_INT_BUCK2_DVS, 2, BD72720_INT_BUCK2_DVS_MASK), 703 REGMAP_IRQ_REG(BD72720_INT_BUCK3_DVS, 2, BD72720_INT_BUCK3_DVS_MASK), 704 REGMAP_IRQ_REG(BD72720_INT_BUCK4_DVS, 2, BD72720_INT_BUCK4_DVS_MASK), 705 REGMAP_IRQ_REG(BD72720_INT_BUCK5_DVS, 2, BD72720_INT_BUCK5_DVS_MASK), 706 REGMAP_IRQ_REG(BD72720_INT_BUCK6_DVS, 2, BD72720_INT_BUCK6_DVS_MASK), 707 REGMAP_IRQ_REG(BD72720_INT_BUCK7_DVS, 2, BD72720_INT_BUCK7_DVS_MASK), 708 REGMAP_IRQ_REG(BD72720_INT_BUCK8_DVS, 2, BD72720_INT_BUCK8_DVS_MASK), 709 REGMAP_IRQ_REG(BD72720_INT_BUCK9_DVS, 3, BD72720_INT_BUCK9_DVS_MASK), 710 REGMAP_IRQ_REG(BD72720_INT_BUCK10_DVS, 3, BD72720_INT_BUCK10_DVS_MASK), 711 REGMAP_IRQ_REG(BD72720_INT_LDO1_DVS, 3, BD72720_INT_LDO1_DVS_MASK), 712 REGMAP_IRQ_REG(BD72720_INT_LDO2_DVS, 3, BD72720_INT_LDO2_DVS_MASK), 713 REGMAP_IRQ_REG(BD72720_INT_LDO3_DVS, 3, BD72720_INT_LDO3_DVS_MASK), 714 REGMAP_IRQ_REG(BD72720_INT_LDO4_DVS, 3, BD72720_INT_LDO4_DVS_MASK), 715 716 REGMAP_IRQ_REG(BD72720_INT_VBUS_RMV, 4, BD72720_INT_VBUS_RMV_MASK), 717 REGMAP_IRQ_REG(BD72720_INT_VBUS_DET, 4, BD72720_INT_VBUS_DET_MASK), 718 REGMAP_IRQ_REG(BD72720_INT_VBUS_MON_RES, 4, BD72720_INT_VBUS_MON_RES_MASK), 719 REGMAP_IRQ_REG(BD72720_INT_VBUS_MON_DET, 4, BD72720_INT_VBUS_MON_DET_MASK), 720 REGMAP_IRQ_REG(BD72720_INT_VSYS_MON_RES, 5, BD72720_INT_VSYS_MON_RES_MASK), 721 REGMAP_IRQ_REG(BD72720_INT_VSYS_MON_DET, 5, BD72720_INT_VSYS_MON_DET_MASK), 722 REGMAP_IRQ_REG(BD72720_INT_VSYS_UV_RES, 5, BD72720_INT_VSYS_UV_RES_MASK), 723 REGMAP_IRQ_REG(BD72720_INT_VSYS_UV_DET, 5, BD72720_INT_VSYS_UV_DET_MASK), 724 REGMAP_IRQ_REG(BD72720_INT_VSYS_LO_RES, 5, BD72720_INT_VSYS_LO_RES_MASK), 725 REGMAP_IRQ_REG(BD72720_INT_VSYS_LO_DET, 5, BD72720_INT_VSYS_LO_DET_MASK), 726 REGMAP_IRQ_REG(BD72720_INT_VSYS_OV_RES, 5, BD72720_INT_VSYS_OV_RES_MASK), 727 REGMAP_IRQ_REG(BD72720_INT_VSYS_OV_DET, 5, BD72720_INT_VSYS_OV_DET_MASK), 728 REGMAP_IRQ_REG(BD72720_INT_BAT_ILIM, 6, BD72720_INT_BAT_ILIM_MASK), 729 REGMAP_IRQ_REG(BD72720_INT_CHG_DONE, 6, BD72720_INT_CHG_DONE_MASK), 730 REGMAP_IRQ_REG(BD72720_INT_EXTEMP_TOUT, 6, BD72720_INT_EXTEMP_TOUT_MASK), 731 REGMAP_IRQ_REG(BD72720_INT_CHG_WDT_EXP, 6, BD72720_INT_CHG_WDT_EXP_MASK), 732 REGMAP_IRQ_REG(BD72720_INT_BAT_MNT_OUT, 6, BD72720_INT_BAT_MNT_OUT_MASK), 733 REGMAP_IRQ_REG(BD72720_INT_BAT_MNT_IN, 6, BD72720_INT_BAT_MNT_IN_MASK), 734 REGMAP_IRQ_REG(BD72720_INT_CHG_TRNS, 6, BD72720_INT_CHG_TRNS_MASK), 735 736 REGMAP_IRQ_REG(BD72720_INT_VBAT_MON_RES, 7, BD72720_INT_VBAT_MON_RES_MASK), 737 REGMAP_IRQ_REG(BD72720_INT_VBAT_MON_DET, 7, BD72720_INT_VBAT_MON_DET_MASK), 738 REGMAP_IRQ_REG(BD72720_INT_VBAT_SHT_RES, 7, BD72720_INT_VBAT_SHT_RES_MASK), 739 REGMAP_IRQ_REG(BD72720_INT_VBAT_SHT_DET, 7, BD72720_INT_VBAT_SHT_DET_MASK), 740 REGMAP_IRQ_REG(BD72720_INT_VBAT_LO_RES, 7, BD72720_INT_VBAT_LO_RES_MASK), 741 REGMAP_IRQ_REG(BD72720_INT_VBAT_LO_DET, 7, BD72720_INT_VBAT_LO_DET_MASK), 742 REGMAP_IRQ_REG(BD72720_INT_VBAT_OV_RES, 7, BD72720_INT_VBAT_OV_RES_MASK), 743 REGMAP_IRQ_REG(BD72720_INT_VBAT_OV_DET, 7, BD72720_INT_VBAT_OV_DET_MASK), 744 REGMAP_IRQ_REG(BD72720_INT_BAT_RMV, 8, BD72720_INT_BAT_RMV_MASK), 745 REGMAP_IRQ_REG(BD72720_INT_BAT_DET, 8, BD72720_INT_BAT_DET_MASK), 746 REGMAP_IRQ_REG(BD72720_INT_DBAT_DET, 8, BD72720_INT_DBAT_DET_MASK), 747 REGMAP_IRQ_REG(BD72720_INT_BAT_TEMP_TRNS, 8, BD72720_INT_BAT_TEMP_TRNS_MASK), 748 REGMAP_IRQ_REG(BD72720_INT_LOBTMP_RES, 8, BD72720_INT_LOBTMP_RES_MASK), 749 REGMAP_IRQ_REG(BD72720_INT_LOBTMP_DET, 8, BD72720_INT_LOBTMP_DET_MASK), 750 REGMAP_IRQ_REG(BD72720_INT_OVBTMP_RES, 8, BD72720_INT_OVBTMP_RES_MASK), 751 REGMAP_IRQ_REG(BD72720_INT_OVBTMP_DET, 8, BD72720_INT_OVBTMP_DET_MASK), 752 REGMAP_IRQ_REG(BD72720_INT_OCUR1_RES, 9, BD72720_INT_OCUR1_RES_MASK), 753 REGMAP_IRQ_REG(BD72720_INT_OCUR1_DET, 9, BD72720_INT_OCUR1_DET_MASK), 754 REGMAP_IRQ_REG(BD72720_INT_OCUR2_RES, 9, BD72720_INT_OCUR2_RES_MASK), 755 REGMAP_IRQ_REG(BD72720_INT_OCUR2_DET, 9, BD72720_INT_OCUR2_DET_MASK), 756 REGMAP_IRQ_REG(BD72720_INT_OCUR3_RES, 9, BD72720_INT_OCUR3_RES_MASK), 757 REGMAP_IRQ_REG(BD72720_INT_OCUR3_DET, 9, BD72720_INT_OCUR3_DET_MASK), 758 REGMAP_IRQ_REG(BD72720_INT_CC_MON1_DET, 10, BD72720_INT_CC_MON1_DET_MASK), 759 REGMAP_IRQ_REG(BD72720_INT_CC_MON2_DET, 10, BD72720_INT_CC_MON2_DET_MASK), 760 REGMAP_IRQ_REG(BD72720_INT_CC_MON3_DET, 10, BD72720_INT_CC_MON3_DET_MASK), 761 /* 762 * The GPIO1_IN and GPIO2_IN IRQs are generated from the PMIC's GPIO1 and GPIO2 763 * pins. Eg, they may be wired to other devices which can then use the PMIC as 764 * an interrupt controller. The GPIO1 and GPIO2 can have the IRQ type 765 * specified. All of the types (falling, rising, and both edges as well as low 766 * and high levels) are supported. 767 */ 768 BD72720_TYPED_IRQ_REG(BD72720_INT_GPIO1_IN, 10, BD72720_INT_GPIO1_IN_MASK, 0), 769 BD72720_TYPED_IRQ_REG(BD72720_INT_GPIO2_IN, 10, BD72720_INT_GPIO2_IN_MASK, 1), 770 REGMAP_IRQ_REG(BD72720_INT_VF125_RES, 11, BD72720_INT_VF125_RES_MASK), 771 REGMAP_IRQ_REG(BD72720_INT_VF125_DET, 11, BD72720_INT_VF125_DET_MASK), 772 REGMAP_IRQ_REG(BD72720_INT_VF_RES, 11, BD72720_INT_VF_RES_MASK), 773 REGMAP_IRQ_REG(BD72720_INT_VF_DET, 11, BD72720_INT_VF_DET_MASK), 774 REGMAP_IRQ_REG(BD72720_INT_RTC0, 11, BD72720_INT_RTC0_MASK), 775 REGMAP_IRQ_REG(BD72720_INT_RTC1, 11, BD72720_INT_RTC1_MASK), 776 REGMAP_IRQ_REG(BD72720_INT_RTC2, 11, BD72720_INT_RTC2_MASK), 777 }; 778 779 static int bd72720_set_type_config(unsigned int **buf, unsigned int type, 780 const struct regmap_irq *irq_data, 781 int idx, void *irq_drv_data) 782 { 783 const struct regmap_irq_type *t = &irq_data->type; 784 785 /* 786 * The regmap IRQ ecpects IRQ_TYPE_EDGE_BOTH to be written to register 787 * as logical OR of the type_falling_val and type_rising_val. This is 788 * not how the BD72720 implements this configuration, hence we need 789 * to handle this specific case separately. 790 */ 791 if (type == IRQ_TYPE_EDGE_BOTH) { 792 buf[0][idx] &= ~t->type_reg_mask; 793 buf[0][idx] |= BD72720_GPIO_IRQ_TYPE_BOTH; 794 795 return 0; 796 } 797 798 return regmap_irq_set_type_config_simple(buf, type, irq_data, idx, irq_drv_data); 799 } 800 801 static const struct regmap_irq_chip bd71828_irq_chip = { 802 .name = "bd71828_irq", 803 .main_status = BD71828_REG_INT_MAIN, 804 .irqs = &bd71828_irqs[0], 805 .num_irqs = ARRAY_SIZE(bd71828_irqs), 806 .status_base = BD71828_REG_INT_BUCK, 807 .unmask_base = BD71828_REG_INT_MASK_BUCK, 808 .ack_base = BD71828_REG_INT_BUCK, 809 .init_ack_masked = true, 810 .num_regs = 12, 811 .num_main_regs = 1, 812 .sub_reg_offsets = &bd718xx_sub_irq_offsets[0], 813 .num_main_status_bits = 8, 814 .irq_reg_stride = 1, 815 }; 816 817 static const struct regmap_irq_chip bd71815_irq_chip = { 818 .name = "bd71815_irq", 819 .main_status = BD71815_REG_INT_STAT, 820 .irqs = &bd71815_irqs[0], 821 .num_irqs = ARRAY_SIZE(bd71815_irqs), 822 .status_base = BD71815_REG_INT_STAT_01, 823 .unmask_base = BD71815_REG_INT_EN_01, 824 .ack_base = BD71815_REG_INT_STAT_01, 825 .init_ack_masked = true, 826 .num_regs = 12, 827 .num_main_regs = 1, 828 .sub_reg_offsets = &bd718xx_sub_irq_offsets[0], 829 .num_main_status_bits = 8, 830 .irq_reg_stride = 1, 831 }; 832 833 static const unsigned int bd72720_irq_type_base[] = { BD72720_REG_GPIO1_CTRL }; 834 835 static const struct regmap_irq_chip bd72720_irq_chip = { 836 .name = "bd72720_irq", 837 .main_status = BD72720_REG_INT_LVL1_STAT, 838 .irqs = &bd72720_irqs[0], 839 .num_irqs = ARRAY_SIZE(bd72720_irqs), 840 .status_base = BD72720_REG_INT_PS1_STAT, 841 .unmask_base = BD72720_REG_INT_PS1_EN, 842 .config_base = &bd72720_irq_type_base[0], 843 .num_config_bases = 1, 844 .num_config_regs = 2, 845 .set_type_config = bd72720_set_type_config, 846 .ack_base = BD72720_REG_INT_PS1_STAT, 847 .init_ack_masked = true, 848 .num_regs = 12, 849 .num_main_regs = 1, 850 .sub_reg_offsets = &bd72720_sub_irq_offsets[0], 851 .num_main_status_bits = 8, 852 .irq_reg_stride = 1, 853 }; 854 855 static int set_clk_mode(struct device *dev, struct regmap *regmap, 856 int clkmode_reg) 857 { 858 int ret; 859 unsigned int open_drain; 860 861 ret = of_property_read_u32(dev->of_node, "rohm,clkout-open-drain", &open_drain); 862 if (ret) { 863 if (ret == -EINVAL) 864 return 0; 865 return ret; 866 } 867 if (open_drain > 1) { 868 dev_err(dev, "bad clk32kout mode configuration"); 869 return -EINVAL; 870 } 871 872 if (open_drain) 873 return regmap_update_bits(regmap, clkmode_reg, OUT32K_MODE, 874 OUT32K_MODE_OPEN_DRAIN); 875 876 return regmap_update_bits(regmap, clkmode_reg, OUT32K_MODE, 877 OUT32K_MODE_CMOS); 878 } 879 880 static struct i2c_client *bd71828_dev; 881 static void bd71828_power_off(void) 882 { 883 while (true) { 884 s32 val; 885 886 /* We are not allowed to sleep, so do not use regmap involving mutexes here. */ 887 val = i2c_smbus_read_byte_data(bd71828_dev, BD71828_REG_PS_CTRL_1); 888 if (val >= 0) 889 i2c_smbus_write_byte_data(bd71828_dev, 890 BD71828_REG_PS_CTRL_1, 891 BD71828_MASK_STATE_HBNT | (u8)val); 892 mdelay(500); 893 } 894 } 895 896 static void bd71828_remove_poweroff(void *data) 897 { 898 pm_power_off = NULL; 899 } 900 901 static struct regmap *bd72720_do_regmaps(struct i2c_client *i2c) 902 { 903 struct bd72720_regmaps *maps; 904 struct i2c_client *secondary_i2c; 905 906 secondary_i2c = devm_i2c_new_dummy_device(&i2c->dev, i2c->adapter, 907 BD72720_SECONDARY_I2C_SLAVE); 908 if (IS_ERR(secondary_i2c)) { 909 dev_err_probe(&i2c->dev, PTR_ERR(secondary_i2c), "Failed to get secondary I2C\n"); 910 911 return ERR_CAST(secondary_i2c); 912 } 913 914 maps = devm_kzalloc(&i2c->dev, sizeof(*maps), GFP_KERNEL); 915 if (!maps) 916 return ERR_PTR(-ENOMEM); 917 918 maps->map1_4b = devm_regmap_init_i2c(i2c, &bd72720_regmap_4b); 919 if (IS_ERR(maps->map1_4b)) 920 return maps->map1_4b; 921 922 maps->map2_4c = devm_regmap_init_i2c(secondary_i2c, &bd72720_regmap_4c); 923 if (IS_ERR(maps->map2_4c)) 924 return maps->map2_4c; 925 926 return devm_regmap_init(&i2c->dev, NULL, maps, &bd72720_wrapper_map_config); 927 } 928 929 static int bd71828_i2c_probe(struct i2c_client *i2c) 930 { 931 struct regmap_irq_chip_data *irq_data; 932 int ret; 933 struct regmap *regmap = NULL; 934 const struct regmap_config *regmap_config; 935 const struct regmap_irq_chip *irqchip; 936 unsigned int chip_type; 937 const struct mfd_cell *mfd; 938 int cells; 939 int button_irq; 940 int clkmode_reg; 941 int main_lvl_mask_reg = 0, main_lvl_val = 0; 942 943 if (!i2c->irq) { 944 dev_err(&i2c->dev, "No IRQ configured\n"); 945 return -EINVAL; 946 } 947 948 chip_type = (unsigned int)(uintptr_t) 949 of_device_get_match_data(&i2c->dev); 950 switch (chip_type) { 951 case ROHM_CHIP_TYPE_BD71828: 952 mfd = bd71828_mfd_cells; 953 cells = ARRAY_SIZE(bd71828_mfd_cells); 954 regmap_config = &bd71828_regmap; 955 irqchip = &bd71828_irq_chip; 956 clkmode_reg = BD71828_REG_OUT32K; 957 button_irq = BD71828_INT_SHORTPUSH; 958 break; 959 case ROHM_CHIP_TYPE_BD71815: 960 mfd = bd71815_mfd_cells; 961 cells = ARRAY_SIZE(bd71815_mfd_cells); 962 regmap_config = &bd71815_regmap; 963 irqchip = &bd71815_irq_chip; 964 clkmode_reg = BD71815_REG_OUT32K; 965 /* 966 * If BD71817 support is needed we should be able to handle it 967 * with proper DT configs + BD71815 drivers + power-button. 968 * BD71815 data-sheet does not list the power-button IRQ so we 969 * don't use it. 970 */ 971 button_irq = 0; 972 break; 973 case ROHM_CHIP_TYPE_BD72720: 974 { 975 mfd = bd72720_mfd_cells; 976 cells = ARRAY_SIZE(bd72720_mfd_cells); 977 978 regmap = bd72720_do_regmaps(i2c); 979 if (IS_ERR(regmap)) 980 return dev_err_probe(&i2c->dev, PTR_ERR(regmap), 981 "Failed to initialize Regmap\n"); 982 983 irqchip = &bd72720_irq_chip; 984 clkmode_reg = BD72720_REG_OUT32K; 985 button_irq = BD72720_INT_SHORTPUSH; 986 main_lvl_mask_reg = BD72720_REG_INT_LVL1_EN; 987 main_lvl_val = BD72720_MASK_LVL1_EN_ALL; 988 break; 989 } 990 default: 991 dev_err(&i2c->dev, "Unknown device type"); 992 return -EINVAL; 993 } 994 995 if (!regmap) { 996 regmap = devm_regmap_init_i2c(i2c, regmap_config); 997 if (IS_ERR(regmap)) 998 return dev_err_probe(&i2c->dev, PTR_ERR(regmap), 999 "Failed to initialize Regmap\n"); 1000 } 1001 1002 ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, i2c->irq, 1003 IRQF_ONESHOT, 0, irqchip, &irq_data); 1004 if (ret) 1005 return dev_err_probe(&i2c->dev, ret, 1006 "Failed to add IRQ chip\n"); 1007 1008 dev_dbg(&i2c->dev, "Registered %d IRQs for chip\n", 1009 irqchip->num_irqs); 1010 1011 /* 1012 * On some ICs the main IRQ register has corresponding mask register. 1013 * This is not handled by the regmap IRQ. Let's enable all the main 1014 * level IRQs here. Further writes to the main level MASK is not 1015 * needed because masking is handled by the per IRQ 2.nd level MASK 1016 * registers. 2.nd level masks are handled by the regmap IRQ. 1017 */ 1018 if (main_lvl_mask_reg) { 1019 ret = regmap_write(regmap, main_lvl_mask_reg, main_lvl_val); 1020 if (ret) { 1021 return dev_err_probe(&i2c->dev, ret, 1022 "Failed to enable main level IRQs\n"); 1023 } 1024 } 1025 if (button_irq) { 1026 ret = regmap_irq_get_virq(irq_data, button_irq); 1027 if (ret < 0) 1028 return dev_err_probe(&i2c->dev, ret, 1029 "Failed to get the power-key IRQ\n"); 1030 1031 button.irq = ret; 1032 } 1033 1034 ret = set_clk_mode(&i2c->dev, regmap, clkmode_reg); 1035 if (ret) 1036 return ret; 1037 1038 ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, mfd, cells, 1039 NULL, 0, regmap_irq_get_domain(irq_data)); 1040 if (ret) 1041 return dev_err_probe(&i2c->dev, ret, "Failed to create subdevices\n"); 1042 1043 if (of_device_is_system_power_controller(i2c->dev.of_node) && 1044 chip_type == ROHM_CHIP_TYPE_BD71828) { 1045 if (!pm_power_off) { 1046 bd71828_dev = i2c; 1047 pm_power_off = bd71828_power_off; 1048 ret = devm_add_action_or_reset(&i2c->dev, 1049 bd71828_remove_poweroff, 1050 NULL); 1051 } else { 1052 dev_warn(&i2c->dev, "Poweroff callback already assigned\n"); 1053 } 1054 } 1055 1056 return ret; 1057 } 1058 1059 static const struct of_device_id bd71828_of_match[] = { 1060 { 1061 .compatible = "rohm,bd71828", 1062 .data = (void *)ROHM_CHIP_TYPE_BD71828, 1063 }, { 1064 .compatible = "rohm,bd71815", 1065 .data = (void *)ROHM_CHIP_TYPE_BD71815, 1066 }, { 1067 .compatible = "rohm,bd72720", 1068 .data = (void *)ROHM_CHIP_TYPE_BD72720, 1069 }, 1070 { }, 1071 }; 1072 MODULE_DEVICE_TABLE(of, bd71828_of_match); 1073 1074 static struct i2c_driver bd71828_drv = { 1075 .driver = { 1076 .name = "rohm-bd71828", 1077 .of_match_table = bd71828_of_match, 1078 }, 1079 .probe = bd71828_i2c_probe, 1080 }; 1081 module_i2c_driver(bd71828_drv); 1082 1083 MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>"); 1084 MODULE_DESCRIPTION("ROHM BD71828 Power Management IC driver"); 1085 MODULE_LICENSE("GPL"); 1086