1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2019, 2026 ROHM Semiconductor 4 * 5 * ROHM BD718[15/28/79], BD72720 and BD73[8/9]00 PMIC driver 6 */ 7 8 #include <linux/i2c.h> 9 #include <linux/input.h> 10 #include <linux/interrupt.h> 11 #include <linux/ioport.h> 12 #include <linux/irq.h> 13 #include <linux/mfd/core.h> 14 #include <linux/mfd/rohm-bd71815.h> 15 #include <linux/mfd/rohm-bd71828.h> 16 #include <linux/mfd/rohm-bd72720.h> 17 #include <linux/mfd/rohm-bd73800.h> 18 #include <linux/mfd/rohm-generic.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/regmap.h> 22 #include <linux/types.h> 23 24 #include "rohm-pwrbutton.h" 25 26 #define BD72720_TYPED_IRQ_REG(_irq, _stat_offset, _mask, _type_offset) \ 27 [_irq] = { \ 28 .reg_offset = (_stat_offset), \ 29 .mask = (_mask), \ 30 { \ 31 .type_reg_offset = (_type_offset), \ 32 .type_reg_mask = BD72720_GPIO_IRQ_TYPE_MASK, \ 33 .type_rising_val = BD72720_GPIO_IRQ_TYPE_RISING, \ 34 .type_falling_val = BD72720_GPIO_IRQ_TYPE_FALLING, \ 35 .type_level_low_val = BD72720_GPIO_IRQ_TYPE_LOW, \ 36 .type_level_high_val = BD72720_GPIO_IRQ_TYPE_HIGH, \ 37 .types_supported = IRQ_TYPE_EDGE_BOTH | \ 38 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW, \ 39 }, \ 40 } 41 42 static const struct resource bd71815_rtc_irqs[] = { 43 DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC0, "bd70528-rtc-alm-0"), 44 DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC1, "bd70528-rtc-alm-1"), 45 DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC2, "bd70528-rtc-alm-2"), 46 }; 47 48 static const struct resource bd71828_rtc_irqs[] = { 49 DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC0, "bd70528-rtc-alm-0"), 50 DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC1, "bd70528-rtc-alm-1"), 51 DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC2, "bd70528-rtc-alm-2"), 52 }; 53 54 static const struct resource bd72720_rtc_irqs[] = { 55 DEFINE_RES_IRQ_NAMED(BD72720_INT_RTC0, "bd70528-rtc-alm-0"), 56 DEFINE_RES_IRQ_NAMED(BD72720_INT_RTC1, "bd70528-rtc-alm-1"), 57 DEFINE_RES_IRQ_NAMED(BD72720_INT_RTC2, "bd70528-rtc-alm-2"), 58 }; 59 60 static const struct resource bd73800_rtc_irqs[] = { 61 DEFINE_RES_IRQ_NAMED(BD73800_INT_RTC0, "bd70528-rtc-alm-0"), 62 DEFINE_RES_IRQ_NAMED(BD73800_INT_RTC1, "bd70528-rtc-alm-1"), 63 DEFINE_RES_IRQ_NAMED(BD73800_INT_RTC2, "bd70528-rtc-alm-2"), 64 }; 65 66 static const struct resource bd71815_power_irqs[] = { 67 DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_RMV, "bd71815-dcin-rmv"), 68 DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_OUT, "bd71815-dcin-clps-out"), 69 DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_IN, "bd71815-dcin-clps-in"), 70 DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_RES, "bd71815-dcin-ovp-res"), 71 DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_DET, "bd71815-dcin-ovp-det"), 72 DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_MON_RES, "bd71815-dcin-mon-res"), 73 DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_MON_DET, "bd71815-dcin-mon-det"), 74 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_UV_RES, "bd71815-vsys-uv-res"), 75 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_UV_DET, "bd71815-vsys-uv-det"), 76 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_RES, "bd71815-vsys-low-res"), 77 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_DET, "bd71815-vsys-low-det"), 78 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_RES, "bd71815-vsys-mon-res"), 79 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_DET, "bd71815-vsys-mon-det"), 80 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TEMP, "bd71815-chg-wdg-temp"), 81 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TIME, "bd71815-chg-wdg"), 82 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RECHARGE_RES, "bd71815-rechg-res"), 83 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RECHARGE_DET, "bd71815-rechg-det"), 84 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RANGED_TEMP_TRANSITION, "bd71815-ranged-temp-transit"), 85 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_STATE_TRANSITION, "bd71815-chg-state-change"), 86 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_TEMP_NORMAL, "bd71815-bat-temp-normal"), 87 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_TEMP_ERANGE, "bd71815-bat-temp-erange"), 88 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_REMOVED, "bd71815-bat-rmv"), 89 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_DETECTED, "bd71815-bat-det"), 90 DEFINE_RES_IRQ_NAMED(BD71815_INT_THERM_REMOVED, "bd71815-therm-rmv"), 91 DEFINE_RES_IRQ_NAMED(BD71815_INT_THERM_DETECTED, "bd71815-therm-det"), 92 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_DEAD, "bd71815-bat-dead"), 93 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_SHORTC_RES, "bd71815-bat-short-res"), 94 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_SHORTC_DET, "bd71815-bat-short-det"), 95 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_LOW_VOLT_RES, "bd71815-bat-low-res"), 96 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_LOW_VOLT_DET, "bd71815-bat-low-det"), 97 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_VOLT_RES, "bd71815-bat-over-res"), 98 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_VOLT_DET, "bd71815-bat-over-det"), 99 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_MON_RES, "bd71815-bat-mon-res"), 100 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_MON_DET, "bd71815-bat-mon-det"), 101 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON1, "bd71815-bat-cc-mon1"), 102 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON2, "bd71815-bat-cc-mon2"), 103 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON3, "bd71815-bat-cc-mon3"), 104 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_1_RES, "bd71815-bat-oc1-res"), 105 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_1_DET, "bd71815-bat-oc1-det"), 106 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_2_RES, "bd71815-bat-oc2-res"), 107 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_2_DET, "bd71815-bat-oc2-det"), 108 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_RES, "bd71815-bat-oc3-res"), 109 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_DET, "bd71815-bat-oc3-det"), 110 DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_RES, "bd71815-temp-bat-low-res"), 111 DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_DET, "bd71815-temp-bat-low-det"), 112 DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_RES, "bd71815-temp-bat-hi-res"), 113 DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_DET, "bd71815-temp-bat-hi-det"), 114 }; 115 116 static const struct mfd_cell bd71815_mfd_cells[] = { 117 { .name = "bd71815-pmic", }, 118 { .name = "bd71815-clk", }, 119 { .name = "bd71815-gpo", }, 120 { 121 .name = "bd71815-power", 122 .num_resources = ARRAY_SIZE(bd71815_power_irqs), 123 .resources = &bd71815_power_irqs[0], 124 }, 125 { 126 .name = "bd71815-rtc", 127 .num_resources = ARRAY_SIZE(bd71815_rtc_irqs), 128 .resources = &bd71815_rtc_irqs[0], 129 }, 130 }; 131 132 static const struct resource bd71828_power_irqs[] = { 133 DEFINE_RES_IRQ_NAMED(BD71828_INT_CHG_TOPOFF_TO_DONE, 134 "bd71828-chg-done"), 135 DEFINE_RES_IRQ_NAMED(BD71828_INT_DCIN_DET, "bd71828-pwr-dcin-in"), 136 DEFINE_RES_IRQ_NAMED(BD71828_INT_DCIN_RMV, "bd71828-pwr-dcin-out"), 137 DEFINE_RES_IRQ_NAMED(BD71828_INT_BAT_LOW_VOLT_RES, 138 "bd71828-vbat-normal"), 139 DEFINE_RES_IRQ_NAMED(BD71828_INT_BAT_LOW_VOLT_DET, "bd71828-vbat-low"), 140 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_HI_DET, "bd71828-btemp-hi"), 141 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_HI_RES, "bd71828-btemp-cool"), 142 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_LOW_DET, "bd71828-btemp-lo"), 143 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_LOW_RES, 144 "bd71828-btemp-warm"), 145 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_VF_DET, 146 "bd71828-temp-hi"), 147 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_VF_RES, 148 "bd71828-temp-norm"), 149 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_125_DET, 150 "bd71828-temp-125-over"), 151 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_125_RES, 152 "bd71828-temp-125-under"), 153 }; 154 155 static struct mfd_cell bd71828_mfd_cells[] = { 156 { .name = "bd71828-pmic", }, 157 { .name = "bd71828-gpio", }, 158 { .name = "bd71828-led", .of_compatible = "rohm,bd71828-leds" }, 159 /* 160 * We use BD71837 driver to drive the clock block. Only differences to 161 * BD70528 clock gate are the register address and mask. 162 */ 163 { .name = "bd71828-clk", }, 164 { 165 .name = "bd71828-power", 166 .resources = bd71828_power_irqs, 167 .num_resources = ARRAY_SIZE(bd71828_power_irqs), 168 }, { 169 .name = "bd71828-rtc", 170 .resources = bd71828_rtc_irqs, 171 .num_resources = ARRAY_SIZE(bd71828_rtc_irqs), 172 }, 173 }; 174 175 static const struct resource bd72720_power_irqs[] = { 176 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_RMV, "bd72720_int_vbus_rmv"), 177 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_DET, "bd72720_int_vbus_det"), 178 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_MON_RES, "bd72720_int_vbus_mon_res"), 179 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_MON_DET, "bd72720_int_vbus_mon_det"), 180 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_MON_RES, "bd72720_int_vsys_mon_res"), 181 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_MON_DET, "bd72720_int_vsys_mon_det"), 182 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_UV_RES, "bd72720_int_vsys_uv_res"), 183 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_UV_DET, "bd72720_int_vsys_uv_det"), 184 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_LO_RES, "bd72720_int_vsys_lo_res"), 185 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_LO_DET, "bd72720_int_vsys_lo_det"), 186 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_OV_RES, "bd72720_int_vsys_ov_res"), 187 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_OV_DET, "bd72720_int_vsys_ov_det"), 188 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_ILIM, "bd72720_int_bat_ilim"), 189 DEFINE_RES_IRQ_NAMED(BD72720_INT_CHG_DONE, "bd72720_int_chg_done"), 190 DEFINE_RES_IRQ_NAMED(BD72720_INT_EXTEMP_TOUT, "bd72720_int_extemp_tout"), 191 DEFINE_RES_IRQ_NAMED(BD72720_INT_CHG_WDT_EXP, "bd72720_int_chg_wdt_exp"), 192 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_MNT_OUT, "bd72720_int_bat_mnt_out"), 193 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_MNT_IN, "bd72720_int_bat_mnt_in"), 194 DEFINE_RES_IRQ_NAMED(BD72720_INT_CHG_TRNS, "bd72720_int_chg_trns"), 195 196 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_MON_RES, "bd72720_int_vbat_mon_res"), 197 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_MON_DET, "bd72720_int_vbat_mon_det"), 198 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_SHT_RES, "bd72720_int_vbat_sht_res"), 199 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_SHT_DET, "bd72720_int_vbat_sht_det"), 200 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_LO_RES, "bd72720_int_vbat_lo_res"), 201 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_LO_DET, "bd72720_int_vbat_lo_det"), 202 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_OV_RES, "bd72720_int_vbat_ov_res"), 203 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_OV_DET, "bd72720_int_vbat_ov_det"), 204 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_RMV, "bd72720_int_bat_rmv"), 205 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_DET, "bd72720_int_bat_det"), 206 DEFINE_RES_IRQ_NAMED(BD72720_INT_DBAT_DET, "bd72720_int_dbat_det"), 207 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_TEMP_TRNS, "bd72720_int_bat_temp_trns"), 208 DEFINE_RES_IRQ_NAMED(BD72720_INT_LOBTMP_RES, "bd72720_int_lobtmp_res"), 209 DEFINE_RES_IRQ_NAMED(BD72720_INT_LOBTMP_DET, "bd72720_int_lobtmp_det"), 210 DEFINE_RES_IRQ_NAMED(BD72720_INT_OVBTMP_RES, "bd72720_int_ovbtmp_res"), 211 DEFINE_RES_IRQ_NAMED(BD72720_INT_OVBTMP_DET, "bd72720_int_ovbtmp_det"), 212 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR1_RES, "bd72720_int_ocur1_res"), 213 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR1_DET, "bd72720_int_ocur1_det"), 214 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR2_RES, "bd72720_int_ocur2_res"), 215 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR2_DET, "bd72720_int_ocur2_det"), 216 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR3_RES, "bd72720_int_ocur3_res"), 217 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR3_DET, "bd72720_int_ocur3_det"), 218 DEFINE_RES_IRQ_NAMED(BD72720_INT_CC_MON1_DET, "bd72720_int_cc_mon1_det"), 219 DEFINE_RES_IRQ_NAMED(BD72720_INT_CC_MON2_DET, "bd72720_int_cc_mon2_det"), 220 DEFINE_RES_IRQ_NAMED(BD72720_INT_CC_MON3_DET, "bd72720_int_cc_mon3_det"), 221 }; 222 223 static const struct mfd_cell bd72720_mfd_cells[] = { 224 { .name = "bd72720-pmic", }, 225 { .name = "bd72720-gpio", }, 226 { .name = "bd72720-led", }, 227 { .name = "bd72720-clk", }, 228 { 229 .name = "bd72720-power", 230 .resources = bd72720_power_irqs, 231 .num_resources = ARRAY_SIZE(bd72720_power_irqs), 232 }, { 233 .name = "bd72720-rtc", 234 .resources = bd72720_rtc_irqs, 235 .num_resources = ARRAY_SIZE(bd72720_rtc_irqs), 236 }, 237 /* Power button is registered separately */ 238 }; 239 240 static const struct mfd_cell bd73800_mfd_cells[] = { 241 { .name = "bd73800-pmic", }, 242 { .name = "bd73800-clk", }, 243 { .name = "bd73800-gpio", }, 244 { 245 .name = "bd73800-rtc", 246 .num_resources = ARRAY_SIZE(bd73800_rtc_irqs), 247 .resources = bd73800_rtc_irqs, 248 }, 249 }; 250 251 static const struct regmap_range bd71815_volatile_ranges[] = { 252 regmap_reg_range(BD71815_REG_SEC, BD71815_REG_YEAR), 253 regmap_reg_range(BD71815_REG_CONF, BD71815_REG_BAT_TEMP), 254 regmap_reg_range(BD71815_REG_VM_IBAT_U, BD71815_REG_CC_CTRL), 255 regmap_reg_range(BD71815_REG_CC_STAT, BD71815_REG_CC_CURCD_L), 256 regmap_reg_range(BD71815_REG_VM_BTMP_MON, BD71815_REG_VM_BTMP_MON), 257 regmap_reg_range(BD71815_REG_INT_STAT, BD71815_REG_INT_UPDATE), 258 regmap_reg_range(BD71815_REG_VM_VSYS_U, BD71815_REG_REX_CTRL_1), 259 regmap_reg_range(BD71815_REG_FULL_CCNTD_3, BD71815_REG_CCNTD_CHG_2), 260 }; 261 262 static const struct regmap_range bd71828_volatile_ranges[] = { 263 regmap_reg_range(BD71828_REG_PS_CTRL_1, BD71828_REG_PS_CTRL_1), 264 regmap_reg_range(BD71828_REG_PS_CTRL_3, BD71828_REG_PS_CTRL_3), 265 regmap_reg_range(BD71828_REG_RTC_SEC, BD71828_REG_RTC_YEAR), 266 /* 267 * For now make all charger registers volatile because many 268 * needs to be and because the charger block is not that 269 * performance critical. 270 */ 271 regmap_reg_range(BD71828_REG_CHG_STATE, BD71828_REG_CHG_FULL), 272 regmap_reg_range(BD71828_REG_INT_MAIN, BD71828_REG_IO_STAT), 273 }; 274 275 static const struct regmap_range bd72720_volatile_ranges_4b[] = { 276 regmap_reg_range(BD72720_REG_RESETSRC_1, BD72720_REG_RESETSRC_2), 277 regmap_reg_range(BD72720_REG_POWER_STATE, BD72720_REG_POWER_STATE), 278 /* The state indicator bit changes when new state is reached */ 279 regmap_reg_range(BD72720_REG_PS_CTRL_1, BD72720_REG_PS_CTRL_1), 280 regmap_reg_range(BD72720_REG_RCVNUM, BD72720_REG_RCVNUM), 281 regmap_reg_range(BD72720_REG_CONF, BD72720_REG_HALL_STAT), 282 regmap_reg_range(BD72720_REG_RTC_SEC, BD72720_REG_RTC_YEAR), 283 regmap_reg_range(BD72720_REG_INT_LVL1_STAT, BD72720_REG_INT_ETC2_SRC), 284 }; 285 286 static const struct regmap_range bd72720_precious_ranges_4b[] = { 287 regmap_reg_range(BD72720_REG_INT_LVL1_STAT, BD72720_REG_INT_ETC2_STAT), 288 }; 289 290 /* 291 * The BD72720 is an odd beast in that it contains two separate sets of 292 * registers, both starting from address 0x0. The twist is that these "pages" 293 * are behind different I2C slave addresses. Most of the registers are behind 294 * a slave address 0x4b, which will be used as the "main" address for this 295 * device. 296 * 297 * Most of the charger related registers are located behind slave address 0x4c. 298 * It is tempting to push the dealing with the charger registers and the extra 299 * 0x4c device in power-supply driver - but perhaps it's better for the sake of 300 * the cleaner re-use to deal with setting up all of the regmaps here. 301 * Furthermore, the LED stuff may need access to both of these devices. 302 * 303 * Instead of providing one of the regmaps to sub-devices in MFD platform data, 304 * we create one more 'wrapper regmap' with custom read/write operations. These 305 * custom accessors will select which of the 'real' regmaps to use, based on 306 * the register address. 307 * 308 * The register addresses are 8-bit, so we add offset 0x100 to the addresses 309 * behind the secondary slave 0x4c. The 'wrapper' regmap can then detect the 310 * correct slave address based on the register address and call regmap_write() 311 * and regmap_read() using correct 'real' regmap. This way the registers of 312 * both of the slaves can be accessed using one 'wrapper' regmap. 313 * 314 * NOTE: The added offsets mean that the defined addresses for slave 0x4c must 315 * be used through the 'wrapper' regmap because the offset must be stripped 316 * from the register addresses. The 0x4b can be accessed both indirectly using 317 * the 'wrapper' regmap, and directly using the 'real' regmap. 318 */ 319 #define BD72720_SECONDARY_I2C_SLAVE 0x4c 320 #define BD72720_SECONDARY_I2C_REG_OFFSET 0x100 321 322 struct bd72720_regmaps { 323 struct regmap *map1_4b; 324 struct regmap *map2_4c; 325 }; 326 327 /* Translate the slave 0x4c wrapper register address to a real one */ 328 #define BD72720_REG_UNWRAP(reg) ((reg) - BD72720_SECONDARY_I2C_REG_OFFSET) 329 330 /* Ranges given to 'real' 0x4c regmap must use unwrapped addresses. */ 331 #define BD72720_UNWRAP_REG_RANGE(startreg, endreg) \ 332 regmap_reg_range(BD72720_REG_UNWRAP(startreg), BD72720_REG_UNWRAP(endreg)) 333 334 static const struct regmap_range bd72720_volatile_ranges_4c[] = { 335 /* Status information */ 336 BD72720_UNWRAP_REG_RANGE(BD72720_REG_CHG_STATE, BD72720_REG_CHG_EN), 337 /* 338 * Under certain circumstances, write to some bits may be 339 * ignored 340 */ 341 BD72720_UNWRAP_REG_RANGE(BD72720_REG_CHG_CTRL, BD72720_REG_CHG_CTRL), 342 /* 343 * TODO: Ensure this is used to advertise state, not (only?) to 344 * control it. 345 */ 346 BD72720_UNWRAP_REG_RANGE(BD72720_REG_VSYS_STATE_STAT, BD72720_REG_VSYS_STATE_STAT), 347 /* Measured data */ 348 BD72720_UNWRAP_REG_RANGE(BD72720_REG_VM_VBAT_U, BD72720_REG_VM_VF_L), 349 /* Self clearing bits */ 350 BD72720_UNWRAP_REG_RANGE(BD72720_REG_VM_VSYS_SA_MINMAX_CTRL, 351 BD72720_REG_VM_VSYS_SA_MINMAX_CTRL), 352 /* Counters, self clearing bits */ 353 BD72720_UNWRAP_REG_RANGE(BD72720_REG_CC_CURCD_U, BD72720_REG_CC_CTRL), 354 /* Self clearing bits */ 355 BD72720_UNWRAP_REG_RANGE(BD72720_REG_CC_CCNTD_CTRL, BD72720_REG_CC_CCNTD_CTRL), 356 /* Self clearing bits */ 357 BD72720_UNWRAP_REG_RANGE(BD72720_REG_IMPCHK_CTRL, BD72720_REG_IMPCHK_CTRL), 358 }; 359 360 static const struct regmap_range bd73800_volatile_ranges[] = { 361 regmap_reg_range(BD73800_REG_POR_REASON, BD73800_REG_POW_STATE), 362 regmap_reg_range(BD73800_REG_PS_CTRL_1, BD73800_REG_PS_CTRL_2), 363 regmap_reg_range(BD73800_REG_RCVNUM, BD73800_REG_RCVNUM), 364 regmap_reg_range(BD73800_REG_RTC_SEC, BD73800_REG_RTC_YEAR), 365 regmap_reg_range(BD73800_REG_RTC_CONF, BD73800_REG_RTC_CONF), 366 regmap_reg_range(BD73800_REG_ADC_ACCUM_KICK, BD73800_REG_ADC_TEMP_VAL0), 367 regmap_reg_range(BD73800_REG_INT_MAIN_STAT, BD73800_REG_INT_5_STAT), 368 regmap_reg_range(BD73800_REG_INT_MAIN_SRC, BD73800_REG_INT_5_SRC), 369 }; 370 371 static const struct regmap_access_table bd71815_volatile_regs = { 372 .yes_ranges = &bd71815_volatile_ranges[0], 373 .n_yes_ranges = ARRAY_SIZE(bd71815_volatile_ranges), 374 }; 375 376 static const struct regmap_access_table bd71828_volatile_regs = { 377 .yes_ranges = &bd71828_volatile_ranges[0], 378 .n_yes_ranges = ARRAY_SIZE(bd71828_volatile_ranges), 379 }; 380 381 static const struct regmap_access_table bd72720_volatile_regs_4b = { 382 .yes_ranges = &bd72720_volatile_ranges_4b[0], 383 .n_yes_ranges = ARRAY_SIZE(bd72720_volatile_ranges_4b), 384 }; 385 386 static const struct regmap_access_table bd72720_precious_regs_4b = { 387 .yes_ranges = &bd72720_precious_ranges_4b[0], 388 .n_yes_ranges = ARRAY_SIZE(bd72720_precious_ranges_4b), 389 }; 390 391 static const struct regmap_access_table bd72720_volatile_regs_4c = { 392 .yes_ranges = &bd72720_volatile_ranges_4c[0], 393 .n_yes_ranges = ARRAY_SIZE(bd72720_volatile_ranges_4c), 394 }; 395 396 static const struct regmap_access_table bd73800_volatile_regs = { 397 .yes_ranges = bd73800_volatile_ranges, 398 .n_yes_ranges = ARRAY_SIZE(bd73800_volatile_ranges), 399 }; 400 401 static const struct regmap_range bd73800_read_only_ranges[] = { 402 regmap_reg_range(BD73800_REG_PRODUCT_ID, BD73800_REG_NVMVERSION), 403 regmap_reg_range(BD73800_REG_POW_STATE, BD73800_REG_POW_STATE), 404 regmap_reg_range(BD73800_REG_ADC_ACCUM_CNT2, BD73800_REG_ADC_TEMP_VAL0), 405 regmap_reg_range(BD73800_REG_INT_MAIN_STAT, BD73800_REG_INT_MAIN_STAT), 406 regmap_reg_range(BD73800_REG_INT_MAIN_SRC, BD73800_REG_INT_5_SRC), 407 }; 408 409 static const struct regmap_access_table bd73800_ro_regs = { 410 .no_ranges = bd73800_read_only_ranges, 411 .n_no_ranges = ARRAY_SIZE(bd73800_read_only_ranges), 412 }; 413 414 static const struct regmap_config bd71815_regmap = { 415 .reg_bits = 8, 416 .val_bits = 8, 417 .volatile_table = &bd71815_volatile_regs, 418 .max_register = BD71815_MAX_REGISTER - 1, 419 .cache_type = REGCACHE_MAPLE, 420 }; 421 422 static const struct regmap_config bd71828_regmap = { 423 .reg_bits = 8, 424 .val_bits = 8, 425 .volatile_table = &bd71828_volatile_regs, 426 .max_register = BD71828_MAX_REGISTER, 427 .cache_type = REGCACHE_MAPLE, 428 }; 429 430 static int regmap_write_wrapper(void *context, unsigned int reg, unsigned int val) 431 { 432 struct bd72720_regmaps *maps = context; 433 434 if (reg < BD72720_SECONDARY_I2C_REG_OFFSET) 435 return regmap_write(maps->map1_4b, reg, val); 436 437 reg = BD72720_REG_UNWRAP(reg); 438 439 return regmap_write(maps->map2_4c, reg, val); 440 } 441 442 static int regmap_read_wrapper(void *context, unsigned int reg, unsigned int *val) 443 { 444 struct bd72720_regmaps *maps = context; 445 446 if (reg < BD72720_SECONDARY_I2C_REG_OFFSET) 447 return regmap_read(maps->map1_4b, reg, val); 448 449 reg = BD72720_REG_UNWRAP(reg); 450 451 return regmap_read(maps->map2_4c, reg, val); 452 } 453 454 static const struct regmap_config bd72720_wrapper_map_config = { 455 .name = "wrap-map", 456 .reg_bits = 9, 457 .val_bits = 8, 458 .max_register = BD72720_REG_IMPCHK_CTRL, 459 /* 460 * We don't want to duplicate caches. It would be a bit faster to 461 * have the cache in this 'wrapper regmap', and not in the 'real 462 * regmaps' bd72720_regmap_4b and bd72720_regmap_4c below. This would 463 * require all the subdevices to use the wrapper-map in order to be 464 * able to benefit from the cache. 465 * Currently most of the sub-devices use only the same slave-address 466 * as this MFD driver. Now, because we don't add the offset to the 467 * registers belonging to this slave, those devices can use either the 468 * wrapper map, or the bd72720_regmap_4b directly. This means majority 469 * of our sub devices don't need to care which regmap they get using 470 * the dev_get_regmap(). This unifies the code between the BD72720 and 471 * those variants which don't have this 'multiple slave addresses' 472 * -hassle. 473 * So, for a small performance penalty, we simplify the code for the 474 * sub-devices by having the caches in the wrapped regmaps and not here. 475 */ 476 .cache_type = REGCACHE_NONE, 477 .reg_write = regmap_write_wrapper, 478 .reg_read = regmap_read_wrapper, 479 }; 480 481 static const struct regmap_config bd72720_regmap_4b = { 482 .reg_bits = 8, 483 .val_bits = 8, 484 .volatile_table = &bd72720_volatile_regs_4b, 485 .precious_table = &bd72720_precious_regs_4b, 486 .max_register = BD72720_REG_INT_ETC2_SRC, 487 .cache_type = REGCACHE_MAPLE, 488 }; 489 490 static const struct regmap_config bd72720_regmap_4c = { 491 .reg_bits = 8, 492 .val_bits = 8, 493 .volatile_table = &bd72720_volatile_regs_4c, 494 .max_register = BD72720_REG_UNWRAP(BD72720_REG_IMPCHK_CTRL), 495 .cache_type = REGCACHE_MAPLE, 496 }; 497 498 static const struct regmap_config bd73800_regmap = { 499 .reg_bits = 8, 500 .val_bits = 8, 501 .wr_table = &bd73800_ro_regs, 502 .volatile_table = &bd73800_volatile_regs, 503 .max_register = BD73800_MAX_REGISTER - 1, 504 .cache_type = REGCACHE_MAPLE, 505 }; 506 507 /* 508 * Mapping of main IRQ register bits to sub-IRQ register offsets so that we can 509 * access corect sub-IRQ registers based on bits that are set in main IRQ 510 * register. BD71815 and BD71828 have same sub-register-block offests, the 511 * BD72720 has a different one. 512 */ 513 514 static unsigned int bit0_offsets[] = {11}; /* RTC IRQ */ 515 static unsigned int bit1_offsets[] = {10}; /* TEMP IRQ */ 516 static unsigned int bit2_offsets[] = {6, 7, 8, 9}; /* BAT MON IRQ */ 517 static unsigned int bit3_offsets[] = {5}; /* BAT IRQ */ 518 static unsigned int bit4_offsets[] = {4}; /* CHG IRQ */ 519 static unsigned int bit5_offsets[] = {3}; /* VSYS IRQ */ 520 static unsigned int bit6_offsets[] = {1, 2}; /* DCIN IRQ */ 521 static unsigned int bit7_offsets[] = {0}; /* BUCK IRQ */ 522 523 static unsigned int bd72720_bit0_offsets[] = {0, 1}; /* PS1 and PS2 */ 524 static unsigned int bd72720_bit1_offsets[] = {2, 3}; /* DVS1 and DVS2 */ 525 static unsigned int bd72720_bit2_offsets[] = {4}; /* VBUS */ 526 static unsigned int bd72720_bit3_offsets[] = {5}; /* VSYS */ 527 static unsigned int bd72720_bit4_offsets[] = {6}; /* CHG */ 528 static unsigned int bd72720_bit5_offsets[] = {7, 8}; /* BAT1 and BAT2 */ 529 static unsigned int bd72720_bit6_offsets[] = {9}; /* IBAT */ 530 static unsigned int bd72720_bit7_offsets[] = {10, 11}; /* ETC1 and ETC2 */ 531 532 static const struct regmap_irq_sub_irq_map bd718xx_sub_irq_offsets[] = { 533 REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets), 534 REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets), 535 REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets), 536 REGMAP_IRQ_MAIN_REG_OFFSET(bit3_offsets), 537 REGMAP_IRQ_MAIN_REG_OFFSET(bit4_offsets), 538 REGMAP_IRQ_MAIN_REG_OFFSET(bit5_offsets), 539 REGMAP_IRQ_MAIN_REG_OFFSET(bit6_offsets), 540 REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets), 541 }; 542 543 static const struct regmap_irq_sub_irq_map bd72720_sub_irq_offsets[] = { 544 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit0_offsets), 545 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit1_offsets), 546 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit2_offsets), 547 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit3_offsets), 548 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit4_offsets), 549 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit5_offsets), 550 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit6_offsets), 551 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit7_offsets), 552 }; 553 554 static const struct regmap_irq bd71815_irqs[] = { 555 REGMAP_IRQ_REG(BD71815_INT_BUCK1_OCP, 0, BD71815_INT_BUCK1_OCP_MASK), 556 REGMAP_IRQ_REG(BD71815_INT_BUCK2_OCP, 0, BD71815_INT_BUCK2_OCP_MASK), 557 REGMAP_IRQ_REG(BD71815_INT_BUCK3_OCP, 0, BD71815_INT_BUCK3_OCP_MASK), 558 REGMAP_IRQ_REG(BD71815_INT_BUCK4_OCP, 0, BD71815_INT_BUCK4_OCP_MASK), 559 REGMAP_IRQ_REG(BD71815_INT_BUCK5_OCP, 0, BD71815_INT_BUCK5_OCP_MASK), 560 REGMAP_IRQ_REG(BD71815_INT_LED_OVP, 0, BD71815_INT_LED_OVP_MASK), 561 REGMAP_IRQ_REG(BD71815_INT_LED_OCP, 0, BD71815_INT_LED_OCP_MASK), 562 REGMAP_IRQ_REG(BD71815_INT_LED_SCP, 0, BD71815_INT_LED_SCP_MASK), 563 /* DCIN1 interrupts */ 564 REGMAP_IRQ_REG(BD71815_INT_DCIN_RMV, 1, BD71815_INT_DCIN_RMV_MASK), 565 REGMAP_IRQ_REG(BD71815_INT_CLPS_OUT, 1, BD71815_INT_CLPS_OUT_MASK), 566 REGMAP_IRQ_REG(BD71815_INT_CLPS_IN, 1, BD71815_INT_CLPS_IN_MASK), 567 REGMAP_IRQ_REG(BD71815_INT_DCIN_OVP_RES, 1, BD71815_INT_DCIN_OVP_RES_MASK), 568 REGMAP_IRQ_REG(BD71815_INT_DCIN_OVP_DET, 1, BD71815_INT_DCIN_OVP_DET_MASK), 569 /* DCIN2 interrupts */ 570 REGMAP_IRQ_REG(BD71815_INT_DCIN_MON_RES, 2, BD71815_INT_DCIN_MON_RES_MASK), 571 REGMAP_IRQ_REG(BD71815_INT_DCIN_MON_DET, 2, BD71815_INT_DCIN_MON_DET_MASK), 572 REGMAP_IRQ_REG(BD71815_INT_WDOG, 2, BD71815_INT_WDOG_MASK), 573 /* Vsys */ 574 REGMAP_IRQ_REG(BD71815_INT_VSYS_UV_RES, 3, BD71815_INT_VSYS_UV_RES_MASK), 575 REGMAP_IRQ_REG(BD71815_INT_VSYS_UV_DET, 3, BD71815_INT_VSYS_UV_DET_MASK), 576 REGMAP_IRQ_REG(BD71815_INT_VSYS_LOW_RES, 3, BD71815_INT_VSYS_LOW_RES_MASK), 577 REGMAP_IRQ_REG(BD71815_INT_VSYS_LOW_DET, 3, BD71815_INT_VSYS_LOW_DET_MASK), 578 REGMAP_IRQ_REG(BD71815_INT_VSYS_MON_RES, 3, BD71815_INT_VSYS_MON_RES_MASK), 579 REGMAP_IRQ_REG(BD71815_INT_VSYS_MON_DET, 3, BD71815_INT_VSYS_MON_DET_MASK), 580 /* Charger */ 581 REGMAP_IRQ_REG(BD71815_INT_CHG_WDG_TEMP, 4, BD71815_INT_CHG_WDG_TEMP_MASK), 582 REGMAP_IRQ_REG(BD71815_INT_CHG_WDG_TIME, 4, BD71815_INT_CHG_WDG_TIME_MASK), 583 REGMAP_IRQ_REG(BD71815_INT_CHG_RECHARGE_RES, 4, BD71815_INT_CHG_RECHARGE_RES_MASK), 584 REGMAP_IRQ_REG(BD71815_INT_CHG_RECHARGE_DET, 4, BD71815_INT_CHG_RECHARGE_DET_MASK), 585 REGMAP_IRQ_REG(BD71815_INT_CHG_RANGED_TEMP_TRANSITION, 4, 586 BD71815_INT_CHG_RANGED_TEMP_TRANSITION_MASK), 587 REGMAP_IRQ_REG(BD71815_INT_CHG_STATE_TRANSITION, 4, BD71815_INT_CHG_STATE_TRANSITION_MASK), 588 /* Battery */ 589 REGMAP_IRQ_REG(BD71815_INT_BAT_TEMP_NORMAL, 5, BD71815_INT_BAT_TEMP_NORMAL_MASK), 590 REGMAP_IRQ_REG(BD71815_INT_BAT_TEMP_ERANGE, 5, BD71815_INT_BAT_TEMP_ERANGE_MASK), 591 REGMAP_IRQ_REG(BD71815_INT_BAT_REMOVED, 5, BD71815_INT_BAT_REMOVED_MASK), 592 REGMAP_IRQ_REG(BD71815_INT_BAT_DETECTED, 5, BD71815_INT_BAT_DETECTED_MASK), 593 REGMAP_IRQ_REG(BD71815_INT_THERM_REMOVED, 5, BD71815_INT_THERM_REMOVED_MASK), 594 REGMAP_IRQ_REG(BD71815_INT_THERM_DETECTED, 5, BD71815_INT_THERM_DETECTED_MASK), 595 /* Battery Mon 1 */ 596 REGMAP_IRQ_REG(BD71815_INT_BAT_DEAD, 6, BD71815_INT_BAT_DEAD_MASK), 597 REGMAP_IRQ_REG(BD71815_INT_BAT_SHORTC_RES, 6, BD71815_INT_BAT_SHORTC_RES_MASK), 598 REGMAP_IRQ_REG(BD71815_INT_BAT_SHORTC_DET, 6, BD71815_INT_BAT_SHORTC_DET_MASK), 599 REGMAP_IRQ_REG(BD71815_INT_BAT_LOW_VOLT_RES, 6, BD71815_INT_BAT_LOW_VOLT_RES_MASK), 600 REGMAP_IRQ_REG(BD71815_INT_BAT_LOW_VOLT_DET, 6, BD71815_INT_BAT_LOW_VOLT_DET_MASK), 601 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_VOLT_RES, 6, BD71815_INT_BAT_OVER_VOLT_RES_MASK), 602 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_VOLT_DET, 6, BD71815_INT_BAT_OVER_VOLT_DET_MASK), 603 /* Battery Mon 2 */ 604 REGMAP_IRQ_REG(BD71815_INT_BAT_MON_RES, 7, BD71815_INT_BAT_MON_RES_MASK), 605 REGMAP_IRQ_REG(BD71815_INT_BAT_MON_DET, 7, BD71815_INT_BAT_MON_DET_MASK), 606 /* Battery Mon 3 (Coulomb counter) */ 607 REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON1, 8, BD71815_INT_BAT_CC_MON1_MASK), 608 REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON2, 8, BD71815_INT_BAT_CC_MON2_MASK), 609 REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON3, 8, BD71815_INT_BAT_CC_MON3_MASK), 610 /* Battery Mon 4 */ 611 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_1_RES, 9, BD71815_INT_BAT_OVER_CURR_1_RES_MASK), 612 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_1_DET, 9, BD71815_INT_BAT_OVER_CURR_1_DET_MASK), 613 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_2_RES, 9, BD71815_INT_BAT_OVER_CURR_2_RES_MASK), 614 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_2_DET, 9, BD71815_INT_BAT_OVER_CURR_2_DET_MASK), 615 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_3_RES, 9, BD71815_INT_BAT_OVER_CURR_3_RES_MASK), 616 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_3_DET, 9, BD71815_INT_BAT_OVER_CURR_3_DET_MASK), 617 /* Temperature */ 618 REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_LOW_RES, 10, BD71815_INT_TEMP_BAT_LOW_RES_MASK), 619 REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_LOW_DET, 10, BD71815_INT_TEMP_BAT_LOW_DET_MASK), 620 REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_HI_RES, 10, BD71815_INT_TEMP_BAT_HI_RES_MASK), 621 REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_HI_DET, 10, BD71815_INT_TEMP_BAT_HI_DET_MASK), 622 REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_125_RES, 10, 623 BD71815_INT_TEMP_CHIP_OVER_125_RES_MASK), 624 REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_125_DET, 10, 625 BD71815_INT_TEMP_CHIP_OVER_125_DET_MASK), 626 REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_VF_RES, 10, 627 BD71815_INT_TEMP_CHIP_OVER_VF_RES_MASK), 628 REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_VF_DET, 10, 629 BD71815_INT_TEMP_CHIP_OVER_VF_DET_MASK), 630 /* RTC Alarm */ 631 REGMAP_IRQ_REG(BD71815_INT_RTC0, 11, BD71815_INT_RTC0_MASK), 632 REGMAP_IRQ_REG(BD71815_INT_RTC1, 11, BD71815_INT_RTC1_MASK), 633 REGMAP_IRQ_REG(BD71815_INT_RTC2, 11, BD71815_INT_RTC2_MASK), 634 }; 635 636 static const struct regmap_irq bd71828_irqs[] = { 637 REGMAP_IRQ_REG(BD71828_INT_BUCK1_OCP, 0, BD71828_INT_BUCK1_OCP_MASK), 638 REGMAP_IRQ_REG(BD71828_INT_BUCK2_OCP, 0, BD71828_INT_BUCK2_OCP_MASK), 639 REGMAP_IRQ_REG(BD71828_INT_BUCK3_OCP, 0, BD71828_INT_BUCK3_OCP_MASK), 640 REGMAP_IRQ_REG(BD71828_INT_BUCK4_OCP, 0, BD71828_INT_BUCK4_OCP_MASK), 641 REGMAP_IRQ_REG(BD71828_INT_BUCK5_OCP, 0, BD71828_INT_BUCK5_OCP_MASK), 642 REGMAP_IRQ_REG(BD71828_INT_BUCK6_OCP, 0, BD71828_INT_BUCK6_OCP_MASK), 643 REGMAP_IRQ_REG(BD71828_INT_BUCK7_OCP, 0, BD71828_INT_BUCK7_OCP_MASK), 644 REGMAP_IRQ_REG(BD71828_INT_PGFAULT, 0, BD71828_INT_PGFAULT_MASK), 645 /* DCIN1 interrupts */ 646 REGMAP_IRQ_REG(BD71828_INT_DCIN_DET, 1, BD71828_INT_DCIN_DET_MASK), 647 REGMAP_IRQ_REG(BD71828_INT_DCIN_RMV, 1, BD71828_INT_DCIN_RMV_MASK), 648 REGMAP_IRQ_REG(BD71828_INT_CLPS_OUT, 1, BD71828_INT_CLPS_OUT_MASK), 649 REGMAP_IRQ_REG(BD71828_INT_CLPS_IN, 1, BD71828_INT_CLPS_IN_MASK), 650 /* DCIN2 interrupts */ 651 REGMAP_IRQ_REG(BD71828_INT_DCIN_MON_RES, 2, BD71828_INT_DCIN_MON_RES_MASK), 652 REGMAP_IRQ_REG(BD71828_INT_DCIN_MON_DET, 2, BD71828_INT_DCIN_MON_DET_MASK), 653 REGMAP_IRQ_REG(BD71828_INT_LONGPUSH, 2, BD71828_INT_LONGPUSH_MASK), 654 REGMAP_IRQ_REG(BD71828_INT_MIDPUSH, 2, BD71828_INT_MIDPUSH_MASK), 655 REGMAP_IRQ_REG(BD71828_INT_SHORTPUSH, 2, BD71828_INT_SHORTPUSH_MASK), 656 REGMAP_IRQ_REG(BD71828_INT_PUSH, 2, BD71828_INT_PUSH_MASK), 657 REGMAP_IRQ_REG(BD71828_INT_WDOG, 2, BD71828_INT_WDOG_MASK), 658 REGMAP_IRQ_REG(BD71828_INT_SWRESET, 2, BD71828_INT_SWRESET_MASK), 659 /* Vsys */ 660 REGMAP_IRQ_REG(BD71828_INT_VSYS_UV_RES, 3, BD71828_INT_VSYS_UV_RES_MASK), 661 REGMAP_IRQ_REG(BD71828_INT_VSYS_UV_DET, 3, BD71828_INT_VSYS_UV_DET_MASK), 662 REGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_RES, 3, BD71828_INT_VSYS_LOW_RES_MASK), 663 REGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_DET, 3, BD71828_INT_VSYS_LOW_DET_MASK), 664 REGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_IN, 3, BD71828_INT_VSYS_HALL_IN_MASK), 665 REGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_TOGGLE, 3, BD71828_INT_VSYS_HALL_TOGGLE_MASK), 666 REGMAP_IRQ_REG(BD71828_INT_VSYS_MON_RES, 3, BD71828_INT_VSYS_MON_RES_MASK), 667 REGMAP_IRQ_REG(BD71828_INT_VSYS_MON_DET, 3, BD71828_INT_VSYS_MON_DET_MASK), 668 /* Charger */ 669 REGMAP_IRQ_REG(BD71828_INT_CHG_DCIN_ILIM, 4, BD71828_INT_CHG_DCIN_ILIM_MASK), 670 REGMAP_IRQ_REG(BD71828_INT_CHG_TOPOFF_TO_DONE, 4, BD71828_INT_CHG_TOPOFF_TO_DONE_MASK), 671 REGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TEMP, 4, BD71828_INT_CHG_WDG_TEMP_MASK), 672 REGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TIME, 4, BD71828_INT_CHG_WDG_TIME_MASK), 673 REGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_RES, 4, BD71828_INT_CHG_RECHARGE_RES_MASK), 674 REGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_DET, 4, BD71828_INT_CHG_RECHARGE_DET_MASK), 675 REGMAP_IRQ_REG(BD71828_INT_CHG_RANGED_TEMP_TRANSITION, 4, 676 BD71828_INT_CHG_RANGED_TEMP_TRANSITION_MASK), 677 REGMAP_IRQ_REG(BD71828_INT_CHG_STATE_TRANSITION, 4, BD71828_INT_CHG_STATE_TRANSITION_MASK), 678 /* Battery */ 679 REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_NORMAL, 5, BD71828_INT_BAT_TEMP_NORMAL_MASK), 680 REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_ERANGE, 5, BD71828_INT_BAT_TEMP_ERANGE_MASK), 681 REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_WARN, 5, BD71828_INT_BAT_TEMP_WARN_MASK), 682 REGMAP_IRQ_REG(BD71828_INT_BAT_REMOVED, 5, BD71828_INT_BAT_REMOVED_MASK), 683 REGMAP_IRQ_REG(BD71828_INT_BAT_DETECTED, 5, BD71828_INT_BAT_DETECTED_MASK), 684 REGMAP_IRQ_REG(BD71828_INT_THERM_REMOVED, 5, BD71828_INT_THERM_REMOVED_MASK), 685 REGMAP_IRQ_REG(BD71828_INT_THERM_DETECTED, 5, BD71828_INT_THERM_DETECTED_MASK), 686 /* Battery Mon 1 */ 687 REGMAP_IRQ_REG(BD71828_INT_BAT_DEAD, 6, BD71828_INT_BAT_DEAD_MASK), 688 REGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_RES, 6, BD71828_INT_BAT_SHORTC_RES_MASK), 689 REGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_DET, 6, BD71828_INT_BAT_SHORTC_DET_MASK), 690 REGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_RES, 6, BD71828_INT_BAT_LOW_VOLT_RES_MASK), 691 REGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_DET, 6, BD71828_INT_BAT_LOW_VOLT_DET_MASK), 692 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_RES, 6, BD71828_INT_BAT_OVER_VOLT_RES_MASK), 693 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_DET, 6, BD71828_INT_BAT_OVER_VOLT_DET_MASK), 694 /* Battery Mon 2 */ 695 REGMAP_IRQ_REG(BD71828_INT_BAT_MON_RES, 7, BD71828_INT_BAT_MON_RES_MASK), 696 REGMAP_IRQ_REG(BD71828_INT_BAT_MON_DET, 7, BD71828_INT_BAT_MON_DET_MASK), 697 /* Battery Mon 3 (Coulomb counter) */ 698 REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON1, 8, BD71828_INT_BAT_CC_MON1_MASK), 699 REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON2, 8, BD71828_INT_BAT_CC_MON2_MASK), 700 REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON3, 8, BD71828_INT_BAT_CC_MON3_MASK), 701 /* Battery Mon 4 */ 702 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_RES, 9, BD71828_INT_BAT_OVER_CURR_1_RES_MASK), 703 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_DET, 9, BD71828_INT_BAT_OVER_CURR_1_DET_MASK), 704 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_RES, 9, BD71828_INT_BAT_OVER_CURR_2_RES_MASK), 705 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_DET, 9, BD71828_INT_BAT_OVER_CURR_2_DET_MASK), 706 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_RES, 9, BD71828_INT_BAT_OVER_CURR_3_RES_MASK), 707 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_DET, 9, BD71828_INT_BAT_OVER_CURR_3_DET_MASK), 708 /* Temperature */ 709 REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_RES, 10, BD71828_INT_TEMP_BAT_LOW_RES_MASK), 710 REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_DET, 10, BD71828_INT_TEMP_BAT_LOW_DET_MASK), 711 REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_RES, 10, BD71828_INT_TEMP_BAT_HI_RES_MASK), 712 REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_DET, 10, BD71828_INT_TEMP_BAT_HI_DET_MASK), 713 REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_125_RES, 10, 714 BD71828_INT_TEMP_CHIP_OVER_125_RES_MASK), 715 REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_125_DET, 10, 716 BD71828_INT_TEMP_CHIP_OVER_125_DET_MASK), 717 REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_VF_DET, 10, 718 BD71828_INT_TEMP_CHIP_OVER_VF_DET_MASK), 719 REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_VF_RES, 10, 720 BD71828_INT_TEMP_CHIP_OVER_VF_RES_MASK), 721 /* RTC Alarm */ 722 REGMAP_IRQ_REG(BD71828_INT_RTC0, 11, BD71828_INT_RTC0_MASK), 723 REGMAP_IRQ_REG(BD71828_INT_RTC1, 11, BD71828_INT_RTC1_MASK), 724 REGMAP_IRQ_REG(BD71828_INT_RTC2, 11, BD71828_INT_RTC2_MASK), 725 }; 726 727 static const struct regmap_irq bd72720_irqs[] = { 728 REGMAP_IRQ_REG(BD72720_INT_LONGPUSH, 0, BD72720_INT_LONGPUSH_MASK), 729 REGMAP_IRQ_REG(BD72720_INT_MIDPUSH, 0, BD72720_INT_MIDPUSH_MASK), 730 REGMAP_IRQ_REG(BD72720_INT_SHORTPUSH, 0, BD72720_INT_SHORTPUSH_MASK), 731 REGMAP_IRQ_REG(BD72720_INT_PUSH, 0, BD72720_INT_PUSH_MASK), 732 REGMAP_IRQ_REG(BD72720_INT_HALL_DET, 0, BD72720_INT_HALL_DET_MASK), 733 REGMAP_IRQ_REG(BD72720_INT_HALL_TGL, 0, BD72720_INT_HALL_TGL_MASK), 734 REGMAP_IRQ_REG(BD72720_INT_WDOG, 0, BD72720_INT_WDOG_MASK), 735 REGMAP_IRQ_REG(BD72720_INT_SWRESET, 0, BD72720_INT_SWRESET_MASK), 736 REGMAP_IRQ_REG(BD72720_INT_SEQ_DONE, 1, BD72720_INT_SEQ_DONE_MASK), 737 REGMAP_IRQ_REG(BD72720_INT_PGFAULT, 1, BD72720_INT_PGFAULT_MASK), 738 REGMAP_IRQ_REG(BD72720_INT_BUCK1_DVS, 2, BD72720_INT_BUCK1_DVS_MASK), 739 REGMAP_IRQ_REG(BD72720_INT_BUCK2_DVS, 2, BD72720_INT_BUCK2_DVS_MASK), 740 REGMAP_IRQ_REG(BD72720_INT_BUCK3_DVS, 2, BD72720_INT_BUCK3_DVS_MASK), 741 REGMAP_IRQ_REG(BD72720_INT_BUCK4_DVS, 2, BD72720_INT_BUCK4_DVS_MASK), 742 REGMAP_IRQ_REG(BD72720_INT_BUCK5_DVS, 2, BD72720_INT_BUCK5_DVS_MASK), 743 REGMAP_IRQ_REG(BD72720_INT_BUCK6_DVS, 2, BD72720_INT_BUCK6_DVS_MASK), 744 REGMAP_IRQ_REG(BD72720_INT_BUCK7_DVS, 2, BD72720_INT_BUCK7_DVS_MASK), 745 REGMAP_IRQ_REG(BD72720_INT_BUCK8_DVS, 2, BD72720_INT_BUCK8_DVS_MASK), 746 REGMAP_IRQ_REG(BD72720_INT_BUCK9_DVS, 3, BD72720_INT_BUCK9_DVS_MASK), 747 REGMAP_IRQ_REG(BD72720_INT_BUCK10_DVS, 3, BD72720_INT_BUCK10_DVS_MASK), 748 REGMAP_IRQ_REG(BD72720_INT_LDO1_DVS, 3, BD72720_INT_LDO1_DVS_MASK), 749 REGMAP_IRQ_REG(BD72720_INT_LDO2_DVS, 3, BD72720_INT_LDO2_DVS_MASK), 750 REGMAP_IRQ_REG(BD72720_INT_LDO3_DVS, 3, BD72720_INT_LDO3_DVS_MASK), 751 REGMAP_IRQ_REG(BD72720_INT_LDO4_DVS, 3, BD72720_INT_LDO4_DVS_MASK), 752 753 REGMAP_IRQ_REG(BD72720_INT_VBUS_RMV, 4, BD72720_INT_VBUS_RMV_MASK), 754 REGMAP_IRQ_REG(BD72720_INT_VBUS_DET, 4, BD72720_INT_VBUS_DET_MASK), 755 REGMAP_IRQ_REG(BD72720_INT_VBUS_MON_RES, 4, BD72720_INT_VBUS_MON_RES_MASK), 756 REGMAP_IRQ_REG(BD72720_INT_VBUS_MON_DET, 4, BD72720_INT_VBUS_MON_DET_MASK), 757 REGMAP_IRQ_REG(BD72720_INT_VSYS_MON_RES, 5, BD72720_INT_VSYS_MON_RES_MASK), 758 REGMAP_IRQ_REG(BD72720_INT_VSYS_MON_DET, 5, BD72720_INT_VSYS_MON_DET_MASK), 759 REGMAP_IRQ_REG(BD72720_INT_VSYS_UV_RES, 5, BD72720_INT_VSYS_UV_RES_MASK), 760 REGMAP_IRQ_REG(BD72720_INT_VSYS_UV_DET, 5, BD72720_INT_VSYS_UV_DET_MASK), 761 REGMAP_IRQ_REG(BD72720_INT_VSYS_LO_RES, 5, BD72720_INT_VSYS_LO_RES_MASK), 762 REGMAP_IRQ_REG(BD72720_INT_VSYS_LO_DET, 5, BD72720_INT_VSYS_LO_DET_MASK), 763 REGMAP_IRQ_REG(BD72720_INT_VSYS_OV_RES, 5, BD72720_INT_VSYS_OV_RES_MASK), 764 REGMAP_IRQ_REG(BD72720_INT_VSYS_OV_DET, 5, BD72720_INT_VSYS_OV_DET_MASK), 765 REGMAP_IRQ_REG(BD72720_INT_BAT_ILIM, 6, BD72720_INT_BAT_ILIM_MASK), 766 REGMAP_IRQ_REG(BD72720_INT_CHG_DONE, 6, BD72720_INT_CHG_DONE_MASK), 767 REGMAP_IRQ_REG(BD72720_INT_EXTEMP_TOUT, 6, BD72720_INT_EXTEMP_TOUT_MASK), 768 REGMAP_IRQ_REG(BD72720_INT_CHG_WDT_EXP, 6, BD72720_INT_CHG_WDT_EXP_MASK), 769 REGMAP_IRQ_REG(BD72720_INT_BAT_MNT_OUT, 6, BD72720_INT_BAT_MNT_OUT_MASK), 770 REGMAP_IRQ_REG(BD72720_INT_BAT_MNT_IN, 6, BD72720_INT_BAT_MNT_IN_MASK), 771 REGMAP_IRQ_REG(BD72720_INT_CHG_TRNS, 6, BD72720_INT_CHG_TRNS_MASK), 772 773 REGMAP_IRQ_REG(BD72720_INT_VBAT_MON_RES, 7, BD72720_INT_VBAT_MON_RES_MASK), 774 REGMAP_IRQ_REG(BD72720_INT_VBAT_MON_DET, 7, BD72720_INT_VBAT_MON_DET_MASK), 775 REGMAP_IRQ_REG(BD72720_INT_VBAT_SHT_RES, 7, BD72720_INT_VBAT_SHT_RES_MASK), 776 REGMAP_IRQ_REG(BD72720_INT_VBAT_SHT_DET, 7, BD72720_INT_VBAT_SHT_DET_MASK), 777 REGMAP_IRQ_REG(BD72720_INT_VBAT_LO_RES, 7, BD72720_INT_VBAT_LO_RES_MASK), 778 REGMAP_IRQ_REG(BD72720_INT_VBAT_LO_DET, 7, BD72720_INT_VBAT_LO_DET_MASK), 779 REGMAP_IRQ_REG(BD72720_INT_VBAT_OV_RES, 7, BD72720_INT_VBAT_OV_RES_MASK), 780 REGMAP_IRQ_REG(BD72720_INT_VBAT_OV_DET, 7, BD72720_INT_VBAT_OV_DET_MASK), 781 REGMAP_IRQ_REG(BD72720_INT_BAT_RMV, 8, BD72720_INT_BAT_RMV_MASK), 782 REGMAP_IRQ_REG(BD72720_INT_BAT_DET, 8, BD72720_INT_BAT_DET_MASK), 783 REGMAP_IRQ_REG(BD72720_INT_DBAT_DET, 8, BD72720_INT_DBAT_DET_MASK), 784 REGMAP_IRQ_REG(BD72720_INT_BAT_TEMP_TRNS, 8, BD72720_INT_BAT_TEMP_TRNS_MASK), 785 REGMAP_IRQ_REG(BD72720_INT_LOBTMP_RES, 8, BD72720_INT_LOBTMP_RES_MASK), 786 REGMAP_IRQ_REG(BD72720_INT_LOBTMP_DET, 8, BD72720_INT_LOBTMP_DET_MASK), 787 REGMAP_IRQ_REG(BD72720_INT_OVBTMP_RES, 8, BD72720_INT_OVBTMP_RES_MASK), 788 REGMAP_IRQ_REG(BD72720_INT_OVBTMP_DET, 8, BD72720_INT_OVBTMP_DET_MASK), 789 REGMAP_IRQ_REG(BD72720_INT_OCUR1_RES, 9, BD72720_INT_OCUR1_RES_MASK), 790 REGMAP_IRQ_REG(BD72720_INT_OCUR1_DET, 9, BD72720_INT_OCUR1_DET_MASK), 791 REGMAP_IRQ_REG(BD72720_INT_OCUR2_RES, 9, BD72720_INT_OCUR2_RES_MASK), 792 REGMAP_IRQ_REG(BD72720_INT_OCUR2_DET, 9, BD72720_INT_OCUR2_DET_MASK), 793 REGMAP_IRQ_REG(BD72720_INT_OCUR3_RES, 9, BD72720_INT_OCUR3_RES_MASK), 794 REGMAP_IRQ_REG(BD72720_INT_OCUR3_DET, 9, BD72720_INT_OCUR3_DET_MASK), 795 REGMAP_IRQ_REG(BD72720_INT_CC_MON1_DET, 10, BD72720_INT_CC_MON1_DET_MASK), 796 REGMAP_IRQ_REG(BD72720_INT_CC_MON2_DET, 10, BD72720_INT_CC_MON2_DET_MASK), 797 REGMAP_IRQ_REG(BD72720_INT_CC_MON3_DET, 10, BD72720_INT_CC_MON3_DET_MASK), 798 /* 799 * The GPIO1_IN and GPIO2_IN IRQs are generated from the PMIC's GPIO1 and GPIO2 800 * pins. Eg, they may be wired to other devices which can then use the PMIC as 801 * an interrupt controller. The GPIO1 and GPIO2 can have the IRQ type 802 * specified. All of the types (falling, rising, and both edges as well as low 803 * and high levels) are supported. 804 */ 805 BD72720_TYPED_IRQ_REG(BD72720_INT_GPIO1_IN, 10, BD72720_INT_GPIO1_IN_MASK, 0), 806 BD72720_TYPED_IRQ_REG(BD72720_INT_GPIO2_IN, 10, BD72720_INT_GPIO2_IN_MASK, 1), 807 REGMAP_IRQ_REG(BD72720_INT_VF125_RES, 11, BD72720_INT_VF125_RES_MASK), 808 REGMAP_IRQ_REG(BD72720_INT_VF125_DET, 11, BD72720_INT_VF125_DET_MASK), 809 REGMAP_IRQ_REG(BD72720_INT_VF_RES, 11, BD72720_INT_VF_RES_MASK), 810 REGMAP_IRQ_REG(BD72720_INT_VF_DET, 11, BD72720_INT_VF_DET_MASK), 811 REGMAP_IRQ_REG(BD72720_INT_RTC0, 11, BD72720_INT_RTC0_MASK), 812 REGMAP_IRQ_REG(BD72720_INT_RTC1, 11, BD72720_INT_RTC1_MASK), 813 REGMAP_IRQ_REG(BD72720_INT_RTC2, 11, BD72720_INT_RTC2_MASK), 814 }; 815 816 static int bd72720_set_type_config(unsigned int **buf, unsigned int type, 817 const struct regmap_irq *irq_data, 818 int idx, void *irq_drv_data) 819 { 820 const struct regmap_irq_type *t = &irq_data->type; 821 822 /* 823 * The regmap IRQ ecpects IRQ_TYPE_EDGE_BOTH to be written to register 824 * as logical OR of the type_falling_val and type_rising_val. This is 825 * not how the BD72720 implements this configuration, hence we need 826 * to handle this specific case separately. 827 */ 828 if (type == IRQ_TYPE_EDGE_BOTH) { 829 buf[0][idx] &= ~t->type_reg_mask; 830 buf[0][idx] |= BD72720_GPIO_IRQ_TYPE_BOTH; 831 832 return 0; 833 } 834 835 return regmap_irq_set_type_config_simple(buf, type, irq_data, idx, irq_drv_data); 836 } 837 838 static const struct regmap_irq bd73800_irqs[] = { 839 /* INT_STAT_1 register IRQs, ADC and RTC */ 840 REGMAP_IRQ_REG(BD73800_INT_ADC_ACCUM_DONE, 0, BD73800_INT_ADC_ACCUM_DONE_MASK), 841 REGMAP_IRQ_REG(BD73800_INT_ADC_ACCUM_OVF, 0, BD73800_INT_ADC_ACCUM_OVF_MASK), 842 REGMAP_IRQ_REG(BD73800_INT_ADC_ACCUM_VAL, 0, BD73800_INT_ADC_ACCUM_VAL_MASK), 843 REGMAP_IRQ_REG(BD73800_INT_ADC_ACCUM_TW, 0, BD73800_INT_ADC_ACCUM_TW_MASK), 844 REGMAP_IRQ_REG(BD73800_INT_ADC_POW_VAL, 0, BD73800_INT_ADC_POW_VAL_MASK), 845 REGMAP_IRQ_REG(BD73800_INT_RTC0, 0, BD73800_INT_RTC0_MASK), 846 REGMAP_IRQ_REG(BD73800_INT_RTC1, 0, BD73800_INT_RTC1_MASK), 847 REGMAP_IRQ_REG(BD73800_INT_RTC2, 0, BD73800_INT_RTC2_MASK), 848 849 /* BUCK reg interrupts */ 850 /* INT_STAT_2 IRQs */ 851 REGMAP_IRQ_REG(BD73800_INT_BUCK1_DVS_DONE, 1, BD73800_INT_BUCK1_DVS_DONE_MASK), 852 REGMAP_IRQ_REG(BD73800_INT_BUCK2_DVS_DONE, 1, BD73800_INT_BUCK2_DVS_DONE_MASK), 853 REGMAP_IRQ_REG(BD73800_INT_BUCK3_DVS_DONE, 1, BD73800_INT_BUCK3_DVS_DONE_MASK), 854 REGMAP_IRQ_REG(BD73800_INT_BUCK4_DVS_DONE, 1, BD73800_INT_BUCK4_DVS_DONE_MASK), 855 REGMAP_IRQ_REG(BD73800_INT_BUCK5_DVS_DONE, 1, BD73800_INT_BUCK5_DVS_DONE_MASK), 856 REGMAP_IRQ_REG(BD73800_INT_BUCK6_DVS_DONE, 1, BD73800_INT_BUCK6_DVS_DONE_MASK), 857 REGMAP_IRQ_REG(BD73800_INT_BUCK7_DVS_DONE, 1, BD73800_INT_BUCK7_DVS_DONE_MASK), 858 REGMAP_IRQ_REG(BD73800_INT_BUCK8_DVS_DONE, 1, BD73800_INT_BUCK8_DVS_DONE_MASK), 859 /* INT_STAT_3 IRQs */ 860 REGMAP_IRQ_REG(BD73800_INT_BUCK1_OCP, 2, BD73800_INT_BUCK1_OCP_MASK), 861 REGMAP_IRQ_REG(BD73800_INT_BUCK2_OCP, 2, BD73800_INT_BUCK2_OCP_MASK), 862 REGMAP_IRQ_REG(BD73800_INT_BUCK3_OCP, 2, BD73800_INT_BUCK3_OCP_MASK), 863 REGMAP_IRQ_REG(BD73800_INT_BUCK4_OCP, 2, BD73800_INT_BUCK4_OCP_MASK), 864 REGMAP_IRQ_REG(BD73800_INT_BUCK5_OCP, 2, BD73800_INT_BUCK5_OCP_MASK), 865 REGMAP_IRQ_REG(BD73800_INT_BUCK6_OCP, 2, BD73800_INT_BUCK6_OCP_MASK), 866 REGMAP_IRQ_REG(BD73800_INT_BUCK7_OCP, 2, BD73800_INT_BUCK7_OCP_MASK), 867 REGMAP_IRQ_REG(BD73800_INT_BUCK8_OCP, 2, BD73800_INT_BUCK8_OCP_MASK), 868 869 /* INT_STAT_4 IRQs, power-button, WDG and reset */ 870 REGMAP_IRQ_REG(BD73800_INT_PBTN_LONG_PRESS, 3, BD73800_INT_PBTN_LONG_PRESS_MASK), 871 REGMAP_IRQ_REG(BD73800_INT_PBTN_MID_PRESS, 3, BD73800_INT_PBTN_MID_PRESS_MASK), 872 /* 873 * The SHORT_PUSH is generated when button is first pressed (longer 874 * than configured time limit), and then released before the MID_PRESS 875 * time limit. The SHORT_PRESS is generated immediately when button is 876 * pressed for longer than configured limit, whether it is released or 877 * not. 878 */ 879 REGMAP_IRQ_REG(BD73800_INT_PBTN_SHORT_PUSH, 3, BD73800_INT_PBTN_SHORT_PUSH_MASK), 880 REGMAP_IRQ_REG(BD73800_INT_PBTN_SHORT_PRESS, 3, BD73800_INT_PBTN_SHORT_PRESS_MASK), 881 REGMAP_IRQ_REG(BD73800_INT_WDG, 3, BD73800_INT_WDG_MASK), 882 REGMAP_IRQ_REG(BD73800_INT_SWRESET, 3, BD73800_INT_SWRESET_MASK), 883 REGMAP_IRQ_REG(BD73800_INT_SEQ_DONE, 3, BD73800_INT_SEQ_DONE_MASK), 884 885 /* INT_STAT_5 IRQs, GPIO */ 886 REGMAP_IRQ_REG(BD73800_INT_GPIO1, 4, BD73800_INT_GPIO1_MASK), 887 REGMAP_IRQ_REG(BD73800_INT_GPIO2, 4, BD73800_INT_GPIO2_MASK), 888 REGMAP_IRQ_REG(BD73800_INT_GPIO3, 4, BD73800_INT_GPIO3_MASK), 889 REGMAP_IRQ_REG(BD73800_INT_GPIO4, 4, BD73800_INT_GPIO4_MASK), 890 }; 891 892 static const struct regmap_irq_chip bd71828_irq_chip = { 893 .name = "bd71828_irq", 894 .main_status = BD71828_REG_INT_MAIN, 895 .irqs = &bd71828_irqs[0], 896 .num_irqs = ARRAY_SIZE(bd71828_irqs), 897 .status_base = BD71828_REG_INT_BUCK, 898 .unmask_base = BD71828_REG_INT_MASK_BUCK, 899 .ack_base = BD71828_REG_INT_BUCK, 900 .init_ack_masked = true, 901 .num_regs = 12, 902 .num_main_regs = 1, 903 .sub_reg_offsets = &bd718xx_sub_irq_offsets[0], 904 .num_main_status_bits = 8, 905 .irq_reg_stride = 1, 906 }; 907 908 static const struct regmap_irq_chip bd71815_irq_chip = { 909 .name = "bd71815_irq", 910 .main_status = BD71815_REG_INT_STAT, 911 .irqs = &bd71815_irqs[0], 912 .num_irqs = ARRAY_SIZE(bd71815_irqs), 913 .status_base = BD71815_REG_INT_STAT_01, 914 .unmask_base = BD71815_REG_INT_EN_01, 915 .ack_base = BD71815_REG_INT_STAT_01, 916 .init_ack_masked = true, 917 .num_regs = 12, 918 .num_main_regs = 1, 919 .sub_reg_offsets = &bd718xx_sub_irq_offsets[0], 920 .num_main_status_bits = 8, 921 .irq_reg_stride = 1, 922 }; 923 924 static const unsigned int bd72720_irq_type_base[] = { BD72720_REG_GPIO1_CTRL }; 925 926 static const struct regmap_irq_chip bd72720_irq_chip = { 927 .name = "bd72720_irq", 928 .main_status = BD72720_REG_INT_LVL1_STAT, 929 .irqs = &bd72720_irqs[0], 930 .num_irqs = ARRAY_SIZE(bd72720_irqs), 931 .status_base = BD72720_REG_INT_PS1_STAT, 932 .unmask_base = BD72720_REG_INT_PS1_EN, 933 .config_base = &bd72720_irq_type_base[0], 934 .num_config_bases = 1, 935 .num_config_regs = 2, 936 .set_type_config = bd72720_set_type_config, 937 .ack_base = BD72720_REG_INT_PS1_STAT, 938 .init_ack_masked = true, 939 .num_regs = 12, 940 .num_main_regs = 1, 941 .sub_reg_offsets = &bd72720_sub_irq_offsets[0], 942 .num_main_status_bits = 8, 943 .irq_reg_stride = 1, 944 }; 945 946 static const struct regmap_irq_chip bd73800_irq_chip = { 947 .name = "bd73800_irq", 948 .main_status = BD73800_REG_INT_MAIN_STAT, 949 .irqs = bd73800_irqs, 950 .num_irqs = ARRAY_SIZE(bd73800_irqs), 951 .status_base = BD73800_REG_INT_1_STAT, 952 .unmask_base = BD73800_REG_INT_1_EN, 953 .ack_base = BD73800_REG_INT_1_STAT, 954 .init_ack_masked = true, 955 .num_regs = 5, 956 .num_main_regs = 1, 957 /* 958 * Ignore mirrored bits [7:5]. They are handled as part of normal INT_4 959 * handling. 960 */ 961 .num_main_status_bits = 5, 962 .irq_reg_stride = 1, 963 }; 964 965 static int set_clk_mode(struct device *dev, struct regmap *regmap, 966 int clkmode_reg) 967 { 968 int ret; 969 unsigned int open_drain; 970 971 ret = of_property_read_u32(dev->of_node, "rohm,clkout-open-drain", &open_drain); 972 if (ret) { 973 if (ret == -EINVAL) 974 return 0; 975 return ret; 976 } 977 if (open_drain > 1) { 978 dev_err(dev, "bad clk32kout mode configuration"); 979 return -EINVAL; 980 } 981 982 if (open_drain) 983 return regmap_update_bits(regmap, clkmode_reg, OUT32K_MODE, 984 OUT32K_MODE_OPEN_DRAIN); 985 986 return regmap_update_bits(regmap, clkmode_reg, OUT32K_MODE, 987 OUT32K_MODE_CMOS); 988 } 989 990 991 992 static struct i2c_client *bd71828_dev; 993 static void bd71828_power_off(void) 994 { 995 while (true) { 996 s32 val; 997 998 /* We are not allowed to sleep, so do not use regmap involving mutexes here. */ 999 val = i2c_smbus_read_byte_data(bd71828_dev, BD71828_REG_PS_CTRL_1); 1000 if (val >= 0) 1001 i2c_smbus_write_byte_data(bd71828_dev, 1002 BD71828_REG_PS_CTRL_1, 1003 BD71828_MASK_STATE_HBNT | (u8)val); 1004 mdelay(500); 1005 } 1006 } 1007 1008 static void bd71828_remove_poweroff(void *data) 1009 { 1010 pm_power_off = NULL; 1011 } 1012 1013 static struct regmap *bd72720_do_regmaps(struct i2c_client *i2c) 1014 { 1015 struct bd72720_regmaps *maps; 1016 struct i2c_client *secondary_i2c; 1017 1018 secondary_i2c = devm_i2c_new_dummy_device(&i2c->dev, i2c->adapter, 1019 BD72720_SECONDARY_I2C_SLAVE); 1020 if (IS_ERR(secondary_i2c)) { 1021 dev_err_probe(&i2c->dev, PTR_ERR(secondary_i2c), "Failed to get secondary I2C\n"); 1022 1023 return ERR_CAST(secondary_i2c); 1024 } 1025 1026 maps = devm_kzalloc(&i2c->dev, sizeof(*maps), GFP_KERNEL); 1027 if (!maps) 1028 return ERR_PTR(-ENOMEM); 1029 1030 maps->map1_4b = devm_regmap_init_i2c(i2c, &bd72720_regmap_4b); 1031 if (IS_ERR(maps->map1_4b)) 1032 return maps->map1_4b; 1033 1034 maps->map2_4c = devm_regmap_init_i2c(secondary_i2c, &bd72720_regmap_4c); 1035 if (IS_ERR(maps->map2_4c)) 1036 return maps->map2_4c; 1037 1038 return devm_regmap_init(&i2c->dev, NULL, maps, &bd72720_wrapper_map_config); 1039 } 1040 1041 static int bd71828_i2c_probe(struct i2c_client *i2c) 1042 { 1043 struct regmap_irq_chip_data *irq_data; 1044 struct irq_domain *irq_domain; 1045 int ret; 1046 struct regmap *regmap = NULL; 1047 const struct regmap_config *regmap_config; 1048 const struct regmap_irq_chip *irqchip; 1049 unsigned int chip_type; 1050 const struct mfd_cell *mfd; 1051 int cells; 1052 int button_irq; 1053 int clkmode_reg; 1054 int main_lvl_mask_reg = 0, main_lvl_val = 0; 1055 1056 if (!i2c->irq) { 1057 dev_err(&i2c->dev, "No IRQ configured\n"); 1058 return -EINVAL; 1059 } 1060 1061 chip_type = (unsigned int)(uintptr_t) 1062 of_device_get_match_data(&i2c->dev); 1063 switch (chip_type) { 1064 case ROHM_CHIP_TYPE_BD71828: 1065 mfd = bd71828_mfd_cells; 1066 cells = ARRAY_SIZE(bd71828_mfd_cells); 1067 regmap_config = &bd71828_regmap; 1068 irqchip = &bd71828_irq_chip; 1069 clkmode_reg = BD71828_REG_OUT32K; 1070 button_irq = BD71828_INT_SHORTPUSH; 1071 break; 1072 case ROHM_CHIP_TYPE_BD71815: 1073 mfd = bd71815_mfd_cells; 1074 cells = ARRAY_SIZE(bd71815_mfd_cells); 1075 regmap_config = &bd71815_regmap; 1076 irqchip = &bd71815_irq_chip; 1077 clkmode_reg = BD71815_REG_OUT32K; 1078 /* 1079 * If BD71817 support is needed we should be able to handle it 1080 * with proper DT configs + BD71815 drivers + power-button. 1081 * BD71815 data-sheet does not list the power-button IRQ so we 1082 * don't use it. 1083 */ 1084 button_irq = 0; 1085 break; 1086 case ROHM_CHIP_TYPE_BD72720: 1087 { 1088 mfd = bd72720_mfd_cells; 1089 cells = ARRAY_SIZE(bd72720_mfd_cells); 1090 1091 regmap = bd72720_do_regmaps(i2c); 1092 if (IS_ERR(regmap)) 1093 return dev_err_probe(&i2c->dev, PTR_ERR(regmap), 1094 "Failed to initialize Regmap\n"); 1095 1096 irqchip = &bd72720_irq_chip; 1097 clkmode_reg = BD72720_REG_OUT32K; 1098 button_irq = BD72720_INT_SHORTPUSH; 1099 main_lvl_mask_reg = BD72720_REG_INT_LVL1_EN; 1100 main_lvl_val = BD72720_MASK_LVL1_EN_ALL; 1101 break; 1102 } 1103 case ROHM_CHIP_TYPE_BD73800: 1104 mfd = bd73800_mfd_cells; 1105 cells = ARRAY_SIZE(bd73800_mfd_cells); 1106 regmap_config = &bd73800_regmap; 1107 irqchip = &bd73800_irq_chip; 1108 clkmode_reg = BD73800_REG_OUT32K; 1109 button_irq = BD73800_INT_PBTN_SHORT_PUSH; 1110 main_lvl_mask_reg = BD73800_REG_INT_MAIN_EN; 1111 main_lvl_val = BD73800_INT_MAIN_EN_ALL; 1112 break; 1113 1114 default: 1115 dev_err(&i2c->dev, "Unknown device type"); 1116 return -EINVAL; 1117 } 1118 1119 if (!regmap) { 1120 regmap = devm_regmap_init_i2c(i2c, regmap_config); 1121 if (IS_ERR(regmap)) 1122 return dev_err_probe(&i2c->dev, PTR_ERR(regmap), 1123 "Failed to initialize Regmap\n"); 1124 } 1125 1126 ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, i2c->irq, 1127 IRQF_ONESHOT, 0, irqchip, &irq_data); 1128 if (ret) 1129 return dev_err_probe(&i2c->dev, ret, 1130 "Failed to add IRQ chip\n"); 1131 1132 dev_dbg(&i2c->dev, "Registered %d IRQs for chip\n", 1133 irqchip->num_irqs); 1134 1135 /* 1136 * On some ICs the main IRQ register has corresponding mask register. 1137 * This is not handled by the regmap IRQ. Let's enable all the main 1138 * level IRQs here. Further writes to the main level MASK is not 1139 * needed because masking is handled by the per IRQ 2.nd level MASK 1140 * registers. 2.nd level masks are handled by the regmap IRQ. 1141 */ 1142 if (main_lvl_mask_reg) { 1143 ret = regmap_write(regmap, main_lvl_mask_reg, main_lvl_val); 1144 if (ret) { 1145 return dev_err_probe(&i2c->dev, ret, 1146 "Failed to enable main level IRQs\n"); 1147 } 1148 } 1149 1150 ret = set_clk_mode(&i2c->dev, regmap, clkmode_reg); 1151 if (ret) 1152 return ret; 1153 1154 irq_domain = regmap_irq_get_domain(irq_data); 1155 1156 ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, mfd, cells, 1157 NULL, 0, irq_domain); 1158 if (ret) 1159 return dev_err_probe(&i2c->dev, ret, "Failed to create subdevices\n"); 1160 1161 if (button_irq) { 1162 ret = rohm_register_pwrbutton(&i2c->dev, button_irq, 1163 "bd71828-pwrkey", true, irq_domain); 1164 if (ret) 1165 return ret; 1166 } 1167 1168 if (of_device_is_system_power_controller(i2c->dev.of_node) && 1169 chip_type == ROHM_CHIP_TYPE_BD71828) { 1170 if (!pm_power_off) { 1171 bd71828_dev = i2c; 1172 pm_power_off = bd71828_power_off; 1173 ret = devm_add_action_or_reset(&i2c->dev, 1174 bd71828_remove_poweroff, 1175 NULL); 1176 } else { 1177 dev_warn(&i2c->dev, "Poweroff callback already assigned\n"); 1178 } 1179 } 1180 1181 return ret; 1182 } 1183 1184 static const struct of_device_id bd71828_of_match[] = { 1185 { 1186 .compatible = "rohm,bd71828", 1187 .data = (void *)ROHM_CHIP_TYPE_BD71828, 1188 }, { 1189 .compatible = "rohm,bd71815", 1190 .data = (void *)ROHM_CHIP_TYPE_BD71815, 1191 }, { 1192 .compatible = "rohm,bd72720", 1193 .data = (void *)ROHM_CHIP_TYPE_BD72720, 1194 }, { 1195 .compatible = "rohm,bd73800", 1196 .data = (void *)ROHM_CHIP_TYPE_BD73800, 1197 }, 1198 { }, 1199 }; 1200 MODULE_DEVICE_TABLE(of, bd71828_of_match); 1201 1202 static struct i2c_driver bd71828_drv = { 1203 .driver = { 1204 .name = "rohm-bd71828", 1205 .of_match_table = bd71828_of_match, 1206 }, 1207 .probe = bd71828_i2c_probe, 1208 }; 1209 module_i2c_driver(bd71828_drv); 1210 1211 MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>"); 1212 MODULE_DESCRIPTION("ROHM BD71828 Power Management IC driver"); 1213 MODULE_LICENSE("GPL"); 1214