1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2019 ROHM Semiconductors 4 * 5 * ROHM BD718[15/28/79] and BD72720 PMIC driver 6 */ 7 8 #include <linux/device/devres.h> 9 #include <linux/gfp_types.h> 10 #include <linux/i2c.h> 11 #include <linux/input.h> 12 #include <linux/interrupt.h> 13 #include <linux/ioport.h> 14 #include <linux/irq.h> 15 #include <linux/mfd/core.h> 16 #include <linux/mfd/rohm-bd71815.h> 17 #include <linux/mfd/rohm-bd71828.h> 18 #include <linux/mfd/rohm-bd72720.h> 19 #include <linux/mfd/rohm-generic.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/property.h> 23 #include <linux/regmap.h> 24 #include <linux/types.h> 25 26 #define BD72720_TYPED_IRQ_REG(_irq, _stat_offset, _mask, _type_offset) \ 27 [_irq] = { \ 28 .reg_offset = (_stat_offset), \ 29 .mask = (_mask), \ 30 { \ 31 .type_reg_offset = (_type_offset), \ 32 .type_reg_mask = BD72720_GPIO_IRQ_TYPE_MASK, \ 33 .type_rising_val = BD72720_GPIO_IRQ_TYPE_RISING, \ 34 .type_falling_val = BD72720_GPIO_IRQ_TYPE_FALLING, \ 35 .type_level_low_val = BD72720_GPIO_IRQ_TYPE_LOW, \ 36 .type_level_high_val = BD72720_GPIO_IRQ_TYPE_HIGH, \ 37 .types_supported = IRQ_TYPE_EDGE_BOTH | \ 38 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW, \ 39 }, \ 40 } 41 42 static const struct resource bd71815_rtc_irqs[] = { 43 DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC0, "bd70528-rtc-alm-0"), 44 DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC1, "bd70528-rtc-alm-1"), 45 DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC2, "bd70528-rtc-alm-2"), 46 }; 47 48 static const struct resource bd71828_rtc_irqs[] = { 49 DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC0, "bd70528-rtc-alm-0"), 50 DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC1, "bd70528-rtc-alm-1"), 51 DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC2, "bd70528-rtc-alm-2"), 52 }; 53 54 static const struct resource bd72720_rtc_irqs[] = { 55 DEFINE_RES_IRQ_NAMED(BD72720_INT_RTC0, "bd70528-rtc-alm-0"), 56 DEFINE_RES_IRQ_NAMED(BD72720_INT_RTC1, "bd70528-rtc-alm-1"), 57 DEFINE_RES_IRQ_NAMED(BD72720_INT_RTC2, "bd70528-rtc-alm-2"), 58 }; 59 60 static const struct resource bd71815_power_irqs[] = { 61 DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_RMV, "bd71815-dcin-rmv"), 62 DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_OUT, "bd71815-dcin-clps-out"), 63 DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_IN, "bd71815-dcin-clps-in"), 64 DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_RES, "bd71815-dcin-ovp-res"), 65 DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_DET, "bd71815-dcin-ovp-det"), 66 DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_MON_RES, "bd71815-dcin-mon-res"), 67 DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_MON_DET, "bd71815-dcin-mon-det"), 68 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_UV_RES, "bd71815-vsys-uv-res"), 69 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_UV_DET, "bd71815-vsys-uv-det"), 70 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_RES, "bd71815-vsys-low-res"), 71 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_DET, "bd71815-vsys-low-det"), 72 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_RES, "bd71815-vsys-mon-res"), 73 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_DET, "bd71815-vsys-mon-det"), 74 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TEMP, "bd71815-chg-wdg-temp"), 75 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TIME, "bd71815-chg-wdg"), 76 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RECHARGE_RES, "bd71815-rechg-res"), 77 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RECHARGE_DET, "bd71815-rechg-det"), 78 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RANGED_TEMP_TRANSITION, "bd71815-ranged-temp-transit"), 79 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_STATE_TRANSITION, "bd71815-chg-state-change"), 80 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_TEMP_NORMAL, "bd71815-bat-temp-normal"), 81 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_TEMP_ERANGE, "bd71815-bat-temp-erange"), 82 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_REMOVED, "bd71815-bat-rmv"), 83 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_DETECTED, "bd71815-bat-det"), 84 DEFINE_RES_IRQ_NAMED(BD71815_INT_THERM_REMOVED, "bd71815-therm-rmv"), 85 DEFINE_RES_IRQ_NAMED(BD71815_INT_THERM_DETECTED, "bd71815-therm-det"), 86 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_DEAD, "bd71815-bat-dead"), 87 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_SHORTC_RES, "bd71815-bat-short-res"), 88 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_SHORTC_DET, "bd71815-bat-short-det"), 89 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_LOW_VOLT_RES, "bd71815-bat-low-res"), 90 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_LOW_VOLT_DET, "bd71815-bat-low-det"), 91 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_VOLT_RES, "bd71815-bat-over-res"), 92 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_VOLT_DET, "bd71815-bat-over-det"), 93 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_MON_RES, "bd71815-bat-mon-res"), 94 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_MON_DET, "bd71815-bat-mon-det"), 95 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON1, "bd71815-bat-cc-mon1"), 96 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON2, "bd71815-bat-cc-mon2"), 97 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON3, "bd71815-bat-cc-mon3"), 98 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_1_RES, "bd71815-bat-oc1-res"), 99 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_1_DET, "bd71815-bat-oc1-det"), 100 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_2_RES, "bd71815-bat-oc2-res"), 101 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_2_DET, "bd71815-bat-oc2-det"), 102 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_RES, "bd71815-bat-oc3-res"), 103 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_DET, "bd71815-bat-oc3-det"), 104 DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_RES, "bd71815-temp-bat-low-res"), 105 DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_DET, "bd71815-temp-bat-low-det"), 106 DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_RES, "bd71815-temp-bat-hi-res"), 107 DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_DET, "bd71815-temp-bat-hi-det"), 108 }; 109 110 static const struct mfd_cell bd71815_mfd_cells[] = { 111 { .name = "bd71815-pmic", }, 112 { .name = "bd71815-clk", }, 113 { .name = "bd71815-gpo", }, 114 { 115 .name = "bd71815-power", 116 .num_resources = ARRAY_SIZE(bd71815_power_irqs), 117 .resources = &bd71815_power_irqs[0], 118 }, 119 { 120 .name = "bd71815-rtc", 121 .num_resources = ARRAY_SIZE(bd71815_rtc_irqs), 122 .resources = &bd71815_rtc_irqs[0], 123 }, 124 }; 125 126 static const struct resource bd71828_power_irqs[] = { 127 DEFINE_RES_IRQ_NAMED(BD71828_INT_CHG_TOPOFF_TO_DONE, 128 "bd71828-chg-done"), 129 DEFINE_RES_IRQ_NAMED(BD71828_INT_DCIN_DET, "bd71828-pwr-dcin-in"), 130 DEFINE_RES_IRQ_NAMED(BD71828_INT_DCIN_RMV, "bd71828-pwr-dcin-out"), 131 DEFINE_RES_IRQ_NAMED(BD71828_INT_BAT_LOW_VOLT_RES, 132 "bd71828-vbat-normal"), 133 DEFINE_RES_IRQ_NAMED(BD71828_INT_BAT_LOW_VOLT_DET, "bd71828-vbat-low"), 134 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_HI_DET, "bd71828-btemp-hi"), 135 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_HI_RES, "bd71828-btemp-cool"), 136 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_LOW_DET, "bd71828-btemp-lo"), 137 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_LOW_RES, 138 "bd71828-btemp-warm"), 139 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_VF_DET, 140 "bd71828-temp-hi"), 141 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_VF_RES, 142 "bd71828-temp-norm"), 143 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_125_DET, 144 "bd71828-temp-125-over"), 145 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_125_RES, 146 "bd71828-temp-125-under"), 147 }; 148 149 static struct mfd_cell bd71828_mfd_cells[] = { 150 { .name = "bd71828-pmic", }, 151 { .name = "bd71828-gpio", }, 152 { .name = "bd71828-led", .of_compatible = "rohm,bd71828-leds" }, 153 /* 154 * We use BD71837 driver to drive the clock block. Only differences to 155 * BD70528 clock gate are the register address and mask. 156 */ 157 { .name = "bd71828-clk", }, 158 { 159 .name = "bd71828-power", 160 .resources = bd71828_power_irqs, 161 .num_resources = ARRAY_SIZE(bd71828_power_irqs), 162 }, { 163 .name = "bd71828-rtc", 164 .resources = bd71828_rtc_irqs, 165 .num_resources = ARRAY_SIZE(bd71828_rtc_irqs), 166 }, 167 }; 168 169 static const struct resource bd72720_power_irqs[] = { 170 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_RMV, "bd72720_int_vbus_rmv"), 171 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_DET, "bd72720_int_vbus_det"), 172 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_MON_RES, "bd72720_int_vbus_mon_res"), 173 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_MON_DET, "bd72720_int_vbus_mon_det"), 174 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_MON_RES, "bd72720_int_vsys_mon_res"), 175 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_MON_DET, "bd72720_int_vsys_mon_det"), 176 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_UV_RES, "bd72720_int_vsys_uv_res"), 177 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_UV_DET, "bd72720_int_vsys_uv_det"), 178 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_LO_RES, "bd72720_int_vsys_lo_res"), 179 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_LO_DET, "bd72720_int_vsys_lo_det"), 180 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_OV_RES, "bd72720_int_vsys_ov_res"), 181 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_OV_DET, "bd72720_int_vsys_ov_det"), 182 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_ILIM, "bd72720_int_bat_ilim"), 183 DEFINE_RES_IRQ_NAMED(BD72720_INT_CHG_DONE, "bd72720_int_chg_done"), 184 DEFINE_RES_IRQ_NAMED(BD72720_INT_EXTEMP_TOUT, "bd72720_int_extemp_tout"), 185 DEFINE_RES_IRQ_NAMED(BD72720_INT_CHG_WDT_EXP, "bd72720_int_chg_wdt_exp"), 186 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_MNT_OUT, "bd72720_int_bat_mnt_out"), 187 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_MNT_IN, "bd72720_int_bat_mnt_in"), 188 DEFINE_RES_IRQ_NAMED(BD72720_INT_CHG_TRNS, "bd72720_int_chg_trns"), 189 190 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_MON_RES, "bd72720_int_vbat_mon_res"), 191 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_MON_DET, "bd72720_int_vbat_mon_det"), 192 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_SHT_RES, "bd72720_int_vbat_sht_res"), 193 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_SHT_DET, "bd72720_int_vbat_sht_det"), 194 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_LO_RES, "bd72720_int_vbat_lo_res"), 195 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_LO_DET, "bd72720_int_vbat_lo_det"), 196 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_OV_RES, "bd72720_int_vbat_ov_res"), 197 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_OV_DET, "bd72720_int_vbat_ov_det"), 198 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_RMV, "bd72720_int_bat_rmv"), 199 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_DET, "bd72720_int_bat_det"), 200 DEFINE_RES_IRQ_NAMED(BD72720_INT_DBAT_DET, "bd72720_int_dbat_det"), 201 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_TEMP_TRNS, "bd72720_int_bat_temp_trns"), 202 DEFINE_RES_IRQ_NAMED(BD72720_INT_LOBTMP_RES, "bd72720_int_lobtmp_res"), 203 DEFINE_RES_IRQ_NAMED(BD72720_INT_LOBTMP_DET, "bd72720_int_lobtmp_det"), 204 DEFINE_RES_IRQ_NAMED(BD72720_INT_OVBTMP_RES, "bd72720_int_ovbtmp_res"), 205 DEFINE_RES_IRQ_NAMED(BD72720_INT_OVBTMP_DET, "bd72720_int_ovbtmp_det"), 206 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR1_RES, "bd72720_int_ocur1_res"), 207 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR1_DET, "bd72720_int_ocur1_det"), 208 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR2_RES, "bd72720_int_ocur2_res"), 209 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR2_DET, "bd72720_int_ocur2_det"), 210 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR3_RES, "bd72720_int_ocur3_res"), 211 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR3_DET, "bd72720_int_ocur3_det"), 212 DEFINE_RES_IRQ_NAMED(BD72720_INT_CC_MON1_DET, "bd72720_int_cc_mon1_det"), 213 DEFINE_RES_IRQ_NAMED(BD72720_INT_CC_MON2_DET, "bd72720_int_cc_mon2_det"), 214 DEFINE_RES_IRQ_NAMED(BD72720_INT_CC_MON3_DET, "bd72720_int_cc_mon3_det"), 215 }; 216 217 static const struct mfd_cell bd72720_mfd_cells[] = { 218 { .name = "bd72720-pmic", }, 219 { .name = "bd72720-gpio", }, 220 { .name = "bd72720-led", }, 221 { .name = "bd72720-clk", }, 222 { 223 .name = "bd72720-power", 224 .resources = bd72720_power_irqs, 225 .num_resources = ARRAY_SIZE(bd72720_power_irqs), 226 }, { 227 .name = "bd72720-rtc", 228 .resources = bd72720_rtc_irqs, 229 .num_resources = ARRAY_SIZE(bd72720_rtc_irqs), 230 }, 231 /* Power button is registered separately */ 232 }; 233 234 static const struct regmap_range bd71815_volatile_ranges[] = { 235 regmap_reg_range(BD71815_REG_SEC, BD71815_REG_YEAR), 236 regmap_reg_range(BD71815_REG_CONF, BD71815_REG_BAT_TEMP), 237 regmap_reg_range(BD71815_REG_VM_IBAT_U, BD71815_REG_CC_CTRL), 238 regmap_reg_range(BD71815_REG_CC_STAT, BD71815_REG_CC_CURCD_L), 239 regmap_reg_range(BD71815_REG_VM_BTMP_MON, BD71815_REG_VM_BTMP_MON), 240 regmap_reg_range(BD71815_REG_INT_STAT, BD71815_REG_INT_UPDATE), 241 regmap_reg_range(BD71815_REG_VM_VSYS_U, BD71815_REG_REX_CTRL_1), 242 regmap_reg_range(BD71815_REG_FULL_CCNTD_3, BD71815_REG_CCNTD_CHG_2), 243 }; 244 245 static const struct regmap_range bd71828_volatile_ranges[] = { 246 regmap_reg_range(BD71828_REG_PS_CTRL_1, BD71828_REG_PS_CTRL_1), 247 regmap_reg_range(BD71828_REG_PS_CTRL_3, BD71828_REG_PS_CTRL_3), 248 regmap_reg_range(BD71828_REG_RTC_SEC, BD71828_REG_RTC_YEAR), 249 /* 250 * For now make all charger registers volatile because many 251 * needs to be and because the charger block is not that 252 * performance critical. 253 */ 254 regmap_reg_range(BD71828_REG_CHG_STATE, BD71828_REG_CHG_FULL), 255 regmap_reg_range(BD71828_REG_INT_MAIN, BD71828_REG_IO_STAT), 256 }; 257 258 static const struct regmap_range bd72720_volatile_ranges_4b[] = { 259 regmap_reg_range(BD72720_REG_RESETSRC_1, BD72720_REG_RESETSRC_2), 260 regmap_reg_range(BD72720_REG_POWER_STATE, BD72720_REG_POWER_STATE), 261 /* The state indicator bit changes when new state is reached */ 262 regmap_reg_range(BD72720_REG_PS_CTRL_1, BD72720_REG_PS_CTRL_1), 263 regmap_reg_range(BD72720_REG_RCVNUM, BD72720_REG_RCVNUM), 264 regmap_reg_range(BD72720_REG_CONF, BD72720_REG_HALL_STAT), 265 regmap_reg_range(BD72720_REG_RTC_SEC, BD72720_REG_RTC_YEAR), 266 regmap_reg_range(BD72720_REG_INT_LVL1_STAT, BD72720_REG_INT_ETC2_SRC), 267 }; 268 269 static const struct regmap_range bd72720_precious_ranges_4b[] = { 270 regmap_reg_range(BD72720_REG_INT_LVL1_STAT, BD72720_REG_INT_ETC2_STAT), 271 }; 272 273 /* 274 * The BD72720 is an odd beast in that it contains two separate sets of 275 * registers, both starting from address 0x0. The twist is that these "pages" 276 * are behind different I2C slave addresses. Most of the registers are behind 277 * a slave address 0x4b, which will be used as the "main" address for this 278 * device. 279 * 280 * Most of the charger related registers are located behind slave address 0x4c. 281 * It is tempting to push the dealing with the charger registers and the extra 282 * 0x4c device in power-supply driver - but perhaps it's better for the sake of 283 * the cleaner re-use to deal with setting up all of the regmaps here. 284 * Furthermore, the LED stuff may need access to both of these devices. 285 * 286 * Instead of providing one of the regmaps to sub-devices in MFD platform data, 287 * we create one more 'wrapper regmap' with custom read/write operations. These 288 * custom accessors will select which of the 'real' regmaps to use, based on 289 * the register address. 290 * 291 * The register addresses are 8-bit, so we add offset 0x100 to the addresses 292 * behind the secondary slave 0x4c. The 'wrapper' regmap can then detect the 293 * correct slave address based on the register address and call regmap_write() 294 * and regmap_read() using correct 'real' regmap. This way the registers of 295 * both of the slaves can be accessed using one 'wrapper' regmap. 296 * 297 * NOTE: The added offsets mean that the defined addresses for slave 0x4c must 298 * be used through the 'wrapper' regmap because the offset must be stripped 299 * from the register addresses. The 0x4b can be accessed both indirectly using 300 * the 'wrapper' regmap, and directly using the 'real' regmap. 301 */ 302 #define BD72720_SECONDARY_I2C_SLAVE 0x4c 303 #define BD72720_SECONDARY_I2C_REG_OFFSET 0x100 304 305 struct bd72720_regmaps { 306 struct regmap *map1_4b; 307 struct regmap *map2_4c; 308 }; 309 310 /* Translate the slave 0x4c wrapper register address to a real one */ 311 #define BD72720_REG_UNWRAP(reg) ((reg) - BD72720_SECONDARY_I2C_REG_OFFSET) 312 313 /* Ranges given to 'real' 0x4c regmap must use unwrapped addresses. */ 314 #define BD72720_UNWRAP_REG_RANGE(startreg, endreg) \ 315 regmap_reg_range(BD72720_REG_UNWRAP(startreg), BD72720_REG_UNWRAP(endreg)) 316 317 static const struct regmap_range bd72720_volatile_ranges_4c[] = { 318 /* Status information */ 319 BD72720_UNWRAP_REG_RANGE(BD72720_REG_CHG_STATE, BD72720_REG_CHG_EN), 320 /* 321 * Under certain circumstances, write to some bits may be 322 * ignored 323 */ 324 BD72720_UNWRAP_REG_RANGE(BD72720_REG_CHG_CTRL, BD72720_REG_CHG_CTRL), 325 /* 326 * TODO: Ensure this is used to advertise state, not (only?) to 327 * control it. 328 */ 329 BD72720_UNWRAP_REG_RANGE(BD72720_REG_VSYS_STATE_STAT, BD72720_REG_VSYS_STATE_STAT), 330 /* Measured data */ 331 BD72720_UNWRAP_REG_RANGE(BD72720_REG_VM_VBAT_U, BD72720_REG_VM_VF_L), 332 /* Self clearing bits */ 333 BD72720_UNWRAP_REG_RANGE(BD72720_REG_VM_VSYS_SA_MINMAX_CTRL, 334 BD72720_REG_VM_VSYS_SA_MINMAX_CTRL), 335 /* Counters, self clearing bits */ 336 BD72720_UNWRAP_REG_RANGE(BD72720_REG_CC_CURCD_U, BD72720_REG_CC_CTRL), 337 /* Self clearing bits */ 338 BD72720_UNWRAP_REG_RANGE(BD72720_REG_CC_CCNTD_CTRL, BD72720_REG_CC_CCNTD_CTRL), 339 /* Self clearing bits */ 340 BD72720_UNWRAP_REG_RANGE(BD72720_REG_IMPCHK_CTRL, BD72720_REG_IMPCHK_CTRL), 341 }; 342 343 static const struct regmap_access_table bd71815_volatile_regs = { 344 .yes_ranges = &bd71815_volatile_ranges[0], 345 .n_yes_ranges = ARRAY_SIZE(bd71815_volatile_ranges), 346 }; 347 348 static const struct regmap_access_table bd71828_volatile_regs = { 349 .yes_ranges = &bd71828_volatile_ranges[0], 350 .n_yes_ranges = ARRAY_SIZE(bd71828_volatile_ranges), 351 }; 352 353 static const struct regmap_access_table bd72720_volatile_regs_4b = { 354 .yes_ranges = &bd72720_volatile_ranges_4b[0], 355 .n_yes_ranges = ARRAY_SIZE(bd72720_volatile_ranges_4b), 356 }; 357 358 static const struct regmap_access_table bd72720_precious_regs_4b = { 359 .yes_ranges = &bd72720_precious_ranges_4b[0], 360 .n_yes_ranges = ARRAY_SIZE(bd72720_precious_ranges_4b), 361 }; 362 363 static const struct regmap_access_table bd72720_volatile_regs_4c = { 364 .yes_ranges = &bd72720_volatile_ranges_4c[0], 365 .n_yes_ranges = ARRAY_SIZE(bd72720_volatile_ranges_4c), 366 }; 367 368 static const struct regmap_config bd71815_regmap = { 369 .reg_bits = 8, 370 .val_bits = 8, 371 .volatile_table = &bd71815_volatile_regs, 372 .max_register = BD71815_MAX_REGISTER - 1, 373 .cache_type = REGCACHE_MAPLE, 374 }; 375 376 static const struct regmap_config bd71828_regmap = { 377 .reg_bits = 8, 378 .val_bits = 8, 379 .volatile_table = &bd71828_volatile_regs, 380 .max_register = BD71828_MAX_REGISTER, 381 .cache_type = REGCACHE_MAPLE, 382 }; 383 384 static int regmap_write_wrapper(void *context, unsigned int reg, unsigned int val) 385 { 386 struct bd72720_regmaps *maps = context; 387 388 if (reg < BD72720_SECONDARY_I2C_REG_OFFSET) 389 return regmap_write(maps->map1_4b, reg, val); 390 391 reg = BD72720_REG_UNWRAP(reg); 392 393 return regmap_write(maps->map2_4c, reg, val); 394 } 395 396 static int regmap_read_wrapper(void *context, unsigned int reg, unsigned int *val) 397 { 398 struct bd72720_regmaps *maps = context; 399 400 if (reg < BD72720_SECONDARY_I2C_REG_OFFSET) 401 return regmap_read(maps->map1_4b, reg, val); 402 403 reg = BD72720_REG_UNWRAP(reg); 404 405 return regmap_read(maps->map2_4c, reg, val); 406 } 407 408 static const struct regmap_config bd72720_wrapper_map_config = { 409 .name = "wrap-map", 410 .reg_bits = 9, 411 .val_bits = 8, 412 .max_register = BD72720_REG_IMPCHK_CTRL, 413 /* 414 * We don't want to duplicate caches. It would be a bit faster to 415 * have the cache in this 'wrapper regmap', and not in the 'real 416 * regmaps' bd72720_regmap_4b and bd72720_regmap_4c below. This would 417 * require all the subdevices to use the wrapper-map in order to be 418 * able to benefit from the cache. 419 * Currently most of the sub-devices use only the same slave-address 420 * as this MFD driver. Now, because we don't add the offset to the 421 * registers belonging to this slave, those devices can use either the 422 * wrapper map, or the bd72720_regmap_4b directly. This means majority 423 * of our sub devices don't need to care which regmap they get using 424 * the dev_get_regmap(). This unifies the code between the BD72720 and 425 * those variants which don't have this 'multiple slave addresses' 426 * -hassle. 427 * So, for a small performance penalty, we simplify the code for the 428 * sub-devices by having the caches in the wrapped regmaps and not here. 429 */ 430 .cache_type = REGCACHE_NONE, 431 .reg_write = regmap_write_wrapper, 432 .reg_read = regmap_read_wrapper, 433 }; 434 435 static const struct regmap_config bd72720_regmap_4b = { 436 .reg_bits = 8, 437 .val_bits = 8, 438 .volatile_table = &bd72720_volatile_regs_4b, 439 .precious_table = &bd72720_precious_regs_4b, 440 .max_register = BD72720_REG_INT_ETC2_SRC, 441 .cache_type = REGCACHE_MAPLE, 442 }; 443 444 static const struct regmap_config bd72720_regmap_4c = { 445 .reg_bits = 8, 446 .val_bits = 8, 447 .volatile_table = &bd72720_volatile_regs_4c, 448 .max_register = BD72720_REG_UNWRAP(BD72720_REG_IMPCHK_CTRL), 449 .cache_type = REGCACHE_MAPLE, 450 }; 451 452 /* 453 * Mapping of main IRQ register bits to sub-IRQ register offsets so that we can 454 * access corect sub-IRQ registers based on bits that are set in main IRQ 455 * register. BD71815 and BD71828 have same sub-register-block offests, the 456 * BD72720 has a different one. 457 */ 458 459 static unsigned int bit0_offsets[] = {11}; /* RTC IRQ */ 460 static unsigned int bit1_offsets[] = {10}; /* TEMP IRQ */ 461 static unsigned int bit2_offsets[] = {6, 7, 8, 9}; /* BAT MON IRQ */ 462 static unsigned int bit3_offsets[] = {5}; /* BAT IRQ */ 463 static unsigned int bit4_offsets[] = {4}; /* CHG IRQ */ 464 static unsigned int bit5_offsets[] = {3}; /* VSYS IRQ */ 465 static unsigned int bit6_offsets[] = {1, 2}; /* DCIN IRQ */ 466 static unsigned int bit7_offsets[] = {0}; /* BUCK IRQ */ 467 468 static unsigned int bd72720_bit0_offsets[] = {0, 1}; /* PS1 and PS2 */ 469 static unsigned int bd72720_bit1_offsets[] = {2, 3}; /* DVS1 and DVS2 */ 470 static unsigned int bd72720_bit2_offsets[] = {4}; /* VBUS */ 471 static unsigned int bd72720_bit3_offsets[] = {5}; /* VSYS */ 472 static unsigned int bd72720_bit4_offsets[] = {6}; /* CHG */ 473 static unsigned int bd72720_bit5_offsets[] = {7, 8}; /* BAT1 and BAT2 */ 474 static unsigned int bd72720_bit6_offsets[] = {9}; /* IBAT */ 475 static unsigned int bd72720_bit7_offsets[] = {10, 11}; /* ETC1 and ETC2 */ 476 477 static const struct regmap_irq_sub_irq_map bd718xx_sub_irq_offsets[] = { 478 REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets), 479 REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets), 480 REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets), 481 REGMAP_IRQ_MAIN_REG_OFFSET(bit3_offsets), 482 REGMAP_IRQ_MAIN_REG_OFFSET(bit4_offsets), 483 REGMAP_IRQ_MAIN_REG_OFFSET(bit5_offsets), 484 REGMAP_IRQ_MAIN_REG_OFFSET(bit6_offsets), 485 REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets), 486 }; 487 488 static const struct regmap_irq_sub_irq_map bd72720_sub_irq_offsets[] = { 489 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit0_offsets), 490 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit1_offsets), 491 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit2_offsets), 492 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit3_offsets), 493 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit4_offsets), 494 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit5_offsets), 495 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit6_offsets), 496 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit7_offsets), 497 }; 498 499 static const struct regmap_irq bd71815_irqs[] = { 500 REGMAP_IRQ_REG(BD71815_INT_BUCK1_OCP, 0, BD71815_INT_BUCK1_OCP_MASK), 501 REGMAP_IRQ_REG(BD71815_INT_BUCK2_OCP, 0, BD71815_INT_BUCK2_OCP_MASK), 502 REGMAP_IRQ_REG(BD71815_INT_BUCK3_OCP, 0, BD71815_INT_BUCK3_OCP_MASK), 503 REGMAP_IRQ_REG(BD71815_INT_BUCK4_OCP, 0, BD71815_INT_BUCK4_OCP_MASK), 504 REGMAP_IRQ_REG(BD71815_INT_BUCK5_OCP, 0, BD71815_INT_BUCK5_OCP_MASK), 505 REGMAP_IRQ_REG(BD71815_INT_LED_OVP, 0, BD71815_INT_LED_OVP_MASK), 506 REGMAP_IRQ_REG(BD71815_INT_LED_OCP, 0, BD71815_INT_LED_OCP_MASK), 507 REGMAP_IRQ_REG(BD71815_INT_LED_SCP, 0, BD71815_INT_LED_SCP_MASK), 508 /* DCIN1 interrupts */ 509 REGMAP_IRQ_REG(BD71815_INT_DCIN_RMV, 1, BD71815_INT_DCIN_RMV_MASK), 510 REGMAP_IRQ_REG(BD71815_INT_CLPS_OUT, 1, BD71815_INT_CLPS_OUT_MASK), 511 REGMAP_IRQ_REG(BD71815_INT_CLPS_IN, 1, BD71815_INT_CLPS_IN_MASK), 512 REGMAP_IRQ_REG(BD71815_INT_DCIN_OVP_RES, 1, BD71815_INT_DCIN_OVP_RES_MASK), 513 REGMAP_IRQ_REG(BD71815_INT_DCIN_OVP_DET, 1, BD71815_INT_DCIN_OVP_DET_MASK), 514 /* DCIN2 interrupts */ 515 REGMAP_IRQ_REG(BD71815_INT_DCIN_MON_RES, 2, BD71815_INT_DCIN_MON_RES_MASK), 516 REGMAP_IRQ_REG(BD71815_INT_DCIN_MON_DET, 2, BD71815_INT_DCIN_MON_DET_MASK), 517 REGMAP_IRQ_REG(BD71815_INT_WDOG, 2, BD71815_INT_WDOG_MASK), 518 /* Vsys */ 519 REGMAP_IRQ_REG(BD71815_INT_VSYS_UV_RES, 3, BD71815_INT_VSYS_UV_RES_MASK), 520 REGMAP_IRQ_REG(BD71815_INT_VSYS_UV_DET, 3, BD71815_INT_VSYS_UV_DET_MASK), 521 REGMAP_IRQ_REG(BD71815_INT_VSYS_LOW_RES, 3, BD71815_INT_VSYS_LOW_RES_MASK), 522 REGMAP_IRQ_REG(BD71815_INT_VSYS_LOW_DET, 3, BD71815_INT_VSYS_LOW_DET_MASK), 523 REGMAP_IRQ_REG(BD71815_INT_VSYS_MON_RES, 3, BD71815_INT_VSYS_MON_RES_MASK), 524 REGMAP_IRQ_REG(BD71815_INT_VSYS_MON_DET, 3, BD71815_INT_VSYS_MON_DET_MASK), 525 /* Charger */ 526 REGMAP_IRQ_REG(BD71815_INT_CHG_WDG_TEMP, 4, BD71815_INT_CHG_WDG_TEMP_MASK), 527 REGMAP_IRQ_REG(BD71815_INT_CHG_WDG_TIME, 4, BD71815_INT_CHG_WDG_TIME_MASK), 528 REGMAP_IRQ_REG(BD71815_INT_CHG_RECHARGE_RES, 4, BD71815_INT_CHG_RECHARGE_RES_MASK), 529 REGMAP_IRQ_REG(BD71815_INT_CHG_RECHARGE_DET, 4, BD71815_INT_CHG_RECHARGE_DET_MASK), 530 REGMAP_IRQ_REG(BD71815_INT_CHG_RANGED_TEMP_TRANSITION, 4, 531 BD71815_INT_CHG_RANGED_TEMP_TRANSITION_MASK), 532 REGMAP_IRQ_REG(BD71815_INT_CHG_STATE_TRANSITION, 4, BD71815_INT_CHG_STATE_TRANSITION_MASK), 533 /* Battery */ 534 REGMAP_IRQ_REG(BD71815_INT_BAT_TEMP_NORMAL, 5, BD71815_INT_BAT_TEMP_NORMAL_MASK), 535 REGMAP_IRQ_REG(BD71815_INT_BAT_TEMP_ERANGE, 5, BD71815_INT_BAT_TEMP_ERANGE_MASK), 536 REGMAP_IRQ_REG(BD71815_INT_BAT_REMOVED, 5, BD71815_INT_BAT_REMOVED_MASK), 537 REGMAP_IRQ_REG(BD71815_INT_BAT_DETECTED, 5, BD71815_INT_BAT_DETECTED_MASK), 538 REGMAP_IRQ_REG(BD71815_INT_THERM_REMOVED, 5, BD71815_INT_THERM_REMOVED_MASK), 539 REGMAP_IRQ_REG(BD71815_INT_THERM_DETECTED, 5, BD71815_INT_THERM_DETECTED_MASK), 540 /* Battery Mon 1 */ 541 REGMAP_IRQ_REG(BD71815_INT_BAT_DEAD, 6, BD71815_INT_BAT_DEAD_MASK), 542 REGMAP_IRQ_REG(BD71815_INT_BAT_SHORTC_RES, 6, BD71815_INT_BAT_SHORTC_RES_MASK), 543 REGMAP_IRQ_REG(BD71815_INT_BAT_SHORTC_DET, 6, BD71815_INT_BAT_SHORTC_DET_MASK), 544 REGMAP_IRQ_REG(BD71815_INT_BAT_LOW_VOLT_RES, 6, BD71815_INT_BAT_LOW_VOLT_RES_MASK), 545 REGMAP_IRQ_REG(BD71815_INT_BAT_LOW_VOLT_DET, 6, BD71815_INT_BAT_LOW_VOLT_DET_MASK), 546 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_VOLT_RES, 6, BD71815_INT_BAT_OVER_VOLT_RES_MASK), 547 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_VOLT_DET, 6, BD71815_INT_BAT_OVER_VOLT_DET_MASK), 548 /* Battery Mon 2 */ 549 REGMAP_IRQ_REG(BD71815_INT_BAT_MON_RES, 7, BD71815_INT_BAT_MON_RES_MASK), 550 REGMAP_IRQ_REG(BD71815_INT_BAT_MON_DET, 7, BD71815_INT_BAT_MON_DET_MASK), 551 /* Battery Mon 3 (Coulomb counter) */ 552 REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON1, 8, BD71815_INT_BAT_CC_MON1_MASK), 553 REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON2, 8, BD71815_INT_BAT_CC_MON2_MASK), 554 REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON3, 8, BD71815_INT_BAT_CC_MON3_MASK), 555 /* Battery Mon 4 */ 556 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_1_RES, 9, BD71815_INT_BAT_OVER_CURR_1_RES_MASK), 557 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_1_DET, 9, BD71815_INT_BAT_OVER_CURR_1_DET_MASK), 558 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_2_RES, 9, BD71815_INT_BAT_OVER_CURR_2_RES_MASK), 559 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_2_DET, 9, BD71815_INT_BAT_OVER_CURR_2_DET_MASK), 560 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_3_RES, 9, BD71815_INT_BAT_OVER_CURR_3_RES_MASK), 561 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_3_DET, 9, BD71815_INT_BAT_OVER_CURR_3_DET_MASK), 562 /* Temperature */ 563 REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_LOW_RES, 10, BD71815_INT_TEMP_BAT_LOW_RES_MASK), 564 REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_LOW_DET, 10, BD71815_INT_TEMP_BAT_LOW_DET_MASK), 565 REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_HI_RES, 10, BD71815_INT_TEMP_BAT_HI_RES_MASK), 566 REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_HI_DET, 10, BD71815_INT_TEMP_BAT_HI_DET_MASK), 567 REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_125_RES, 10, 568 BD71815_INT_TEMP_CHIP_OVER_125_RES_MASK), 569 REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_125_DET, 10, 570 BD71815_INT_TEMP_CHIP_OVER_125_DET_MASK), 571 REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_VF_RES, 10, 572 BD71815_INT_TEMP_CHIP_OVER_VF_RES_MASK), 573 REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_VF_DET, 10, 574 BD71815_INT_TEMP_CHIP_OVER_VF_DET_MASK), 575 /* RTC Alarm */ 576 REGMAP_IRQ_REG(BD71815_INT_RTC0, 11, BD71815_INT_RTC0_MASK), 577 REGMAP_IRQ_REG(BD71815_INT_RTC1, 11, BD71815_INT_RTC1_MASK), 578 REGMAP_IRQ_REG(BD71815_INT_RTC2, 11, BD71815_INT_RTC2_MASK), 579 }; 580 581 static const struct regmap_irq bd71828_irqs[] = { 582 REGMAP_IRQ_REG(BD71828_INT_BUCK1_OCP, 0, BD71828_INT_BUCK1_OCP_MASK), 583 REGMAP_IRQ_REG(BD71828_INT_BUCK2_OCP, 0, BD71828_INT_BUCK2_OCP_MASK), 584 REGMAP_IRQ_REG(BD71828_INT_BUCK3_OCP, 0, BD71828_INT_BUCK3_OCP_MASK), 585 REGMAP_IRQ_REG(BD71828_INT_BUCK4_OCP, 0, BD71828_INT_BUCK4_OCP_MASK), 586 REGMAP_IRQ_REG(BD71828_INT_BUCK5_OCP, 0, BD71828_INT_BUCK5_OCP_MASK), 587 REGMAP_IRQ_REG(BD71828_INT_BUCK6_OCP, 0, BD71828_INT_BUCK6_OCP_MASK), 588 REGMAP_IRQ_REG(BD71828_INT_BUCK7_OCP, 0, BD71828_INT_BUCK7_OCP_MASK), 589 REGMAP_IRQ_REG(BD71828_INT_PGFAULT, 0, BD71828_INT_PGFAULT_MASK), 590 /* DCIN1 interrupts */ 591 REGMAP_IRQ_REG(BD71828_INT_DCIN_DET, 1, BD71828_INT_DCIN_DET_MASK), 592 REGMAP_IRQ_REG(BD71828_INT_DCIN_RMV, 1, BD71828_INT_DCIN_RMV_MASK), 593 REGMAP_IRQ_REG(BD71828_INT_CLPS_OUT, 1, BD71828_INT_CLPS_OUT_MASK), 594 REGMAP_IRQ_REG(BD71828_INT_CLPS_IN, 1, BD71828_INT_CLPS_IN_MASK), 595 /* DCIN2 interrupts */ 596 REGMAP_IRQ_REG(BD71828_INT_DCIN_MON_RES, 2, BD71828_INT_DCIN_MON_RES_MASK), 597 REGMAP_IRQ_REG(BD71828_INT_DCIN_MON_DET, 2, BD71828_INT_DCIN_MON_DET_MASK), 598 REGMAP_IRQ_REG(BD71828_INT_LONGPUSH, 2, BD71828_INT_LONGPUSH_MASK), 599 REGMAP_IRQ_REG(BD71828_INT_MIDPUSH, 2, BD71828_INT_MIDPUSH_MASK), 600 REGMAP_IRQ_REG(BD71828_INT_SHORTPUSH, 2, BD71828_INT_SHORTPUSH_MASK), 601 REGMAP_IRQ_REG(BD71828_INT_PUSH, 2, BD71828_INT_PUSH_MASK), 602 REGMAP_IRQ_REG(BD71828_INT_WDOG, 2, BD71828_INT_WDOG_MASK), 603 REGMAP_IRQ_REG(BD71828_INT_SWRESET, 2, BD71828_INT_SWRESET_MASK), 604 /* Vsys */ 605 REGMAP_IRQ_REG(BD71828_INT_VSYS_UV_RES, 3, BD71828_INT_VSYS_UV_RES_MASK), 606 REGMAP_IRQ_REG(BD71828_INT_VSYS_UV_DET, 3, BD71828_INT_VSYS_UV_DET_MASK), 607 REGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_RES, 3, BD71828_INT_VSYS_LOW_RES_MASK), 608 REGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_DET, 3, BD71828_INT_VSYS_LOW_DET_MASK), 609 REGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_IN, 3, BD71828_INT_VSYS_HALL_IN_MASK), 610 REGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_TOGGLE, 3, BD71828_INT_VSYS_HALL_TOGGLE_MASK), 611 REGMAP_IRQ_REG(BD71828_INT_VSYS_MON_RES, 3, BD71828_INT_VSYS_MON_RES_MASK), 612 REGMAP_IRQ_REG(BD71828_INT_VSYS_MON_DET, 3, BD71828_INT_VSYS_MON_DET_MASK), 613 /* Charger */ 614 REGMAP_IRQ_REG(BD71828_INT_CHG_DCIN_ILIM, 4, BD71828_INT_CHG_DCIN_ILIM_MASK), 615 REGMAP_IRQ_REG(BD71828_INT_CHG_TOPOFF_TO_DONE, 4, BD71828_INT_CHG_TOPOFF_TO_DONE_MASK), 616 REGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TEMP, 4, BD71828_INT_CHG_WDG_TEMP_MASK), 617 REGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TIME, 4, BD71828_INT_CHG_WDG_TIME_MASK), 618 REGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_RES, 4, BD71828_INT_CHG_RECHARGE_RES_MASK), 619 REGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_DET, 4, BD71828_INT_CHG_RECHARGE_DET_MASK), 620 REGMAP_IRQ_REG(BD71828_INT_CHG_RANGED_TEMP_TRANSITION, 4, 621 BD71828_INT_CHG_RANGED_TEMP_TRANSITION_MASK), 622 REGMAP_IRQ_REG(BD71828_INT_CHG_STATE_TRANSITION, 4, BD71828_INT_CHG_STATE_TRANSITION_MASK), 623 /* Battery */ 624 REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_NORMAL, 5, BD71828_INT_BAT_TEMP_NORMAL_MASK), 625 REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_ERANGE, 5, BD71828_INT_BAT_TEMP_ERANGE_MASK), 626 REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_WARN, 5, BD71828_INT_BAT_TEMP_WARN_MASK), 627 REGMAP_IRQ_REG(BD71828_INT_BAT_REMOVED, 5, BD71828_INT_BAT_REMOVED_MASK), 628 REGMAP_IRQ_REG(BD71828_INT_BAT_DETECTED, 5, BD71828_INT_BAT_DETECTED_MASK), 629 REGMAP_IRQ_REG(BD71828_INT_THERM_REMOVED, 5, BD71828_INT_THERM_REMOVED_MASK), 630 REGMAP_IRQ_REG(BD71828_INT_THERM_DETECTED, 5, BD71828_INT_THERM_DETECTED_MASK), 631 /* Battery Mon 1 */ 632 REGMAP_IRQ_REG(BD71828_INT_BAT_DEAD, 6, BD71828_INT_BAT_DEAD_MASK), 633 REGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_RES, 6, BD71828_INT_BAT_SHORTC_RES_MASK), 634 REGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_DET, 6, BD71828_INT_BAT_SHORTC_DET_MASK), 635 REGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_RES, 6, BD71828_INT_BAT_LOW_VOLT_RES_MASK), 636 REGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_DET, 6, BD71828_INT_BAT_LOW_VOLT_DET_MASK), 637 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_RES, 6, BD71828_INT_BAT_OVER_VOLT_RES_MASK), 638 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_DET, 6, BD71828_INT_BAT_OVER_VOLT_DET_MASK), 639 /* Battery Mon 2 */ 640 REGMAP_IRQ_REG(BD71828_INT_BAT_MON_RES, 7, BD71828_INT_BAT_MON_RES_MASK), 641 REGMAP_IRQ_REG(BD71828_INT_BAT_MON_DET, 7, BD71828_INT_BAT_MON_DET_MASK), 642 /* Battery Mon 3 (Coulomb counter) */ 643 REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON1, 8, BD71828_INT_BAT_CC_MON1_MASK), 644 REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON2, 8, BD71828_INT_BAT_CC_MON2_MASK), 645 REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON3, 8, BD71828_INT_BAT_CC_MON3_MASK), 646 /* Battery Mon 4 */ 647 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_RES, 9, BD71828_INT_BAT_OVER_CURR_1_RES_MASK), 648 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_DET, 9, BD71828_INT_BAT_OVER_CURR_1_DET_MASK), 649 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_RES, 9, BD71828_INT_BAT_OVER_CURR_2_RES_MASK), 650 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_DET, 9, BD71828_INT_BAT_OVER_CURR_2_DET_MASK), 651 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_RES, 9, BD71828_INT_BAT_OVER_CURR_3_RES_MASK), 652 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_DET, 9, BD71828_INT_BAT_OVER_CURR_3_DET_MASK), 653 /* Temperature */ 654 REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_RES, 10, BD71828_INT_TEMP_BAT_LOW_RES_MASK), 655 REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_DET, 10, BD71828_INT_TEMP_BAT_LOW_DET_MASK), 656 REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_RES, 10, BD71828_INT_TEMP_BAT_HI_RES_MASK), 657 REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_DET, 10, BD71828_INT_TEMP_BAT_HI_DET_MASK), 658 REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_125_RES, 10, 659 BD71828_INT_TEMP_CHIP_OVER_125_RES_MASK), 660 REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_125_DET, 10, 661 BD71828_INT_TEMP_CHIP_OVER_125_DET_MASK), 662 REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_VF_DET, 10, 663 BD71828_INT_TEMP_CHIP_OVER_VF_DET_MASK), 664 REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_VF_RES, 10, 665 BD71828_INT_TEMP_CHIP_OVER_VF_RES_MASK), 666 /* RTC Alarm */ 667 REGMAP_IRQ_REG(BD71828_INT_RTC0, 11, BD71828_INT_RTC0_MASK), 668 REGMAP_IRQ_REG(BD71828_INT_RTC1, 11, BD71828_INT_RTC1_MASK), 669 REGMAP_IRQ_REG(BD71828_INT_RTC2, 11, BD71828_INT_RTC2_MASK), 670 }; 671 672 static const struct regmap_irq bd72720_irqs[] = { 673 REGMAP_IRQ_REG(BD72720_INT_LONGPUSH, 0, BD72720_INT_LONGPUSH_MASK), 674 REGMAP_IRQ_REG(BD72720_INT_MIDPUSH, 0, BD72720_INT_MIDPUSH_MASK), 675 REGMAP_IRQ_REG(BD72720_INT_SHORTPUSH, 0, BD72720_INT_SHORTPUSH_MASK), 676 REGMAP_IRQ_REG(BD72720_INT_PUSH, 0, BD72720_INT_PUSH_MASK), 677 REGMAP_IRQ_REG(BD72720_INT_HALL_DET, 0, BD72720_INT_HALL_DET_MASK), 678 REGMAP_IRQ_REG(BD72720_INT_HALL_TGL, 0, BD72720_INT_HALL_TGL_MASK), 679 REGMAP_IRQ_REG(BD72720_INT_WDOG, 0, BD72720_INT_WDOG_MASK), 680 REGMAP_IRQ_REG(BD72720_INT_SWRESET, 0, BD72720_INT_SWRESET_MASK), 681 REGMAP_IRQ_REG(BD72720_INT_SEQ_DONE, 1, BD72720_INT_SEQ_DONE_MASK), 682 REGMAP_IRQ_REG(BD72720_INT_PGFAULT, 1, BD72720_INT_PGFAULT_MASK), 683 REGMAP_IRQ_REG(BD72720_INT_BUCK1_DVS, 2, BD72720_INT_BUCK1_DVS_MASK), 684 REGMAP_IRQ_REG(BD72720_INT_BUCK2_DVS, 2, BD72720_INT_BUCK2_DVS_MASK), 685 REGMAP_IRQ_REG(BD72720_INT_BUCK3_DVS, 2, BD72720_INT_BUCK3_DVS_MASK), 686 REGMAP_IRQ_REG(BD72720_INT_BUCK4_DVS, 2, BD72720_INT_BUCK4_DVS_MASK), 687 REGMAP_IRQ_REG(BD72720_INT_BUCK5_DVS, 2, BD72720_INT_BUCK5_DVS_MASK), 688 REGMAP_IRQ_REG(BD72720_INT_BUCK6_DVS, 2, BD72720_INT_BUCK6_DVS_MASK), 689 REGMAP_IRQ_REG(BD72720_INT_BUCK7_DVS, 2, BD72720_INT_BUCK7_DVS_MASK), 690 REGMAP_IRQ_REG(BD72720_INT_BUCK8_DVS, 2, BD72720_INT_BUCK8_DVS_MASK), 691 REGMAP_IRQ_REG(BD72720_INT_BUCK9_DVS, 3, BD72720_INT_BUCK9_DVS_MASK), 692 REGMAP_IRQ_REG(BD72720_INT_BUCK10_DVS, 3, BD72720_INT_BUCK10_DVS_MASK), 693 REGMAP_IRQ_REG(BD72720_INT_LDO1_DVS, 3, BD72720_INT_LDO1_DVS_MASK), 694 REGMAP_IRQ_REG(BD72720_INT_LDO2_DVS, 3, BD72720_INT_LDO2_DVS_MASK), 695 REGMAP_IRQ_REG(BD72720_INT_LDO3_DVS, 3, BD72720_INT_LDO3_DVS_MASK), 696 REGMAP_IRQ_REG(BD72720_INT_LDO4_DVS, 3, BD72720_INT_LDO4_DVS_MASK), 697 698 REGMAP_IRQ_REG(BD72720_INT_VBUS_RMV, 4, BD72720_INT_VBUS_RMV_MASK), 699 REGMAP_IRQ_REG(BD72720_INT_VBUS_DET, 4, BD72720_INT_VBUS_DET_MASK), 700 REGMAP_IRQ_REG(BD72720_INT_VBUS_MON_RES, 4, BD72720_INT_VBUS_MON_RES_MASK), 701 REGMAP_IRQ_REG(BD72720_INT_VBUS_MON_DET, 4, BD72720_INT_VBUS_MON_DET_MASK), 702 REGMAP_IRQ_REG(BD72720_INT_VSYS_MON_RES, 5, BD72720_INT_VSYS_MON_RES_MASK), 703 REGMAP_IRQ_REG(BD72720_INT_VSYS_MON_DET, 5, BD72720_INT_VSYS_MON_DET_MASK), 704 REGMAP_IRQ_REG(BD72720_INT_VSYS_UV_RES, 5, BD72720_INT_VSYS_UV_RES_MASK), 705 REGMAP_IRQ_REG(BD72720_INT_VSYS_UV_DET, 5, BD72720_INT_VSYS_UV_DET_MASK), 706 REGMAP_IRQ_REG(BD72720_INT_VSYS_LO_RES, 5, BD72720_INT_VSYS_LO_RES_MASK), 707 REGMAP_IRQ_REG(BD72720_INT_VSYS_LO_DET, 5, BD72720_INT_VSYS_LO_DET_MASK), 708 REGMAP_IRQ_REG(BD72720_INT_VSYS_OV_RES, 5, BD72720_INT_VSYS_OV_RES_MASK), 709 REGMAP_IRQ_REG(BD72720_INT_VSYS_OV_DET, 5, BD72720_INT_VSYS_OV_DET_MASK), 710 REGMAP_IRQ_REG(BD72720_INT_BAT_ILIM, 6, BD72720_INT_BAT_ILIM_MASK), 711 REGMAP_IRQ_REG(BD72720_INT_CHG_DONE, 6, BD72720_INT_CHG_DONE_MASK), 712 REGMAP_IRQ_REG(BD72720_INT_EXTEMP_TOUT, 6, BD72720_INT_EXTEMP_TOUT_MASK), 713 REGMAP_IRQ_REG(BD72720_INT_CHG_WDT_EXP, 6, BD72720_INT_CHG_WDT_EXP_MASK), 714 REGMAP_IRQ_REG(BD72720_INT_BAT_MNT_OUT, 6, BD72720_INT_BAT_MNT_OUT_MASK), 715 REGMAP_IRQ_REG(BD72720_INT_BAT_MNT_IN, 6, BD72720_INT_BAT_MNT_IN_MASK), 716 REGMAP_IRQ_REG(BD72720_INT_CHG_TRNS, 6, BD72720_INT_CHG_TRNS_MASK), 717 718 REGMAP_IRQ_REG(BD72720_INT_VBAT_MON_RES, 7, BD72720_INT_VBAT_MON_RES_MASK), 719 REGMAP_IRQ_REG(BD72720_INT_VBAT_MON_DET, 7, BD72720_INT_VBAT_MON_DET_MASK), 720 REGMAP_IRQ_REG(BD72720_INT_VBAT_SHT_RES, 7, BD72720_INT_VBAT_SHT_RES_MASK), 721 REGMAP_IRQ_REG(BD72720_INT_VBAT_SHT_DET, 7, BD72720_INT_VBAT_SHT_DET_MASK), 722 REGMAP_IRQ_REG(BD72720_INT_VBAT_LO_RES, 7, BD72720_INT_VBAT_LO_RES_MASK), 723 REGMAP_IRQ_REG(BD72720_INT_VBAT_LO_DET, 7, BD72720_INT_VBAT_LO_DET_MASK), 724 REGMAP_IRQ_REG(BD72720_INT_VBAT_OV_RES, 7, BD72720_INT_VBAT_OV_RES_MASK), 725 REGMAP_IRQ_REG(BD72720_INT_VBAT_OV_DET, 7, BD72720_INT_VBAT_OV_DET_MASK), 726 REGMAP_IRQ_REG(BD72720_INT_BAT_RMV, 8, BD72720_INT_BAT_RMV_MASK), 727 REGMAP_IRQ_REG(BD72720_INT_BAT_DET, 8, BD72720_INT_BAT_DET_MASK), 728 REGMAP_IRQ_REG(BD72720_INT_DBAT_DET, 8, BD72720_INT_DBAT_DET_MASK), 729 REGMAP_IRQ_REG(BD72720_INT_BAT_TEMP_TRNS, 8, BD72720_INT_BAT_TEMP_TRNS_MASK), 730 REGMAP_IRQ_REG(BD72720_INT_LOBTMP_RES, 8, BD72720_INT_LOBTMP_RES_MASK), 731 REGMAP_IRQ_REG(BD72720_INT_LOBTMP_DET, 8, BD72720_INT_LOBTMP_DET_MASK), 732 REGMAP_IRQ_REG(BD72720_INT_OVBTMP_RES, 8, BD72720_INT_OVBTMP_RES_MASK), 733 REGMAP_IRQ_REG(BD72720_INT_OVBTMP_DET, 8, BD72720_INT_OVBTMP_DET_MASK), 734 REGMAP_IRQ_REG(BD72720_INT_OCUR1_RES, 9, BD72720_INT_OCUR1_RES_MASK), 735 REGMAP_IRQ_REG(BD72720_INT_OCUR1_DET, 9, BD72720_INT_OCUR1_DET_MASK), 736 REGMAP_IRQ_REG(BD72720_INT_OCUR2_RES, 9, BD72720_INT_OCUR2_RES_MASK), 737 REGMAP_IRQ_REG(BD72720_INT_OCUR2_DET, 9, BD72720_INT_OCUR2_DET_MASK), 738 REGMAP_IRQ_REG(BD72720_INT_OCUR3_RES, 9, BD72720_INT_OCUR3_RES_MASK), 739 REGMAP_IRQ_REG(BD72720_INT_OCUR3_DET, 9, BD72720_INT_OCUR3_DET_MASK), 740 REGMAP_IRQ_REG(BD72720_INT_CC_MON1_DET, 10, BD72720_INT_CC_MON1_DET_MASK), 741 REGMAP_IRQ_REG(BD72720_INT_CC_MON2_DET, 10, BD72720_INT_CC_MON2_DET_MASK), 742 REGMAP_IRQ_REG(BD72720_INT_CC_MON3_DET, 10, BD72720_INT_CC_MON3_DET_MASK), 743 /* 744 * The GPIO1_IN and GPIO2_IN IRQs are generated from the PMIC's GPIO1 and GPIO2 745 * pins. Eg, they may be wired to other devices which can then use the PMIC as 746 * an interrupt controller. The GPIO1 and GPIO2 can have the IRQ type 747 * specified. All of the types (falling, rising, and both edges as well as low 748 * and high levels) are supported. 749 */ 750 BD72720_TYPED_IRQ_REG(BD72720_INT_GPIO1_IN, 10, BD72720_INT_GPIO1_IN_MASK, 0), 751 BD72720_TYPED_IRQ_REG(BD72720_INT_GPIO2_IN, 10, BD72720_INT_GPIO2_IN_MASK, 1), 752 REGMAP_IRQ_REG(BD72720_INT_VF125_RES, 11, BD72720_INT_VF125_RES_MASK), 753 REGMAP_IRQ_REG(BD72720_INT_VF125_DET, 11, BD72720_INT_VF125_DET_MASK), 754 REGMAP_IRQ_REG(BD72720_INT_VF_RES, 11, BD72720_INT_VF_RES_MASK), 755 REGMAP_IRQ_REG(BD72720_INT_VF_DET, 11, BD72720_INT_VF_DET_MASK), 756 REGMAP_IRQ_REG(BD72720_INT_RTC0, 11, BD72720_INT_RTC0_MASK), 757 REGMAP_IRQ_REG(BD72720_INT_RTC1, 11, BD72720_INT_RTC1_MASK), 758 REGMAP_IRQ_REG(BD72720_INT_RTC2, 11, BD72720_INT_RTC2_MASK), 759 }; 760 761 static int bd72720_set_type_config(unsigned int **buf, unsigned int type, 762 const struct regmap_irq *irq_data, 763 int idx, void *irq_drv_data) 764 { 765 const struct regmap_irq_type *t = &irq_data->type; 766 767 /* 768 * The regmap IRQ ecpects IRQ_TYPE_EDGE_BOTH to be written to register 769 * as logical OR of the type_falling_val and type_rising_val. This is 770 * not how the BD72720 implements this configuration, hence we need 771 * to handle this specific case separately. 772 */ 773 if (type == IRQ_TYPE_EDGE_BOTH) { 774 buf[0][idx] &= ~t->type_reg_mask; 775 buf[0][idx] |= BD72720_GPIO_IRQ_TYPE_BOTH; 776 777 return 0; 778 } 779 780 return regmap_irq_set_type_config_simple(buf, type, irq_data, idx, irq_drv_data); 781 } 782 783 static const struct regmap_irq_chip bd71828_irq_chip = { 784 .name = "bd71828_irq", 785 .main_status = BD71828_REG_INT_MAIN, 786 .irqs = &bd71828_irqs[0], 787 .num_irqs = ARRAY_SIZE(bd71828_irqs), 788 .status_base = BD71828_REG_INT_BUCK, 789 .unmask_base = BD71828_REG_INT_MASK_BUCK, 790 .ack_base = BD71828_REG_INT_BUCK, 791 .init_ack_masked = true, 792 .num_regs = 12, 793 .num_main_regs = 1, 794 .sub_reg_offsets = &bd718xx_sub_irq_offsets[0], 795 .num_main_status_bits = 8, 796 .irq_reg_stride = 1, 797 }; 798 799 static const struct regmap_irq_chip bd71815_irq_chip = { 800 .name = "bd71815_irq", 801 .main_status = BD71815_REG_INT_STAT, 802 .irqs = &bd71815_irqs[0], 803 .num_irqs = ARRAY_SIZE(bd71815_irqs), 804 .status_base = BD71815_REG_INT_STAT_01, 805 .unmask_base = BD71815_REG_INT_EN_01, 806 .ack_base = BD71815_REG_INT_STAT_01, 807 .init_ack_masked = true, 808 .num_regs = 12, 809 .num_main_regs = 1, 810 .sub_reg_offsets = &bd718xx_sub_irq_offsets[0], 811 .num_main_status_bits = 8, 812 .irq_reg_stride = 1, 813 }; 814 815 static const unsigned int bd72720_irq_type_base[] = { BD72720_REG_GPIO1_CTRL }; 816 817 static const struct regmap_irq_chip bd72720_irq_chip = { 818 .name = "bd72720_irq", 819 .main_status = BD72720_REG_INT_LVL1_STAT, 820 .irqs = &bd72720_irqs[0], 821 .num_irqs = ARRAY_SIZE(bd72720_irqs), 822 .status_base = BD72720_REG_INT_PS1_STAT, 823 .unmask_base = BD72720_REG_INT_PS1_EN, 824 .config_base = &bd72720_irq_type_base[0], 825 .num_config_bases = 1, 826 .num_config_regs = 2, 827 .set_type_config = bd72720_set_type_config, 828 .ack_base = BD72720_REG_INT_PS1_STAT, 829 .init_ack_masked = true, 830 .num_regs = 12, 831 .num_main_regs = 1, 832 .sub_reg_offsets = &bd72720_sub_irq_offsets[0], 833 .num_main_status_bits = 8, 834 .irq_reg_stride = 1, 835 }; 836 837 static int set_clk_mode(struct device *dev, struct regmap *regmap, 838 int clkmode_reg) 839 { 840 int ret; 841 unsigned int open_drain; 842 843 ret = of_property_read_u32(dev->of_node, "rohm,clkout-open-drain", &open_drain); 844 if (ret) { 845 if (ret == -EINVAL) 846 return 0; 847 return ret; 848 } 849 if (open_drain > 1) { 850 dev_err(dev, "bad clk32kout mode configuration"); 851 return -EINVAL; 852 } 853 854 if (open_drain) 855 return regmap_update_bits(regmap, clkmode_reg, OUT32K_MODE, 856 OUT32K_MODE_OPEN_DRAIN); 857 858 return regmap_update_bits(regmap, clkmode_reg, OUT32K_MODE, 859 OUT32K_MODE_CMOS); 860 } 861 862 static const struct property_entry bd71828_powerkey_parent_props[] = { 863 PROPERTY_ENTRY_STRING("label", "bd71828-pwrkey"), 864 { } 865 }; 866 867 static const struct property_entry bd71828_powerkey_props[] = { 868 PROPERTY_ENTRY_U32("linux,code", KEY_POWER), 869 PROPERTY_ENTRY_BOOL("wakeup-source"), 870 { } 871 }; 872 873 #define GPIO_KEYS 0 /* Node corresponding to gpio-keys device itself */ 874 #define PWRON_KEY 1 /* Node describing power button in gpio-keys */ 875 876 static int bd71828_i2c_register_swnodes(const struct software_node *nodes) 877 { 878 const struct software_node * const node_group[] = { 879 &nodes[GPIO_KEYS], &nodes[PWRON_KEY], NULL 880 }; 881 882 return software_node_register_node_group(node_group); 883 } 884 885 static void bd71828_i2c_unregister_swnodes(void *data) 886 { 887 const struct software_node *nodes = data; 888 const struct software_node * const node_group[] = { 889 &nodes[GPIO_KEYS], &nodes[PWRON_KEY], NULL 890 }; 891 892 software_node_unregister_node_group(node_group); 893 } 894 895 static int bd71828_i2c_register_pwrbutton(struct device *dev, int button_irq, 896 struct irq_domain *irq_domain) 897 { 898 const struct resource res[] = { 899 DEFINE_RES_IRQ_NAMED(button_irq, "bd71828-pwrkey"), 900 }; 901 struct mfd_cell gpio_keys_cell = { 902 .name = "gpio-keys", 903 .resources = res, 904 .num_resources = ARRAY_SIZE(res), 905 }; 906 struct software_node *nodes; 907 int ret; 908 909 nodes = devm_kcalloc(dev, 2, sizeof(*nodes), GFP_KERNEL); 910 if (!nodes) 911 return -ENOMEM; 912 913 nodes[GPIO_KEYS].name = devm_kasprintf(dev, GFP_KERNEL, "%s-power-key", dev_name(dev)); 914 if (!nodes[GPIO_KEYS].name) 915 return -ENOMEM; 916 917 nodes[GPIO_KEYS].properties = bd71828_powerkey_parent_props; 918 919 nodes[PWRON_KEY].parent = &nodes[GPIO_KEYS]; 920 nodes[PWRON_KEY].properties = bd71828_powerkey_props; 921 922 ret = bd71828_i2c_register_swnodes(nodes); 923 if (ret) 924 return ret; 925 926 ret = devm_add_action_or_reset(dev, bd71828_i2c_unregister_swnodes, nodes); 927 if (ret) 928 return ret; 929 930 gpio_keys_cell.swnode = &nodes[GPIO_KEYS]; 931 932 ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, &gpio_keys_cell, 1, 933 NULL, 0, irq_domain); 934 if (ret) 935 return dev_err_probe(dev, ret, "Failed to register power-button"); 936 937 return 0; 938 } 939 940 static struct i2c_client *bd71828_dev; 941 static void bd71828_power_off(void) 942 { 943 while (true) { 944 s32 val; 945 946 /* We are not allowed to sleep, so do not use regmap involving mutexes here. */ 947 val = i2c_smbus_read_byte_data(bd71828_dev, BD71828_REG_PS_CTRL_1); 948 if (val >= 0) 949 i2c_smbus_write_byte_data(bd71828_dev, 950 BD71828_REG_PS_CTRL_1, 951 BD71828_MASK_STATE_HBNT | (u8)val); 952 mdelay(500); 953 } 954 } 955 956 static void bd71828_remove_poweroff(void *data) 957 { 958 pm_power_off = NULL; 959 } 960 961 static struct regmap *bd72720_do_regmaps(struct i2c_client *i2c) 962 { 963 struct bd72720_regmaps *maps; 964 struct i2c_client *secondary_i2c; 965 966 secondary_i2c = devm_i2c_new_dummy_device(&i2c->dev, i2c->adapter, 967 BD72720_SECONDARY_I2C_SLAVE); 968 if (IS_ERR(secondary_i2c)) { 969 dev_err_probe(&i2c->dev, PTR_ERR(secondary_i2c), "Failed to get secondary I2C\n"); 970 971 return ERR_CAST(secondary_i2c); 972 } 973 974 maps = devm_kzalloc(&i2c->dev, sizeof(*maps), GFP_KERNEL); 975 if (!maps) 976 return ERR_PTR(-ENOMEM); 977 978 maps->map1_4b = devm_regmap_init_i2c(i2c, &bd72720_regmap_4b); 979 if (IS_ERR(maps->map1_4b)) 980 return maps->map1_4b; 981 982 maps->map2_4c = devm_regmap_init_i2c(secondary_i2c, &bd72720_regmap_4c); 983 if (IS_ERR(maps->map2_4c)) 984 return maps->map2_4c; 985 986 return devm_regmap_init(&i2c->dev, NULL, maps, &bd72720_wrapper_map_config); 987 } 988 989 static int bd71828_i2c_probe(struct i2c_client *i2c) 990 { 991 struct regmap_irq_chip_data *irq_data; 992 struct irq_domain *irq_domain; 993 int ret; 994 struct regmap *regmap = NULL; 995 const struct regmap_config *regmap_config; 996 const struct regmap_irq_chip *irqchip; 997 unsigned int chip_type; 998 const struct mfd_cell *mfd; 999 int cells; 1000 int button_irq; 1001 int clkmode_reg; 1002 int main_lvl_mask_reg = 0, main_lvl_val = 0; 1003 1004 if (!i2c->irq) { 1005 dev_err(&i2c->dev, "No IRQ configured\n"); 1006 return -EINVAL; 1007 } 1008 1009 chip_type = (unsigned int)(uintptr_t) 1010 of_device_get_match_data(&i2c->dev); 1011 switch (chip_type) { 1012 case ROHM_CHIP_TYPE_BD71828: 1013 mfd = bd71828_mfd_cells; 1014 cells = ARRAY_SIZE(bd71828_mfd_cells); 1015 regmap_config = &bd71828_regmap; 1016 irqchip = &bd71828_irq_chip; 1017 clkmode_reg = BD71828_REG_OUT32K; 1018 button_irq = BD71828_INT_SHORTPUSH; 1019 break; 1020 case ROHM_CHIP_TYPE_BD71815: 1021 mfd = bd71815_mfd_cells; 1022 cells = ARRAY_SIZE(bd71815_mfd_cells); 1023 regmap_config = &bd71815_regmap; 1024 irqchip = &bd71815_irq_chip; 1025 clkmode_reg = BD71815_REG_OUT32K; 1026 /* 1027 * If BD71817 support is needed we should be able to handle it 1028 * with proper DT configs + BD71815 drivers + power-button. 1029 * BD71815 data-sheet does not list the power-button IRQ so we 1030 * don't use it. 1031 */ 1032 button_irq = 0; 1033 break; 1034 case ROHM_CHIP_TYPE_BD72720: 1035 { 1036 mfd = bd72720_mfd_cells; 1037 cells = ARRAY_SIZE(bd72720_mfd_cells); 1038 1039 regmap = bd72720_do_regmaps(i2c); 1040 if (IS_ERR(regmap)) 1041 return dev_err_probe(&i2c->dev, PTR_ERR(regmap), 1042 "Failed to initialize Regmap\n"); 1043 1044 irqchip = &bd72720_irq_chip; 1045 clkmode_reg = BD72720_REG_OUT32K; 1046 button_irq = BD72720_INT_SHORTPUSH; 1047 main_lvl_mask_reg = BD72720_REG_INT_LVL1_EN; 1048 main_lvl_val = BD72720_MASK_LVL1_EN_ALL; 1049 break; 1050 } 1051 default: 1052 dev_err(&i2c->dev, "Unknown device type"); 1053 return -EINVAL; 1054 } 1055 1056 if (!regmap) { 1057 regmap = devm_regmap_init_i2c(i2c, regmap_config); 1058 if (IS_ERR(regmap)) 1059 return dev_err_probe(&i2c->dev, PTR_ERR(regmap), 1060 "Failed to initialize Regmap\n"); 1061 } 1062 1063 ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, i2c->irq, 1064 IRQF_ONESHOT, 0, irqchip, &irq_data); 1065 if (ret) 1066 return dev_err_probe(&i2c->dev, ret, 1067 "Failed to add IRQ chip\n"); 1068 1069 dev_dbg(&i2c->dev, "Registered %d IRQs for chip\n", 1070 irqchip->num_irqs); 1071 1072 /* 1073 * On some ICs the main IRQ register has corresponding mask register. 1074 * This is not handled by the regmap IRQ. Let's enable all the main 1075 * level IRQs here. Further writes to the main level MASK is not 1076 * needed because masking is handled by the per IRQ 2.nd level MASK 1077 * registers. 2.nd level masks are handled by the regmap IRQ. 1078 */ 1079 if (main_lvl_mask_reg) { 1080 ret = regmap_write(regmap, main_lvl_mask_reg, main_lvl_val); 1081 if (ret) { 1082 return dev_err_probe(&i2c->dev, ret, 1083 "Failed to enable main level IRQs\n"); 1084 } 1085 } 1086 1087 ret = set_clk_mode(&i2c->dev, regmap, clkmode_reg); 1088 if (ret) 1089 return ret; 1090 1091 irq_domain = regmap_irq_get_domain(irq_data); 1092 1093 ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, mfd, cells, 1094 NULL, 0, irq_domain); 1095 if (ret) 1096 return dev_err_probe(&i2c->dev, ret, "Failed to create subdevices\n"); 1097 1098 if (button_irq) { 1099 ret = bd71828_i2c_register_pwrbutton(&i2c->dev, button_irq, irq_domain); 1100 if (ret) 1101 return ret; 1102 } 1103 1104 if (of_device_is_system_power_controller(i2c->dev.of_node) && 1105 chip_type == ROHM_CHIP_TYPE_BD71828) { 1106 if (!pm_power_off) { 1107 bd71828_dev = i2c; 1108 pm_power_off = bd71828_power_off; 1109 ret = devm_add_action_or_reset(&i2c->dev, 1110 bd71828_remove_poweroff, 1111 NULL); 1112 } else { 1113 dev_warn(&i2c->dev, "Poweroff callback already assigned\n"); 1114 } 1115 } 1116 1117 return ret; 1118 } 1119 1120 static const struct of_device_id bd71828_of_match[] = { 1121 { 1122 .compatible = "rohm,bd71828", 1123 .data = (void *)ROHM_CHIP_TYPE_BD71828, 1124 }, { 1125 .compatible = "rohm,bd71815", 1126 .data = (void *)ROHM_CHIP_TYPE_BD71815, 1127 }, { 1128 .compatible = "rohm,bd72720", 1129 .data = (void *)ROHM_CHIP_TYPE_BD72720, 1130 }, 1131 { }, 1132 }; 1133 MODULE_DEVICE_TABLE(of, bd71828_of_match); 1134 1135 static struct i2c_driver bd71828_drv = { 1136 .driver = { 1137 .name = "rohm-bd71828", 1138 .of_match_table = bd71828_of_match, 1139 }, 1140 .probe = bd71828_i2c_probe, 1141 }; 1142 module_i2c_driver(bd71828_drv); 1143 1144 MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>"); 1145 MODULE_DESCRIPTION("ROHM BD71828 Power Management IC driver"); 1146 MODULE_LICENSE("GPL"); 1147