1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2019 ROHM Semiconductors 4 * 5 * ROHM BD718[15/28/79] and BD72720 PMIC driver 6 */ 7 8 #include <linux/i2c.h> 9 #include <linux/input.h> 10 #include <linux/interrupt.h> 11 #include <linux/ioport.h> 12 #include <linux/irq.h> 13 #include <linux/mfd/core.h> 14 #include <linux/mfd/rohm-bd71815.h> 15 #include <linux/mfd/rohm-bd71828.h> 16 #include <linux/mfd/rohm-bd72720.h> 17 #include <linux/mfd/rohm-generic.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/regmap.h> 21 #include <linux/types.h> 22 23 #include "rohm-pwrbutton.h" 24 25 #define BD72720_TYPED_IRQ_REG(_irq, _stat_offset, _mask, _type_offset) \ 26 [_irq] = { \ 27 .reg_offset = (_stat_offset), \ 28 .mask = (_mask), \ 29 { \ 30 .type_reg_offset = (_type_offset), \ 31 .type_reg_mask = BD72720_GPIO_IRQ_TYPE_MASK, \ 32 .type_rising_val = BD72720_GPIO_IRQ_TYPE_RISING, \ 33 .type_falling_val = BD72720_GPIO_IRQ_TYPE_FALLING, \ 34 .type_level_low_val = BD72720_GPIO_IRQ_TYPE_LOW, \ 35 .type_level_high_val = BD72720_GPIO_IRQ_TYPE_HIGH, \ 36 .types_supported = IRQ_TYPE_EDGE_BOTH | \ 37 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW, \ 38 }, \ 39 } 40 41 static const struct resource bd71815_rtc_irqs[] = { 42 DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC0, "bd70528-rtc-alm-0"), 43 DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC1, "bd70528-rtc-alm-1"), 44 DEFINE_RES_IRQ_NAMED(BD71815_INT_RTC2, "bd70528-rtc-alm-2"), 45 }; 46 47 static const struct resource bd71828_rtc_irqs[] = { 48 DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC0, "bd70528-rtc-alm-0"), 49 DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC1, "bd70528-rtc-alm-1"), 50 DEFINE_RES_IRQ_NAMED(BD71828_INT_RTC2, "bd70528-rtc-alm-2"), 51 }; 52 53 static const struct resource bd72720_rtc_irqs[] = { 54 DEFINE_RES_IRQ_NAMED(BD72720_INT_RTC0, "bd70528-rtc-alm-0"), 55 DEFINE_RES_IRQ_NAMED(BD72720_INT_RTC1, "bd70528-rtc-alm-1"), 56 DEFINE_RES_IRQ_NAMED(BD72720_INT_RTC2, "bd70528-rtc-alm-2"), 57 }; 58 59 static const struct resource bd71815_power_irqs[] = { 60 DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_RMV, "bd71815-dcin-rmv"), 61 DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_OUT, "bd71815-dcin-clps-out"), 62 DEFINE_RES_IRQ_NAMED(BD71815_INT_CLPS_IN, "bd71815-dcin-clps-in"), 63 DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_RES, "bd71815-dcin-ovp-res"), 64 DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_OVP_DET, "bd71815-dcin-ovp-det"), 65 DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_MON_RES, "bd71815-dcin-mon-res"), 66 DEFINE_RES_IRQ_NAMED(BD71815_INT_DCIN_MON_DET, "bd71815-dcin-mon-det"), 67 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_UV_RES, "bd71815-vsys-uv-res"), 68 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_UV_DET, "bd71815-vsys-uv-det"), 69 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_RES, "bd71815-vsys-low-res"), 70 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_LOW_DET, "bd71815-vsys-low-det"), 71 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_RES, "bd71815-vsys-mon-res"), 72 DEFINE_RES_IRQ_NAMED(BD71815_INT_VSYS_MON_DET, "bd71815-vsys-mon-det"), 73 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TEMP, "bd71815-chg-wdg-temp"), 74 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_WDG_TIME, "bd71815-chg-wdg"), 75 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RECHARGE_RES, "bd71815-rechg-res"), 76 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RECHARGE_DET, "bd71815-rechg-det"), 77 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_RANGED_TEMP_TRANSITION, "bd71815-ranged-temp-transit"), 78 DEFINE_RES_IRQ_NAMED(BD71815_INT_CHG_STATE_TRANSITION, "bd71815-chg-state-change"), 79 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_TEMP_NORMAL, "bd71815-bat-temp-normal"), 80 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_TEMP_ERANGE, "bd71815-bat-temp-erange"), 81 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_REMOVED, "bd71815-bat-rmv"), 82 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_DETECTED, "bd71815-bat-det"), 83 DEFINE_RES_IRQ_NAMED(BD71815_INT_THERM_REMOVED, "bd71815-therm-rmv"), 84 DEFINE_RES_IRQ_NAMED(BD71815_INT_THERM_DETECTED, "bd71815-therm-det"), 85 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_DEAD, "bd71815-bat-dead"), 86 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_SHORTC_RES, "bd71815-bat-short-res"), 87 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_SHORTC_DET, "bd71815-bat-short-det"), 88 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_LOW_VOLT_RES, "bd71815-bat-low-res"), 89 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_LOW_VOLT_DET, "bd71815-bat-low-det"), 90 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_VOLT_RES, "bd71815-bat-over-res"), 91 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_VOLT_DET, "bd71815-bat-over-det"), 92 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_MON_RES, "bd71815-bat-mon-res"), 93 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_MON_DET, "bd71815-bat-mon-det"), 94 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON1, "bd71815-bat-cc-mon1"), 95 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON2, "bd71815-bat-cc-mon2"), 96 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_CC_MON3, "bd71815-bat-cc-mon3"), 97 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_1_RES, "bd71815-bat-oc1-res"), 98 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_1_DET, "bd71815-bat-oc1-det"), 99 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_2_RES, "bd71815-bat-oc2-res"), 100 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_2_DET, "bd71815-bat-oc2-det"), 101 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_RES, "bd71815-bat-oc3-res"), 102 DEFINE_RES_IRQ_NAMED(BD71815_INT_BAT_OVER_CURR_3_DET, "bd71815-bat-oc3-det"), 103 DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_RES, "bd71815-temp-bat-low-res"), 104 DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_LOW_DET, "bd71815-temp-bat-low-det"), 105 DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_RES, "bd71815-temp-bat-hi-res"), 106 DEFINE_RES_IRQ_NAMED(BD71815_INT_TEMP_BAT_HI_DET, "bd71815-temp-bat-hi-det"), 107 }; 108 109 static const struct mfd_cell bd71815_mfd_cells[] = { 110 { .name = "bd71815-pmic", }, 111 { .name = "bd71815-clk", }, 112 { .name = "bd71815-gpo", }, 113 { 114 .name = "bd71815-power", 115 .num_resources = ARRAY_SIZE(bd71815_power_irqs), 116 .resources = &bd71815_power_irqs[0], 117 }, 118 { 119 .name = "bd71815-rtc", 120 .num_resources = ARRAY_SIZE(bd71815_rtc_irqs), 121 .resources = &bd71815_rtc_irqs[0], 122 }, 123 }; 124 125 static const struct resource bd71828_power_irqs[] = { 126 DEFINE_RES_IRQ_NAMED(BD71828_INT_CHG_TOPOFF_TO_DONE, 127 "bd71828-chg-done"), 128 DEFINE_RES_IRQ_NAMED(BD71828_INT_DCIN_DET, "bd71828-pwr-dcin-in"), 129 DEFINE_RES_IRQ_NAMED(BD71828_INT_DCIN_RMV, "bd71828-pwr-dcin-out"), 130 DEFINE_RES_IRQ_NAMED(BD71828_INT_BAT_LOW_VOLT_RES, 131 "bd71828-vbat-normal"), 132 DEFINE_RES_IRQ_NAMED(BD71828_INT_BAT_LOW_VOLT_DET, "bd71828-vbat-low"), 133 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_HI_DET, "bd71828-btemp-hi"), 134 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_HI_RES, "bd71828-btemp-cool"), 135 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_LOW_DET, "bd71828-btemp-lo"), 136 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_BAT_LOW_RES, 137 "bd71828-btemp-warm"), 138 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_VF_DET, 139 "bd71828-temp-hi"), 140 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_VF_RES, 141 "bd71828-temp-norm"), 142 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_125_DET, 143 "bd71828-temp-125-over"), 144 DEFINE_RES_IRQ_NAMED(BD71828_INT_TEMP_CHIP_OVER_125_RES, 145 "bd71828-temp-125-under"), 146 }; 147 148 static struct mfd_cell bd71828_mfd_cells[] = { 149 { .name = "bd71828-pmic", }, 150 { .name = "bd71828-gpio", }, 151 { .name = "bd71828-led", .of_compatible = "rohm,bd71828-leds" }, 152 /* 153 * We use BD71837 driver to drive the clock block. Only differences to 154 * BD70528 clock gate are the register address and mask. 155 */ 156 { .name = "bd71828-clk", }, 157 { 158 .name = "bd71828-power", 159 .resources = bd71828_power_irqs, 160 .num_resources = ARRAY_SIZE(bd71828_power_irqs), 161 }, { 162 .name = "bd71828-rtc", 163 .resources = bd71828_rtc_irqs, 164 .num_resources = ARRAY_SIZE(bd71828_rtc_irqs), 165 }, 166 }; 167 168 static const struct resource bd72720_power_irqs[] = { 169 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_RMV, "bd72720_int_vbus_rmv"), 170 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_DET, "bd72720_int_vbus_det"), 171 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_MON_RES, "bd72720_int_vbus_mon_res"), 172 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBUS_MON_DET, "bd72720_int_vbus_mon_det"), 173 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_MON_RES, "bd72720_int_vsys_mon_res"), 174 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_MON_DET, "bd72720_int_vsys_mon_det"), 175 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_UV_RES, "bd72720_int_vsys_uv_res"), 176 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_UV_DET, "bd72720_int_vsys_uv_det"), 177 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_LO_RES, "bd72720_int_vsys_lo_res"), 178 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_LO_DET, "bd72720_int_vsys_lo_det"), 179 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_OV_RES, "bd72720_int_vsys_ov_res"), 180 DEFINE_RES_IRQ_NAMED(BD72720_INT_VSYS_OV_DET, "bd72720_int_vsys_ov_det"), 181 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_ILIM, "bd72720_int_bat_ilim"), 182 DEFINE_RES_IRQ_NAMED(BD72720_INT_CHG_DONE, "bd72720_int_chg_done"), 183 DEFINE_RES_IRQ_NAMED(BD72720_INT_EXTEMP_TOUT, "bd72720_int_extemp_tout"), 184 DEFINE_RES_IRQ_NAMED(BD72720_INT_CHG_WDT_EXP, "bd72720_int_chg_wdt_exp"), 185 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_MNT_OUT, "bd72720_int_bat_mnt_out"), 186 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_MNT_IN, "bd72720_int_bat_mnt_in"), 187 DEFINE_RES_IRQ_NAMED(BD72720_INT_CHG_TRNS, "bd72720_int_chg_trns"), 188 189 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_MON_RES, "bd72720_int_vbat_mon_res"), 190 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_MON_DET, "bd72720_int_vbat_mon_det"), 191 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_SHT_RES, "bd72720_int_vbat_sht_res"), 192 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_SHT_DET, "bd72720_int_vbat_sht_det"), 193 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_LO_RES, "bd72720_int_vbat_lo_res"), 194 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_LO_DET, "bd72720_int_vbat_lo_det"), 195 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_OV_RES, "bd72720_int_vbat_ov_res"), 196 DEFINE_RES_IRQ_NAMED(BD72720_INT_VBAT_OV_DET, "bd72720_int_vbat_ov_det"), 197 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_RMV, "bd72720_int_bat_rmv"), 198 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_DET, "bd72720_int_bat_det"), 199 DEFINE_RES_IRQ_NAMED(BD72720_INT_DBAT_DET, "bd72720_int_dbat_det"), 200 DEFINE_RES_IRQ_NAMED(BD72720_INT_BAT_TEMP_TRNS, "bd72720_int_bat_temp_trns"), 201 DEFINE_RES_IRQ_NAMED(BD72720_INT_LOBTMP_RES, "bd72720_int_lobtmp_res"), 202 DEFINE_RES_IRQ_NAMED(BD72720_INT_LOBTMP_DET, "bd72720_int_lobtmp_det"), 203 DEFINE_RES_IRQ_NAMED(BD72720_INT_OVBTMP_RES, "bd72720_int_ovbtmp_res"), 204 DEFINE_RES_IRQ_NAMED(BD72720_INT_OVBTMP_DET, "bd72720_int_ovbtmp_det"), 205 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR1_RES, "bd72720_int_ocur1_res"), 206 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR1_DET, "bd72720_int_ocur1_det"), 207 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR2_RES, "bd72720_int_ocur2_res"), 208 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR2_DET, "bd72720_int_ocur2_det"), 209 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR3_RES, "bd72720_int_ocur3_res"), 210 DEFINE_RES_IRQ_NAMED(BD72720_INT_OCUR3_DET, "bd72720_int_ocur3_det"), 211 DEFINE_RES_IRQ_NAMED(BD72720_INT_CC_MON1_DET, "bd72720_int_cc_mon1_det"), 212 DEFINE_RES_IRQ_NAMED(BD72720_INT_CC_MON2_DET, "bd72720_int_cc_mon2_det"), 213 DEFINE_RES_IRQ_NAMED(BD72720_INT_CC_MON3_DET, "bd72720_int_cc_mon3_det"), 214 }; 215 216 static const struct mfd_cell bd72720_mfd_cells[] = { 217 { .name = "bd72720-pmic", }, 218 { .name = "bd72720-gpio", }, 219 { .name = "bd72720-led", }, 220 { .name = "bd72720-clk", }, 221 { 222 .name = "bd72720-power", 223 .resources = bd72720_power_irqs, 224 .num_resources = ARRAY_SIZE(bd72720_power_irqs), 225 }, { 226 .name = "bd72720-rtc", 227 .resources = bd72720_rtc_irqs, 228 .num_resources = ARRAY_SIZE(bd72720_rtc_irqs), 229 }, 230 /* Power button is registered separately */ 231 }; 232 233 static const struct regmap_range bd71815_volatile_ranges[] = { 234 regmap_reg_range(BD71815_REG_SEC, BD71815_REG_YEAR), 235 regmap_reg_range(BD71815_REG_CONF, BD71815_REG_BAT_TEMP), 236 regmap_reg_range(BD71815_REG_VM_IBAT_U, BD71815_REG_CC_CTRL), 237 regmap_reg_range(BD71815_REG_CC_STAT, BD71815_REG_CC_CURCD_L), 238 regmap_reg_range(BD71815_REG_VM_BTMP_MON, BD71815_REG_VM_BTMP_MON), 239 regmap_reg_range(BD71815_REG_INT_STAT, BD71815_REG_INT_UPDATE), 240 regmap_reg_range(BD71815_REG_VM_VSYS_U, BD71815_REG_REX_CTRL_1), 241 regmap_reg_range(BD71815_REG_FULL_CCNTD_3, BD71815_REG_CCNTD_CHG_2), 242 }; 243 244 static const struct regmap_range bd71828_volatile_ranges[] = { 245 regmap_reg_range(BD71828_REG_PS_CTRL_1, BD71828_REG_PS_CTRL_1), 246 regmap_reg_range(BD71828_REG_PS_CTRL_3, BD71828_REG_PS_CTRL_3), 247 regmap_reg_range(BD71828_REG_RTC_SEC, BD71828_REG_RTC_YEAR), 248 /* 249 * For now make all charger registers volatile because many 250 * needs to be and because the charger block is not that 251 * performance critical. 252 */ 253 regmap_reg_range(BD71828_REG_CHG_STATE, BD71828_REG_CHG_FULL), 254 regmap_reg_range(BD71828_REG_INT_MAIN, BD71828_REG_IO_STAT), 255 }; 256 257 static const struct regmap_range bd72720_volatile_ranges_4b[] = { 258 regmap_reg_range(BD72720_REG_RESETSRC_1, BD72720_REG_RESETSRC_2), 259 regmap_reg_range(BD72720_REG_POWER_STATE, BD72720_REG_POWER_STATE), 260 /* The state indicator bit changes when new state is reached */ 261 regmap_reg_range(BD72720_REG_PS_CTRL_1, BD72720_REG_PS_CTRL_1), 262 regmap_reg_range(BD72720_REG_RCVNUM, BD72720_REG_RCVNUM), 263 regmap_reg_range(BD72720_REG_CONF, BD72720_REG_HALL_STAT), 264 regmap_reg_range(BD72720_REG_RTC_SEC, BD72720_REG_RTC_YEAR), 265 regmap_reg_range(BD72720_REG_INT_LVL1_STAT, BD72720_REG_INT_ETC2_SRC), 266 }; 267 268 static const struct regmap_range bd72720_precious_ranges_4b[] = { 269 regmap_reg_range(BD72720_REG_INT_LVL1_STAT, BD72720_REG_INT_ETC2_STAT), 270 }; 271 272 /* 273 * The BD72720 is an odd beast in that it contains two separate sets of 274 * registers, both starting from address 0x0. The twist is that these "pages" 275 * are behind different I2C slave addresses. Most of the registers are behind 276 * a slave address 0x4b, which will be used as the "main" address for this 277 * device. 278 * 279 * Most of the charger related registers are located behind slave address 0x4c. 280 * It is tempting to push the dealing with the charger registers and the extra 281 * 0x4c device in power-supply driver - but perhaps it's better for the sake of 282 * the cleaner re-use to deal with setting up all of the regmaps here. 283 * Furthermore, the LED stuff may need access to both of these devices. 284 * 285 * Instead of providing one of the regmaps to sub-devices in MFD platform data, 286 * we create one more 'wrapper regmap' with custom read/write operations. These 287 * custom accessors will select which of the 'real' regmaps to use, based on 288 * the register address. 289 * 290 * The register addresses are 8-bit, so we add offset 0x100 to the addresses 291 * behind the secondary slave 0x4c. The 'wrapper' regmap can then detect the 292 * correct slave address based on the register address and call regmap_write() 293 * and regmap_read() using correct 'real' regmap. This way the registers of 294 * both of the slaves can be accessed using one 'wrapper' regmap. 295 * 296 * NOTE: The added offsets mean that the defined addresses for slave 0x4c must 297 * be used through the 'wrapper' regmap because the offset must be stripped 298 * from the register addresses. The 0x4b can be accessed both indirectly using 299 * the 'wrapper' regmap, and directly using the 'real' regmap. 300 */ 301 #define BD72720_SECONDARY_I2C_SLAVE 0x4c 302 #define BD72720_SECONDARY_I2C_REG_OFFSET 0x100 303 304 struct bd72720_regmaps { 305 struct regmap *map1_4b; 306 struct regmap *map2_4c; 307 }; 308 309 /* Translate the slave 0x4c wrapper register address to a real one */ 310 #define BD72720_REG_UNWRAP(reg) ((reg) - BD72720_SECONDARY_I2C_REG_OFFSET) 311 312 /* Ranges given to 'real' 0x4c regmap must use unwrapped addresses. */ 313 #define BD72720_UNWRAP_REG_RANGE(startreg, endreg) \ 314 regmap_reg_range(BD72720_REG_UNWRAP(startreg), BD72720_REG_UNWRAP(endreg)) 315 316 static const struct regmap_range bd72720_volatile_ranges_4c[] = { 317 /* Status information */ 318 BD72720_UNWRAP_REG_RANGE(BD72720_REG_CHG_STATE, BD72720_REG_CHG_EN), 319 /* 320 * Under certain circumstances, write to some bits may be 321 * ignored 322 */ 323 BD72720_UNWRAP_REG_RANGE(BD72720_REG_CHG_CTRL, BD72720_REG_CHG_CTRL), 324 /* 325 * TODO: Ensure this is used to advertise state, not (only?) to 326 * control it. 327 */ 328 BD72720_UNWRAP_REG_RANGE(BD72720_REG_VSYS_STATE_STAT, BD72720_REG_VSYS_STATE_STAT), 329 /* Measured data */ 330 BD72720_UNWRAP_REG_RANGE(BD72720_REG_VM_VBAT_U, BD72720_REG_VM_VF_L), 331 /* Self clearing bits */ 332 BD72720_UNWRAP_REG_RANGE(BD72720_REG_VM_VSYS_SA_MINMAX_CTRL, 333 BD72720_REG_VM_VSYS_SA_MINMAX_CTRL), 334 /* Counters, self clearing bits */ 335 BD72720_UNWRAP_REG_RANGE(BD72720_REG_CC_CURCD_U, BD72720_REG_CC_CTRL), 336 /* Self clearing bits */ 337 BD72720_UNWRAP_REG_RANGE(BD72720_REG_CC_CCNTD_CTRL, BD72720_REG_CC_CCNTD_CTRL), 338 /* Self clearing bits */ 339 BD72720_UNWRAP_REG_RANGE(BD72720_REG_IMPCHK_CTRL, BD72720_REG_IMPCHK_CTRL), 340 }; 341 342 static const struct regmap_access_table bd71815_volatile_regs = { 343 .yes_ranges = &bd71815_volatile_ranges[0], 344 .n_yes_ranges = ARRAY_SIZE(bd71815_volatile_ranges), 345 }; 346 347 static const struct regmap_access_table bd71828_volatile_regs = { 348 .yes_ranges = &bd71828_volatile_ranges[0], 349 .n_yes_ranges = ARRAY_SIZE(bd71828_volatile_ranges), 350 }; 351 352 static const struct regmap_access_table bd72720_volatile_regs_4b = { 353 .yes_ranges = &bd72720_volatile_ranges_4b[0], 354 .n_yes_ranges = ARRAY_SIZE(bd72720_volatile_ranges_4b), 355 }; 356 357 static const struct regmap_access_table bd72720_precious_regs_4b = { 358 .yes_ranges = &bd72720_precious_ranges_4b[0], 359 .n_yes_ranges = ARRAY_SIZE(bd72720_precious_ranges_4b), 360 }; 361 362 static const struct regmap_access_table bd72720_volatile_regs_4c = { 363 .yes_ranges = &bd72720_volatile_ranges_4c[0], 364 .n_yes_ranges = ARRAY_SIZE(bd72720_volatile_ranges_4c), 365 }; 366 367 static const struct regmap_config bd71815_regmap = { 368 .reg_bits = 8, 369 .val_bits = 8, 370 .volatile_table = &bd71815_volatile_regs, 371 .max_register = BD71815_MAX_REGISTER - 1, 372 .cache_type = REGCACHE_MAPLE, 373 }; 374 375 static const struct regmap_config bd71828_regmap = { 376 .reg_bits = 8, 377 .val_bits = 8, 378 .volatile_table = &bd71828_volatile_regs, 379 .max_register = BD71828_MAX_REGISTER, 380 .cache_type = REGCACHE_MAPLE, 381 }; 382 383 static int regmap_write_wrapper(void *context, unsigned int reg, unsigned int val) 384 { 385 struct bd72720_regmaps *maps = context; 386 387 if (reg < BD72720_SECONDARY_I2C_REG_OFFSET) 388 return regmap_write(maps->map1_4b, reg, val); 389 390 reg = BD72720_REG_UNWRAP(reg); 391 392 return regmap_write(maps->map2_4c, reg, val); 393 } 394 395 static int regmap_read_wrapper(void *context, unsigned int reg, unsigned int *val) 396 { 397 struct bd72720_regmaps *maps = context; 398 399 if (reg < BD72720_SECONDARY_I2C_REG_OFFSET) 400 return regmap_read(maps->map1_4b, reg, val); 401 402 reg = BD72720_REG_UNWRAP(reg); 403 404 return regmap_read(maps->map2_4c, reg, val); 405 } 406 407 static const struct regmap_config bd72720_wrapper_map_config = { 408 .name = "wrap-map", 409 .reg_bits = 9, 410 .val_bits = 8, 411 .max_register = BD72720_REG_IMPCHK_CTRL, 412 /* 413 * We don't want to duplicate caches. It would be a bit faster to 414 * have the cache in this 'wrapper regmap', and not in the 'real 415 * regmaps' bd72720_regmap_4b and bd72720_regmap_4c below. This would 416 * require all the subdevices to use the wrapper-map in order to be 417 * able to benefit from the cache. 418 * Currently most of the sub-devices use only the same slave-address 419 * as this MFD driver. Now, because we don't add the offset to the 420 * registers belonging to this slave, those devices can use either the 421 * wrapper map, or the bd72720_regmap_4b directly. This means majority 422 * of our sub devices don't need to care which regmap they get using 423 * the dev_get_regmap(). This unifies the code between the BD72720 and 424 * those variants which don't have this 'multiple slave addresses' 425 * -hassle. 426 * So, for a small performance penalty, we simplify the code for the 427 * sub-devices by having the caches in the wrapped regmaps and not here. 428 */ 429 .cache_type = REGCACHE_NONE, 430 .reg_write = regmap_write_wrapper, 431 .reg_read = regmap_read_wrapper, 432 }; 433 434 static const struct regmap_config bd72720_regmap_4b = { 435 .reg_bits = 8, 436 .val_bits = 8, 437 .volatile_table = &bd72720_volatile_regs_4b, 438 .precious_table = &bd72720_precious_regs_4b, 439 .max_register = BD72720_REG_INT_ETC2_SRC, 440 .cache_type = REGCACHE_MAPLE, 441 }; 442 443 static const struct regmap_config bd72720_regmap_4c = { 444 .reg_bits = 8, 445 .val_bits = 8, 446 .volatile_table = &bd72720_volatile_regs_4c, 447 .max_register = BD72720_REG_UNWRAP(BD72720_REG_IMPCHK_CTRL), 448 .cache_type = REGCACHE_MAPLE, 449 }; 450 451 /* 452 * Mapping of main IRQ register bits to sub-IRQ register offsets so that we can 453 * access corect sub-IRQ registers based on bits that are set in main IRQ 454 * register. BD71815 and BD71828 have same sub-register-block offests, the 455 * BD72720 has a different one. 456 */ 457 458 static unsigned int bit0_offsets[] = {11}; /* RTC IRQ */ 459 static unsigned int bit1_offsets[] = {10}; /* TEMP IRQ */ 460 static unsigned int bit2_offsets[] = {6, 7, 8, 9}; /* BAT MON IRQ */ 461 static unsigned int bit3_offsets[] = {5}; /* BAT IRQ */ 462 static unsigned int bit4_offsets[] = {4}; /* CHG IRQ */ 463 static unsigned int bit5_offsets[] = {3}; /* VSYS IRQ */ 464 static unsigned int bit6_offsets[] = {1, 2}; /* DCIN IRQ */ 465 static unsigned int bit7_offsets[] = {0}; /* BUCK IRQ */ 466 467 static unsigned int bd72720_bit0_offsets[] = {0, 1}; /* PS1 and PS2 */ 468 static unsigned int bd72720_bit1_offsets[] = {2, 3}; /* DVS1 and DVS2 */ 469 static unsigned int bd72720_bit2_offsets[] = {4}; /* VBUS */ 470 static unsigned int bd72720_bit3_offsets[] = {5}; /* VSYS */ 471 static unsigned int bd72720_bit4_offsets[] = {6}; /* CHG */ 472 static unsigned int bd72720_bit5_offsets[] = {7, 8}; /* BAT1 and BAT2 */ 473 static unsigned int bd72720_bit6_offsets[] = {9}; /* IBAT */ 474 static unsigned int bd72720_bit7_offsets[] = {10, 11}; /* ETC1 and ETC2 */ 475 476 static const struct regmap_irq_sub_irq_map bd718xx_sub_irq_offsets[] = { 477 REGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets), 478 REGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets), 479 REGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets), 480 REGMAP_IRQ_MAIN_REG_OFFSET(bit3_offsets), 481 REGMAP_IRQ_MAIN_REG_OFFSET(bit4_offsets), 482 REGMAP_IRQ_MAIN_REG_OFFSET(bit5_offsets), 483 REGMAP_IRQ_MAIN_REG_OFFSET(bit6_offsets), 484 REGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets), 485 }; 486 487 static const struct regmap_irq_sub_irq_map bd72720_sub_irq_offsets[] = { 488 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit0_offsets), 489 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit1_offsets), 490 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit2_offsets), 491 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit3_offsets), 492 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit4_offsets), 493 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit5_offsets), 494 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit6_offsets), 495 REGMAP_IRQ_MAIN_REG_OFFSET(bd72720_bit7_offsets), 496 }; 497 498 static const struct regmap_irq bd71815_irqs[] = { 499 REGMAP_IRQ_REG(BD71815_INT_BUCK1_OCP, 0, BD71815_INT_BUCK1_OCP_MASK), 500 REGMAP_IRQ_REG(BD71815_INT_BUCK2_OCP, 0, BD71815_INT_BUCK2_OCP_MASK), 501 REGMAP_IRQ_REG(BD71815_INT_BUCK3_OCP, 0, BD71815_INT_BUCK3_OCP_MASK), 502 REGMAP_IRQ_REG(BD71815_INT_BUCK4_OCP, 0, BD71815_INT_BUCK4_OCP_MASK), 503 REGMAP_IRQ_REG(BD71815_INT_BUCK5_OCP, 0, BD71815_INT_BUCK5_OCP_MASK), 504 REGMAP_IRQ_REG(BD71815_INT_LED_OVP, 0, BD71815_INT_LED_OVP_MASK), 505 REGMAP_IRQ_REG(BD71815_INT_LED_OCP, 0, BD71815_INT_LED_OCP_MASK), 506 REGMAP_IRQ_REG(BD71815_INT_LED_SCP, 0, BD71815_INT_LED_SCP_MASK), 507 /* DCIN1 interrupts */ 508 REGMAP_IRQ_REG(BD71815_INT_DCIN_RMV, 1, BD71815_INT_DCIN_RMV_MASK), 509 REGMAP_IRQ_REG(BD71815_INT_CLPS_OUT, 1, BD71815_INT_CLPS_OUT_MASK), 510 REGMAP_IRQ_REG(BD71815_INT_CLPS_IN, 1, BD71815_INT_CLPS_IN_MASK), 511 REGMAP_IRQ_REG(BD71815_INT_DCIN_OVP_RES, 1, BD71815_INT_DCIN_OVP_RES_MASK), 512 REGMAP_IRQ_REG(BD71815_INT_DCIN_OVP_DET, 1, BD71815_INT_DCIN_OVP_DET_MASK), 513 /* DCIN2 interrupts */ 514 REGMAP_IRQ_REG(BD71815_INT_DCIN_MON_RES, 2, BD71815_INT_DCIN_MON_RES_MASK), 515 REGMAP_IRQ_REG(BD71815_INT_DCIN_MON_DET, 2, BD71815_INT_DCIN_MON_DET_MASK), 516 REGMAP_IRQ_REG(BD71815_INT_WDOG, 2, BD71815_INT_WDOG_MASK), 517 /* Vsys */ 518 REGMAP_IRQ_REG(BD71815_INT_VSYS_UV_RES, 3, BD71815_INT_VSYS_UV_RES_MASK), 519 REGMAP_IRQ_REG(BD71815_INT_VSYS_UV_DET, 3, BD71815_INT_VSYS_UV_DET_MASK), 520 REGMAP_IRQ_REG(BD71815_INT_VSYS_LOW_RES, 3, BD71815_INT_VSYS_LOW_RES_MASK), 521 REGMAP_IRQ_REG(BD71815_INT_VSYS_LOW_DET, 3, BD71815_INT_VSYS_LOW_DET_MASK), 522 REGMAP_IRQ_REG(BD71815_INT_VSYS_MON_RES, 3, BD71815_INT_VSYS_MON_RES_MASK), 523 REGMAP_IRQ_REG(BD71815_INT_VSYS_MON_DET, 3, BD71815_INT_VSYS_MON_DET_MASK), 524 /* Charger */ 525 REGMAP_IRQ_REG(BD71815_INT_CHG_WDG_TEMP, 4, BD71815_INT_CHG_WDG_TEMP_MASK), 526 REGMAP_IRQ_REG(BD71815_INT_CHG_WDG_TIME, 4, BD71815_INT_CHG_WDG_TIME_MASK), 527 REGMAP_IRQ_REG(BD71815_INT_CHG_RECHARGE_RES, 4, BD71815_INT_CHG_RECHARGE_RES_MASK), 528 REGMAP_IRQ_REG(BD71815_INT_CHG_RECHARGE_DET, 4, BD71815_INT_CHG_RECHARGE_DET_MASK), 529 REGMAP_IRQ_REG(BD71815_INT_CHG_RANGED_TEMP_TRANSITION, 4, 530 BD71815_INT_CHG_RANGED_TEMP_TRANSITION_MASK), 531 REGMAP_IRQ_REG(BD71815_INT_CHG_STATE_TRANSITION, 4, BD71815_INT_CHG_STATE_TRANSITION_MASK), 532 /* Battery */ 533 REGMAP_IRQ_REG(BD71815_INT_BAT_TEMP_NORMAL, 5, BD71815_INT_BAT_TEMP_NORMAL_MASK), 534 REGMAP_IRQ_REG(BD71815_INT_BAT_TEMP_ERANGE, 5, BD71815_INT_BAT_TEMP_ERANGE_MASK), 535 REGMAP_IRQ_REG(BD71815_INT_BAT_REMOVED, 5, BD71815_INT_BAT_REMOVED_MASK), 536 REGMAP_IRQ_REG(BD71815_INT_BAT_DETECTED, 5, BD71815_INT_BAT_DETECTED_MASK), 537 REGMAP_IRQ_REG(BD71815_INT_THERM_REMOVED, 5, BD71815_INT_THERM_REMOVED_MASK), 538 REGMAP_IRQ_REG(BD71815_INT_THERM_DETECTED, 5, BD71815_INT_THERM_DETECTED_MASK), 539 /* Battery Mon 1 */ 540 REGMAP_IRQ_REG(BD71815_INT_BAT_DEAD, 6, BD71815_INT_BAT_DEAD_MASK), 541 REGMAP_IRQ_REG(BD71815_INT_BAT_SHORTC_RES, 6, BD71815_INT_BAT_SHORTC_RES_MASK), 542 REGMAP_IRQ_REG(BD71815_INT_BAT_SHORTC_DET, 6, BD71815_INT_BAT_SHORTC_DET_MASK), 543 REGMAP_IRQ_REG(BD71815_INT_BAT_LOW_VOLT_RES, 6, BD71815_INT_BAT_LOW_VOLT_RES_MASK), 544 REGMAP_IRQ_REG(BD71815_INT_BAT_LOW_VOLT_DET, 6, BD71815_INT_BAT_LOW_VOLT_DET_MASK), 545 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_VOLT_RES, 6, BD71815_INT_BAT_OVER_VOLT_RES_MASK), 546 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_VOLT_DET, 6, BD71815_INT_BAT_OVER_VOLT_DET_MASK), 547 /* Battery Mon 2 */ 548 REGMAP_IRQ_REG(BD71815_INT_BAT_MON_RES, 7, BD71815_INT_BAT_MON_RES_MASK), 549 REGMAP_IRQ_REG(BD71815_INT_BAT_MON_DET, 7, BD71815_INT_BAT_MON_DET_MASK), 550 /* Battery Mon 3 (Coulomb counter) */ 551 REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON1, 8, BD71815_INT_BAT_CC_MON1_MASK), 552 REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON2, 8, BD71815_INT_BAT_CC_MON2_MASK), 553 REGMAP_IRQ_REG(BD71815_INT_BAT_CC_MON3, 8, BD71815_INT_BAT_CC_MON3_MASK), 554 /* Battery Mon 4 */ 555 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_1_RES, 9, BD71815_INT_BAT_OVER_CURR_1_RES_MASK), 556 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_1_DET, 9, BD71815_INT_BAT_OVER_CURR_1_DET_MASK), 557 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_2_RES, 9, BD71815_INT_BAT_OVER_CURR_2_RES_MASK), 558 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_2_DET, 9, BD71815_INT_BAT_OVER_CURR_2_DET_MASK), 559 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_3_RES, 9, BD71815_INT_BAT_OVER_CURR_3_RES_MASK), 560 REGMAP_IRQ_REG(BD71815_INT_BAT_OVER_CURR_3_DET, 9, BD71815_INT_BAT_OVER_CURR_3_DET_MASK), 561 /* Temperature */ 562 REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_LOW_RES, 10, BD71815_INT_TEMP_BAT_LOW_RES_MASK), 563 REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_LOW_DET, 10, BD71815_INT_TEMP_BAT_LOW_DET_MASK), 564 REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_HI_RES, 10, BD71815_INT_TEMP_BAT_HI_RES_MASK), 565 REGMAP_IRQ_REG(BD71815_INT_TEMP_BAT_HI_DET, 10, BD71815_INT_TEMP_BAT_HI_DET_MASK), 566 REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_125_RES, 10, 567 BD71815_INT_TEMP_CHIP_OVER_125_RES_MASK), 568 REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_125_DET, 10, 569 BD71815_INT_TEMP_CHIP_OVER_125_DET_MASK), 570 REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_VF_RES, 10, 571 BD71815_INT_TEMP_CHIP_OVER_VF_RES_MASK), 572 REGMAP_IRQ_REG(BD71815_INT_TEMP_CHIP_OVER_VF_DET, 10, 573 BD71815_INT_TEMP_CHIP_OVER_VF_DET_MASK), 574 /* RTC Alarm */ 575 REGMAP_IRQ_REG(BD71815_INT_RTC0, 11, BD71815_INT_RTC0_MASK), 576 REGMAP_IRQ_REG(BD71815_INT_RTC1, 11, BD71815_INT_RTC1_MASK), 577 REGMAP_IRQ_REG(BD71815_INT_RTC2, 11, BD71815_INT_RTC2_MASK), 578 }; 579 580 static const struct regmap_irq bd71828_irqs[] = { 581 REGMAP_IRQ_REG(BD71828_INT_BUCK1_OCP, 0, BD71828_INT_BUCK1_OCP_MASK), 582 REGMAP_IRQ_REG(BD71828_INT_BUCK2_OCP, 0, BD71828_INT_BUCK2_OCP_MASK), 583 REGMAP_IRQ_REG(BD71828_INT_BUCK3_OCP, 0, BD71828_INT_BUCK3_OCP_MASK), 584 REGMAP_IRQ_REG(BD71828_INT_BUCK4_OCP, 0, BD71828_INT_BUCK4_OCP_MASK), 585 REGMAP_IRQ_REG(BD71828_INT_BUCK5_OCP, 0, BD71828_INT_BUCK5_OCP_MASK), 586 REGMAP_IRQ_REG(BD71828_INT_BUCK6_OCP, 0, BD71828_INT_BUCK6_OCP_MASK), 587 REGMAP_IRQ_REG(BD71828_INT_BUCK7_OCP, 0, BD71828_INT_BUCK7_OCP_MASK), 588 REGMAP_IRQ_REG(BD71828_INT_PGFAULT, 0, BD71828_INT_PGFAULT_MASK), 589 /* DCIN1 interrupts */ 590 REGMAP_IRQ_REG(BD71828_INT_DCIN_DET, 1, BD71828_INT_DCIN_DET_MASK), 591 REGMAP_IRQ_REG(BD71828_INT_DCIN_RMV, 1, BD71828_INT_DCIN_RMV_MASK), 592 REGMAP_IRQ_REG(BD71828_INT_CLPS_OUT, 1, BD71828_INT_CLPS_OUT_MASK), 593 REGMAP_IRQ_REG(BD71828_INT_CLPS_IN, 1, BD71828_INT_CLPS_IN_MASK), 594 /* DCIN2 interrupts */ 595 REGMAP_IRQ_REG(BD71828_INT_DCIN_MON_RES, 2, BD71828_INT_DCIN_MON_RES_MASK), 596 REGMAP_IRQ_REG(BD71828_INT_DCIN_MON_DET, 2, BD71828_INT_DCIN_MON_DET_MASK), 597 REGMAP_IRQ_REG(BD71828_INT_LONGPUSH, 2, BD71828_INT_LONGPUSH_MASK), 598 REGMAP_IRQ_REG(BD71828_INT_MIDPUSH, 2, BD71828_INT_MIDPUSH_MASK), 599 REGMAP_IRQ_REG(BD71828_INT_SHORTPUSH, 2, BD71828_INT_SHORTPUSH_MASK), 600 REGMAP_IRQ_REG(BD71828_INT_PUSH, 2, BD71828_INT_PUSH_MASK), 601 REGMAP_IRQ_REG(BD71828_INT_WDOG, 2, BD71828_INT_WDOG_MASK), 602 REGMAP_IRQ_REG(BD71828_INT_SWRESET, 2, BD71828_INT_SWRESET_MASK), 603 /* Vsys */ 604 REGMAP_IRQ_REG(BD71828_INT_VSYS_UV_RES, 3, BD71828_INT_VSYS_UV_RES_MASK), 605 REGMAP_IRQ_REG(BD71828_INT_VSYS_UV_DET, 3, BD71828_INT_VSYS_UV_DET_MASK), 606 REGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_RES, 3, BD71828_INT_VSYS_LOW_RES_MASK), 607 REGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_DET, 3, BD71828_INT_VSYS_LOW_DET_MASK), 608 REGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_IN, 3, BD71828_INT_VSYS_HALL_IN_MASK), 609 REGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_TOGGLE, 3, BD71828_INT_VSYS_HALL_TOGGLE_MASK), 610 REGMAP_IRQ_REG(BD71828_INT_VSYS_MON_RES, 3, BD71828_INT_VSYS_MON_RES_MASK), 611 REGMAP_IRQ_REG(BD71828_INT_VSYS_MON_DET, 3, BD71828_INT_VSYS_MON_DET_MASK), 612 /* Charger */ 613 REGMAP_IRQ_REG(BD71828_INT_CHG_DCIN_ILIM, 4, BD71828_INT_CHG_DCIN_ILIM_MASK), 614 REGMAP_IRQ_REG(BD71828_INT_CHG_TOPOFF_TO_DONE, 4, BD71828_INT_CHG_TOPOFF_TO_DONE_MASK), 615 REGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TEMP, 4, BD71828_INT_CHG_WDG_TEMP_MASK), 616 REGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TIME, 4, BD71828_INT_CHG_WDG_TIME_MASK), 617 REGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_RES, 4, BD71828_INT_CHG_RECHARGE_RES_MASK), 618 REGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_DET, 4, BD71828_INT_CHG_RECHARGE_DET_MASK), 619 REGMAP_IRQ_REG(BD71828_INT_CHG_RANGED_TEMP_TRANSITION, 4, 620 BD71828_INT_CHG_RANGED_TEMP_TRANSITION_MASK), 621 REGMAP_IRQ_REG(BD71828_INT_CHG_STATE_TRANSITION, 4, BD71828_INT_CHG_STATE_TRANSITION_MASK), 622 /* Battery */ 623 REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_NORMAL, 5, BD71828_INT_BAT_TEMP_NORMAL_MASK), 624 REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_ERANGE, 5, BD71828_INT_BAT_TEMP_ERANGE_MASK), 625 REGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_WARN, 5, BD71828_INT_BAT_TEMP_WARN_MASK), 626 REGMAP_IRQ_REG(BD71828_INT_BAT_REMOVED, 5, BD71828_INT_BAT_REMOVED_MASK), 627 REGMAP_IRQ_REG(BD71828_INT_BAT_DETECTED, 5, BD71828_INT_BAT_DETECTED_MASK), 628 REGMAP_IRQ_REG(BD71828_INT_THERM_REMOVED, 5, BD71828_INT_THERM_REMOVED_MASK), 629 REGMAP_IRQ_REG(BD71828_INT_THERM_DETECTED, 5, BD71828_INT_THERM_DETECTED_MASK), 630 /* Battery Mon 1 */ 631 REGMAP_IRQ_REG(BD71828_INT_BAT_DEAD, 6, BD71828_INT_BAT_DEAD_MASK), 632 REGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_RES, 6, BD71828_INT_BAT_SHORTC_RES_MASK), 633 REGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_DET, 6, BD71828_INT_BAT_SHORTC_DET_MASK), 634 REGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_RES, 6, BD71828_INT_BAT_LOW_VOLT_RES_MASK), 635 REGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_DET, 6, BD71828_INT_BAT_LOW_VOLT_DET_MASK), 636 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_RES, 6, BD71828_INT_BAT_OVER_VOLT_RES_MASK), 637 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_DET, 6, BD71828_INT_BAT_OVER_VOLT_DET_MASK), 638 /* Battery Mon 2 */ 639 REGMAP_IRQ_REG(BD71828_INT_BAT_MON_RES, 7, BD71828_INT_BAT_MON_RES_MASK), 640 REGMAP_IRQ_REG(BD71828_INT_BAT_MON_DET, 7, BD71828_INT_BAT_MON_DET_MASK), 641 /* Battery Mon 3 (Coulomb counter) */ 642 REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON1, 8, BD71828_INT_BAT_CC_MON1_MASK), 643 REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON2, 8, BD71828_INT_BAT_CC_MON2_MASK), 644 REGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON3, 8, BD71828_INT_BAT_CC_MON3_MASK), 645 /* Battery Mon 4 */ 646 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_RES, 9, BD71828_INT_BAT_OVER_CURR_1_RES_MASK), 647 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_DET, 9, BD71828_INT_BAT_OVER_CURR_1_DET_MASK), 648 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_RES, 9, BD71828_INT_BAT_OVER_CURR_2_RES_MASK), 649 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_DET, 9, BD71828_INT_BAT_OVER_CURR_2_DET_MASK), 650 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_RES, 9, BD71828_INT_BAT_OVER_CURR_3_RES_MASK), 651 REGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_DET, 9, BD71828_INT_BAT_OVER_CURR_3_DET_MASK), 652 /* Temperature */ 653 REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_RES, 10, BD71828_INT_TEMP_BAT_LOW_RES_MASK), 654 REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_DET, 10, BD71828_INT_TEMP_BAT_LOW_DET_MASK), 655 REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_RES, 10, BD71828_INT_TEMP_BAT_HI_RES_MASK), 656 REGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_DET, 10, BD71828_INT_TEMP_BAT_HI_DET_MASK), 657 REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_125_RES, 10, 658 BD71828_INT_TEMP_CHIP_OVER_125_RES_MASK), 659 REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_125_DET, 10, 660 BD71828_INT_TEMP_CHIP_OVER_125_DET_MASK), 661 REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_VF_DET, 10, 662 BD71828_INT_TEMP_CHIP_OVER_VF_DET_MASK), 663 REGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_VF_RES, 10, 664 BD71828_INT_TEMP_CHIP_OVER_VF_RES_MASK), 665 /* RTC Alarm */ 666 REGMAP_IRQ_REG(BD71828_INT_RTC0, 11, BD71828_INT_RTC0_MASK), 667 REGMAP_IRQ_REG(BD71828_INT_RTC1, 11, BD71828_INT_RTC1_MASK), 668 REGMAP_IRQ_REG(BD71828_INT_RTC2, 11, BD71828_INT_RTC2_MASK), 669 }; 670 671 static const struct regmap_irq bd72720_irqs[] = { 672 REGMAP_IRQ_REG(BD72720_INT_LONGPUSH, 0, BD72720_INT_LONGPUSH_MASK), 673 REGMAP_IRQ_REG(BD72720_INT_MIDPUSH, 0, BD72720_INT_MIDPUSH_MASK), 674 REGMAP_IRQ_REG(BD72720_INT_SHORTPUSH, 0, BD72720_INT_SHORTPUSH_MASK), 675 REGMAP_IRQ_REG(BD72720_INT_PUSH, 0, BD72720_INT_PUSH_MASK), 676 REGMAP_IRQ_REG(BD72720_INT_HALL_DET, 0, BD72720_INT_HALL_DET_MASK), 677 REGMAP_IRQ_REG(BD72720_INT_HALL_TGL, 0, BD72720_INT_HALL_TGL_MASK), 678 REGMAP_IRQ_REG(BD72720_INT_WDOG, 0, BD72720_INT_WDOG_MASK), 679 REGMAP_IRQ_REG(BD72720_INT_SWRESET, 0, BD72720_INT_SWRESET_MASK), 680 REGMAP_IRQ_REG(BD72720_INT_SEQ_DONE, 1, BD72720_INT_SEQ_DONE_MASK), 681 REGMAP_IRQ_REG(BD72720_INT_PGFAULT, 1, BD72720_INT_PGFAULT_MASK), 682 REGMAP_IRQ_REG(BD72720_INT_BUCK1_DVS, 2, BD72720_INT_BUCK1_DVS_MASK), 683 REGMAP_IRQ_REG(BD72720_INT_BUCK2_DVS, 2, BD72720_INT_BUCK2_DVS_MASK), 684 REGMAP_IRQ_REG(BD72720_INT_BUCK3_DVS, 2, BD72720_INT_BUCK3_DVS_MASK), 685 REGMAP_IRQ_REG(BD72720_INT_BUCK4_DVS, 2, BD72720_INT_BUCK4_DVS_MASK), 686 REGMAP_IRQ_REG(BD72720_INT_BUCK5_DVS, 2, BD72720_INT_BUCK5_DVS_MASK), 687 REGMAP_IRQ_REG(BD72720_INT_BUCK6_DVS, 2, BD72720_INT_BUCK6_DVS_MASK), 688 REGMAP_IRQ_REG(BD72720_INT_BUCK7_DVS, 2, BD72720_INT_BUCK7_DVS_MASK), 689 REGMAP_IRQ_REG(BD72720_INT_BUCK8_DVS, 2, BD72720_INT_BUCK8_DVS_MASK), 690 REGMAP_IRQ_REG(BD72720_INT_BUCK9_DVS, 3, BD72720_INT_BUCK9_DVS_MASK), 691 REGMAP_IRQ_REG(BD72720_INT_BUCK10_DVS, 3, BD72720_INT_BUCK10_DVS_MASK), 692 REGMAP_IRQ_REG(BD72720_INT_LDO1_DVS, 3, BD72720_INT_LDO1_DVS_MASK), 693 REGMAP_IRQ_REG(BD72720_INT_LDO2_DVS, 3, BD72720_INT_LDO2_DVS_MASK), 694 REGMAP_IRQ_REG(BD72720_INT_LDO3_DVS, 3, BD72720_INT_LDO3_DVS_MASK), 695 REGMAP_IRQ_REG(BD72720_INT_LDO4_DVS, 3, BD72720_INT_LDO4_DVS_MASK), 696 697 REGMAP_IRQ_REG(BD72720_INT_VBUS_RMV, 4, BD72720_INT_VBUS_RMV_MASK), 698 REGMAP_IRQ_REG(BD72720_INT_VBUS_DET, 4, BD72720_INT_VBUS_DET_MASK), 699 REGMAP_IRQ_REG(BD72720_INT_VBUS_MON_RES, 4, BD72720_INT_VBUS_MON_RES_MASK), 700 REGMAP_IRQ_REG(BD72720_INT_VBUS_MON_DET, 4, BD72720_INT_VBUS_MON_DET_MASK), 701 REGMAP_IRQ_REG(BD72720_INT_VSYS_MON_RES, 5, BD72720_INT_VSYS_MON_RES_MASK), 702 REGMAP_IRQ_REG(BD72720_INT_VSYS_MON_DET, 5, BD72720_INT_VSYS_MON_DET_MASK), 703 REGMAP_IRQ_REG(BD72720_INT_VSYS_UV_RES, 5, BD72720_INT_VSYS_UV_RES_MASK), 704 REGMAP_IRQ_REG(BD72720_INT_VSYS_UV_DET, 5, BD72720_INT_VSYS_UV_DET_MASK), 705 REGMAP_IRQ_REG(BD72720_INT_VSYS_LO_RES, 5, BD72720_INT_VSYS_LO_RES_MASK), 706 REGMAP_IRQ_REG(BD72720_INT_VSYS_LO_DET, 5, BD72720_INT_VSYS_LO_DET_MASK), 707 REGMAP_IRQ_REG(BD72720_INT_VSYS_OV_RES, 5, BD72720_INT_VSYS_OV_RES_MASK), 708 REGMAP_IRQ_REG(BD72720_INT_VSYS_OV_DET, 5, BD72720_INT_VSYS_OV_DET_MASK), 709 REGMAP_IRQ_REG(BD72720_INT_BAT_ILIM, 6, BD72720_INT_BAT_ILIM_MASK), 710 REGMAP_IRQ_REG(BD72720_INT_CHG_DONE, 6, BD72720_INT_CHG_DONE_MASK), 711 REGMAP_IRQ_REG(BD72720_INT_EXTEMP_TOUT, 6, BD72720_INT_EXTEMP_TOUT_MASK), 712 REGMAP_IRQ_REG(BD72720_INT_CHG_WDT_EXP, 6, BD72720_INT_CHG_WDT_EXP_MASK), 713 REGMAP_IRQ_REG(BD72720_INT_BAT_MNT_OUT, 6, BD72720_INT_BAT_MNT_OUT_MASK), 714 REGMAP_IRQ_REG(BD72720_INT_BAT_MNT_IN, 6, BD72720_INT_BAT_MNT_IN_MASK), 715 REGMAP_IRQ_REG(BD72720_INT_CHG_TRNS, 6, BD72720_INT_CHG_TRNS_MASK), 716 717 REGMAP_IRQ_REG(BD72720_INT_VBAT_MON_RES, 7, BD72720_INT_VBAT_MON_RES_MASK), 718 REGMAP_IRQ_REG(BD72720_INT_VBAT_MON_DET, 7, BD72720_INT_VBAT_MON_DET_MASK), 719 REGMAP_IRQ_REG(BD72720_INT_VBAT_SHT_RES, 7, BD72720_INT_VBAT_SHT_RES_MASK), 720 REGMAP_IRQ_REG(BD72720_INT_VBAT_SHT_DET, 7, BD72720_INT_VBAT_SHT_DET_MASK), 721 REGMAP_IRQ_REG(BD72720_INT_VBAT_LO_RES, 7, BD72720_INT_VBAT_LO_RES_MASK), 722 REGMAP_IRQ_REG(BD72720_INT_VBAT_LO_DET, 7, BD72720_INT_VBAT_LO_DET_MASK), 723 REGMAP_IRQ_REG(BD72720_INT_VBAT_OV_RES, 7, BD72720_INT_VBAT_OV_RES_MASK), 724 REGMAP_IRQ_REG(BD72720_INT_VBAT_OV_DET, 7, BD72720_INT_VBAT_OV_DET_MASK), 725 REGMAP_IRQ_REG(BD72720_INT_BAT_RMV, 8, BD72720_INT_BAT_RMV_MASK), 726 REGMAP_IRQ_REG(BD72720_INT_BAT_DET, 8, BD72720_INT_BAT_DET_MASK), 727 REGMAP_IRQ_REG(BD72720_INT_DBAT_DET, 8, BD72720_INT_DBAT_DET_MASK), 728 REGMAP_IRQ_REG(BD72720_INT_BAT_TEMP_TRNS, 8, BD72720_INT_BAT_TEMP_TRNS_MASK), 729 REGMAP_IRQ_REG(BD72720_INT_LOBTMP_RES, 8, BD72720_INT_LOBTMP_RES_MASK), 730 REGMAP_IRQ_REG(BD72720_INT_LOBTMP_DET, 8, BD72720_INT_LOBTMP_DET_MASK), 731 REGMAP_IRQ_REG(BD72720_INT_OVBTMP_RES, 8, BD72720_INT_OVBTMP_RES_MASK), 732 REGMAP_IRQ_REG(BD72720_INT_OVBTMP_DET, 8, BD72720_INT_OVBTMP_DET_MASK), 733 REGMAP_IRQ_REG(BD72720_INT_OCUR1_RES, 9, BD72720_INT_OCUR1_RES_MASK), 734 REGMAP_IRQ_REG(BD72720_INT_OCUR1_DET, 9, BD72720_INT_OCUR1_DET_MASK), 735 REGMAP_IRQ_REG(BD72720_INT_OCUR2_RES, 9, BD72720_INT_OCUR2_RES_MASK), 736 REGMAP_IRQ_REG(BD72720_INT_OCUR2_DET, 9, BD72720_INT_OCUR2_DET_MASK), 737 REGMAP_IRQ_REG(BD72720_INT_OCUR3_RES, 9, BD72720_INT_OCUR3_RES_MASK), 738 REGMAP_IRQ_REG(BD72720_INT_OCUR3_DET, 9, BD72720_INT_OCUR3_DET_MASK), 739 REGMAP_IRQ_REG(BD72720_INT_CC_MON1_DET, 10, BD72720_INT_CC_MON1_DET_MASK), 740 REGMAP_IRQ_REG(BD72720_INT_CC_MON2_DET, 10, BD72720_INT_CC_MON2_DET_MASK), 741 REGMAP_IRQ_REG(BD72720_INT_CC_MON3_DET, 10, BD72720_INT_CC_MON3_DET_MASK), 742 /* 743 * The GPIO1_IN and GPIO2_IN IRQs are generated from the PMIC's GPIO1 and GPIO2 744 * pins. Eg, they may be wired to other devices which can then use the PMIC as 745 * an interrupt controller. The GPIO1 and GPIO2 can have the IRQ type 746 * specified. All of the types (falling, rising, and both edges as well as low 747 * and high levels) are supported. 748 */ 749 BD72720_TYPED_IRQ_REG(BD72720_INT_GPIO1_IN, 10, BD72720_INT_GPIO1_IN_MASK, 0), 750 BD72720_TYPED_IRQ_REG(BD72720_INT_GPIO2_IN, 10, BD72720_INT_GPIO2_IN_MASK, 1), 751 REGMAP_IRQ_REG(BD72720_INT_VF125_RES, 11, BD72720_INT_VF125_RES_MASK), 752 REGMAP_IRQ_REG(BD72720_INT_VF125_DET, 11, BD72720_INT_VF125_DET_MASK), 753 REGMAP_IRQ_REG(BD72720_INT_VF_RES, 11, BD72720_INT_VF_RES_MASK), 754 REGMAP_IRQ_REG(BD72720_INT_VF_DET, 11, BD72720_INT_VF_DET_MASK), 755 REGMAP_IRQ_REG(BD72720_INT_RTC0, 11, BD72720_INT_RTC0_MASK), 756 REGMAP_IRQ_REG(BD72720_INT_RTC1, 11, BD72720_INT_RTC1_MASK), 757 REGMAP_IRQ_REG(BD72720_INT_RTC2, 11, BD72720_INT_RTC2_MASK), 758 }; 759 760 static int bd72720_set_type_config(unsigned int **buf, unsigned int type, 761 const struct regmap_irq *irq_data, 762 int idx, void *irq_drv_data) 763 { 764 const struct regmap_irq_type *t = &irq_data->type; 765 766 /* 767 * The regmap IRQ ecpects IRQ_TYPE_EDGE_BOTH to be written to register 768 * as logical OR of the type_falling_val and type_rising_val. This is 769 * not how the BD72720 implements this configuration, hence we need 770 * to handle this specific case separately. 771 */ 772 if (type == IRQ_TYPE_EDGE_BOTH) { 773 buf[0][idx] &= ~t->type_reg_mask; 774 buf[0][idx] |= BD72720_GPIO_IRQ_TYPE_BOTH; 775 776 return 0; 777 } 778 779 return regmap_irq_set_type_config_simple(buf, type, irq_data, idx, irq_drv_data); 780 } 781 782 static const struct regmap_irq_chip bd71828_irq_chip = { 783 .name = "bd71828_irq", 784 .main_status = BD71828_REG_INT_MAIN, 785 .irqs = &bd71828_irqs[0], 786 .num_irqs = ARRAY_SIZE(bd71828_irqs), 787 .status_base = BD71828_REG_INT_BUCK, 788 .unmask_base = BD71828_REG_INT_MASK_BUCK, 789 .ack_base = BD71828_REG_INT_BUCK, 790 .init_ack_masked = true, 791 .num_regs = 12, 792 .num_main_regs = 1, 793 .sub_reg_offsets = &bd718xx_sub_irq_offsets[0], 794 .num_main_status_bits = 8, 795 .irq_reg_stride = 1, 796 }; 797 798 static const struct regmap_irq_chip bd71815_irq_chip = { 799 .name = "bd71815_irq", 800 .main_status = BD71815_REG_INT_STAT, 801 .irqs = &bd71815_irqs[0], 802 .num_irqs = ARRAY_SIZE(bd71815_irqs), 803 .status_base = BD71815_REG_INT_STAT_01, 804 .unmask_base = BD71815_REG_INT_EN_01, 805 .ack_base = BD71815_REG_INT_STAT_01, 806 .init_ack_masked = true, 807 .num_regs = 12, 808 .num_main_regs = 1, 809 .sub_reg_offsets = &bd718xx_sub_irq_offsets[0], 810 .num_main_status_bits = 8, 811 .irq_reg_stride = 1, 812 }; 813 814 static const unsigned int bd72720_irq_type_base[] = { BD72720_REG_GPIO1_CTRL }; 815 816 static const struct regmap_irq_chip bd72720_irq_chip = { 817 .name = "bd72720_irq", 818 .main_status = BD72720_REG_INT_LVL1_STAT, 819 .irqs = &bd72720_irqs[0], 820 .num_irqs = ARRAY_SIZE(bd72720_irqs), 821 .status_base = BD72720_REG_INT_PS1_STAT, 822 .unmask_base = BD72720_REG_INT_PS1_EN, 823 .config_base = &bd72720_irq_type_base[0], 824 .num_config_bases = 1, 825 .num_config_regs = 2, 826 .set_type_config = bd72720_set_type_config, 827 .ack_base = BD72720_REG_INT_PS1_STAT, 828 .init_ack_masked = true, 829 .num_regs = 12, 830 .num_main_regs = 1, 831 .sub_reg_offsets = &bd72720_sub_irq_offsets[0], 832 .num_main_status_bits = 8, 833 .irq_reg_stride = 1, 834 }; 835 836 static int set_clk_mode(struct device *dev, struct regmap *regmap, 837 int clkmode_reg) 838 { 839 int ret; 840 unsigned int open_drain; 841 842 ret = of_property_read_u32(dev->of_node, "rohm,clkout-open-drain", &open_drain); 843 if (ret) { 844 if (ret == -EINVAL) 845 return 0; 846 return ret; 847 } 848 if (open_drain > 1) { 849 dev_err(dev, "bad clk32kout mode configuration"); 850 return -EINVAL; 851 } 852 853 if (open_drain) 854 return regmap_update_bits(regmap, clkmode_reg, OUT32K_MODE, 855 OUT32K_MODE_OPEN_DRAIN); 856 857 return regmap_update_bits(regmap, clkmode_reg, OUT32K_MODE, 858 OUT32K_MODE_CMOS); 859 } 860 861 862 863 static struct i2c_client *bd71828_dev; 864 static void bd71828_power_off(void) 865 { 866 while (true) { 867 s32 val; 868 869 /* We are not allowed to sleep, so do not use regmap involving mutexes here. */ 870 val = i2c_smbus_read_byte_data(bd71828_dev, BD71828_REG_PS_CTRL_1); 871 if (val >= 0) 872 i2c_smbus_write_byte_data(bd71828_dev, 873 BD71828_REG_PS_CTRL_1, 874 BD71828_MASK_STATE_HBNT | (u8)val); 875 mdelay(500); 876 } 877 } 878 879 static void bd71828_remove_poweroff(void *data) 880 { 881 pm_power_off = NULL; 882 } 883 884 static struct regmap *bd72720_do_regmaps(struct i2c_client *i2c) 885 { 886 struct bd72720_regmaps *maps; 887 struct i2c_client *secondary_i2c; 888 889 secondary_i2c = devm_i2c_new_dummy_device(&i2c->dev, i2c->adapter, 890 BD72720_SECONDARY_I2C_SLAVE); 891 if (IS_ERR(secondary_i2c)) { 892 dev_err_probe(&i2c->dev, PTR_ERR(secondary_i2c), "Failed to get secondary I2C\n"); 893 894 return ERR_CAST(secondary_i2c); 895 } 896 897 maps = devm_kzalloc(&i2c->dev, sizeof(*maps), GFP_KERNEL); 898 if (!maps) 899 return ERR_PTR(-ENOMEM); 900 901 maps->map1_4b = devm_regmap_init_i2c(i2c, &bd72720_regmap_4b); 902 if (IS_ERR(maps->map1_4b)) 903 return maps->map1_4b; 904 905 maps->map2_4c = devm_regmap_init_i2c(secondary_i2c, &bd72720_regmap_4c); 906 if (IS_ERR(maps->map2_4c)) 907 return maps->map2_4c; 908 909 return devm_regmap_init(&i2c->dev, NULL, maps, &bd72720_wrapper_map_config); 910 } 911 912 static int bd71828_i2c_probe(struct i2c_client *i2c) 913 { 914 struct regmap_irq_chip_data *irq_data; 915 struct irq_domain *irq_domain; 916 int ret; 917 struct regmap *regmap = NULL; 918 const struct regmap_config *regmap_config; 919 const struct regmap_irq_chip *irqchip; 920 unsigned int chip_type; 921 const struct mfd_cell *mfd; 922 int cells; 923 int button_irq; 924 int clkmode_reg; 925 int main_lvl_mask_reg = 0, main_lvl_val = 0; 926 927 if (!i2c->irq) { 928 dev_err(&i2c->dev, "No IRQ configured\n"); 929 return -EINVAL; 930 } 931 932 chip_type = (unsigned int)(uintptr_t) 933 of_device_get_match_data(&i2c->dev); 934 switch (chip_type) { 935 case ROHM_CHIP_TYPE_BD71828: 936 mfd = bd71828_mfd_cells; 937 cells = ARRAY_SIZE(bd71828_mfd_cells); 938 regmap_config = &bd71828_regmap; 939 irqchip = &bd71828_irq_chip; 940 clkmode_reg = BD71828_REG_OUT32K; 941 button_irq = BD71828_INT_SHORTPUSH; 942 break; 943 case ROHM_CHIP_TYPE_BD71815: 944 mfd = bd71815_mfd_cells; 945 cells = ARRAY_SIZE(bd71815_mfd_cells); 946 regmap_config = &bd71815_regmap; 947 irqchip = &bd71815_irq_chip; 948 clkmode_reg = BD71815_REG_OUT32K; 949 /* 950 * If BD71817 support is needed we should be able to handle it 951 * with proper DT configs + BD71815 drivers + power-button. 952 * BD71815 data-sheet does not list the power-button IRQ so we 953 * don't use it. 954 */ 955 button_irq = 0; 956 break; 957 case ROHM_CHIP_TYPE_BD72720: 958 { 959 mfd = bd72720_mfd_cells; 960 cells = ARRAY_SIZE(bd72720_mfd_cells); 961 962 regmap = bd72720_do_regmaps(i2c); 963 if (IS_ERR(regmap)) 964 return dev_err_probe(&i2c->dev, PTR_ERR(regmap), 965 "Failed to initialize Regmap\n"); 966 967 irqchip = &bd72720_irq_chip; 968 clkmode_reg = BD72720_REG_OUT32K; 969 button_irq = BD72720_INT_SHORTPUSH; 970 main_lvl_mask_reg = BD72720_REG_INT_LVL1_EN; 971 main_lvl_val = BD72720_MASK_LVL1_EN_ALL; 972 break; 973 } 974 default: 975 dev_err(&i2c->dev, "Unknown device type"); 976 return -EINVAL; 977 } 978 979 if (!regmap) { 980 regmap = devm_regmap_init_i2c(i2c, regmap_config); 981 if (IS_ERR(regmap)) 982 return dev_err_probe(&i2c->dev, PTR_ERR(regmap), 983 "Failed to initialize Regmap\n"); 984 } 985 986 ret = devm_regmap_add_irq_chip(&i2c->dev, regmap, i2c->irq, 987 IRQF_ONESHOT, 0, irqchip, &irq_data); 988 if (ret) 989 return dev_err_probe(&i2c->dev, ret, 990 "Failed to add IRQ chip\n"); 991 992 dev_dbg(&i2c->dev, "Registered %d IRQs for chip\n", 993 irqchip->num_irqs); 994 995 /* 996 * On some ICs the main IRQ register has corresponding mask register. 997 * This is not handled by the regmap IRQ. Let's enable all the main 998 * level IRQs here. Further writes to the main level MASK is not 999 * needed because masking is handled by the per IRQ 2.nd level MASK 1000 * registers. 2.nd level masks are handled by the regmap IRQ. 1001 */ 1002 if (main_lvl_mask_reg) { 1003 ret = regmap_write(regmap, main_lvl_mask_reg, main_lvl_val); 1004 if (ret) { 1005 return dev_err_probe(&i2c->dev, ret, 1006 "Failed to enable main level IRQs\n"); 1007 } 1008 } 1009 1010 ret = set_clk_mode(&i2c->dev, regmap, clkmode_reg); 1011 if (ret) 1012 return ret; 1013 1014 irq_domain = regmap_irq_get_domain(irq_data); 1015 1016 ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO, mfd, cells, 1017 NULL, 0, irq_domain); 1018 if (ret) 1019 return dev_err_probe(&i2c->dev, ret, "Failed to create subdevices\n"); 1020 1021 if (button_irq) { 1022 ret = rohm_register_pwrbutton(&i2c->dev, button_irq, 1023 "bd71828-pwrkey", true, irq_domain); 1024 if (ret) 1025 return ret; 1026 } 1027 1028 if (of_device_is_system_power_controller(i2c->dev.of_node) && 1029 chip_type == ROHM_CHIP_TYPE_BD71828) { 1030 if (!pm_power_off) { 1031 bd71828_dev = i2c; 1032 pm_power_off = bd71828_power_off; 1033 ret = devm_add_action_or_reset(&i2c->dev, 1034 bd71828_remove_poweroff, 1035 NULL); 1036 } else { 1037 dev_warn(&i2c->dev, "Poweroff callback already assigned\n"); 1038 } 1039 } 1040 1041 return ret; 1042 } 1043 1044 static const struct of_device_id bd71828_of_match[] = { 1045 { 1046 .compatible = "rohm,bd71828", 1047 .data = (void *)ROHM_CHIP_TYPE_BD71828, 1048 }, { 1049 .compatible = "rohm,bd71815", 1050 .data = (void *)ROHM_CHIP_TYPE_BD71815, 1051 }, { 1052 .compatible = "rohm,bd72720", 1053 .data = (void *)ROHM_CHIP_TYPE_BD72720, 1054 }, 1055 { }, 1056 }; 1057 MODULE_DEVICE_TABLE(of, bd71828_of_match); 1058 1059 static struct i2c_driver bd71828_drv = { 1060 .driver = { 1061 .name = "rohm-bd71828", 1062 .of_match_table = bd71828_of_match, 1063 }, 1064 .probe = bd71828_i2c_probe, 1065 }; 1066 module_i2c_driver(bd71828_drv); 1067 1068 MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>"); 1069 MODULE_DESCRIPTION("ROHM BD71828 Power Management IC driver"); 1070 MODULE_LICENSE("GPL"); 1071