1 /* 2 * Interrupt driver for RICOH583 power management chip. 3 * 4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. 5 * Author: Laxman dewangan <ldewangan@nvidia.com> 6 * 7 * based on code 8 * Copyright (C) 2011 RICOH COMPANY,LTD 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms and conditions of the GNU General Public License, 12 * version 2, as published by the Free Software Foundation. 13 * 14 * This program is distributed in the hope it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program. If not, see <http://www.gnu.org/licenses/>. 21 * 22 */ 23 #include <linux/interrupt.h> 24 #include <linux/irq.h> 25 #include <linux/init.h> 26 #include <linux/i2c.h> 27 #include <linux/mfd/rc5t583.h> 28 29 enum int_type { 30 SYS_INT = 0x1, 31 DCDC_INT = 0x2, 32 RTC_INT = 0x4, 33 ADC_INT = 0x8, 34 GPIO_INT = 0x10, 35 }; 36 37 static int gpedge_add[] = { 38 RC5T583_GPIO_GPEDGE2, 39 RC5T583_GPIO_GPEDGE2 40 }; 41 42 static int irq_en_add[] = { 43 RC5T583_INT_EN_SYS1, 44 RC5T583_INT_EN_SYS2, 45 RC5T583_INT_EN_DCDC, 46 RC5T583_INT_EN_RTC, 47 RC5T583_INT_EN_ADC1, 48 RC5T583_INT_EN_ADC2, 49 RC5T583_INT_EN_ADC3, 50 RC5T583_GPIO_EN_INT 51 }; 52 53 static int irq_mon_add[] = { 54 RC5T583_INT_MON_SYS1, 55 RC5T583_INT_MON_SYS2, 56 RC5T583_INT_MON_DCDC, 57 RC5T583_INT_MON_RTC, 58 RC5T583_INT_IR_ADCL, 59 RC5T583_INT_IR_ADCH, 60 RC5T583_INT_IR_ADCEND, 61 RC5T583_INT_IR_GPIOF, 62 RC5T583_INT_IR_GPIOR 63 }; 64 65 static int irq_clr_add[] = { 66 RC5T583_INT_IR_SYS1, 67 RC5T583_INT_IR_SYS2, 68 RC5T583_INT_IR_DCDC, 69 RC5T583_INT_IR_RTC, 70 RC5T583_INT_IR_ADCL, 71 RC5T583_INT_IR_ADCH, 72 RC5T583_INT_IR_ADCEND, 73 RC5T583_INT_IR_GPIOF, 74 RC5T583_INT_IR_GPIOR 75 }; 76 77 static int main_int_type[] = { 78 SYS_INT, 79 SYS_INT, 80 DCDC_INT, 81 RTC_INT, 82 ADC_INT, 83 ADC_INT, 84 ADC_INT, 85 GPIO_INT, 86 GPIO_INT, 87 }; 88 89 struct rc5t583_irq_data { 90 u8 int_type; 91 u8 master_bit; 92 u8 int_en_bit; 93 u8 mask_reg_index; 94 int grp_index; 95 }; 96 97 #define RC5T583_IRQ(_int_type, _master_bit, _grp_index, \ 98 _int_bit, _mask_ind) \ 99 { \ 100 .int_type = _int_type, \ 101 .master_bit = _master_bit, \ 102 .grp_index = _grp_index, \ 103 .int_en_bit = _int_bit, \ 104 .mask_reg_index = _mask_ind, \ 105 } 106 107 static const struct rc5t583_irq_data rc5t583_irqs[RC5T583_MAX_IRQS] = { 108 [RC5T583_IRQ_ONKEY] = RC5T583_IRQ(SYS_INT, 0, 0, 0, 0), 109 [RC5T583_IRQ_ACOK] = RC5T583_IRQ(SYS_INT, 0, 1, 1, 0), 110 [RC5T583_IRQ_LIDOPEN] = RC5T583_IRQ(SYS_INT, 0, 2, 2, 0), 111 [RC5T583_IRQ_PREOT] = RC5T583_IRQ(SYS_INT, 0, 3, 3, 0), 112 [RC5T583_IRQ_CLKSTP] = RC5T583_IRQ(SYS_INT, 0, 4, 4, 0), 113 [RC5T583_IRQ_ONKEY_OFF] = RC5T583_IRQ(SYS_INT, 0, 5, 5, 0), 114 [RC5T583_IRQ_WD] = RC5T583_IRQ(SYS_INT, 0, 7, 7, 0), 115 [RC5T583_IRQ_EN_PWRREQ1] = RC5T583_IRQ(SYS_INT, 0, 8, 0, 1), 116 [RC5T583_IRQ_EN_PWRREQ2] = RC5T583_IRQ(SYS_INT, 0, 9, 1, 1), 117 [RC5T583_IRQ_PRE_VINDET] = RC5T583_IRQ(SYS_INT, 0, 10, 2, 1), 118 119 [RC5T583_IRQ_DC0LIM] = RC5T583_IRQ(DCDC_INT, 1, 0, 0, 2), 120 [RC5T583_IRQ_DC1LIM] = RC5T583_IRQ(DCDC_INT, 1, 1, 1, 2), 121 [RC5T583_IRQ_DC2LIM] = RC5T583_IRQ(DCDC_INT, 1, 2, 2, 2), 122 [RC5T583_IRQ_DC3LIM] = RC5T583_IRQ(DCDC_INT, 1, 3, 3, 2), 123 124 [RC5T583_IRQ_CTC] = RC5T583_IRQ(RTC_INT, 2, 0, 0, 3), 125 [RC5T583_IRQ_YALE] = RC5T583_IRQ(RTC_INT, 2, 5, 5, 3), 126 [RC5T583_IRQ_DALE] = RC5T583_IRQ(RTC_INT, 2, 6, 6, 3), 127 [RC5T583_IRQ_WALE] = RC5T583_IRQ(RTC_INT, 2, 7, 7, 3), 128 129 [RC5T583_IRQ_AIN1L] = RC5T583_IRQ(ADC_INT, 3, 0, 0, 4), 130 [RC5T583_IRQ_AIN2L] = RC5T583_IRQ(ADC_INT, 3, 1, 1, 4), 131 [RC5T583_IRQ_AIN3L] = RC5T583_IRQ(ADC_INT, 3, 2, 2, 4), 132 [RC5T583_IRQ_VBATL] = RC5T583_IRQ(ADC_INT, 3, 3, 3, 4), 133 [RC5T583_IRQ_VIN3L] = RC5T583_IRQ(ADC_INT, 3, 4, 4, 4), 134 [RC5T583_IRQ_VIN8L] = RC5T583_IRQ(ADC_INT, 3, 5, 5, 4), 135 [RC5T583_IRQ_AIN1H] = RC5T583_IRQ(ADC_INT, 3, 6, 0, 5), 136 [RC5T583_IRQ_AIN2H] = RC5T583_IRQ(ADC_INT, 3, 7, 1, 5), 137 [RC5T583_IRQ_AIN3H] = RC5T583_IRQ(ADC_INT, 3, 8, 2, 5), 138 [RC5T583_IRQ_VBATH] = RC5T583_IRQ(ADC_INT, 3, 9, 3, 5), 139 [RC5T583_IRQ_VIN3H] = RC5T583_IRQ(ADC_INT, 3, 10, 4, 5), 140 [RC5T583_IRQ_VIN8H] = RC5T583_IRQ(ADC_INT, 3, 11, 5, 5), 141 [RC5T583_IRQ_ADCEND] = RC5T583_IRQ(ADC_INT, 3, 12, 0, 6), 142 143 [RC5T583_IRQ_GPIO0] = RC5T583_IRQ(GPIO_INT, 4, 0, 0, 7), 144 [RC5T583_IRQ_GPIO1] = RC5T583_IRQ(GPIO_INT, 4, 1, 1, 7), 145 [RC5T583_IRQ_GPIO2] = RC5T583_IRQ(GPIO_INT, 4, 2, 2, 7), 146 [RC5T583_IRQ_GPIO3] = RC5T583_IRQ(GPIO_INT, 4, 3, 3, 7), 147 [RC5T583_IRQ_GPIO4] = RC5T583_IRQ(GPIO_INT, 4, 4, 4, 7), 148 [RC5T583_IRQ_GPIO5] = RC5T583_IRQ(GPIO_INT, 4, 5, 5, 7), 149 [RC5T583_IRQ_GPIO6] = RC5T583_IRQ(GPIO_INT, 4, 6, 6, 7), 150 [RC5T583_IRQ_GPIO7] = RC5T583_IRQ(GPIO_INT, 4, 7, 7, 7), 151 }; 152 153 static void rc5t583_irq_lock(struct irq_data *irq_data) 154 { 155 struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data); 156 mutex_lock(&rc5t583->irq_lock); 157 } 158 159 static void rc5t583_irq_unmask(struct irq_data *irq_data) 160 { 161 struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data); 162 unsigned int __irq = irq_data->irq - rc5t583->irq_base; 163 const struct rc5t583_irq_data *data = &rc5t583_irqs[__irq]; 164 165 rc5t583->group_irq_en[data->grp_index] |= 1 << data->grp_index; 166 rc5t583->intc_inten_reg |= 1 << data->master_bit; 167 rc5t583->irq_en_reg[data->mask_reg_index] |= 1 << data->int_en_bit; 168 } 169 170 static void rc5t583_irq_mask(struct irq_data *irq_data) 171 { 172 struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data); 173 unsigned int __irq = irq_data->irq - rc5t583->irq_base; 174 const struct rc5t583_irq_data *data = &rc5t583_irqs[__irq]; 175 176 rc5t583->group_irq_en[data->grp_index] &= ~(1 << data->grp_index); 177 if (!rc5t583->group_irq_en[data->grp_index]) 178 rc5t583->intc_inten_reg &= ~(1 << data->master_bit); 179 180 rc5t583->irq_en_reg[data->mask_reg_index] &= ~(1 << data->int_en_bit); 181 } 182 183 static int rc5t583_irq_set_type(struct irq_data *irq_data, unsigned int type) 184 { 185 struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data); 186 unsigned int __irq = irq_data->irq - rc5t583->irq_base; 187 const struct rc5t583_irq_data *data = &rc5t583_irqs[__irq]; 188 int val = 0; 189 int gpedge_index; 190 int gpedge_bit_pos; 191 192 /* Supporting only trigger level inetrrupt */ 193 if ((data->int_type & GPIO_INT) && (type & IRQ_TYPE_EDGE_BOTH)) { 194 gpedge_index = data->int_en_bit / 4; 195 gpedge_bit_pos = data->int_en_bit % 4; 196 197 if (type & IRQ_TYPE_EDGE_FALLING) 198 val |= 0x2; 199 200 if (type & IRQ_TYPE_EDGE_RISING) 201 val |= 0x1; 202 203 rc5t583->gpedge_reg[gpedge_index] &= ~(3 << gpedge_bit_pos); 204 rc5t583->gpedge_reg[gpedge_index] |= (val << gpedge_bit_pos); 205 rc5t583_irq_unmask(irq_data); 206 return 0; 207 } 208 return -EINVAL; 209 } 210 211 static void rc5t583_irq_sync_unlock(struct irq_data *irq_data) 212 { 213 struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data); 214 int i; 215 int ret; 216 217 for (i = 0; i < ARRAY_SIZE(rc5t583->gpedge_reg); i++) { 218 ret = rc5t583_write(rc5t583->dev, gpedge_add[i], 219 rc5t583->gpedge_reg[i]); 220 if (ret < 0) 221 dev_warn(rc5t583->dev, 222 "Error in writing reg 0x%02x error: %d\n", 223 gpedge_add[i], ret); 224 } 225 226 for (i = 0; i < ARRAY_SIZE(rc5t583->irq_en_reg); i++) { 227 ret = rc5t583_write(rc5t583->dev, irq_en_add[i], 228 rc5t583->irq_en_reg[i]); 229 if (ret < 0) 230 dev_warn(rc5t583->dev, 231 "Error in writing reg 0x%02x error: %d\n", 232 irq_en_add[i], ret); 233 } 234 235 ret = rc5t583_write(rc5t583->dev, RC5T583_INTC_INTEN, 236 rc5t583->intc_inten_reg); 237 if (ret < 0) 238 dev_warn(rc5t583->dev, 239 "Error in writing reg 0x%02x error: %d\n", 240 RC5T583_INTC_INTEN, ret); 241 242 mutex_unlock(&rc5t583->irq_lock); 243 } 244 #ifdef CONFIG_PM_SLEEP 245 static int rc5t583_irq_set_wake(struct irq_data *irq_data, unsigned int on) 246 { 247 struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data); 248 return irq_set_irq_wake(rc5t583->chip_irq, on); 249 } 250 #else 251 #define rc5t583_irq_set_wake NULL 252 #endif 253 254 static irqreturn_t rc5t583_irq(int irq, void *data) 255 { 256 struct rc5t583 *rc5t583 = data; 257 uint8_t int_sts[RC5T583_MAX_INTERRUPT_MASK_REGS]; 258 uint8_t master_int; 259 int i; 260 int ret; 261 unsigned int rtc_int_sts = 0; 262 263 /* Clear the status */ 264 for (i = 0; i < RC5T583_MAX_INTERRUPT_MASK_REGS; i++) 265 int_sts[i] = 0; 266 267 ret = rc5t583_read(rc5t583->dev, RC5T583_INTC_INTMON, &master_int); 268 if (ret < 0) { 269 dev_err(rc5t583->dev, 270 "Error in reading reg 0x%02x error: %d\n", 271 RC5T583_INTC_INTMON, ret); 272 return IRQ_HANDLED; 273 } 274 275 for (i = 0; i < RC5T583_MAX_INTERRUPT_MASK_REGS; ++i) { 276 if (!(master_int & main_int_type[i])) 277 continue; 278 279 ret = rc5t583_read(rc5t583->dev, irq_mon_add[i], &int_sts[i]); 280 if (ret < 0) { 281 dev_warn(rc5t583->dev, 282 "Error in reading reg 0x%02x error: %d\n", 283 irq_mon_add[i], ret); 284 int_sts[i] = 0; 285 continue; 286 } 287 288 if (main_int_type[i] & RTC_INT) { 289 rtc_int_sts = 0; 290 if (int_sts[i] & 0x1) 291 rtc_int_sts |= BIT(6); 292 if (int_sts[i] & 0x2) 293 rtc_int_sts |= BIT(7); 294 if (int_sts[i] & 0x4) 295 rtc_int_sts |= BIT(0); 296 if (int_sts[i] & 0x8) 297 rtc_int_sts |= BIT(5); 298 } 299 300 ret = rc5t583_write(rc5t583->dev, irq_clr_add[i], 301 ~int_sts[i]); 302 if (ret < 0) 303 dev_warn(rc5t583->dev, 304 "Error in reading reg 0x%02x error: %d\n", 305 irq_clr_add[i], ret); 306 307 if (main_int_type[i] & RTC_INT) 308 int_sts[i] = rtc_int_sts; 309 } 310 311 /* Merge gpio interrupts for rising and falling case*/ 312 int_sts[7] |= int_sts[8]; 313 314 /* Call interrupt handler if enabled */ 315 for (i = 0; i < RC5T583_MAX_IRQS; ++i) { 316 const struct rc5t583_irq_data *data = &rc5t583_irqs[i]; 317 if ((int_sts[data->mask_reg_index] & (1 << data->int_en_bit)) && 318 (rc5t583->group_irq_en[data->master_bit] & 319 (1 << data->grp_index))) 320 handle_nested_irq(rc5t583->irq_base + i); 321 } 322 323 return IRQ_HANDLED; 324 } 325 326 static struct irq_chip rc5t583_irq_chip = { 327 .name = "rc5t583-irq", 328 .irq_mask = rc5t583_irq_mask, 329 .irq_unmask = rc5t583_irq_unmask, 330 .irq_bus_lock = rc5t583_irq_lock, 331 .irq_bus_sync_unlock = rc5t583_irq_sync_unlock, 332 .irq_set_type = rc5t583_irq_set_type, 333 .irq_set_wake = rc5t583_irq_set_wake, 334 }; 335 336 int rc5t583_irq_init(struct rc5t583 *rc5t583, int irq, int irq_base) 337 { 338 int i, ret; 339 340 if (!irq_base) { 341 dev_warn(rc5t583->dev, "No interrupt support on IRQ base\n"); 342 return -EINVAL; 343 } 344 345 mutex_init(&rc5t583->irq_lock); 346 347 /* Initailize all int register to 0 */ 348 for (i = 0; i < RC5T583_MAX_INTERRUPT_MASK_REGS; i++) { 349 ret = rc5t583_write(rc5t583->dev, irq_en_add[i], 350 rc5t583->irq_en_reg[i]); 351 if (ret < 0) 352 dev_warn(rc5t583->dev, 353 "Error in writing reg 0x%02x error: %d\n", 354 irq_en_add[i], ret); 355 } 356 357 for (i = 0; i < RC5T583_MAX_GPEDGE_REG; i++) { 358 ret = rc5t583_write(rc5t583->dev, gpedge_add[i], 359 rc5t583->gpedge_reg[i]); 360 if (ret < 0) 361 dev_warn(rc5t583->dev, 362 "Error in writing reg 0x%02x error: %d\n", 363 gpedge_add[i], ret); 364 } 365 366 ret = rc5t583_write(rc5t583->dev, RC5T583_INTC_INTEN, 0x0); 367 if (ret < 0) 368 dev_warn(rc5t583->dev, 369 "Error in writing reg 0x%02x error: %d\n", 370 RC5T583_INTC_INTEN, ret); 371 372 /* Clear all interrupts in case they woke up active. */ 373 for (i = 0; i < RC5T583_MAX_INTERRUPT_MASK_REGS; i++) { 374 ret = rc5t583_write(rc5t583->dev, irq_clr_add[i], 0); 375 if (ret < 0) 376 dev_warn(rc5t583->dev, 377 "Error in writing reg 0x%02x error: %d\n", 378 irq_clr_add[i], ret); 379 } 380 381 rc5t583->irq_base = irq_base; 382 rc5t583->chip_irq = irq; 383 384 for (i = 0; i < RC5T583_MAX_IRQS; i++) { 385 int __irq = i + rc5t583->irq_base; 386 irq_set_chip_data(__irq, rc5t583); 387 irq_set_chip_and_handler(__irq, &rc5t583_irq_chip, 388 handle_simple_irq); 389 irq_set_nested_thread(__irq, 1); 390 #ifdef CONFIG_ARM 391 set_irq_flags(__irq, IRQF_VALID); 392 #endif 393 } 394 395 ret = request_threaded_irq(irq, NULL, rc5t583_irq, IRQF_ONESHOT, 396 "rc5t583", rc5t583); 397 if (ret < 0) 398 dev_err(rc5t583->dev, 399 "Error in registering interrupt error: %d\n", ret); 400 return ret; 401 } 402 403 int rc5t583_irq_exit(struct rc5t583 *rc5t583) 404 { 405 if (rc5t583->chip_irq) 406 free_irq(rc5t583->chip_irq, rc5t583); 407 return 0; 408 } 409