19952f691SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
21b1247ddSLaxman Dewangan /*
31b1247ddSLaxman Dewangan * Interrupt driver for RICOH583 power management chip.
41b1247ddSLaxman Dewangan *
51b1247ddSLaxman Dewangan * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
61b1247ddSLaxman Dewangan * Author: Laxman dewangan <ldewangan@nvidia.com>
71b1247ddSLaxman Dewangan *
81b1247ddSLaxman Dewangan * based on code
91b1247ddSLaxman Dewangan * Copyright (C) 2011 RICOH COMPANY,LTD
101b1247ddSLaxman Dewangan */
11*bab5ab47SChristophe JAILLET #include <linux/device.h>
121b1247ddSLaxman Dewangan #include <linux/interrupt.h>
131b1247ddSLaxman Dewangan #include <linux/irq.h>
141b1247ddSLaxman Dewangan #include <linux/mfd/rc5t583.h>
151b1247ddSLaxman Dewangan
161b1247ddSLaxman Dewangan enum int_type {
171b1247ddSLaxman Dewangan SYS_INT = 0x1,
181b1247ddSLaxman Dewangan DCDC_INT = 0x2,
191b1247ddSLaxman Dewangan RTC_INT = 0x4,
201b1247ddSLaxman Dewangan ADC_INT = 0x8,
211b1247ddSLaxman Dewangan GPIO_INT = 0x10,
221b1247ddSLaxman Dewangan };
231b1247ddSLaxman Dewangan
241b1247ddSLaxman Dewangan static int gpedge_add[] = {
251b1247ddSLaxman Dewangan RC5T583_GPIO_GPEDGE2,
261b1247ddSLaxman Dewangan RC5T583_GPIO_GPEDGE2
271b1247ddSLaxman Dewangan };
281b1247ddSLaxman Dewangan
291b1247ddSLaxman Dewangan static int irq_en_add[] = {
301b1247ddSLaxman Dewangan RC5T583_INT_EN_SYS1,
311b1247ddSLaxman Dewangan RC5T583_INT_EN_SYS2,
321b1247ddSLaxman Dewangan RC5T583_INT_EN_DCDC,
331b1247ddSLaxman Dewangan RC5T583_INT_EN_RTC,
341b1247ddSLaxman Dewangan RC5T583_INT_EN_ADC1,
351b1247ddSLaxman Dewangan RC5T583_INT_EN_ADC2,
361b1247ddSLaxman Dewangan RC5T583_INT_EN_ADC3,
371b1247ddSLaxman Dewangan RC5T583_GPIO_EN_INT
381b1247ddSLaxman Dewangan };
391b1247ddSLaxman Dewangan
401b1247ddSLaxman Dewangan static int irq_mon_add[] = {
411b1247ddSLaxman Dewangan RC5T583_INT_MON_SYS1,
421b1247ddSLaxman Dewangan RC5T583_INT_MON_SYS2,
431b1247ddSLaxman Dewangan RC5T583_INT_MON_DCDC,
441b1247ddSLaxman Dewangan RC5T583_INT_MON_RTC,
451b1247ddSLaxman Dewangan RC5T583_INT_IR_ADCL,
461b1247ddSLaxman Dewangan RC5T583_INT_IR_ADCH,
471b1247ddSLaxman Dewangan RC5T583_INT_IR_ADCEND,
481b1247ddSLaxman Dewangan RC5T583_INT_IR_GPIOF,
491b1247ddSLaxman Dewangan RC5T583_INT_IR_GPIOR
501b1247ddSLaxman Dewangan };
511b1247ddSLaxman Dewangan
521b1247ddSLaxman Dewangan static int irq_clr_add[] = {
531b1247ddSLaxman Dewangan RC5T583_INT_IR_SYS1,
541b1247ddSLaxman Dewangan RC5T583_INT_IR_SYS2,
551b1247ddSLaxman Dewangan RC5T583_INT_IR_DCDC,
561b1247ddSLaxman Dewangan RC5T583_INT_IR_RTC,
571b1247ddSLaxman Dewangan RC5T583_INT_IR_ADCL,
581b1247ddSLaxman Dewangan RC5T583_INT_IR_ADCH,
591b1247ddSLaxman Dewangan RC5T583_INT_IR_ADCEND,
601b1247ddSLaxman Dewangan RC5T583_INT_IR_GPIOF,
611b1247ddSLaxman Dewangan RC5T583_INT_IR_GPIOR
621b1247ddSLaxman Dewangan };
631b1247ddSLaxman Dewangan
641b1247ddSLaxman Dewangan static int main_int_type[] = {
651b1247ddSLaxman Dewangan SYS_INT,
661b1247ddSLaxman Dewangan SYS_INT,
671b1247ddSLaxman Dewangan DCDC_INT,
681b1247ddSLaxman Dewangan RTC_INT,
691b1247ddSLaxman Dewangan ADC_INT,
701b1247ddSLaxman Dewangan ADC_INT,
711b1247ddSLaxman Dewangan ADC_INT,
721b1247ddSLaxman Dewangan GPIO_INT,
731b1247ddSLaxman Dewangan GPIO_INT,
741b1247ddSLaxman Dewangan };
751b1247ddSLaxman Dewangan
761b1247ddSLaxman Dewangan struct rc5t583_irq_data {
771b1247ddSLaxman Dewangan u8 int_type;
781b1247ddSLaxman Dewangan u8 master_bit;
791b1247ddSLaxman Dewangan u8 int_en_bit;
801b1247ddSLaxman Dewangan u8 mask_reg_index;
811b1247ddSLaxman Dewangan int grp_index;
821b1247ddSLaxman Dewangan };
831b1247ddSLaxman Dewangan
841b1247ddSLaxman Dewangan #define RC5T583_IRQ(_int_type, _master_bit, _grp_index, \
851b1247ddSLaxman Dewangan _int_bit, _mask_ind) \
861b1247ddSLaxman Dewangan { \
871b1247ddSLaxman Dewangan .int_type = _int_type, \
881b1247ddSLaxman Dewangan .master_bit = _master_bit, \
891b1247ddSLaxman Dewangan .grp_index = _grp_index, \
901b1247ddSLaxman Dewangan .int_en_bit = _int_bit, \
911b1247ddSLaxman Dewangan .mask_reg_index = _mask_ind, \
921b1247ddSLaxman Dewangan }
931b1247ddSLaxman Dewangan
941b1247ddSLaxman Dewangan static const struct rc5t583_irq_data rc5t583_irqs[RC5T583_MAX_IRQS] = {
951b1247ddSLaxman Dewangan [RC5T583_IRQ_ONKEY] = RC5T583_IRQ(SYS_INT, 0, 0, 0, 0),
961b1247ddSLaxman Dewangan [RC5T583_IRQ_ACOK] = RC5T583_IRQ(SYS_INT, 0, 1, 1, 0),
971b1247ddSLaxman Dewangan [RC5T583_IRQ_LIDOPEN] = RC5T583_IRQ(SYS_INT, 0, 2, 2, 0),
981b1247ddSLaxman Dewangan [RC5T583_IRQ_PREOT] = RC5T583_IRQ(SYS_INT, 0, 3, 3, 0),
991b1247ddSLaxman Dewangan [RC5T583_IRQ_CLKSTP] = RC5T583_IRQ(SYS_INT, 0, 4, 4, 0),
1001b1247ddSLaxman Dewangan [RC5T583_IRQ_ONKEY_OFF] = RC5T583_IRQ(SYS_INT, 0, 5, 5, 0),
1011b1247ddSLaxman Dewangan [RC5T583_IRQ_WD] = RC5T583_IRQ(SYS_INT, 0, 7, 7, 0),
1021b1247ddSLaxman Dewangan [RC5T583_IRQ_EN_PWRREQ1] = RC5T583_IRQ(SYS_INT, 0, 8, 0, 1),
1031b1247ddSLaxman Dewangan [RC5T583_IRQ_EN_PWRREQ2] = RC5T583_IRQ(SYS_INT, 0, 9, 1, 1),
1041b1247ddSLaxman Dewangan [RC5T583_IRQ_PRE_VINDET] = RC5T583_IRQ(SYS_INT, 0, 10, 2, 1),
1051b1247ddSLaxman Dewangan
1061b1247ddSLaxman Dewangan [RC5T583_IRQ_DC0LIM] = RC5T583_IRQ(DCDC_INT, 1, 0, 0, 2),
1071b1247ddSLaxman Dewangan [RC5T583_IRQ_DC1LIM] = RC5T583_IRQ(DCDC_INT, 1, 1, 1, 2),
1081b1247ddSLaxman Dewangan [RC5T583_IRQ_DC2LIM] = RC5T583_IRQ(DCDC_INT, 1, 2, 2, 2),
1091b1247ddSLaxman Dewangan [RC5T583_IRQ_DC3LIM] = RC5T583_IRQ(DCDC_INT, 1, 3, 3, 2),
1101b1247ddSLaxman Dewangan
1111b1247ddSLaxman Dewangan [RC5T583_IRQ_CTC] = RC5T583_IRQ(RTC_INT, 2, 0, 0, 3),
1121b1247ddSLaxman Dewangan [RC5T583_IRQ_YALE] = RC5T583_IRQ(RTC_INT, 2, 5, 5, 3),
1131b1247ddSLaxman Dewangan [RC5T583_IRQ_DALE] = RC5T583_IRQ(RTC_INT, 2, 6, 6, 3),
1141b1247ddSLaxman Dewangan [RC5T583_IRQ_WALE] = RC5T583_IRQ(RTC_INT, 2, 7, 7, 3),
1151b1247ddSLaxman Dewangan
1161b1247ddSLaxman Dewangan [RC5T583_IRQ_AIN1L] = RC5T583_IRQ(ADC_INT, 3, 0, 0, 4),
1171b1247ddSLaxman Dewangan [RC5T583_IRQ_AIN2L] = RC5T583_IRQ(ADC_INT, 3, 1, 1, 4),
1181b1247ddSLaxman Dewangan [RC5T583_IRQ_AIN3L] = RC5T583_IRQ(ADC_INT, 3, 2, 2, 4),
1191b1247ddSLaxman Dewangan [RC5T583_IRQ_VBATL] = RC5T583_IRQ(ADC_INT, 3, 3, 3, 4),
1201b1247ddSLaxman Dewangan [RC5T583_IRQ_VIN3L] = RC5T583_IRQ(ADC_INT, 3, 4, 4, 4),
1211b1247ddSLaxman Dewangan [RC5T583_IRQ_VIN8L] = RC5T583_IRQ(ADC_INT, 3, 5, 5, 4),
1221b1247ddSLaxman Dewangan [RC5T583_IRQ_AIN1H] = RC5T583_IRQ(ADC_INT, 3, 6, 0, 5),
1231b1247ddSLaxman Dewangan [RC5T583_IRQ_AIN2H] = RC5T583_IRQ(ADC_INT, 3, 7, 1, 5),
1241b1247ddSLaxman Dewangan [RC5T583_IRQ_AIN3H] = RC5T583_IRQ(ADC_INT, 3, 8, 2, 5),
1251b1247ddSLaxman Dewangan [RC5T583_IRQ_VBATH] = RC5T583_IRQ(ADC_INT, 3, 9, 3, 5),
1261b1247ddSLaxman Dewangan [RC5T583_IRQ_VIN3H] = RC5T583_IRQ(ADC_INT, 3, 10, 4, 5),
1271b1247ddSLaxman Dewangan [RC5T583_IRQ_VIN8H] = RC5T583_IRQ(ADC_INT, 3, 11, 5, 5),
1281b1247ddSLaxman Dewangan [RC5T583_IRQ_ADCEND] = RC5T583_IRQ(ADC_INT, 3, 12, 0, 6),
1291b1247ddSLaxman Dewangan
1301b1247ddSLaxman Dewangan [RC5T583_IRQ_GPIO0] = RC5T583_IRQ(GPIO_INT, 4, 0, 0, 7),
1311b1247ddSLaxman Dewangan [RC5T583_IRQ_GPIO1] = RC5T583_IRQ(GPIO_INT, 4, 1, 1, 7),
1321b1247ddSLaxman Dewangan [RC5T583_IRQ_GPIO2] = RC5T583_IRQ(GPIO_INT, 4, 2, 2, 7),
1331b1247ddSLaxman Dewangan [RC5T583_IRQ_GPIO3] = RC5T583_IRQ(GPIO_INT, 4, 3, 3, 7),
1341b1247ddSLaxman Dewangan [RC5T583_IRQ_GPIO4] = RC5T583_IRQ(GPIO_INT, 4, 4, 4, 7),
1351b1247ddSLaxman Dewangan [RC5T583_IRQ_GPIO5] = RC5T583_IRQ(GPIO_INT, 4, 5, 5, 7),
1361b1247ddSLaxman Dewangan [RC5T583_IRQ_GPIO6] = RC5T583_IRQ(GPIO_INT, 4, 6, 6, 7),
1371b1247ddSLaxman Dewangan [RC5T583_IRQ_GPIO7] = RC5T583_IRQ(GPIO_INT, 4, 7, 7, 7),
1381b1247ddSLaxman Dewangan };
1391b1247ddSLaxman Dewangan
rc5t583_irq_lock(struct irq_data * irq_data)1401b1247ddSLaxman Dewangan static void rc5t583_irq_lock(struct irq_data *irq_data)
1411b1247ddSLaxman Dewangan {
1421b1247ddSLaxman Dewangan struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
1431b1247ddSLaxman Dewangan mutex_lock(&rc5t583->irq_lock);
1441b1247ddSLaxman Dewangan }
1451b1247ddSLaxman Dewangan
rc5t583_irq_unmask(struct irq_data * irq_data)1461b1247ddSLaxman Dewangan static void rc5t583_irq_unmask(struct irq_data *irq_data)
1471b1247ddSLaxman Dewangan {
1481b1247ddSLaxman Dewangan struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
1491b1247ddSLaxman Dewangan unsigned int __irq = irq_data->irq - rc5t583->irq_base;
1501b1247ddSLaxman Dewangan const struct rc5t583_irq_data *data = &rc5t583_irqs[__irq];
1511b1247ddSLaxman Dewangan
1521b1247ddSLaxman Dewangan rc5t583->group_irq_en[data->grp_index] |= 1 << data->grp_index;
1531b1247ddSLaxman Dewangan rc5t583->intc_inten_reg |= 1 << data->master_bit;
1541b1247ddSLaxman Dewangan rc5t583->irq_en_reg[data->mask_reg_index] |= 1 << data->int_en_bit;
1551b1247ddSLaxman Dewangan }
1561b1247ddSLaxman Dewangan
rc5t583_irq_mask(struct irq_data * irq_data)1571b1247ddSLaxman Dewangan static void rc5t583_irq_mask(struct irq_data *irq_data)
1581b1247ddSLaxman Dewangan {
1591b1247ddSLaxman Dewangan struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
1601b1247ddSLaxman Dewangan unsigned int __irq = irq_data->irq - rc5t583->irq_base;
1611b1247ddSLaxman Dewangan const struct rc5t583_irq_data *data = &rc5t583_irqs[__irq];
1621b1247ddSLaxman Dewangan
1631b1247ddSLaxman Dewangan rc5t583->group_irq_en[data->grp_index] &= ~(1 << data->grp_index);
1641b1247ddSLaxman Dewangan if (!rc5t583->group_irq_en[data->grp_index])
1651b1247ddSLaxman Dewangan rc5t583->intc_inten_reg &= ~(1 << data->master_bit);
1661b1247ddSLaxman Dewangan
1671b1247ddSLaxman Dewangan rc5t583->irq_en_reg[data->mask_reg_index] &= ~(1 << data->int_en_bit);
1681b1247ddSLaxman Dewangan }
1691b1247ddSLaxman Dewangan
rc5t583_irq_set_type(struct irq_data * irq_data,unsigned int type)1701b1247ddSLaxman Dewangan static int rc5t583_irq_set_type(struct irq_data *irq_data, unsigned int type)
1711b1247ddSLaxman Dewangan {
1721b1247ddSLaxman Dewangan struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
1731b1247ddSLaxman Dewangan unsigned int __irq = irq_data->irq - rc5t583->irq_base;
1741b1247ddSLaxman Dewangan const struct rc5t583_irq_data *data = &rc5t583_irqs[__irq];
1751b1247ddSLaxman Dewangan int val = 0;
1761b1247ddSLaxman Dewangan int gpedge_index;
1771b1247ddSLaxman Dewangan int gpedge_bit_pos;
1781b1247ddSLaxman Dewangan
1791b1247ddSLaxman Dewangan /* Supporting only trigger level inetrrupt */
1801b1247ddSLaxman Dewangan if ((data->int_type & GPIO_INT) && (type & IRQ_TYPE_EDGE_BOTH)) {
1811b1247ddSLaxman Dewangan gpedge_index = data->int_en_bit / 4;
1821b1247ddSLaxman Dewangan gpedge_bit_pos = data->int_en_bit % 4;
1831b1247ddSLaxman Dewangan
1841b1247ddSLaxman Dewangan if (type & IRQ_TYPE_EDGE_FALLING)
1851b1247ddSLaxman Dewangan val |= 0x2;
1861b1247ddSLaxman Dewangan
1871b1247ddSLaxman Dewangan if (type & IRQ_TYPE_EDGE_RISING)
1881b1247ddSLaxman Dewangan val |= 0x1;
1891b1247ddSLaxman Dewangan
1901b1247ddSLaxman Dewangan rc5t583->gpedge_reg[gpedge_index] &= ~(3 << gpedge_bit_pos);
1911b1247ddSLaxman Dewangan rc5t583->gpedge_reg[gpedge_index] |= (val << gpedge_bit_pos);
1921b1247ddSLaxman Dewangan rc5t583_irq_unmask(irq_data);
1931b1247ddSLaxman Dewangan return 0;
1941b1247ddSLaxman Dewangan }
1951b1247ddSLaxman Dewangan return -EINVAL;
1961b1247ddSLaxman Dewangan }
1971b1247ddSLaxman Dewangan
rc5t583_irq_sync_unlock(struct irq_data * irq_data)1981b1247ddSLaxman Dewangan static void rc5t583_irq_sync_unlock(struct irq_data *irq_data)
1991b1247ddSLaxman Dewangan {
2001b1247ddSLaxman Dewangan struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
2011b1247ddSLaxman Dewangan int i;
2021b1247ddSLaxman Dewangan int ret;
2031b1247ddSLaxman Dewangan
2041b1247ddSLaxman Dewangan for (i = 0; i < ARRAY_SIZE(rc5t583->gpedge_reg); i++) {
2051b1247ddSLaxman Dewangan ret = rc5t583_write(rc5t583->dev, gpedge_add[i],
2061b1247ddSLaxman Dewangan rc5t583->gpedge_reg[i]);
2071b1247ddSLaxman Dewangan if (ret < 0)
2081b1247ddSLaxman Dewangan dev_warn(rc5t583->dev,
2091b1247ddSLaxman Dewangan "Error in writing reg 0x%02x error: %d\n",
2101b1247ddSLaxman Dewangan gpedge_add[i], ret);
2111b1247ddSLaxman Dewangan }
2121b1247ddSLaxman Dewangan
2131b1247ddSLaxman Dewangan for (i = 0; i < ARRAY_SIZE(rc5t583->irq_en_reg); i++) {
2141b1247ddSLaxman Dewangan ret = rc5t583_write(rc5t583->dev, irq_en_add[i],
2151b1247ddSLaxman Dewangan rc5t583->irq_en_reg[i]);
2161b1247ddSLaxman Dewangan if (ret < 0)
2171b1247ddSLaxman Dewangan dev_warn(rc5t583->dev,
2181b1247ddSLaxman Dewangan "Error in writing reg 0x%02x error: %d\n",
2191b1247ddSLaxman Dewangan irq_en_add[i], ret);
2201b1247ddSLaxman Dewangan }
2211b1247ddSLaxman Dewangan
2221b1247ddSLaxman Dewangan ret = rc5t583_write(rc5t583->dev, RC5T583_INTC_INTEN,
2231b1247ddSLaxman Dewangan rc5t583->intc_inten_reg);
2241b1247ddSLaxman Dewangan if (ret < 0)
2251b1247ddSLaxman Dewangan dev_warn(rc5t583->dev,
2261b1247ddSLaxman Dewangan "Error in writing reg 0x%02x error: %d\n",
2271b1247ddSLaxman Dewangan RC5T583_INTC_INTEN, ret);
2281b1247ddSLaxman Dewangan
2291b1247ddSLaxman Dewangan mutex_unlock(&rc5t583->irq_lock);
2301b1247ddSLaxman Dewangan }
2312662b90fSPaul Cercueil
rc5t583_irq_set_wake(struct irq_data * irq_data,unsigned int on)2321b1247ddSLaxman Dewangan static int rc5t583_irq_set_wake(struct irq_data *irq_data, unsigned int on)
2331b1247ddSLaxman Dewangan {
2341b1247ddSLaxman Dewangan struct rc5t583 *rc5t583 = irq_data_get_irq_chip_data(irq_data);
2351b1247ddSLaxman Dewangan return irq_set_irq_wake(rc5t583->chip_irq, on);
2361b1247ddSLaxman Dewangan }
2371b1247ddSLaxman Dewangan
rc5t583_irq(int irq,void * data)2381b1247ddSLaxman Dewangan static irqreturn_t rc5t583_irq(int irq, void *data)
2391b1247ddSLaxman Dewangan {
2401b1247ddSLaxman Dewangan struct rc5t583 *rc5t583 = data;
2411b1247ddSLaxman Dewangan uint8_t int_sts[RC5T583_MAX_INTERRUPT_MASK_REGS];
2420dd96360SVenu Byravarasu uint8_t master_int = 0;
2431b1247ddSLaxman Dewangan int i;
2441b1247ddSLaxman Dewangan int ret;
2451b1247ddSLaxman Dewangan unsigned int rtc_int_sts = 0;
2461b1247ddSLaxman Dewangan
2471b1247ddSLaxman Dewangan /* Clear the status */
2481b1247ddSLaxman Dewangan for (i = 0; i < RC5T583_MAX_INTERRUPT_MASK_REGS; i++)
2491b1247ddSLaxman Dewangan int_sts[i] = 0;
2501b1247ddSLaxman Dewangan
2511b1247ddSLaxman Dewangan ret = rc5t583_read(rc5t583->dev, RC5T583_INTC_INTMON, &master_int);
2521b1247ddSLaxman Dewangan if (ret < 0) {
2531b1247ddSLaxman Dewangan dev_err(rc5t583->dev,
2541b1247ddSLaxman Dewangan "Error in reading reg 0x%02x error: %d\n",
2551b1247ddSLaxman Dewangan RC5T583_INTC_INTMON, ret);
2561b1247ddSLaxman Dewangan return IRQ_HANDLED;
2571b1247ddSLaxman Dewangan }
2581b1247ddSLaxman Dewangan
2591b1247ddSLaxman Dewangan for (i = 0; i < RC5T583_MAX_INTERRUPT_MASK_REGS; ++i) {
2601b1247ddSLaxman Dewangan if (!(master_int & main_int_type[i]))
2611b1247ddSLaxman Dewangan continue;
2621b1247ddSLaxman Dewangan
2631b1247ddSLaxman Dewangan ret = rc5t583_read(rc5t583->dev, irq_mon_add[i], &int_sts[i]);
2641b1247ddSLaxman Dewangan if (ret < 0) {
2651b1247ddSLaxman Dewangan dev_warn(rc5t583->dev,
2661b1247ddSLaxman Dewangan "Error in reading reg 0x%02x error: %d\n",
2671b1247ddSLaxman Dewangan irq_mon_add[i], ret);
2681b1247ddSLaxman Dewangan int_sts[i] = 0;
2691b1247ddSLaxman Dewangan continue;
2701b1247ddSLaxman Dewangan }
2711b1247ddSLaxman Dewangan
2721b1247ddSLaxman Dewangan if (main_int_type[i] & RTC_INT) {
2731b1247ddSLaxman Dewangan rtc_int_sts = 0;
2741b1247ddSLaxman Dewangan if (int_sts[i] & 0x1)
2751b1247ddSLaxman Dewangan rtc_int_sts |= BIT(6);
2761b1247ddSLaxman Dewangan if (int_sts[i] & 0x2)
2771b1247ddSLaxman Dewangan rtc_int_sts |= BIT(7);
2781b1247ddSLaxman Dewangan if (int_sts[i] & 0x4)
2791b1247ddSLaxman Dewangan rtc_int_sts |= BIT(0);
2801b1247ddSLaxman Dewangan if (int_sts[i] & 0x8)
2811b1247ddSLaxman Dewangan rtc_int_sts |= BIT(5);
2821b1247ddSLaxman Dewangan }
2831b1247ddSLaxman Dewangan
2841b1247ddSLaxman Dewangan ret = rc5t583_write(rc5t583->dev, irq_clr_add[i],
2851b1247ddSLaxman Dewangan ~int_sts[i]);
2861b1247ddSLaxman Dewangan if (ret < 0)
2871b1247ddSLaxman Dewangan dev_warn(rc5t583->dev,
2881b1247ddSLaxman Dewangan "Error in reading reg 0x%02x error: %d\n",
2891b1247ddSLaxman Dewangan irq_clr_add[i], ret);
2901b1247ddSLaxman Dewangan
2911b1247ddSLaxman Dewangan if (main_int_type[i] & RTC_INT)
2921b1247ddSLaxman Dewangan int_sts[i] = rtc_int_sts;
2931b1247ddSLaxman Dewangan }
2941b1247ddSLaxman Dewangan
2951b1247ddSLaxman Dewangan /* Merge gpio interrupts for rising and falling case*/
2961b1247ddSLaxman Dewangan int_sts[7] |= int_sts[8];
2971b1247ddSLaxman Dewangan
2981b1247ddSLaxman Dewangan /* Call interrupt handler if enabled */
2991b1247ddSLaxman Dewangan for (i = 0; i < RC5T583_MAX_IRQS; ++i) {
3001b1247ddSLaxman Dewangan const struct rc5t583_irq_data *data = &rc5t583_irqs[i];
3011b1247ddSLaxman Dewangan if ((int_sts[data->mask_reg_index] & (1 << data->int_en_bit)) &&
3021b1247ddSLaxman Dewangan (rc5t583->group_irq_en[data->master_bit] &
3031b1247ddSLaxman Dewangan (1 << data->grp_index)))
3041b1247ddSLaxman Dewangan handle_nested_irq(rc5t583->irq_base + i);
3051b1247ddSLaxman Dewangan }
3061b1247ddSLaxman Dewangan
3071b1247ddSLaxman Dewangan return IRQ_HANDLED;
3081b1247ddSLaxman Dewangan }
3091b1247ddSLaxman Dewangan
3101b1247ddSLaxman Dewangan static struct irq_chip rc5t583_irq_chip = {
3111b1247ddSLaxman Dewangan .name = "rc5t583-irq",
3121b1247ddSLaxman Dewangan .irq_mask = rc5t583_irq_mask,
3131b1247ddSLaxman Dewangan .irq_unmask = rc5t583_irq_unmask,
3141b1247ddSLaxman Dewangan .irq_bus_lock = rc5t583_irq_lock,
3151b1247ddSLaxman Dewangan .irq_bus_sync_unlock = rc5t583_irq_sync_unlock,
3161b1247ddSLaxman Dewangan .irq_set_type = rc5t583_irq_set_type,
3172662b90fSPaul Cercueil .irq_set_wake = pm_sleep_ptr(rc5t583_irq_set_wake),
3181b1247ddSLaxman Dewangan };
3191b1247ddSLaxman Dewangan
rc5t583_irq_init(struct rc5t583 * rc5t583,int irq,int irq_base)3201b1247ddSLaxman Dewangan int rc5t583_irq_init(struct rc5t583 *rc5t583, int irq, int irq_base)
3211b1247ddSLaxman Dewangan {
3221b1247ddSLaxman Dewangan int i, ret;
3231b1247ddSLaxman Dewangan
3241b1247ddSLaxman Dewangan if (!irq_base) {
3251b1247ddSLaxman Dewangan dev_warn(rc5t583->dev, "No interrupt support on IRQ base\n");
3261b1247ddSLaxman Dewangan return -EINVAL;
3271b1247ddSLaxman Dewangan }
3281b1247ddSLaxman Dewangan
3291b1247ddSLaxman Dewangan mutex_init(&rc5t583->irq_lock);
3301b1247ddSLaxman Dewangan
3311b1247ddSLaxman Dewangan /* Initailize all int register to 0 */
3323f9be35bSAxel Lin for (i = 0; i < RC5T583_MAX_INTERRUPT_EN_REGS; i++) {
3331b1247ddSLaxman Dewangan ret = rc5t583_write(rc5t583->dev, irq_en_add[i],
3341b1247ddSLaxman Dewangan rc5t583->irq_en_reg[i]);
3351b1247ddSLaxman Dewangan if (ret < 0)
3361b1247ddSLaxman Dewangan dev_warn(rc5t583->dev,
3371b1247ddSLaxman Dewangan "Error in writing reg 0x%02x error: %d\n",
3381b1247ddSLaxman Dewangan irq_en_add[i], ret);
3391b1247ddSLaxman Dewangan }
3401b1247ddSLaxman Dewangan
3411b1247ddSLaxman Dewangan for (i = 0; i < RC5T583_MAX_GPEDGE_REG; i++) {
3421b1247ddSLaxman Dewangan ret = rc5t583_write(rc5t583->dev, gpedge_add[i],
3431b1247ddSLaxman Dewangan rc5t583->gpedge_reg[i]);
3441b1247ddSLaxman Dewangan if (ret < 0)
3451b1247ddSLaxman Dewangan dev_warn(rc5t583->dev,
3461b1247ddSLaxman Dewangan "Error in writing reg 0x%02x error: %d\n",
3471b1247ddSLaxman Dewangan gpedge_add[i], ret);
3481b1247ddSLaxman Dewangan }
3491b1247ddSLaxman Dewangan
3501b1247ddSLaxman Dewangan ret = rc5t583_write(rc5t583->dev, RC5T583_INTC_INTEN, 0x0);
3511b1247ddSLaxman Dewangan if (ret < 0)
3521b1247ddSLaxman Dewangan dev_warn(rc5t583->dev,
3531b1247ddSLaxman Dewangan "Error in writing reg 0x%02x error: %d\n",
3541b1247ddSLaxman Dewangan RC5T583_INTC_INTEN, ret);
3551b1247ddSLaxman Dewangan
3561b1247ddSLaxman Dewangan /* Clear all interrupts in case they woke up active. */
3571b1247ddSLaxman Dewangan for (i = 0; i < RC5T583_MAX_INTERRUPT_MASK_REGS; i++) {
3581b1247ddSLaxman Dewangan ret = rc5t583_write(rc5t583->dev, irq_clr_add[i], 0);
3591b1247ddSLaxman Dewangan if (ret < 0)
3601b1247ddSLaxman Dewangan dev_warn(rc5t583->dev,
3611b1247ddSLaxman Dewangan "Error in writing reg 0x%02x error: %d\n",
3621b1247ddSLaxman Dewangan irq_clr_add[i], ret);
3631b1247ddSLaxman Dewangan }
3641b1247ddSLaxman Dewangan
3651b1247ddSLaxman Dewangan rc5t583->irq_base = irq_base;
3661b1247ddSLaxman Dewangan rc5t583->chip_irq = irq;
3671b1247ddSLaxman Dewangan
3681b1247ddSLaxman Dewangan for (i = 0; i < RC5T583_MAX_IRQS; i++) {
3691b1247ddSLaxman Dewangan int __irq = i + rc5t583->irq_base;
3701b1247ddSLaxman Dewangan irq_set_chip_data(__irq, rc5t583);
3711b1247ddSLaxman Dewangan irq_set_chip_and_handler(__irq, &rc5t583_irq_chip,
3721b1247ddSLaxman Dewangan handle_simple_irq);
3731b1247ddSLaxman Dewangan irq_set_nested_thread(__irq, 1);
3749bd09f34SRob Herring irq_clear_status_flags(__irq, IRQ_NOREQUEST);
3751b1247ddSLaxman Dewangan }
3761b1247ddSLaxman Dewangan
377b36c8272SLaxman Dewangan ret = devm_request_threaded_irq(rc5t583->dev, irq, NULL, rc5t583_irq,
378b36c8272SLaxman Dewangan IRQF_ONESHOT, "rc5t583", rc5t583);
3791b1247ddSLaxman Dewangan if (ret < 0)
3801b1247ddSLaxman Dewangan dev_err(rc5t583->dev,
3811b1247ddSLaxman Dewangan "Error in registering interrupt error: %d\n", ret);
3821b1247ddSLaxman Dewangan return ret;
3831b1247ddSLaxman Dewangan }
384