1 /** 2 * omap-usb-host.c - The USBHS core driver for OMAP EHCI & OHCI 3 * 4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com 5 * Author: Keshava Munegowda <keshava_mgowda@ti.com> 6 * 7 * This program is free software: you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 of 9 * the License as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include <linux/kernel.h> 20 #include <linux/types.h> 21 #include <linux/slab.h> 22 #include <linux/delay.h> 23 #include <linux/platform_device.h> 24 #include <linux/clk.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/spinlock.h> 27 #include <linux/gpio.h> 28 #include <plat/usb.h> 29 30 #define USBHS_DRIVER_NAME "usbhs-omap" 31 #define OMAP_EHCI_DEVICE "ehci-omap" 32 #define OMAP_OHCI_DEVICE "ohci-omap3" 33 34 /* OMAP USBHOST Register addresses */ 35 36 /* TLL Register Set */ 37 #define OMAP_USBTLL_REVISION (0x00) 38 #define OMAP_USBTLL_SYSCONFIG (0x10) 39 #define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8) 40 #define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3) 41 #define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2) 42 #define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1) 43 #define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0) 44 45 #define OMAP_USBTLL_SYSSTATUS (0x14) 46 #define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0) 47 48 #define OMAP_USBTLL_IRQSTATUS (0x18) 49 #define OMAP_USBTLL_IRQENABLE (0x1C) 50 51 #define OMAP_TLL_SHARED_CONF (0x30) 52 #define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6) 53 #define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5) 54 #define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2) 55 #define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1) 56 #define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0) 57 58 #define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num) 59 #define OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT 24 60 #define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11) 61 #define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10) 62 #define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9) 63 #define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8) 64 #define OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS (1 << 1) 65 #define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0) 66 67 #define OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0 0x0 68 #define OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM 0x1 69 #define OMAP_TLL_FSLSMODE_3PIN_PHY 0x2 70 #define OMAP_TLL_FSLSMODE_4PIN_PHY 0x3 71 #define OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0 0x4 72 #define OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM 0x5 73 #define OMAP_TLL_FSLSMODE_3PIN_TLL 0x6 74 #define OMAP_TLL_FSLSMODE_4PIN_TLL 0x7 75 #define OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0 0xA 76 #define OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM 0xB 77 78 #define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num) 79 #define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num) 80 #define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num) 81 #define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num) 82 #define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num) 83 #define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num) 84 #define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num) 85 #define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num) 86 #define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num) 87 88 #define OMAP_TLL_CHANNEL_COUNT 3 89 #define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 0) 90 #define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 1) 91 #define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 2) 92 93 /* UHH Register Set */ 94 #define OMAP_UHH_REVISION (0x00) 95 #define OMAP_UHH_SYSCONFIG (0x10) 96 #define OMAP_UHH_SYSCONFIG_MIDLEMODE (1 << 12) 97 #define OMAP_UHH_SYSCONFIG_CACTIVITY (1 << 8) 98 #define OMAP_UHH_SYSCONFIG_SIDLEMODE (1 << 3) 99 #define OMAP_UHH_SYSCONFIG_ENAWAKEUP (1 << 2) 100 #define OMAP_UHH_SYSCONFIG_SOFTRESET (1 << 1) 101 #define OMAP_UHH_SYSCONFIG_AUTOIDLE (1 << 0) 102 103 #define OMAP_UHH_SYSSTATUS (0x14) 104 #define OMAP_UHH_HOSTCONFIG (0x40) 105 #define OMAP_UHH_HOSTCONFIG_ULPI_BYPASS (1 << 0) 106 #define OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS (1 << 0) 107 #define OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS (1 << 11) 108 #define OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS (1 << 12) 109 #define OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN (1 << 2) 110 #define OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN (1 << 3) 111 #define OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN (1 << 4) 112 #define OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN (1 << 5) 113 #define OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS (1 << 8) 114 #define OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS (1 << 9) 115 #define OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS (1 << 10) 116 #define OMAP4_UHH_HOSTCONFIG_APP_START_CLK (1 << 31) 117 118 /* OMAP4-specific defines */ 119 #define OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR (3 << 2) 120 #define OMAP4_UHH_SYSCONFIG_NOIDLE (1 << 2) 121 #define OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR (3 << 4) 122 #define OMAP4_UHH_SYSCONFIG_NOSTDBY (1 << 4) 123 #define OMAP4_UHH_SYSCONFIG_SOFTRESET (1 << 0) 124 125 #define OMAP4_P1_MODE_CLEAR (3 << 16) 126 #define OMAP4_P1_MODE_TLL (1 << 16) 127 #define OMAP4_P1_MODE_HSIC (3 << 16) 128 #define OMAP4_P2_MODE_CLEAR (3 << 18) 129 #define OMAP4_P2_MODE_TLL (1 << 18) 130 #define OMAP4_P2_MODE_HSIC (3 << 18) 131 132 #define OMAP_REV2_TLL_CHANNEL_COUNT 2 133 134 #define OMAP_UHH_DEBUG_CSR (0x44) 135 136 /* Values of UHH_REVISION - Note: these are not given in the TRM */ 137 #define OMAP_USBHS_REV1 0x00000010 /* OMAP3 */ 138 #define OMAP_USBHS_REV2 0x50700100 /* OMAP4 */ 139 140 #define is_omap_usbhs_rev1(x) (x->usbhs_rev == OMAP_USBHS_REV1) 141 #define is_omap_usbhs_rev2(x) (x->usbhs_rev == OMAP_USBHS_REV2) 142 143 #define is_ehci_phy_mode(x) (x == OMAP_EHCI_PORT_MODE_PHY) 144 #define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL) 145 #define is_ehci_hsic_mode(x) (x == OMAP_EHCI_PORT_MODE_HSIC) 146 147 148 struct usbhs_hcd_omap { 149 struct clk *usbhost_ick; 150 struct clk *usbhost_hs_fck; 151 struct clk *usbhost_fs_fck; 152 struct clk *xclk60mhsp1_ck; 153 struct clk *xclk60mhsp2_ck; 154 struct clk *utmi_p1_fck; 155 struct clk *usbhost_p1_fck; 156 struct clk *usbtll_p1_fck; 157 struct clk *utmi_p2_fck; 158 struct clk *usbhost_p2_fck; 159 struct clk *usbtll_p2_fck; 160 struct clk *init_60m_fclk; 161 struct clk *usbtll_fck; 162 struct clk *usbtll_ick; 163 164 void __iomem *uhh_base; 165 void __iomem *tll_base; 166 167 struct usbhs_omap_platform_data platdata; 168 169 u32 usbhs_rev; 170 spinlock_t lock; 171 int count; 172 }; 173 /*-------------------------------------------------------------------------*/ 174 175 const char usbhs_driver_name[] = USBHS_DRIVER_NAME; 176 static u64 usbhs_dmamask = ~(u32)0; 177 178 /*-------------------------------------------------------------------------*/ 179 180 static inline void usbhs_write(void __iomem *base, u32 reg, u32 val) 181 { 182 __raw_writel(val, base + reg); 183 } 184 185 static inline u32 usbhs_read(void __iomem *base, u32 reg) 186 { 187 return __raw_readl(base + reg); 188 } 189 190 static inline void usbhs_writeb(void __iomem *base, u8 reg, u8 val) 191 { 192 __raw_writeb(val, base + reg); 193 } 194 195 static inline u8 usbhs_readb(void __iomem *base, u8 reg) 196 { 197 return __raw_readb(base + reg); 198 } 199 200 /*-------------------------------------------------------------------------*/ 201 202 static struct platform_device *omap_usbhs_alloc_child(const char *name, 203 struct resource *res, int num_resources, void *pdata, 204 size_t pdata_size, struct device *dev) 205 { 206 struct platform_device *child; 207 int ret; 208 209 child = platform_device_alloc(name, 0); 210 211 if (!child) { 212 dev_err(dev, "platform_device_alloc %s failed\n", name); 213 goto err_end; 214 } 215 216 ret = platform_device_add_resources(child, res, num_resources); 217 if (ret) { 218 dev_err(dev, "platform_device_add_resources failed\n"); 219 goto err_alloc; 220 } 221 222 ret = platform_device_add_data(child, pdata, pdata_size); 223 if (ret) { 224 dev_err(dev, "platform_device_add_data failed\n"); 225 goto err_alloc; 226 } 227 228 child->dev.dma_mask = &usbhs_dmamask; 229 child->dev.coherent_dma_mask = 0xffffffff; 230 child->dev.parent = dev; 231 232 ret = platform_device_add(child); 233 if (ret) { 234 dev_err(dev, "platform_device_add failed\n"); 235 goto err_alloc; 236 } 237 238 return child; 239 240 err_alloc: 241 platform_device_put(child); 242 243 err_end: 244 return NULL; 245 } 246 247 static int omap_usbhs_alloc_children(struct platform_device *pdev) 248 { 249 struct device *dev = &pdev->dev; 250 struct usbhs_hcd_omap *omap; 251 struct ehci_hcd_omap_platform_data *ehci_data; 252 struct ohci_hcd_omap_platform_data *ohci_data; 253 struct platform_device *ehci; 254 struct platform_device *ohci; 255 struct resource *res; 256 struct resource resources[2]; 257 int ret; 258 259 omap = platform_get_drvdata(pdev); 260 ehci_data = omap->platdata.ehci_data; 261 ohci_data = omap->platdata.ohci_data; 262 263 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ehci"); 264 if (!res) { 265 dev_err(dev, "EHCI get resource IORESOURCE_MEM failed\n"); 266 ret = -ENODEV; 267 goto err_end; 268 } 269 resources[0] = *res; 270 271 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ehci-irq"); 272 if (!res) { 273 dev_err(dev, " EHCI get resource IORESOURCE_IRQ failed\n"); 274 ret = -ENODEV; 275 goto err_end; 276 } 277 resources[1] = *res; 278 279 ehci = omap_usbhs_alloc_child(OMAP_EHCI_DEVICE, resources, 2, ehci_data, 280 sizeof(*ehci_data), dev); 281 282 if (!ehci) { 283 dev_err(dev, "omap_usbhs_alloc_child failed\n"); 284 goto err_end; 285 } 286 287 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ohci"); 288 if (!res) { 289 dev_err(dev, "OHCI get resource IORESOURCE_MEM failed\n"); 290 ret = -ENODEV; 291 goto err_ehci; 292 } 293 resources[0] = *res; 294 295 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "ohci-irq"); 296 if (!res) { 297 dev_err(dev, "OHCI get resource IORESOURCE_IRQ failed\n"); 298 ret = -ENODEV; 299 goto err_ehci; 300 } 301 resources[1] = *res; 302 303 ohci = omap_usbhs_alloc_child(OMAP_OHCI_DEVICE, resources, 2, ohci_data, 304 sizeof(*ohci_data), dev); 305 if (!ohci) { 306 dev_err(dev, "omap_usbhs_alloc_child failed\n"); 307 goto err_ehci; 308 } 309 310 return 0; 311 312 err_ehci: 313 platform_device_put(ehci); 314 315 err_end: 316 return ret; 317 } 318 319 /** 320 * usbhs_omap_probe - initialize TI-based HCDs 321 * 322 * Allocates basic resources for this USB host controller. 323 */ 324 static int __devinit usbhs_omap_probe(struct platform_device *pdev) 325 { 326 struct device *dev = &pdev->dev; 327 struct usbhs_omap_platform_data *pdata = dev->platform_data; 328 struct usbhs_hcd_omap *omap; 329 struct resource *res; 330 int ret = 0; 331 int i; 332 333 if (!pdata) { 334 dev_err(dev, "Missing platform data\n"); 335 ret = -ENOMEM; 336 goto end_probe; 337 } 338 339 omap = kzalloc(sizeof(*omap), GFP_KERNEL); 340 if (!omap) { 341 dev_err(dev, "Memory allocation failed\n"); 342 ret = -ENOMEM; 343 goto end_probe; 344 } 345 346 spin_lock_init(&omap->lock); 347 348 for (i = 0; i < OMAP3_HS_USB_PORTS; i++) 349 omap->platdata.port_mode[i] = pdata->port_mode[i]; 350 351 omap->platdata.ehci_data = pdata->ehci_data; 352 omap->platdata.ohci_data = pdata->ohci_data; 353 354 omap->usbhost_ick = clk_get(dev, "usbhost_ick"); 355 if (IS_ERR(omap->usbhost_ick)) { 356 ret = PTR_ERR(omap->usbhost_ick); 357 dev_err(dev, "usbhost_ick failed error:%d\n", ret); 358 goto err_end; 359 } 360 361 omap->usbhost_hs_fck = clk_get(dev, "hs_fck"); 362 if (IS_ERR(omap->usbhost_hs_fck)) { 363 ret = PTR_ERR(omap->usbhost_hs_fck); 364 dev_err(dev, "usbhost_hs_fck failed error:%d\n", ret); 365 goto err_usbhost_ick; 366 } 367 368 omap->usbhost_fs_fck = clk_get(dev, "fs_fck"); 369 if (IS_ERR(omap->usbhost_fs_fck)) { 370 ret = PTR_ERR(omap->usbhost_fs_fck); 371 dev_err(dev, "usbhost_fs_fck failed error:%d\n", ret); 372 goto err_usbhost_hs_fck; 373 } 374 375 omap->usbtll_fck = clk_get(dev, "usbtll_fck"); 376 if (IS_ERR(omap->usbtll_fck)) { 377 ret = PTR_ERR(omap->usbtll_fck); 378 dev_err(dev, "usbtll_fck failed error:%d\n", ret); 379 goto err_usbhost_fs_fck; 380 } 381 382 omap->usbtll_ick = clk_get(dev, "usbtll_ick"); 383 if (IS_ERR(omap->usbtll_ick)) { 384 ret = PTR_ERR(omap->usbtll_ick); 385 dev_err(dev, "usbtll_ick failed error:%d\n", ret); 386 goto err_usbtll_fck; 387 } 388 389 omap->utmi_p1_fck = clk_get(dev, "utmi_p1_gfclk"); 390 if (IS_ERR(omap->utmi_p1_fck)) { 391 ret = PTR_ERR(omap->utmi_p1_fck); 392 dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret); 393 goto err_usbtll_ick; 394 } 395 396 omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck"); 397 if (IS_ERR(omap->xclk60mhsp1_ck)) { 398 ret = PTR_ERR(omap->xclk60mhsp1_ck); 399 dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret); 400 goto err_utmi_p1_fck; 401 } 402 403 omap->utmi_p2_fck = clk_get(dev, "utmi_p2_gfclk"); 404 if (IS_ERR(omap->utmi_p2_fck)) { 405 ret = PTR_ERR(omap->utmi_p2_fck); 406 dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret); 407 goto err_xclk60mhsp1_ck; 408 } 409 410 omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck"); 411 if (IS_ERR(omap->xclk60mhsp2_ck)) { 412 ret = PTR_ERR(omap->xclk60mhsp2_ck); 413 dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret); 414 goto err_utmi_p2_fck; 415 } 416 417 omap->usbhost_p1_fck = clk_get(dev, "usb_host_hs_utmi_p1_clk"); 418 if (IS_ERR(omap->usbhost_p1_fck)) { 419 ret = PTR_ERR(omap->usbhost_p1_fck); 420 dev_err(dev, "usbhost_p1_fck failed error:%d\n", ret); 421 goto err_xclk60mhsp2_ck; 422 } 423 424 omap->usbtll_p1_fck = clk_get(dev, "usb_tll_hs_usb_ch0_clk"); 425 if (IS_ERR(omap->usbtll_p1_fck)) { 426 ret = PTR_ERR(omap->usbtll_p1_fck); 427 dev_err(dev, "usbtll_p1_fck failed error:%d\n", ret); 428 goto err_usbhost_p1_fck; 429 } 430 431 omap->usbhost_p2_fck = clk_get(dev, "usb_host_hs_utmi_p2_clk"); 432 if (IS_ERR(omap->usbhost_p2_fck)) { 433 ret = PTR_ERR(omap->usbhost_p2_fck); 434 dev_err(dev, "usbhost_p2_fck failed error:%d\n", ret); 435 goto err_usbtll_p1_fck; 436 } 437 438 omap->usbtll_p2_fck = clk_get(dev, "usb_tll_hs_usb_ch1_clk"); 439 if (IS_ERR(omap->usbtll_p2_fck)) { 440 ret = PTR_ERR(omap->usbtll_p2_fck); 441 dev_err(dev, "usbtll_p2_fck failed error:%d\n", ret); 442 goto err_usbhost_p2_fck; 443 } 444 445 omap->init_60m_fclk = clk_get(dev, "init_60m_fclk"); 446 if (IS_ERR(omap->init_60m_fclk)) { 447 ret = PTR_ERR(omap->init_60m_fclk); 448 dev_err(dev, "init_60m_fclk failed error:%d\n", ret); 449 goto err_usbtll_p2_fck; 450 } 451 452 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh"); 453 if (!res) { 454 dev_err(dev, "UHH EHCI get resource failed\n"); 455 ret = -ENODEV; 456 goto err_init_60m_fclk; 457 } 458 459 omap->uhh_base = ioremap(res->start, resource_size(res)); 460 if (!omap->uhh_base) { 461 dev_err(dev, "UHH ioremap failed\n"); 462 ret = -ENOMEM; 463 goto err_init_60m_fclk; 464 } 465 466 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tll"); 467 if (!res) { 468 dev_err(dev, "UHH EHCI get resource failed\n"); 469 ret = -ENODEV; 470 goto err_tll; 471 } 472 473 omap->tll_base = ioremap(res->start, resource_size(res)); 474 if (!omap->tll_base) { 475 dev_err(dev, "TLL ioremap failed\n"); 476 ret = -ENOMEM; 477 goto err_tll; 478 } 479 480 platform_set_drvdata(pdev, omap); 481 482 ret = omap_usbhs_alloc_children(pdev); 483 if (ret) { 484 dev_err(dev, "omap_usbhs_alloc_children failed\n"); 485 goto err_alloc; 486 } 487 488 goto end_probe; 489 490 err_alloc: 491 iounmap(omap->tll_base); 492 493 err_tll: 494 iounmap(omap->uhh_base); 495 496 err_init_60m_fclk: 497 clk_put(omap->init_60m_fclk); 498 499 err_usbtll_p2_fck: 500 clk_put(omap->usbtll_p2_fck); 501 502 err_usbhost_p2_fck: 503 clk_put(omap->usbhost_p2_fck); 504 505 err_usbtll_p1_fck: 506 clk_put(omap->usbtll_p1_fck); 507 508 err_usbhost_p1_fck: 509 clk_put(omap->usbhost_p1_fck); 510 511 err_xclk60mhsp2_ck: 512 clk_put(omap->xclk60mhsp2_ck); 513 514 err_utmi_p2_fck: 515 clk_put(omap->utmi_p2_fck); 516 517 err_xclk60mhsp1_ck: 518 clk_put(omap->xclk60mhsp1_ck); 519 520 err_utmi_p1_fck: 521 clk_put(omap->utmi_p1_fck); 522 523 err_usbtll_ick: 524 clk_put(omap->usbtll_ick); 525 526 err_usbtll_fck: 527 clk_put(omap->usbtll_fck); 528 529 err_usbhost_fs_fck: 530 clk_put(omap->usbhost_fs_fck); 531 532 err_usbhost_hs_fck: 533 clk_put(omap->usbhost_hs_fck); 534 535 err_usbhost_ick: 536 clk_put(omap->usbhost_ick); 537 538 err_end: 539 kfree(omap); 540 541 end_probe: 542 return ret; 543 } 544 545 /** 546 * usbhs_omap_remove - shutdown processing for UHH & TLL HCDs 547 * @pdev: USB Host Controller being removed 548 * 549 * Reverses the effect of usbhs_omap_probe(). 550 */ 551 static int __devexit usbhs_omap_remove(struct platform_device *pdev) 552 { 553 struct usbhs_hcd_omap *omap = platform_get_drvdata(pdev); 554 555 if (omap->count != 0) { 556 dev_err(&pdev->dev, 557 "Either EHCI or OHCI is still using usbhs core\n"); 558 return -EBUSY; 559 } 560 561 iounmap(omap->tll_base); 562 iounmap(omap->uhh_base); 563 clk_put(omap->init_60m_fclk); 564 clk_put(omap->usbtll_p2_fck); 565 clk_put(omap->usbhost_p2_fck); 566 clk_put(omap->usbtll_p1_fck); 567 clk_put(omap->usbhost_p1_fck); 568 clk_put(omap->xclk60mhsp2_ck); 569 clk_put(omap->utmi_p2_fck); 570 clk_put(omap->xclk60mhsp1_ck); 571 clk_put(omap->utmi_p1_fck); 572 clk_put(omap->usbtll_ick); 573 clk_put(omap->usbtll_fck); 574 clk_put(omap->usbhost_fs_fck); 575 clk_put(omap->usbhost_hs_fck); 576 clk_put(omap->usbhost_ick); 577 kfree(omap); 578 579 return 0; 580 } 581 582 static bool is_ohci_port(enum usbhs_omap_port_mode pmode) 583 { 584 switch (pmode) { 585 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: 586 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM: 587 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0: 588 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM: 589 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0: 590 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM: 591 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0: 592 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM: 593 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0: 594 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM: 595 return true; 596 597 default: 598 return false; 599 } 600 } 601 602 /* 603 * convert the port-mode enum to a value we can use in the FSLSMODE 604 * field of USBTLL_CHANNEL_CONF 605 */ 606 static unsigned ohci_omap3_fslsmode(enum usbhs_omap_port_mode mode) 607 { 608 switch (mode) { 609 case OMAP_USBHS_PORT_MODE_UNUSED: 610 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0: 611 return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0; 612 613 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM: 614 return OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM; 615 616 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0: 617 return OMAP_TLL_FSLSMODE_3PIN_PHY; 618 619 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM: 620 return OMAP_TLL_FSLSMODE_4PIN_PHY; 621 622 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0: 623 return OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0; 624 625 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM: 626 return OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM; 627 628 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0: 629 return OMAP_TLL_FSLSMODE_3PIN_TLL; 630 631 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM: 632 return OMAP_TLL_FSLSMODE_4PIN_TLL; 633 634 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0: 635 return OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0; 636 637 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM: 638 return OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM; 639 default: 640 pr_warning("Invalid port mode, using default\n"); 641 return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0; 642 } 643 } 644 645 static void usbhs_omap_tll_init(struct device *dev, u8 tll_channel_count) 646 { 647 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); 648 struct usbhs_omap_platform_data *pdata = dev->platform_data; 649 unsigned reg; 650 int i; 651 652 /* Program Common TLL register */ 653 reg = usbhs_read(omap->tll_base, OMAP_TLL_SHARED_CONF); 654 reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON 655 | OMAP_TLL_SHARED_CONF_USB_DIVRATION); 656 reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN; 657 reg &= ~OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN; 658 659 usbhs_write(omap->tll_base, OMAP_TLL_SHARED_CONF, reg); 660 661 /* Enable channels now */ 662 for (i = 0; i < tll_channel_count; i++) { 663 reg = usbhs_read(omap->tll_base, 664 OMAP_TLL_CHANNEL_CONF(i)); 665 666 if (is_ohci_port(pdata->port_mode[i])) { 667 reg |= ohci_omap3_fslsmode(pdata->port_mode[i]) 668 << OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT; 669 reg |= OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS; 670 } else if (pdata->port_mode[i] == OMAP_EHCI_PORT_MODE_TLL) { 671 672 /* Disable AutoIdle, BitStuffing and use SDR Mode */ 673 reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE 674 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF 675 | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE); 676 677 reg |= (1 << (i + 1)); 678 } else 679 continue; 680 681 reg |= OMAP_TLL_CHANNEL_CONF_CHANEN; 682 usbhs_write(omap->tll_base, 683 OMAP_TLL_CHANNEL_CONF(i), reg); 684 685 usbhs_writeb(omap->tll_base, 686 OMAP_TLL_ULPI_SCRATCH_REGISTER(i), 0xbe); 687 } 688 } 689 690 static int usbhs_enable(struct device *dev) 691 { 692 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); 693 struct usbhs_omap_platform_data *pdata = &omap->platdata; 694 unsigned long flags = 0; 695 int ret = 0; 696 unsigned long timeout; 697 unsigned reg; 698 699 dev_dbg(dev, "starting TI HSUSB Controller\n"); 700 if (!pdata) { 701 dev_dbg(dev, "missing platform_data\n"); 702 return -ENODEV; 703 } 704 705 spin_lock_irqsave(&omap->lock, flags); 706 if (omap->count > 0) 707 goto end_count; 708 709 clk_enable(omap->usbhost_ick); 710 clk_enable(omap->usbhost_hs_fck); 711 clk_enable(omap->usbhost_fs_fck); 712 clk_enable(omap->usbtll_fck); 713 clk_enable(omap->usbtll_ick); 714 715 if (pdata->ehci_data->phy_reset) { 716 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) { 717 gpio_request(pdata->ehci_data->reset_gpio_port[0], 718 "USB1 PHY reset"); 719 gpio_direction_output 720 (pdata->ehci_data->reset_gpio_port[0], 1); 721 } 722 723 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) { 724 gpio_request(pdata->ehci_data->reset_gpio_port[1], 725 "USB2 PHY reset"); 726 gpio_direction_output 727 (pdata->ehci_data->reset_gpio_port[1], 1); 728 } 729 730 /* Hold the PHY in RESET for enough time till DIR is high */ 731 udelay(10); 732 } 733 734 omap->usbhs_rev = usbhs_read(omap->uhh_base, OMAP_UHH_REVISION); 735 dev_dbg(dev, "OMAP UHH_REVISION 0x%x\n", omap->usbhs_rev); 736 737 /* perform TLL soft reset, and wait until reset is complete */ 738 usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG, 739 OMAP_USBTLL_SYSCONFIG_SOFTRESET); 740 741 /* Wait for TLL reset to complete */ 742 timeout = jiffies + msecs_to_jiffies(1000); 743 while (!(usbhs_read(omap->tll_base, OMAP_USBTLL_SYSSTATUS) 744 & OMAP_USBTLL_SYSSTATUS_RESETDONE)) { 745 cpu_relax(); 746 747 if (time_after(jiffies, timeout)) { 748 dev_dbg(dev, "operation timed out\n"); 749 ret = -EINVAL; 750 goto err_tll; 751 } 752 } 753 754 dev_dbg(dev, "TLL RESET DONE\n"); 755 756 /* (1<<3) = no idle mode only for initial debugging */ 757 usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG, 758 OMAP_USBTLL_SYSCONFIG_ENAWAKEUP | 759 OMAP_USBTLL_SYSCONFIG_SIDLEMODE | 760 OMAP_USBTLL_SYSCONFIG_AUTOIDLE); 761 762 /* Put UHH in NoIdle/NoStandby mode */ 763 reg = usbhs_read(omap->uhh_base, OMAP_UHH_SYSCONFIG); 764 if (is_omap_usbhs_rev1(omap)) { 765 reg |= (OMAP_UHH_SYSCONFIG_ENAWAKEUP 766 | OMAP_UHH_SYSCONFIG_SIDLEMODE 767 | OMAP_UHH_SYSCONFIG_CACTIVITY 768 | OMAP_UHH_SYSCONFIG_MIDLEMODE); 769 reg &= ~OMAP_UHH_SYSCONFIG_AUTOIDLE; 770 771 772 } else if (is_omap_usbhs_rev2(omap)) { 773 reg &= ~OMAP4_UHH_SYSCONFIG_IDLEMODE_CLEAR; 774 reg |= OMAP4_UHH_SYSCONFIG_NOIDLE; 775 reg &= ~OMAP4_UHH_SYSCONFIG_STDBYMODE_CLEAR; 776 reg |= OMAP4_UHH_SYSCONFIG_NOSTDBY; 777 } 778 779 usbhs_write(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg); 780 781 reg = usbhs_read(omap->uhh_base, OMAP_UHH_HOSTCONFIG); 782 /* setup ULPI bypass and burst configurations */ 783 reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN 784 | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN 785 | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN); 786 reg |= OMAP4_UHH_HOSTCONFIG_APP_START_CLK; 787 reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN; 788 789 if (is_omap_usbhs_rev1(omap)) { 790 if (pdata->port_mode[0] == OMAP_USBHS_PORT_MODE_UNUSED) 791 reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS; 792 if (pdata->port_mode[1] == OMAP_USBHS_PORT_MODE_UNUSED) 793 reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS; 794 if (pdata->port_mode[2] == OMAP_USBHS_PORT_MODE_UNUSED) 795 reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS; 796 797 /* Bypass the TLL module for PHY mode operation */ 798 if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) { 799 dev_dbg(dev, "OMAP3 ES version <= ES2.1\n"); 800 if (is_ehci_phy_mode(pdata->port_mode[0]) || 801 is_ehci_phy_mode(pdata->port_mode[1]) || 802 is_ehci_phy_mode(pdata->port_mode[2])) 803 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; 804 else 805 reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; 806 } else { 807 dev_dbg(dev, "OMAP3 ES version > ES2.1\n"); 808 if (is_ehci_phy_mode(pdata->port_mode[0])) 809 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; 810 else 811 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; 812 if (is_ehci_phy_mode(pdata->port_mode[1])) 813 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; 814 else 815 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; 816 if (is_ehci_phy_mode(pdata->port_mode[2])) 817 reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; 818 else 819 reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; 820 } 821 } else if (is_omap_usbhs_rev2(omap)) { 822 /* Clear port mode fields for PHY mode*/ 823 reg &= ~OMAP4_P1_MODE_CLEAR; 824 reg &= ~OMAP4_P2_MODE_CLEAR; 825 826 if (is_ehci_phy_mode(pdata->port_mode[0])) { 827 ret = clk_set_parent(omap->utmi_p1_fck, 828 omap->xclk60mhsp1_ck); 829 if (ret != 0) { 830 dev_err(dev, "xclk60mhsp1_ck set parent" 831 "failed error:%d\n", ret); 832 goto err_tll; 833 } 834 } else if (is_ehci_tll_mode(pdata->port_mode[0])) { 835 ret = clk_set_parent(omap->utmi_p1_fck, 836 omap->init_60m_fclk); 837 if (ret != 0) { 838 dev_err(dev, "init_60m_fclk set parent" 839 "failed error:%d\n", ret); 840 goto err_tll; 841 } 842 clk_enable(omap->usbhost_p1_fck); 843 clk_enable(omap->usbtll_p1_fck); 844 } 845 846 if (is_ehci_phy_mode(pdata->port_mode[1])) { 847 ret = clk_set_parent(omap->utmi_p2_fck, 848 omap->xclk60mhsp2_ck); 849 if (ret != 0) { 850 dev_err(dev, "xclk60mhsp1_ck set parent" 851 "failed error:%d\n", ret); 852 goto err_tll; 853 } 854 } else if (is_ehci_tll_mode(pdata->port_mode[1])) { 855 ret = clk_set_parent(omap->utmi_p2_fck, 856 omap->init_60m_fclk); 857 if (ret != 0) { 858 dev_err(dev, "init_60m_fclk set parent" 859 "failed error:%d\n", ret); 860 goto err_tll; 861 } 862 clk_enable(omap->usbhost_p2_fck); 863 clk_enable(omap->usbtll_p2_fck); 864 } 865 866 clk_enable(omap->utmi_p1_fck); 867 clk_enable(omap->utmi_p2_fck); 868 869 if (is_ehci_tll_mode(pdata->port_mode[0]) || 870 (is_ohci_port(pdata->port_mode[0]))) 871 reg |= OMAP4_P1_MODE_TLL; 872 else if (is_ehci_hsic_mode(pdata->port_mode[0])) 873 reg |= OMAP4_P1_MODE_HSIC; 874 875 if (is_ehci_tll_mode(pdata->port_mode[1]) || 876 (is_ohci_port(pdata->port_mode[1]))) 877 reg |= OMAP4_P2_MODE_TLL; 878 else if (is_ehci_hsic_mode(pdata->port_mode[1])) 879 reg |= OMAP4_P2_MODE_HSIC; 880 } 881 882 usbhs_write(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg); 883 dev_dbg(dev, "UHH setup done, uhh_hostconfig=%x\n", reg); 884 885 if (is_ehci_tll_mode(pdata->port_mode[0]) || 886 is_ehci_tll_mode(pdata->port_mode[1]) || 887 is_ehci_tll_mode(pdata->port_mode[2]) || 888 (is_ohci_port(pdata->port_mode[0])) || 889 (is_ohci_port(pdata->port_mode[1])) || 890 (is_ohci_port(pdata->port_mode[2]))) { 891 892 /* Enable UTMI mode for required TLL channels */ 893 if (is_omap_usbhs_rev2(omap)) 894 usbhs_omap_tll_init(dev, OMAP_REV2_TLL_CHANNEL_COUNT); 895 else 896 usbhs_omap_tll_init(dev, OMAP_TLL_CHANNEL_COUNT); 897 } 898 899 if (pdata->ehci_data->phy_reset) { 900 /* Hold the PHY in RESET for enough time till 901 * PHY is settled and ready 902 */ 903 udelay(10); 904 905 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) 906 gpio_set_value 907 (pdata->ehci_data->reset_gpio_port[0], 0); 908 909 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) 910 gpio_set_value 911 (pdata->ehci_data->reset_gpio_port[1], 0); 912 } 913 914 end_count: 915 omap->count++; 916 spin_unlock_irqrestore(&omap->lock, flags); 917 return 0; 918 919 err_tll: 920 if (pdata->ehci_data->phy_reset) { 921 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) 922 gpio_free(pdata->ehci_data->reset_gpio_port[0]); 923 924 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) 925 gpio_free(pdata->ehci_data->reset_gpio_port[1]); 926 } 927 928 clk_disable(omap->usbtll_ick); 929 clk_disable(omap->usbtll_fck); 930 clk_disable(omap->usbhost_fs_fck); 931 clk_disable(omap->usbhost_hs_fck); 932 clk_disable(omap->usbhost_ick); 933 spin_unlock_irqrestore(&omap->lock, flags); 934 return ret; 935 } 936 937 static void usbhs_disable(struct device *dev) 938 { 939 struct usbhs_hcd_omap *omap = dev_get_drvdata(dev); 940 struct usbhs_omap_platform_data *pdata = &omap->platdata; 941 unsigned long flags = 0; 942 unsigned long timeout; 943 944 dev_dbg(dev, "stopping TI HSUSB Controller\n"); 945 946 spin_lock_irqsave(&omap->lock, flags); 947 948 if (omap->count == 0) 949 goto end_disble; 950 951 omap->count--; 952 953 if (omap->count != 0) 954 goto end_disble; 955 956 /* Reset OMAP modules for insmod/rmmod to work */ 957 usbhs_write(omap->uhh_base, OMAP_UHH_SYSCONFIG, 958 is_omap_usbhs_rev2(omap) ? 959 OMAP4_UHH_SYSCONFIG_SOFTRESET : 960 OMAP_UHH_SYSCONFIG_SOFTRESET); 961 962 timeout = jiffies + msecs_to_jiffies(100); 963 while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS) 964 & (1 << 0))) { 965 cpu_relax(); 966 967 if (time_after(jiffies, timeout)) 968 dev_dbg(dev, "operation timed out\n"); 969 } 970 971 while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS) 972 & (1 << 1))) { 973 cpu_relax(); 974 975 if (time_after(jiffies, timeout)) 976 dev_dbg(dev, "operation timed out\n"); 977 } 978 979 while (!(usbhs_read(omap->uhh_base, OMAP_UHH_SYSSTATUS) 980 & (1 << 2))) { 981 cpu_relax(); 982 983 if (time_after(jiffies, timeout)) 984 dev_dbg(dev, "operation timed out\n"); 985 } 986 987 usbhs_write(omap->tll_base, OMAP_USBTLL_SYSCONFIG, (1 << 1)); 988 989 while (!(usbhs_read(omap->tll_base, OMAP_USBTLL_SYSSTATUS) 990 & (1 << 0))) { 991 cpu_relax(); 992 993 if (time_after(jiffies, timeout)) 994 dev_dbg(dev, "operation timed out\n"); 995 } 996 997 if (pdata->ehci_data->phy_reset) { 998 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[0])) 999 gpio_free(pdata->ehci_data->reset_gpio_port[0]); 1000 1001 if (gpio_is_valid(pdata->ehci_data->reset_gpio_port[1])) 1002 gpio_free(pdata->ehci_data->reset_gpio_port[1]); 1003 } 1004 1005 clk_disable(omap->utmi_p2_fck); 1006 clk_disable(omap->utmi_p1_fck); 1007 clk_disable(omap->usbtll_ick); 1008 clk_disable(omap->usbtll_fck); 1009 clk_disable(omap->usbhost_fs_fck); 1010 clk_disable(omap->usbhost_hs_fck); 1011 clk_disable(omap->usbhost_ick); 1012 1013 end_disble: 1014 spin_unlock_irqrestore(&omap->lock, flags); 1015 } 1016 1017 int omap_usbhs_enable(struct device *dev) 1018 { 1019 return usbhs_enable(dev->parent); 1020 } 1021 EXPORT_SYMBOL_GPL(omap_usbhs_enable); 1022 1023 void omap_usbhs_disable(struct device *dev) 1024 { 1025 usbhs_disable(dev->parent); 1026 } 1027 EXPORT_SYMBOL_GPL(omap_usbhs_disable); 1028 1029 static struct platform_driver usbhs_omap_driver = { 1030 .driver = { 1031 .name = (char *)usbhs_driver_name, 1032 .owner = THIS_MODULE, 1033 }, 1034 .remove = __exit_p(usbhs_omap_remove), 1035 }; 1036 1037 MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>"); 1038 MODULE_ALIAS("platform:" USBHS_DRIVER_NAME); 1039 MODULE_LICENSE("GPL v2"); 1040 MODULE_DESCRIPTION("usb host common core driver for omap EHCI and OHCI"); 1041 1042 static int __init omap_usbhs_drvinit(void) 1043 { 1044 return platform_driver_probe(&usbhs_omap_driver, usbhs_omap_probe); 1045 } 1046 1047 /* 1048 * init before ehci and ohci drivers; 1049 * The usbhs core driver should be initialized much before 1050 * the omap ehci and ohci probe functions are called. 1051 */ 1052 fs_initcall(omap_usbhs_drvinit); 1053 1054 static void __exit omap_usbhs_drvexit(void) 1055 { 1056 platform_driver_unregister(&usbhs_omap_driver); 1057 } 1058 module_exit(omap_usbhs_drvexit); 1059