1 /* 2 * max8997-irq.c - Interrupt controller support for MAX8997 3 * 4 * Copyright (C) 2011 Samsung Electronics Co.Ltd 5 * MyungJoo Ham <myungjoo.ham@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 * 21 * This driver is based on max8998-irq.c 22 */ 23 24 #include <linux/err.h> 25 #include <linux/irq.h> 26 #include <linux/interrupt.h> 27 #include <linux/mfd/max8997.h> 28 #include <linux/mfd/max8997-private.h> 29 30 static const u8 max8997_mask_reg[] = { 31 [PMIC_INT1] = MAX8997_REG_INT1MSK, 32 [PMIC_INT2] = MAX8997_REG_INT2MSK, 33 [PMIC_INT3] = MAX8997_REG_INT3MSK, 34 [PMIC_INT4] = MAX8997_REG_INT4MSK, 35 [FUEL_GAUGE] = MAX8997_REG_INVALID, 36 [MUIC_INT1] = MAX8997_MUIC_REG_INTMASK1, 37 [MUIC_INT2] = MAX8997_MUIC_REG_INTMASK2, 38 [MUIC_INT3] = MAX8997_MUIC_REG_INTMASK3, 39 [GPIO_LOW] = MAX8997_REG_INVALID, 40 [GPIO_HI] = MAX8997_REG_INVALID, 41 [FLASH_STATUS] = MAX8997_REG_INVALID, 42 }; 43 44 static struct i2c_client *get_i2c(struct max8997_dev *max8997, 45 enum max8997_irq_source src) 46 { 47 switch (src) { 48 case PMIC_INT1 ... PMIC_INT4: 49 return max8997->i2c; 50 case FUEL_GAUGE: 51 return NULL; 52 case MUIC_INT1 ... MUIC_INT3: 53 return max8997->muic; 54 case GPIO_LOW ... GPIO_HI: 55 return max8997->i2c; 56 case FLASH_STATUS: 57 return max8997->i2c; 58 default: 59 return ERR_PTR(-EINVAL); 60 } 61 } 62 63 struct max8997_irq_data { 64 int mask; 65 enum max8997_irq_source group; 66 }; 67 68 #define DECLARE_IRQ(idx, _group, _mask) \ 69 [(idx)] = { .group = (_group), .mask = (_mask) } 70 static const struct max8997_irq_data max8997_irqs[] = { 71 DECLARE_IRQ(MAX8997_PMICIRQ_PWRONR, PMIC_INT1, 1 << 0), 72 DECLARE_IRQ(MAX8997_PMICIRQ_PWRONF, PMIC_INT1, 1 << 1), 73 DECLARE_IRQ(MAX8997_PMICIRQ_PWRON1SEC, PMIC_INT1, 1 << 3), 74 DECLARE_IRQ(MAX8997_PMICIRQ_JIGONR, PMIC_INT1, 1 << 4), 75 DECLARE_IRQ(MAX8997_PMICIRQ_JIGONF, PMIC_INT1, 1 << 5), 76 DECLARE_IRQ(MAX8997_PMICIRQ_LOWBAT2, PMIC_INT1, 1 << 6), 77 DECLARE_IRQ(MAX8997_PMICIRQ_LOWBAT1, PMIC_INT1, 1 << 7), 78 79 DECLARE_IRQ(MAX8997_PMICIRQ_JIGR, PMIC_INT2, 1 << 0), 80 DECLARE_IRQ(MAX8997_PMICIRQ_JIGF, PMIC_INT2, 1 << 1), 81 DECLARE_IRQ(MAX8997_PMICIRQ_MR, PMIC_INT2, 1 << 2), 82 DECLARE_IRQ(MAX8997_PMICIRQ_DVS1OK, PMIC_INT2, 1 << 3), 83 DECLARE_IRQ(MAX8997_PMICIRQ_DVS2OK, PMIC_INT2, 1 << 4), 84 DECLARE_IRQ(MAX8997_PMICIRQ_DVS3OK, PMIC_INT2, 1 << 5), 85 DECLARE_IRQ(MAX8997_PMICIRQ_DVS4OK, PMIC_INT2, 1 << 6), 86 87 DECLARE_IRQ(MAX8997_PMICIRQ_CHGINS, PMIC_INT3, 1 << 0), 88 DECLARE_IRQ(MAX8997_PMICIRQ_CHGRM, PMIC_INT3, 1 << 1), 89 DECLARE_IRQ(MAX8997_PMICIRQ_DCINOVP, PMIC_INT3, 1 << 2), 90 DECLARE_IRQ(MAX8997_PMICIRQ_TOPOFFR, PMIC_INT3, 1 << 3), 91 DECLARE_IRQ(MAX8997_PMICIRQ_CHGRSTF, PMIC_INT3, 1 << 5), 92 DECLARE_IRQ(MAX8997_PMICIRQ_MBCHGTMEXPD, PMIC_INT3, 1 << 7), 93 94 DECLARE_IRQ(MAX8997_PMICIRQ_RTC60S, PMIC_INT4, 1 << 0), 95 DECLARE_IRQ(MAX8997_PMICIRQ_RTCA1, PMIC_INT4, 1 << 1), 96 DECLARE_IRQ(MAX8997_PMICIRQ_RTCA2, PMIC_INT4, 1 << 2), 97 DECLARE_IRQ(MAX8997_PMICIRQ_SMPL_INT, PMIC_INT4, 1 << 3), 98 DECLARE_IRQ(MAX8997_PMICIRQ_RTC1S, PMIC_INT4, 1 << 4), 99 DECLARE_IRQ(MAX8997_PMICIRQ_WTSR, PMIC_INT4, 1 << 5), 100 101 DECLARE_IRQ(MAX8997_MUICIRQ_ADCError, MUIC_INT1, 1 << 2), 102 DECLARE_IRQ(MAX8997_MUICIRQ_ADCLow, MUIC_INT1, 1 << 1), 103 DECLARE_IRQ(MAX8997_MUICIRQ_ADC, MUIC_INT1, 1 << 0), 104 105 DECLARE_IRQ(MAX8997_MUICIRQ_VBVolt, MUIC_INT2, 1 << 4), 106 DECLARE_IRQ(MAX8997_MUICIRQ_DBChg, MUIC_INT2, 1 << 3), 107 DECLARE_IRQ(MAX8997_MUICIRQ_DCDTmr, MUIC_INT2, 1 << 2), 108 DECLARE_IRQ(MAX8997_MUICIRQ_ChgDetRun, MUIC_INT2, 1 << 1), 109 DECLARE_IRQ(MAX8997_MUICIRQ_ChgTyp, MUIC_INT2, 1 << 0), 110 111 DECLARE_IRQ(MAX8997_MUICIRQ_OVP, MUIC_INT3, 1 << 2), 112 }; 113 114 static void max8997_irq_lock(struct irq_data *data) 115 { 116 struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data); 117 118 mutex_lock(&max8997->irqlock); 119 } 120 121 static void max8997_irq_sync_unlock(struct irq_data *data) 122 { 123 struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data); 124 int i; 125 126 for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++) { 127 u8 mask_reg = max8997_mask_reg[i]; 128 struct i2c_client *i2c = get_i2c(max8997, i); 129 130 if (mask_reg == MAX8997_REG_INVALID || 131 IS_ERR_OR_NULL(i2c)) 132 continue; 133 max8997->irq_masks_cache[i] = max8997->irq_masks_cur[i]; 134 135 max8997_write_reg(i2c, max8997_mask_reg[i], 136 max8997->irq_masks_cur[i]); 137 } 138 139 mutex_unlock(&max8997->irqlock); 140 } 141 142 static const inline struct max8997_irq_data * 143 irq_to_max8997_irq(struct max8997_dev *max8997, struct irq_data *data) 144 { 145 return &max8997_irqs[data->hwirq]; 146 } 147 148 static void max8997_irq_mask(struct irq_data *data) 149 { 150 struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data); 151 const struct max8997_irq_data *irq_data = irq_to_max8997_irq(max8997, 152 data); 153 154 max8997->irq_masks_cur[irq_data->group] |= irq_data->mask; 155 } 156 157 static void max8997_irq_unmask(struct irq_data *data) 158 { 159 struct max8997_dev *max8997 = irq_data_get_irq_chip_data(data); 160 const struct max8997_irq_data *irq_data = irq_to_max8997_irq(max8997, 161 data); 162 163 max8997->irq_masks_cur[irq_data->group] &= ~irq_data->mask; 164 } 165 166 static struct irq_chip max8997_irq_chip = { 167 .name = "max8997", 168 .irq_bus_lock = max8997_irq_lock, 169 .irq_bus_sync_unlock = max8997_irq_sync_unlock, 170 .irq_mask = max8997_irq_mask, 171 .irq_unmask = max8997_irq_unmask, 172 }; 173 174 #define MAX8997_IRQSRC_PMIC (1 << 1) 175 #define MAX8997_IRQSRC_FUELGAUGE (1 << 2) 176 #define MAX8997_IRQSRC_MUIC (1 << 3) 177 #define MAX8997_IRQSRC_GPIO (1 << 4) 178 #define MAX8997_IRQSRC_FLASH (1 << 5) 179 static irqreturn_t max8997_irq_thread(int irq, void *data) 180 { 181 struct max8997_dev *max8997 = data; 182 u8 irq_reg[MAX8997_IRQ_GROUP_NR] = {}; 183 u8 irq_src; 184 int ret; 185 int i, cur_irq; 186 187 ret = max8997_read_reg(max8997->i2c, MAX8997_REG_INTSRC, &irq_src); 188 if (ret < 0) { 189 dev_err(max8997->dev, "Failed to read interrupt source: %d\n", 190 ret); 191 return IRQ_NONE; 192 } 193 194 if (irq_src & MAX8997_IRQSRC_PMIC) { 195 /* PMIC INT1 ~ INT4 */ 196 max8997_bulk_read(max8997->i2c, MAX8997_REG_INT1, 4, 197 &irq_reg[PMIC_INT1]); 198 } 199 if (irq_src & MAX8997_IRQSRC_FUELGAUGE) { 200 /* 201 * TODO: FUEL GAUGE 202 * 203 * This is to be supported by Max17042 driver. When 204 * an interrupt incurs here, it should be relayed to a 205 * Max17042 device that is connected (probably by 206 * platform-data). However, we do not have interrupt 207 * handling in Max17042 driver currently. The Max17042 IRQ 208 * driver should be ready to be used as a stand-alone device and 209 * a Max8997-dependent device. Because it is not ready in 210 * Max17042-side and it is not too critical in operating 211 * Max8997, we do not implement this in initial releases. 212 */ 213 irq_reg[FUEL_GAUGE] = 0; 214 } 215 if (irq_src & MAX8997_IRQSRC_MUIC) { 216 /* MUIC INT1 ~ INT3 */ 217 max8997_bulk_read(max8997->muic, MAX8997_MUIC_REG_INT1, 3, 218 &irq_reg[MUIC_INT1]); 219 } 220 if (irq_src & MAX8997_IRQSRC_GPIO) { 221 /* GPIO Interrupt */ 222 u8 gpio_info[MAX8997_NUM_GPIO]; 223 224 irq_reg[GPIO_LOW] = 0; 225 irq_reg[GPIO_HI] = 0; 226 227 max8997_bulk_read(max8997->i2c, MAX8997_REG_GPIOCNTL1, 228 MAX8997_NUM_GPIO, gpio_info); 229 for (i = 0; i < MAX8997_NUM_GPIO; i++) { 230 bool interrupt = false; 231 232 switch (gpio_info[i] & MAX8997_GPIO_INT_MASK) { 233 case MAX8997_GPIO_INT_BOTH: 234 if (max8997->gpio_status[i] != gpio_info[i]) 235 interrupt = true; 236 break; 237 case MAX8997_GPIO_INT_RISE: 238 if ((max8997->gpio_status[i] != gpio_info[i]) && 239 (gpio_info[i] & MAX8997_GPIO_DATA_MASK)) 240 interrupt = true; 241 break; 242 case MAX8997_GPIO_INT_FALL: 243 if ((max8997->gpio_status[i] != gpio_info[i]) && 244 !(gpio_info[i] & MAX8997_GPIO_DATA_MASK)) 245 interrupt = true; 246 break; 247 default: 248 break; 249 } 250 251 if (interrupt) { 252 if (i < 8) 253 irq_reg[GPIO_LOW] |= (1 << i); 254 else 255 irq_reg[GPIO_HI] |= (1 << (i - 8)); 256 } 257 258 } 259 } 260 if (irq_src & MAX8997_IRQSRC_FLASH) { 261 /* Flash Status Interrupt */ 262 ret = max8997_read_reg(max8997->i2c, MAX8997_REG_FLASHSTATUS, 263 &irq_reg[FLASH_STATUS]); 264 } 265 266 /* Apply masking */ 267 for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++) 268 irq_reg[i] &= ~max8997->irq_masks_cur[i]; 269 270 /* Report */ 271 for (i = 0; i < MAX8997_IRQ_NR; i++) { 272 if (irq_reg[max8997_irqs[i].group] & max8997_irqs[i].mask) { 273 cur_irq = irq_find_mapping(max8997->irq_domain, i); 274 if (cur_irq) 275 handle_nested_irq(cur_irq); 276 } 277 } 278 279 return IRQ_HANDLED; 280 } 281 282 int max8997_irq_resume(struct max8997_dev *max8997) 283 { 284 if (max8997->irq && max8997->irq_domain) 285 max8997_irq_thread(0, max8997); 286 return 0; 287 } 288 289 static int max8997_irq_domain_map(struct irq_domain *d, unsigned int irq, 290 irq_hw_number_t hw) 291 { 292 struct max8997_dev *max8997 = d->host_data; 293 294 irq_set_chip_data(irq, max8997); 295 irq_set_chip_and_handler(irq, &max8997_irq_chip, handle_edge_irq); 296 irq_set_nested_thread(irq, 1); 297 irq_set_noprobe(irq); 298 299 return 0; 300 } 301 302 static const struct irq_domain_ops max8997_irq_domain_ops = { 303 .map = max8997_irq_domain_map, 304 }; 305 306 int max8997_irq_init(struct max8997_dev *max8997) 307 { 308 struct irq_domain *domain; 309 int i; 310 int ret; 311 u8 val; 312 313 if (!max8997->irq) { 314 dev_warn(max8997->dev, "No interrupt specified.\n"); 315 return 0; 316 } 317 318 mutex_init(&max8997->irqlock); 319 320 /* Mask individual interrupt sources */ 321 for (i = 0; i < MAX8997_IRQ_GROUP_NR; i++) { 322 struct i2c_client *i2c; 323 324 max8997->irq_masks_cur[i] = 0xff; 325 max8997->irq_masks_cache[i] = 0xff; 326 i2c = get_i2c(max8997, i); 327 328 if (IS_ERR_OR_NULL(i2c)) 329 continue; 330 if (max8997_mask_reg[i] == MAX8997_REG_INVALID) 331 continue; 332 333 max8997_write_reg(i2c, max8997_mask_reg[i], 0xff); 334 } 335 336 for (i = 0; i < MAX8997_NUM_GPIO; i++) { 337 max8997->gpio_status[i] = (max8997_read_reg(max8997->i2c, 338 MAX8997_REG_GPIOCNTL1 + i, 339 &val) 340 & MAX8997_GPIO_DATA_MASK) ? 341 true : false; 342 } 343 344 domain = irq_domain_add_linear(NULL, MAX8997_IRQ_NR, 345 &max8997_irq_domain_ops, max8997); 346 if (!domain) { 347 dev_err(max8997->dev, "could not create irq domain\n"); 348 return -ENODEV; 349 } 350 max8997->irq_domain = domain; 351 352 ret = request_threaded_irq(max8997->irq, NULL, max8997_irq_thread, 353 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 354 "max8997-irq", max8997); 355 356 if (ret) { 357 dev_err(max8997->dev, "Failed to request IRQ %d: %d\n", 358 max8997->irq, ret); 359 return ret; 360 } 361 362 if (!max8997->ono) 363 return 0; 364 365 ret = request_threaded_irq(max8997->ono, NULL, max8997_irq_thread, 366 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING | 367 IRQF_ONESHOT, "max8997-ono", max8997); 368 369 if (ret) 370 dev_err(max8997->dev, "Failed to request ono-IRQ %d: %d\n", 371 max8997->ono, ret); 372 373 return 0; 374 } 375 376 void max8997_irq_exit(struct max8997_dev *max8997) 377 { 378 if (max8997->ono) 379 free_irq(max8997->ono, max8997); 380 381 if (max8997->irq) 382 free_irq(max8997->irq, max8997); 383 } 384