1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright 2020 Google Inc 4 * Copyright 2025 Linaro Ltd. 5 * 6 * Core driver for Maxim MAX77759 companion PMIC for USB Type-C 7 */ 8 9 #include <linux/array_size.h> 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/cleanup.h> 13 #include <linux/completion.h> 14 #include <linux/dev_printk.h> 15 #include <linux/device.h> 16 #include <linux/err.h> 17 #include <linux/i2c.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/jiffies.h> 22 #include <linux/mfd/core.h> 23 #include <linux/mfd/max77759.h> 24 #include <linux/mod_devicetable.h> 25 #include <linux/module.h> 26 #include <linux/mutex.h> 27 #include <linux/of.h> 28 #include <linux/overflow.h> 29 #include <linux/regmap.h> 30 31 /* Chip ID as per MAX77759_PMIC_REG_PMIC_ID */ 32 enum { 33 MAX77759_CHIP_ID = 59, 34 }; 35 36 enum max77759_i2c_subdev_id { 37 /* 38 * These are arbitrary and simply used to match struct 39 * max77759_i2c_subdev entries to the regmap pointers in struct 40 * max77759 during probe(). 41 */ 42 MAX77759_I2C_SUBDEV_ID_MAXQ, 43 MAX77759_I2C_SUBDEV_ID_CHARGER, 44 }; 45 46 struct max77759_i2c_subdev { 47 enum max77759_i2c_subdev_id id; 48 const struct regmap_config *cfg; 49 u16 i2c_address; 50 }; 51 52 static const struct regmap_range max77759_top_registers[] = { 53 regmap_reg_range(0x00, 0x02), /* PMIC_ID / PMIC_REVISION / OTP_REVISION */ 54 regmap_reg_range(0x22, 0x24), /* INTSRC / INTSRCMASK / TOPSYS_INT */ 55 regmap_reg_range(0x26, 0x26), /* TOPSYS_INT_MASK */ 56 regmap_reg_range(0x40, 0x40), /* I2C_CNFG */ 57 regmap_reg_range(0x50, 0x51), /* SWRESET / CONTROL_FG */ 58 }; 59 60 static const struct regmap_range max77759_top_ro_registers[] = { 61 regmap_reg_range(0x00, 0x02), 62 regmap_reg_range(0x22, 0x22), 63 }; 64 65 static const struct regmap_range max77759_top_volatile_registers[] = { 66 regmap_reg_range(0x22, 0x22), 67 regmap_reg_range(0x24, 0x24), 68 }; 69 70 static const struct regmap_access_table max77759_top_wr_table = { 71 .yes_ranges = max77759_top_registers, 72 .n_yes_ranges = ARRAY_SIZE(max77759_top_registers), 73 .no_ranges = max77759_top_ro_registers, 74 .n_no_ranges = ARRAY_SIZE(max77759_top_ro_registers), 75 }; 76 77 static const struct regmap_access_table max77759_top_rd_table = { 78 .yes_ranges = max77759_top_registers, 79 .n_yes_ranges = ARRAY_SIZE(max77759_top_registers), 80 }; 81 82 static const struct regmap_access_table max77759_top_volatile_table = { 83 .yes_ranges = max77759_top_volatile_registers, 84 .n_yes_ranges = ARRAY_SIZE(max77759_top_volatile_registers), 85 }; 86 87 static const struct regmap_config max77759_regmap_config_top = { 88 .name = "top", 89 .reg_bits = 8, 90 .val_bits = 8, 91 .max_register = MAX77759_PMIC_REG_CONTROL_FG, 92 .wr_table = &max77759_top_wr_table, 93 .rd_table = &max77759_top_rd_table, 94 .volatile_table = &max77759_top_volatile_table, 95 .num_reg_defaults_raw = MAX77759_PMIC_REG_CONTROL_FG + 1, 96 .cache_type = REGCACHE_FLAT, 97 }; 98 99 static const struct regmap_range max77759_maxq_registers[] = { 100 regmap_reg_range(0x60, 0x73), /* Device ID, Rev, INTx, STATUSx, MASKx */ 101 regmap_reg_range(0x81, 0xa1), /* AP_DATAOUTx */ 102 regmap_reg_range(0xb1, 0xd1), /* AP_DATAINx */ 103 regmap_reg_range(0xe0, 0xe0), /* UIC_SWRST */ 104 }; 105 106 static const struct regmap_range max77759_maxq_ro_registers[] = { 107 regmap_reg_range(0x60, 0x63), /* Device ID, Rev */ 108 regmap_reg_range(0x68, 0x6f), /* STATUSx */ 109 regmap_reg_range(0xb1, 0xd1), 110 }; 111 112 static const struct regmap_range max77759_maxq_volatile_registers[] = { 113 regmap_reg_range(0x64, 0x6f), /* INTx, STATUSx */ 114 regmap_reg_range(0xb1, 0xd1), 115 regmap_reg_range(0xe0, 0xe0), 116 }; 117 118 static const struct regmap_access_table max77759_maxq_wr_table = { 119 .yes_ranges = max77759_maxq_registers, 120 .n_yes_ranges = ARRAY_SIZE(max77759_maxq_registers), 121 .no_ranges = max77759_maxq_ro_registers, 122 .n_no_ranges = ARRAY_SIZE(max77759_maxq_ro_registers), 123 }; 124 125 static const struct regmap_access_table max77759_maxq_rd_table = { 126 .yes_ranges = max77759_maxq_registers, 127 .n_yes_ranges = ARRAY_SIZE(max77759_maxq_registers), 128 }; 129 130 static const struct regmap_access_table max77759_maxq_volatile_table = { 131 .yes_ranges = max77759_maxq_volatile_registers, 132 .n_yes_ranges = ARRAY_SIZE(max77759_maxq_volatile_registers), 133 }; 134 135 static const struct regmap_config max77759_regmap_config_maxq = { 136 .name = "maxq", 137 .reg_bits = 8, 138 .val_bits = 8, 139 .max_register = MAX77759_MAXQ_REG_UIC_SWRST, 140 .wr_table = &max77759_maxq_wr_table, 141 .rd_table = &max77759_maxq_rd_table, 142 .volatile_table = &max77759_maxq_volatile_table, 143 .num_reg_defaults_raw = MAX77759_MAXQ_REG_UIC_SWRST + 1, 144 .cache_type = REGCACHE_FLAT, 145 }; 146 147 static const struct regmap_range max77759_charger_registers[] = { 148 regmap_reg_range(0xb0, 0xcc), 149 }; 150 151 static const struct regmap_range max77759_charger_ro_registers[] = { 152 regmap_reg_range(0xb4, 0xb8), /* INT_OK, DETAILS_0x */ 153 }; 154 155 static const struct regmap_range max77759_charger_volatile_registers[] = { 156 regmap_reg_range(0xb0, 0xb1), /* INTx */ 157 regmap_reg_range(0xb4, 0xb8), 158 }; 159 160 static const struct regmap_access_table max77759_charger_wr_table = { 161 .yes_ranges = max77759_charger_registers, 162 .n_yes_ranges = ARRAY_SIZE(max77759_charger_registers), 163 .no_ranges = max77759_charger_ro_registers, 164 .n_no_ranges = ARRAY_SIZE(max77759_charger_ro_registers), 165 }; 166 167 static const struct regmap_access_table max77759_charger_rd_table = { 168 .yes_ranges = max77759_charger_registers, 169 .n_yes_ranges = ARRAY_SIZE(max77759_charger_registers), 170 }; 171 172 static const struct regmap_access_table max77759_charger_volatile_table = { 173 .yes_ranges = max77759_charger_volatile_registers, 174 .n_yes_ranges = ARRAY_SIZE(max77759_charger_volatile_registers), 175 }; 176 177 static const struct regmap_config max77759_regmap_config_charger = { 178 .name = "charger", 179 .reg_bits = 8, 180 .val_bits = 8, 181 .max_register = MAX77759_CHGR_REG_CHG_CNFG_19, 182 .wr_table = &max77759_charger_wr_table, 183 .rd_table = &max77759_charger_rd_table, 184 .volatile_table = &max77759_charger_volatile_table, 185 .num_reg_defaults_raw = MAX77759_CHGR_REG_CHG_CNFG_19 + 1, 186 .cache_type = REGCACHE_FLAT, 187 }; 188 189 /* 190 * Interrupts - with the following interrupt hierarchy: 191 * pmic IRQs (INTSRC) 192 * - MAXQ_INT: MaxQ IRQs 193 * - UIC_INT1 194 * - APCmdResI 195 * - SysMsgI 196 * - GPIOxI 197 * - TOPSYS_INT: topsys 198 * - TOPSYS_INT 199 * - TSHDN_INT 200 * - SYSOVLO_INT 201 * - SYSUVLO_INT 202 * - FSHIP_NOT_RD 203 * - CHGR_INT: charger 204 * - INT1 205 * - AICL 206 * - CHGIN 207 * - WCIN 208 * - CHG 209 * - BAT 210 * - INLIM 211 * - THM2 212 * - BYP 213 * - INT2 214 * - INSEL 215 * - SYS_UVLO1 216 * - SYS_UVLO2 217 * - BAT_OILO 218 * - CHG_STA_CC 219 * - CHG_STA_CV 220 * - CHG_STA_TO 221 * - CHG_STA_DONE 222 */ 223 enum { 224 MAX77759_INT_MAXQ, 225 MAX77759_INT_TOPSYS, 226 MAX77759_INT_CHGR, 227 }; 228 229 enum { 230 MAX77759_TOPSYS_INT_TSHDN, 231 MAX77759_TOPSYS_INT_SYSOVLO, 232 MAX77759_TOPSYS_INT_SYSUVLO, 233 MAX77759_TOPSYS_INT_FSHIP_NOT_RD, 234 }; 235 236 enum { 237 MAX77759_MAXQ_INT_APCMDRESI, 238 MAX77759_MAXQ_INT_SYSMSGI, 239 MAX77759_MAXQ_INT_GPIO, 240 MAX77759_MAXQ_INT_UIC1, 241 MAX77759_MAXQ_INT_UIC2, 242 MAX77759_MAXQ_INT_UIC3, 243 MAX77759_MAXQ_INT_UIC4, 244 }; 245 246 enum { 247 MAX77759_CHGR_INT1_AICL, 248 MAX77759_CHGR_INT1_CHGIN, 249 MAX77759_CHGR_INT1_WCIN, 250 MAX77759_CHGR_INT1_CHG, 251 MAX77759_CHGR_INT1_BAT, 252 MAX77759_CHGR_INT1_INLIM, 253 MAX77759_CHGR_INT1_THM2, 254 MAX77759_CHGR_INT1_BYP, 255 MAX77759_CHGR_INT2_INSEL, 256 MAX77759_CHGR_INT2_SYS_UVLO1, 257 MAX77759_CHGR_INT2_SYS_UVLO2, 258 MAX77759_CHGR_INT2_BAT_OILO, 259 MAX77759_CHGR_INT2_CHG_STA_CC, 260 MAX77759_CHGR_INT2_CHG_STA_CV, 261 MAX77759_CHGR_INT2_CHG_STA_TO, 262 MAX77759_CHGR_INT2_CHG_STA_DONE, 263 }; 264 265 static const struct regmap_irq max77759_pmic_irqs[] = { 266 REGMAP_IRQ_REG(MAX77759_INT_MAXQ, 0, MAX77759_PMIC_REG_INTSRC_MAXQ), 267 REGMAP_IRQ_REG(MAX77759_INT_TOPSYS, 0, MAX77759_PMIC_REG_INTSRC_TOPSYS), 268 REGMAP_IRQ_REG(MAX77759_INT_CHGR, 0, MAX77759_PMIC_REG_INTSRC_CHGR), 269 }; 270 271 static const struct regmap_irq max77759_maxq_irqs[] = { 272 REGMAP_IRQ_REG(MAX77759_MAXQ_INT_APCMDRESI, 0, MAX77759_MAXQ_REG_UIC_INT1_APCMDRESI), 273 REGMAP_IRQ_REG(MAX77759_MAXQ_INT_SYSMSGI, 0, MAX77759_MAXQ_REG_UIC_INT1_SYSMSGI), 274 REGMAP_IRQ_REG(MAX77759_MAXQ_INT_GPIO, 0, GENMASK(1, 0)), 275 REGMAP_IRQ_REG(MAX77759_MAXQ_INT_UIC1, 0, GENMASK(5, 2)), 276 REGMAP_IRQ_REG(MAX77759_MAXQ_INT_UIC2, 1, GENMASK(7, 0)), 277 REGMAP_IRQ_REG(MAX77759_MAXQ_INT_UIC3, 2, GENMASK(7, 0)), 278 REGMAP_IRQ_REG(MAX77759_MAXQ_INT_UIC4, 3, GENMASK(7, 0)), 279 }; 280 281 static const struct regmap_irq max77759_topsys_irqs[] = { 282 REGMAP_IRQ_REG(MAX77759_TOPSYS_INT_TSHDN, 0, MAX77759_PMIC_REG_TOPSYS_INT_TSHDN), 283 REGMAP_IRQ_REG(MAX77759_TOPSYS_INT_SYSOVLO, 0, MAX77759_PMIC_REG_TOPSYS_INT_SYSOVLO), 284 REGMAP_IRQ_REG(MAX77759_TOPSYS_INT_SYSUVLO, 0, MAX77759_PMIC_REG_TOPSYS_INT_SYSUVLO), 285 REGMAP_IRQ_REG(MAX77759_TOPSYS_INT_FSHIP_NOT_RD, 0, MAX77759_PMIC_REG_TOPSYS_INT_FSHIP), 286 }; 287 288 static const struct regmap_irq max77759_chgr_irqs[] = { 289 REGMAP_IRQ_REG(MAX77759_CHGR_INT1_AICL, 0, MAX77759_CHGR_REG_CHG_INT_AICL), 290 REGMAP_IRQ_REG(MAX77759_CHGR_INT1_CHGIN, 0, MAX77759_CHGR_REG_CHG_INT_CHGIN), 291 REGMAP_IRQ_REG(MAX77759_CHGR_INT1_WCIN, 0, MAX77759_CHGR_REG_CHG_INT_WCIN), 292 REGMAP_IRQ_REG(MAX77759_CHGR_INT1_CHG, 0, MAX77759_CHGR_REG_CHG_INT_CHG), 293 REGMAP_IRQ_REG(MAX77759_CHGR_INT1_BAT, 0, MAX77759_CHGR_REG_CHG_INT_BAT), 294 REGMAP_IRQ_REG(MAX77759_CHGR_INT1_INLIM, 0, MAX77759_CHGR_REG_CHG_INT_INLIM), 295 REGMAP_IRQ_REG(MAX77759_CHGR_INT1_THM2, 0, MAX77759_CHGR_REG_CHG_INT_THM2), 296 REGMAP_IRQ_REG(MAX77759_CHGR_INT1_BYP, 0, MAX77759_CHGR_REG_CHG_INT_BYP), 297 REGMAP_IRQ_REG(MAX77759_CHGR_INT2_INSEL, 1, MAX77759_CHGR_REG_CHG_INT2_INSEL), 298 REGMAP_IRQ_REG(MAX77759_CHGR_INT2_SYS_UVLO1, 1, MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO1), 299 REGMAP_IRQ_REG(MAX77759_CHGR_INT2_SYS_UVLO2, 1, MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO2), 300 REGMAP_IRQ_REG(MAX77759_CHGR_INT2_BAT_OILO, 1, MAX77759_CHGR_REG_CHG_INT2_BAT_OILO), 301 REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_CC, 1, MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CC), 302 REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_CV, 1, MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CV), 303 REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_TO, 1, MAX77759_CHGR_REG_CHG_INT2_CHG_STA_TO), 304 REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_DONE, 1, MAX77759_CHGR_REG_CHG_INT2_CHG_STA_DONE), 305 }; 306 307 static const struct regmap_irq_chip max77759_pmic_irq_chip = { 308 .name = "max77759-pmic", 309 /* INTSRC is read-only and doesn't require clearing */ 310 .status_base = MAX77759_PMIC_REG_INTSRC, 311 .mask_base = MAX77759_PMIC_REG_INTSRCMASK, 312 .num_regs = 1, 313 .irqs = max77759_pmic_irqs, 314 .num_irqs = ARRAY_SIZE(max77759_pmic_irqs), 315 }; 316 317 /* 318 * We can let regmap-irq auto-ack the topsys interrupt bits as required, but 319 * for all others the individual drivers need to know which interrupt bit 320 * exactly is set inside their interrupt handlers, and therefore we can not set 321 * .ack_base for those. 322 */ 323 static const struct regmap_irq_chip max77759_maxq_irq_chip = { 324 .name = "max77759-maxq", 325 .domain_suffix = "MAXQ", 326 .status_base = MAX77759_MAXQ_REG_UIC_INT1, 327 .mask_base = MAX77759_MAXQ_REG_UIC_INT1_M, 328 .num_regs = 4, 329 .irqs = max77759_maxq_irqs, 330 .num_irqs = ARRAY_SIZE(max77759_maxq_irqs), 331 }; 332 333 static const struct regmap_irq_chip max77759_topsys_irq_chip = { 334 .name = "max77759-topsys", 335 .domain_suffix = "TOPSYS", 336 .status_base = MAX77759_PMIC_REG_TOPSYS_INT, 337 .mask_base = MAX77759_PMIC_REG_TOPSYS_INT_MASK, 338 .ack_base = MAX77759_PMIC_REG_TOPSYS_INT, 339 .num_regs = 1, 340 .irqs = max77759_topsys_irqs, 341 .num_irqs = ARRAY_SIZE(max77759_topsys_irqs), 342 }; 343 344 static const struct regmap_irq_chip max77759_chgr_irq_chip = { 345 .name = "max77759-chgr", 346 .domain_suffix = "CHGR", 347 .status_base = MAX77759_CHGR_REG_CHG_INT, 348 .mask_base = MAX77759_CHGR_REG_CHG_INT_MASK, 349 .ack_base = MAX77759_CHGR_REG_CHG_INT, 350 .num_regs = 2, 351 .irqs = max77759_chgr_irqs, 352 .num_irqs = ARRAY_SIZE(max77759_chgr_irqs), 353 }; 354 355 static const struct max77759_i2c_subdev max77759_i2c_subdevs[] = { 356 { 357 .id = MAX77759_I2C_SUBDEV_ID_MAXQ, 358 .cfg = &max77759_regmap_config_maxq, 359 /* I2C address is same as for sub-block 'top' */ 360 }, 361 { 362 .id = MAX77759_I2C_SUBDEV_ID_CHARGER, 363 .cfg = &max77759_regmap_config_charger, 364 .i2c_address = 0x69, 365 }, 366 }; 367 368 static const struct resource max77759_gpio_resources[] = { 369 DEFINE_RES_IRQ_NAMED(MAX77759_MAXQ_INT_GPIO, "GPI"), 370 }; 371 372 static const struct resource max77759_charger_resources[] = { 373 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_AICL, "AICL"), 374 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_CHGIN, "CHGIN"), 375 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_WCIN, "WCIN"), 376 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_CHG, "CHG"), 377 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_BAT, "BAT"), 378 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_INLIM, "INLIM"), 379 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_THM2, "THM2"), 380 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_BYP, "BYP"), 381 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_INSEL, "INSEL"), 382 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_SYS_UVLO1, "SYS_UVLO1"), 383 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_SYS_UVLO2, "SYS_UVLO2"), 384 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_BAT_OILO, "BAT_OILO"), 385 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_CHG_STA_CC, "CHG_STA_CC"), 386 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_CHG_STA_CV, "CHG_STA_CV"), 387 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_CHG_STA_TO, "CHG_STA_TO"), 388 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_CHG_STA_DONE, "CHG_STA_DONE"), 389 }; 390 391 static const struct mfd_cell max77759_cells[] = { 392 MFD_CELL_OF("max77759-nvmem", NULL, NULL, 0, 0, 393 "maxim,max77759-nvmem"), 394 }; 395 396 static const struct mfd_cell max77759_maxq_cells[] = { 397 MFD_CELL_OF("max77759-gpio", max77759_gpio_resources, NULL, 0, 0, 398 "maxim,max77759-gpio"), 399 }; 400 401 static const struct mfd_cell max77759_charger_cells[] = { 402 MFD_CELL_RES("max77759-charger", max77759_charger_resources), 403 }; 404 405 int max77759_maxq_command(struct max77759 *max77759, 406 const struct max77759_maxq_command *cmd, 407 struct max77759_maxq_response *rsp) 408 { 409 DEFINE_FLEX(struct max77759_maxq_response, _rsp, rsp, length, 1); 410 struct device *dev = regmap_get_device(max77759->regmap_maxq); 411 static const unsigned int timeout_ms = 200; 412 int ret; 413 414 if (cmd->length > MAX77759_MAXQ_OPCODE_MAXLENGTH) 415 return -EINVAL; 416 417 /* 418 * As a convenience for API users when issuing simple commands, rsp is 419 * allowed to be NULL. In that case we need a temporary here to write 420 * the response to, as we need to verify that the command was indeed 421 * completed correctly. 422 */ 423 if (!rsp) 424 rsp = _rsp; 425 426 if (!rsp->length || rsp->length > MAX77759_MAXQ_OPCODE_MAXLENGTH) 427 return -EINVAL; 428 429 guard(mutex)(&max77759->maxq_lock); 430 431 reinit_completion(&max77759->cmd_done); 432 433 /* 434 * MaxQ latches the message when the DATAOUT32 register is written. If 435 * cmd->length is shorter we still need to write 0 to it. 436 */ 437 ret = regmap_bulk_write(max77759->regmap_maxq, 438 MAX77759_MAXQ_REG_AP_DATAOUT0, cmd->cmd, 439 cmd->length); 440 if (!ret && cmd->length < MAX77759_MAXQ_OPCODE_MAXLENGTH) 441 ret = regmap_write(max77759->regmap_maxq, 442 MAX77759_MAXQ_REG_AP_DATAOUT32, 0); 443 if (ret) { 444 dev_err(dev, "writing command failed: %d\n", ret); 445 return ret; 446 } 447 448 /* Wait for response from MaxQ */ 449 if (!wait_for_completion_timeout(&max77759->cmd_done, 450 msecs_to_jiffies(timeout_ms))) { 451 dev_err(dev, "timed out waiting for response\n"); 452 return -ETIMEDOUT; 453 } 454 455 ret = regmap_bulk_read(max77759->regmap_maxq, 456 MAX77759_MAXQ_REG_AP_DATAIN0, 457 rsp->rsp, rsp->length); 458 if (ret) { 459 dev_err(dev, "reading response failed: %d\n", ret); 460 return ret; 461 } 462 463 /* 464 * As per the protocol, the first byte of the reply will match the 465 * request. 466 */ 467 if (cmd->cmd[0] != rsp->rsp[0]) { 468 dev_err(dev, "unexpected opcode response for %#.2x: %*ph\n", 469 cmd->cmd[0], (int)rsp->length, rsp->rsp); 470 return -EIO; 471 } 472 473 return 0; 474 } 475 EXPORT_SYMBOL_GPL(max77759_maxq_command); 476 477 static irqreturn_t apcmdres_irq_handler(int irq, void *irq_data) 478 { 479 struct max77759 *max77759 = irq_data; 480 481 regmap_write(max77759->regmap_maxq, MAX77759_MAXQ_REG_UIC_INT1, 482 MAX77759_MAXQ_REG_UIC_INT1_APCMDRESI); 483 484 complete(&max77759->cmd_done); 485 486 return IRQ_HANDLED; 487 } 488 489 static int max77759_create_i2c_subdev(struct i2c_client *client, 490 struct max77759 *max77759, 491 const struct max77759_i2c_subdev *sd) 492 { 493 struct i2c_client *sub; 494 struct regmap *regmap; 495 int ret; 496 497 /* 498 * If 'sd' has an I2C address, 'sub' will be assigned a new 'dummy' 499 * device, otherwise use it as-is. 500 */ 501 sub = client; 502 if (sd->i2c_address) { 503 sub = devm_i2c_new_dummy_device(&client->dev, 504 client->adapter, 505 sd->i2c_address); 506 507 if (IS_ERR(sub)) 508 return dev_err_probe(&client->dev, PTR_ERR(sub), 509 "failed to claim I2C device %s\n", 510 sd->cfg->name); 511 } 512 513 regmap = devm_regmap_init_i2c(sub, sd->cfg); 514 if (IS_ERR(regmap)) 515 return dev_err_probe(&sub->dev, PTR_ERR(regmap), 516 "regmap init for '%s' failed\n", 517 sd->cfg->name); 518 519 ret = regmap_attach_dev(&client->dev, regmap, sd->cfg); 520 if (ret) 521 return dev_err_probe(&client->dev, ret, 522 "regmap attach of '%s' failed\n", 523 sd->cfg->name); 524 525 if (sd->id == MAX77759_I2C_SUBDEV_ID_MAXQ) 526 max77759->regmap_maxq = regmap; 527 else if (sd->id == MAX77759_I2C_SUBDEV_ID_CHARGER) 528 max77759->regmap_charger = regmap; 529 530 return 0; 531 } 532 533 static int max77759_add_chained_irq_chip(struct device *dev, 534 struct regmap *regmap, 535 int pirq, 536 struct regmap_irq_chip_data *parent, 537 const struct regmap_irq_chip *chip, 538 struct regmap_irq_chip_data **data) 539 { 540 int irq, ret; 541 542 irq = regmap_irq_get_virq(parent, pirq); 543 if (irq < 0) 544 return dev_err_probe(dev, irq, 545 "failed to get parent vIRQ(%d) for chip %s\n", 546 pirq, chip->name); 547 548 ret = devm_regmap_add_irq_chip(dev, regmap, irq, 549 IRQF_ONESHOT | IRQF_SHARED, 0, chip, 550 data); 551 if (ret) 552 return dev_err_probe(dev, ret, "failed to add %s IRQ chip\n", 553 chip->name); 554 555 return 0; 556 } 557 558 static int max77759_add_chained_maxq(struct i2c_client *client, 559 struct max77759 *max77759, 560 struct regmap_irq_chip_data *parent) 561 { 562 struct regmap_irq_chip_data *irq_chip_data; 563 int apcmdres_irq; 564 int ret; 565 566 ret = max77759_add_chained_irq_chip(&client->dev, 567 max77759->regmap_maxq, 568 MAX77759_INT_MAXQ, 569 parent, 570 &max77759_maxq_irq_chip, 571 &irq_chip_data); 572 if (ret) 573 return ret; 574 575 init_completion(&max77759->cmd_done); 576 apcmdres_irq = regmap_irq_get_virq(irq_chip_data, 577 MAX77759_MAXQ_INT_APCMDRESI); 578 579 ret = devm_request_threaded_irq(&client->dev, apcmdres_irq, 580 NULL, apcmdres_irq_handler, 581 IRQF_ONESHOT | IRQF_SHARED, 582 dev_name(&client->dev), max77759); 583 if (ret) 584 return dev_err_probe(&client->dev, ret, 585 "MAX77759_MAXQ_INT_APCMDRESI failed\n"); 586 587 ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO, 588 max77759_maxq_cells, 589 ARRAY_SIZE(max77759_maxq_cells), 590 NULL, 0, 591 regmap_irq_get_domain(irq_chip_data)); 592 if (ret) 593 return dev_err_probe(&client->dev, ret, 594 "failed to add child devices (MaxQ)\n"); 595 596 return 0; 597 } 598 599 static int max77759_add_chained_topsys(struct i2c_client *client, 600 struct max77759 *max77759, 601 struct regmap_irq_chip_data *parent) 602 { 603 struct regmap_irq_chip_data *irq_chip_data; 604 int ret; 605 606 ret = max77759_add_chained_irq_chip(&client->dev, 607 max77759->regmap_top, 608 MAX77759_INT_TOPSYS, 609 parent, 610 &max77759_topsys_irq_chip, 611 &irq_chip_data); 612 if (ret) 613 return ret; 614 615 return 0; 616 } 617 618 static int max77759_add_chained_charger(struct i2c_client *client, 619 struct max77759 *max77759, 620 struct regmap_irq_chip_data *parent) 621 { 622 struct regmap_irq_chip_data *irq_chip_data; 623 int ret; 624 625 ret = max77759_add_chained_irq_chip(&client->dev, 626 max77759->regmap_charger, 627 MAX77759_INT_CHGR, 628 parent, 629 &max77759_chgr_irq_chip, 630 &irq_chip_data); 631 if (ret) 632 return ret; 633 634 ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO, 635 max77759_charger_cells, 636 ARRAY_SIZE(max77759_charger_cells), 637 NULL, 0, 638 regmap_irq_get_domain(irq_chip_data)); 639 if (ret) 640 return dev_err_probe(&client->dev, ret, 641 "failed to add child devices (charger)\n"); 642 643 return 0; 644 } 645 646 static int max77759_probe(struct i2c_client *client) 647 { 648 struct regmap_irq_chip_data *irq_chip_data_pmic; 649 struct max77759 *max77759; 650 unsigned int pmic_id; 651 int ret; 652 653 max77759 = devm_kzalloc(&client->dev, sizeof(*max77759), GFP_KERNEL); 654 if (!max77759) 655 return -ENOMEM; 656 657 i2c_set_clientdata(client, max77759); 658 659 max77759->regmap_top = devm_regmap_init_i2c(client, 660 &max77759_regmap_config_top); 661 if (IS_ERR(max77759->regmap_top)) 662 return dev_err_probe(&client->dev, PTR_ERR(max77759->regmap_top), 663 "regmap init for '%s' failed\n", 664 max77759_regmap_config_top.name); 665 666 ret = regmap_read(max77759->regmap_top, 667 MAX77759_PMIC_REG_PMIC_ID, &pmic_id); 668 if (ret) 669 return dev_err_probe(&client->dev, ret, 670 "unable to read device ID\n"); 671 672 if (pmic_id != MAX77759_CHIP_ID) 673 return dev_err_probe(&client->dev, -ENODEV, 674 "unsupported device ID %#.2x (%d)\n", 675 pmic_id, pmic_id); 676 677 ret = devm_mutex_init(&client->dev, &max77759->maxq_lock); 678 if (ret) 679 return ret; 680 681 for (int i = 0; i < ARRAY_SIZE(max77759_i2c_subdevs); i++) { 682 ret = max77759_create_i2c_subdev(client, max77759, 683 &max77759_i2c_subdevs[i]); 684 if (ret) 685 return ret; 686 } 687 688 ret = devm_regmap_add_irq_chip(&client->dev, max77759->regmap_top, 689 client->irq, IRQF_ONESHOT | IRQF_SHARED, 0, 690 &max77759_pmic_irq_chip, 691 &irq_chip_data_pmic); 692 if (ret) 693 return dev_err_probe(&client->dev, ret, 694 "failed to add IRQ chip '%s'\n", 695 max77759_pmic_irq_chip.name); 696 697 ret = max77759_add_chained_maxq(client, max77759, irq_chip_data_pmic); 698 if (ret) 699 return ret; 700 701 ret = max77759_add_chained_topsys(client, max77759, irq_chip_data_pmic); 702 if (ret) 703 return ret; 704 705 ret = max77759_add_chained_charger(client, max77759, irq_chip_data_pmic); 706 if (ret) 707 return ret; 708 709 return devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO, 710 max77759_cells, ARRAY_SIZE(max77759_cells), 711 NULL, 0, 712 regmap_irq_get_domain(irq_chip_data_pmic)); 713 } 714 715 static const struct i2c_device_id max77759_i2c_id[] = { 716 { "max77759" }, 717 { } 718 }; 719 MODULE_DEVICE_TABLE(i2c, max77759_i2c_id); 720 721 static const struct of_device_id max77759_of_id[] = { 722 { .compatible = "maxim,max77759", }, 723 { } 724 }; 725 MODULE_DEVICE_TABLE(of, max77759_of_id); 726 727 static struct i2c_driver max77759_i2c_driver = { 728 .driver = { 729 .name = "max77759", 730 .of_match_table = max77759_of_id, 731 }, 732 .probe = max77759_probe, 733 .id_table = max77759_i2c_id, 734 }; 735 module_i2c_driver(max77759_i2c_driver); 736 737 MODULE_AUTHOR("André Draszik <andre.draszik@linaro.org>"); 738 MODULE_DESCRIPTION("Maxim MAX77759 core driver"); 739 MODULE_LICENSE("GPL"); 740