1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright 2020 Google Inc 4 * Copyright 2025 Linaro Ltd. 5 * 6 * Core driver for Maxim MAX77759 companion PMIC for USB Type-C 7 */ 8 9 #include <linux/array_size.h> 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/cleanup.h> 13 #include <linux/completion.h> 14 #include <linux/dev_printk.h> 15 #include <linux/device.h> 16 #include <linux/err.h> 17 #include <linux/i2c.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/jiffies.h> 22 #include <linux/mfd/core.h> 23 #include <linux/mfd/max77759.h> 24 #include <linux/mod_devicetable.h> 25 #include <linux/module.h> 26 #include <linux/mutex.h> 27 #include <linux/of.h> 28 #include <linux/overflow.h> 29 #include <linux/regmap.h> 30 31 /* Chip ID as per MAX77759_PMIC_REG_PMIC_ID */ 32 enum { 33 MAX77759_CHIP_ID = 59, 34 }; 35 36 enum max77759_i2c_subdev_id { 37 /* 38 * These are arbitrary and simply used to match struct 39 * max77759_i2c_subdev entries to the regmap pointers in struct 40 * max77759 during probe(). 41 */ 42 MAX77759_I2C_SUBDEV_ID_MAXQ, 43 MAX77759_I2C_SUBDEV_ID_CHARGER, 44 }; 45 46 struct max77759_i2c_subdev { 47 enum max77759_i2c_subdev_id id; 48 const struct regmap_config *cfg; 49 u16 i2c_address; 50 }; 51 52 static const struct regmap_range max77759_top_registers[] = { 53 regmap_reg_range(0x00, 0x02), /* PMIC_ID / PMIC_REVISION / OTP_REVISION */ 54 regmap_reg_range(0x22, 0x24), /* INTSRC / INTSRCMASK / TOPSYS_INT */ 55 regmap_reg_range(0x26, 0x26), /* TOPSYS_INT_MASK */ 56 regmap_reg_range(0x40, 0x40), /* I2C_CNFG */ 57 regmap_reg_range(0x50, 0x51), /* SWRESET / CONTROL_FG */ 58 }; 59 60 static const struct regmap_range max77759_top_ro_registers[] = { 61 regmap_reg_range(0x00, 0x02), 62 regmap_reg_range(0x22, 0x22), 63 }; 64 65 static const struct regmap_range max77759_top_volatile_registers[] = { 66 regmap_reg_range(0x22, 0x22), 67 regmap_reg_range(0x24, 0x24), 68 }; 69 70 static const struct regmap_access_table max77759_top_wr_table = { 71 .yes_ranges = max77759_top_registers, 72 .n_yes_ranges = ARRAY_SIZE(max77759_top_registers), 73 .no_ranges = max77759_top_ro_registers, 74 .n_no_ranges = ARRAY_SIZE(max77759_top_ro_registers), 75 }; 76 77 static const struct regmap_access_table max77759_top_rd_table = { 78 .yes_ranges = max77759_top_registers, 79 .n_yes_ranges = ARRAY_SIZE(max77759_top_registers), 80 }; 81 82 static const struct regmap_access_table max77759_top_volatile_table = { 83 .yes_ranges = max77759_top_volatile_registers, 84 .n_yes_ranges = ARRAY_SIZE(max77759_top_volatile_registers), 85 }; 86 87 static const struct regmap_config max77759_regmap_config_top = { 88 .name = "top", 89 .reg_bits = 8, 90 .val_bits = 8, 91 .max_register = MAX77759_PMIC_REG_CONTROL_FG, 92 .wr_table = &max77759_top_wr_table, 93 .rd_table = &max77759_top_rd_table, 94 .volatile_table = &max77759_top_volatile_table, 95 .num_reg_defaults_raw = MAX77759_PMIC_REG_CONTROL_FG + 1, 96 .cache_type = REGCACHE_FLAT, 97 }; 98 99 static const struct regmap_range max77759_maxq_registers[] = { 100 regmap_reg_range(0x60, 0x73), /* Device ID, Rev, INTx, STATUSx, MASKx */ 101 regmap_reg_range(0x81, 0xa1), /* AP_DATAOUTx */ 102 regmap_reg_range(0xb1, 0xd1), /* AP_DATAINx */ 103 regmap_reg_range(0xe0, 0xe0), /* UIC_SWRST */ 104 }; 105 106 static const struct regmap_range max77759_maxq_ro_registers[] = { 107 regmap_reg_range(0x60, 0x63), /* Device ID, Rev */ 108 regmap_reg_range(0x68, 0x6f), /* STATUSx */ 109 regmap_reg_range(0xb1, 0xd1), 110 }; 111 112 static const struct regmap_range max77759_maxq_volatile_registers[] = { 113 regmap_reg_range(0x64, 0x6f), /* INTx, STATUSx */ 114 regmap_reg_range(0xb1, 0xd1), 115 regmap_reg_range(0xe0, 0xe0), 116 }; 117 118 static const struct regmap_access_table max77759_maxq_wr_table = { 119 .yes_ranges = max77759_maxq_registers, 120 .n_yes_ranges = ARRAY_SIZE(max77759_maxq_registers), 121 .no_ranges = max77759_maxq_ro_registers, 122 .n_no_ranges = ARRAY_SIZE(max77759_maxq_ro_registers), 123 }; 124 125 static const struct regmap_access_table max77759_maxq_rd_table = { 126 .yes_ranges = max77759_maxq_registers, 127 .n_yes_ranges = ARRAY_SIZE(max77759_maxq_registers), 128 }; 129 130 static const struct regmap_access_table max77759_maxq_volatile_table = { 131 .yes_ranges = max77759_maxq_volatile_registers, 132 .n_yes_ranges = ARRAY_SIZE(max77759_maxq_volatile_registers), 133 }; 134 135 static const struct regmap_config max77759_regmap_config_maxq = { 136 .name = "maxq", 137 .reg_bits = 8, 138 .val_bits = 8, 139 .max_register = MAX77759_MAXQ_REG_UIC_SWRST, 140 .wr_table = &max77759_maxq_wr_table, 141 .rd_table = &max77759_maxq_rd_table, 142 .volatile_table = &max77759_maxq_volatile_table, 143 .num_reg_defaults_raw = MAX77759_MAXQ_REG_UIC_SWRST + 1, 144 .cache_type = REGCACHE_FLAT, 145 }; 146 147 static const struct regmap_range max77759_charger_registers[] = { 148 regmap_reg_range(0xb0, 0xcc), 149 }; 150 151 static const struct regmap_range max77759_charger_ro_registers[] = { 152 regmap_reg_range(0xb4, 0xb8), /* INT_OK, DETAILS_0x */ 153 }; 154 155 static const struct regmap_range max77759_charger_volatile_registers[] = { 156 regmap_reg_range(0xb0, 0xb1), /* INTx */ 157 regmap_reg_range(0xb4, 0xb8), 158 }; 159 160 static const struct regmap_access_table max77759_charger_wr_table = { 161 .yes_ranges = max77759_charger_registers, 162 .n_yes_ranges = ARRAY_SIZE(max77759_charger_registers), 163 .no_ranges = max77759_charger_ro_registers, 164 .n_no_ranges = ARRAY_SIZE(max77759_charger_ro_registers), 165 }; 166 167 static const struct regmap_access_table max77759_charger_rd_table = { 168 .yes_ranges = max77759_charger_registers, 169 .n_yes_ranges = ARRAY_SIZE(max77759_charger_registers), 170 }; 171 172 static const struct regmap_access_table max77759_charger_volatile_table = { 173 .yes_ranges = max77759_charger_volatile_registers, 174 .n_yes_ranges = ARRAY_SIZE(max77759_charger_volatile_registers), 175 }; 176 177 static const struct regmap_config max77759_regmap_config_charger = { 178 .name = "charger", 179 .reg_bits = 8, 180 .val_bits = 8, 181 .max_register = MAX77759_CHGR_REG_CHG_CNFG_19, 182 .wr_table = &max77759_charger_wr_table, 183 .rd_table = &max77759_charger_rd_table, 184 .volatile_table = &max77759_charger_volatile_table, 185 .num_reg_defaults_raw = MAX77759_CHGR_REG_CHG_CNFG_19 + 1, 186 .cache_type = REGCACHE_FLAT, 187 }; 188 189 /* 190 * Interrupts - with the following interrupt hierarchy: 191 * pmic IRQs (INTSRC) 192 * - MAXQ_INT: MaxQ IRQs 193 * - UIC_INT1 194 * - APCmdResI 195 * - SysMsgI 196 * - GPIOxI 197 * - TOPSYS_INT: topsys 198 * - TOPSYS_INT 199 * - TSHDN_INT 200 * - SYSOVLO_INT 201 * - SYSUVLO_INT 202 * - FSHIP_NOT_RD 203 * - CHGR_INT: charger 204 * - INT1 205 * - AICL 206 * - CHGIN 207 * - WCIN 208 * - CHG 209 * - BAT 210 * - INLIM 211 * - THM2 212 * - BYP 213 * - INT2 214 * - INSEL 215 * - SYS_UVLO1 216 * - SYS_UVLO2 217 * - BAT_OILO 218 * - CHG_STA_CC 219 * - CHG_STA_CV 220 * - CHG_STA_TO 221 * - CHG_STA_DONE 222 */ 223 enum { 224 MAX77759_INT_MAXQ, 225 MAX77759_INT_TOPSYS, 226 MAX77759_INT_CHGR, 227 }; 228 229 enum { 230 MAX77759_TOPSYS_INT_TSHDN, 231 MAX77759_TOPSYS_INT_SYSOVLO, 232 MAX77759_TOPSYS_INT_SYSUVLO, 233 MAX77759_TOPSYS_INT_FSHIP_NOT_RD, 234 }; 235 236 enum { 237 MAX77759_MAXQ_INT_APCMDRESI, 238 MAX77759_MAXQ_INT_SYSMSGI, 239 MAX77759_MAXQ_INT_GPIO, 240 MAX77759_MAXQ_INT_UIC1, 241 MAX77759_MAXQ_INT_UIC2, 242 MAX77759_MAXQ_INT_UIC3, 243 MAX77759_MAXQ_INT_UIC4, 244 }; 245 246 enum { 247 MAX77759_CHGR_INT1_AICL, 248 MAX77759_CHGR_INT1_CHGIN, 249 MAX77759_CHGR_INT1_WCIN, 250 MAX77759_CHGR_INT1_CHG, 251 MAX77759_CHGR_INT1_BAT, 252 MAX77759_CHGR_INT1_INLIM, 253 MAX77759_CHGR_INT1_THM2, 254 MAX77759_CHGR_INT1_BYP, 255 MAX77759_CHGR_INT2_INSEL, 256 MAX77759_CHGR_INT2_SYS_UVLO1, 257 MAX77759_CHGR_INT2_SYS_UVLO2, 258 MAX77759_CHGR_INT2_BAT_OILO, 259 MAX77759_CHGR_INT2_CHG_STA_CC, 260 MAX77759_CHGR_INT2_CHG_STA_CV, 261 MAX77759_CHGR_INT2_CHG_STA_TO, 262 MAX77759_CHGR_INT2_CHG_STA_DONE, 263 }; 264 265 static const struct regmap_irq max77759_pmic_irqs[] = { 266 REGMAP_IRQ_REG(MAX77759_INT_MAXQ, 0, MAX77759_PMIC_REG_INTSRC_MAXQ), 267 REGMAP_IRQ_REG(MAX77759_INT_TOPSYS, 0, MAX77759_PMIC_REG_INTSRC_TOPSYS), 268 REGMAP_IRQ_REG(MAX77759_INT_CHGR, 0, MAX77759_PMIC_REG_INTSRC_CHGR), 269 }; 270 271 static const struct regmap_irq max77759_maxq_irqs[] = { 272 REGMAP_IRQ_REG(MAX77759_MAXQ_INT_APCMDRESI, 0, MAX77759_MAXQ_REG_UIC_INT1_APCMDRESI), 273 REGMAP_IRQ_REG(MAX77759_MAXQ_INT_SYSMSGI, 0, MAX77759_MAXQ_REG_UIC_INT1_SYSMSGI), 274 REGMAP_IRQ_REG(MAX77759_MAXQ_INT_GPIO, 0, GENMASK(1, 0)), 275 REGMAP_IRQ_REG(MAX77759_MAXQ_INT_UIC1, 0, GENMASK(5, 2)), 276 REGMAP_IRQ_REG(MAX77759_MAXQ_INT_UIC2, 1, GENMASK(7, 0)), 277 REGMAP_IRQ_REG(MAX77759_MAXQ_INT_UIC3, 2, GENMASK(7, 0)), 278 REGMAP_IRQ_REG(MAX77759_MAXQ_INT_UIC4, 3, GENMASK(7, 0)), 279 }; 280 281 static const struct regmap_irq max77759_topsys_irqs[] = { 282 REGMAP_IRQ_REG(MAX77759_TOPSYS_INT_TSHDN, 0, MAX77759_PMIC_REG_TOPSYS_INT_TSHDN), 283 REGMAP_IRQ_REG(MAX77759_TOPSYS_INT_SYSOVLO, 0, MAX77759_PMIC_REG_TOPSYS_INT_SYSOVLO), 284 REGMAP_IRQ_REG(MAX77759_TOPSYS_INT_SYSUVLO, 0, MAX77759_PMIC_REG_TOPSYS_INT_SYSUVLO), 285 REGMAP_IRQ_REG(MAX77759_TOPSYS_INT_FSHIP_NOT_RD, 0, MAX77759_PMIC_REG_TOPSYS_INT_FSHIP), 286 }; 287 288 static const struct regmap_irq max77759_chgr_irqs[] = { 289 REGMAP_IRQ_REG(MAX77759_CHGR_INT1_AICL, 0, 290 MAX77759_CHGR_REG_CHG_INT_AICL), 291 REGMAP_IRQ_REG(MAX77759_CHGR_INT1_CHGIN, 0, 292 MAX77759_CHGR_REG_CHG_INT_CHGIN), 293 REGMAP_IRQ_REG(MAX77759_CHGR_INT1_WCIN, 0, 294 MAX77759_CHGR_REG_CHG_INT_WCIN), 295 REGMAP_IRQ_REG(MAX77759_CHGR_INT1_CHG, 0, 296 MAX77759_CHGR_REG_CHG_INT_CHG), 297 REGMAP_IRQ_REG(MAX77759_CHGR_INT1_BAT, 0, 298 MAX77759_CHGR_REG_CHG_INT_BAT), 299 REGMAP_IRQ_REG(MAX77759_CHGR_INT1_INLIM, 0, 300 MAX77759_CHGR_REG_CHG_INT_INLIM), 301 REGMAP_IRQ_REG(MAX77759_CHGR_INT1_THM2, 0, 302 MAX77759_CHGR_REG_CHG_INT_THM2), 303 REGMAP_IRQ_REG(MAX77759_CHGR_INT1_BYP, 0, 304 MAX77759_CHGR_REG_CHG_INT_BYP), 305 REGMAP_IRQ_REG(MAX77759_CHGR_INT2_INSEL, 1, 306 MAX77759_CHGR_REG_CHG_INT2_INSEL), 307 REGMAP_IRQ_REG(MAX77759_CHGR_INT2_SYS_UVLO1, 1, 308 MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO1), 309 REGMAP_IRQ_REG(MAX77759_CHGR_INT2_SYS_UVLO2, 1, 310 MAX77759_CHGR_REG_CHG_INT2_SYS_UVLO2), 311 REGMAP_IRQ_REG(MAX77759_CHGR_INT2_BAT_OILO, 1, 312 MAX77759_CHGR_REG_CHG_INT2_BAT_OILO), 313 REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_CC, 1, 314 MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CC), 315 REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_CV, 1, 316 MAX77759_CHGR_REG_CHG_INT2_CHG_STA_CV), 317 REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_TO, 1, 318 MAX77759_CHGR_REG_CHG_INT2_CHG_STA_TO), 319 REGMAP_IRQ_REG(MAX77759_CHGR_INT2_CHG_STA_DONE, 1, 320 MAX77759_CHGR_REG_CHG_INT2_CHG_STA_DONE), 321 }; 322 323 static const struct regmap_irq_chip max77759_pmic_irq_chip = { 324 .name = "max77759-pmic", 325 /* INTSRC is read-only and doesn't require clearing */ 326 .status_base = MAX77759_PMIC_REG_INTSRC, 327 .mask_base = MAX77759_PMIC_REG_INTSRCMASK, 328 .num_regs = 1, 329 .irqs = max77759_pmic_irqs, 330 .num_irqs = ARRAY_SIZE(max77759_pmic_irqs), 331 }; 332 333 /* 334 * We can let regmap-irq auto-ack the topsys interrupt bits as required, but 335 * for all others the individual drivers need to know which interrupt bit 336 * exactly is set inside their interrupt handlers, and therefore we can not set 337 * .ack_base for those. 338 */ 339 static const struct regmap_irq_chip max77759_maxq_irq_chip = { 340 .name = "max77759-maxq", 341 .domain_suffix = "MAXQ", 342 .status_base = MAX77759_MAXQ_REG_UIC_INT1, 343 .mask_base = MAX77759_MAXQ_REG_UIC_INT1_M, 344 .num_regs = 4, 345 .irqs = max77759_maxq_irqs, 346 .num_irqs = ARRAY_SIZE(max77759_maxq_irqs), 347 }; 348 349 static const struct regmap_irq_chip max77759_topsys_irq_chip = { 350 .name = "max77759-topsys", 351 .domain_suffix = "TOPSYS", 352 .status_base = MAX77759_PMIC_REG_TOPSYS_INT, 353 .mask_base = MAX77759_PMIC_REG_TOPSYS_INT_MASK, 354 .ack_base = MAX77759_PMIC_REG_TOPSYS_INT, 355 .num_regs = 1, 356 .irqs = max77759_topsys_irqs, 357 .num_irqs = ARRAY_SIZE(max77759_topsys_irqs), 358 }; 359 360 static const struct regmap_irq_chip max77759_chgr_irq_chip = { 361 .name = "max77759-chgr", 362 .domain_suffix = "CHGR", 363 .status_base = MAX77759_CHGR_REG_CHG_INT, 364 .mask_base = MAX77759_CHGR_REG_CHG_INT_MASK, 365 .ack_base = MAX77759_CHGR_REG_CHG_INT, 366 .num_regs = 2, 367 .irqs = max77759_chgr_irqs, 368 .num_irqs = ARRAY_SIZE(max77759_chgr_irqs), 369 }; 370 371 static const struct max77759_i2c_subdev max77759_i2c_subdevs[] = { 372 { 373 .id = MAX77759_I2C_SUBDEV_ID_MAXQ, 374 .cfg = &max77759_regmap_config_maxq, 375 /* I2C address is same as for sub-block 'top' */ 376 }, 377 { 378 .id = MAX77759_I2C_SUBDEV_ID_CHARGER, 379 .cfg = &max77759_regmap_config_charger, 380 .i2c_address = 0x69, 381 }, 382 }; 383 384 static const struct resource max77759_gpio_resources[] = { 385 DEFINE_RES_IRQ_NAMED(MAX77759_MAXQ_INT_GPIO, "GPI"), 386 }; 387 388 static const struct resource max77759_charger_resources[] = { 389 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_AICL, "AICL"), 390 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_CHGIN, "CHGIN"), 391 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_WCIN, "WCIN"), 392 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_CHG, "CHG"), 393 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_BAT, "BAT"), 394 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_INLIM, "INLIM"), 395 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_THM2, "THM2"), 396 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT1_BYP, "BYP"), 397 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_INSEL, "INSEL"), 398 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_SYS_UVLO1, "SYS_UVLO1"), 399 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_SYS_UVLO2, "SYS_UVLO2"), 400 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_BAT_OILO, "BAT_OILO"), 401 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_CHG_STA_CC, "CHG_STA_CC"), 402 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_CHG_STA_CV, "CHG_STA_CV"), 403 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_CHG_STA_TO, "CHG_STA_TO"), 404 DEFINE_RES_IRQ_NAMED(MAX77759_CHGR_INT2_CHG_STA_DONE, "CHG_STA_DONE"), 405 }; 406 407 static const struct mfd_cell max77759_cells[] = { 408 MFD_CELL_OF("max77759-nvmem", NULL, NULL, 0, 0, 409 "maxim,max77759-nvmem"), 410 }; 411 412 static const struct mfd_cell max77759_maxq_cells[] = { 413 MFD_CELL_OF("max77759-gpio", max77759_gpio_resources, NULL, 0, 0, 414 "maxim,max77759-gpio"), 415 }; 416 417 static const struct mfd_cell max77759_charger_cells[] = { 418 MFD_CELL_RES("max77759-charger", max77759_charger_resources), 419 }; 420 421 int max77759_maxq_command(struct max77759 *max77759, 422 const struct max77759_maxq_command *cmd, 423 struct max77759_maxq_response *rsp) 424 { 425 DEFINE_FLEX(struct max77759_maxq_response, _rsp, rsp, length, 1); 426 struct device *dev = regmap_get_device(max77759->regmap_maxq); 427 static const unsigned int timeout_ms = 200; 428 int ret; 429 430 if (cmd->length > MAX77759_MAXQ_OPCODE_MAXLENGTH) 431 return -EINVAL; 432 433 /* 434 * As a convenience for API users when issuing simple commands, rsp is 435 * allowed to be NULL. In that case we need a temporary here to write 436 * the response to, as we need to verify that the command was indeed 437 * completed correctly. 438 */ 439 if (!rsp) 440 rsp = _rsp; 441 442 if (!rsp->length || rsp->length > MAX77759_MAXQ_OPCODE_MAXLENGTH) 443 return -EINVAL; 444 445 guard(mutex)(&max77759->maxq_lock); 446 447 reinit_completion(&max77759->cmd_done); 448 449 /* 450 * MaxQ latches the message when the DATAOUT32 register is written. If 451 * cmd->length is shorter we still need to write 0 to it. 452 */ 453 ret = regmap_bulk_write(max77759->regmap_maxq, 454 MAX77759_MAXQ_REG_AP_DATAOUT0, cmd->cmd, 455 cmd->length); 456 if (!ret && cmd->length < MAX77759_MAXQ_OPCODE_MAXLENGTH) 457 ret = regmap_write(max77759->regmap_maxq, 458 MAX77759_MAXQ_REG_AP_DATAOUT32, 0); 459 if (ret) { 460 dev_err(dev, "writing command failed: %d\n", ret); 461 return ret; 462 } 463 464 /* Wait for response from MaxQ */ 465 if (!wait_for_completion_timeout(&max77759->cmd_done, 466 msecs_to_jiffies(timeout_ms))) { 467 dev_err(dev, "timed out waiting for response\n"); 468 return -ETIMEDOUT; 469 } 470 471 ret = regmap_bulk_read(max77759->regmap_maxq, 472 MAX77759_MAXQ_REG_AP_DATAIN0, 473 rsp->rsp, rsp->length); 474 if (ret) { 475 dev_err(dev, "reading response failed: %d\n", ret); 476 return ret; 477 } 478 479 /* 480 * As per the protocol, the first byte of the reply will match the 481 * request. 482 */ 483 if (cmd->cmd[0] != rsp->rsp[0]) { 484 dev_err(dev, "unexpected opcode response for %#.2x: %*ph\n", 485 cmd->cmd[0], (int)rsp->length, rsp->rsp); 486 return -EIO; 487 } 488 489 return 0; 490 } 491 EXPORT_SYMBOL_GPL(max77759_maxq_command); 492 493 static irqreturn_t apcmdres_irq_handler(int irq, void *irq_data) 494 { 495 struct max77759 *max77759 = irq_data; 496 497 regmap_write(max77759->regmap_maxq, MAX77759_MAXQ_REG_UIC_INT1, 498 MAX77759_MAXQ_REG_UIC_INT1_APCMDRESI); 499 500 complete(&max77759->cmd_done); 501 502 return IRQ_HANDLED; 503 } 504 505 static int max77759_create_i2c_subdev(struct i2c_client *client, 506 struct max77759 *max77759, 507 const struct max77759_i2c_subdev *sd) 508 { 509 struct i2c_client *sub; 510 struct regmap *regmap; 511 int ret; 512 513 /* 514 * If 'sd' has an I2C address, 'sub' will be assigned a new 'dummy' 515 * device, otherwise use it as-is. 516 */ 517 sub = client; 518 if (sd->i2c_address) { 519 sub = devm_i2c_new_dummy_device(&client->dev, 520 client->adapter, 521 sd->i2c_address); 522 523 if (IS_ERR(sub)) 524 return dev_err_probe(&client->dev, PTR_ERR(sub), 525 "failed to claim I2C device %s\n", 526 sd->cfg->name); 527 } 528 529 regmap = devm_regmap_init_i2c(sub, sd->cfg); 530 if (IS_ERR(regmap)) 531 return dev_err_probe(&sub->dev, PTR_ERR(regmap), 532 "regmap init for '%s' failed\n", 533 sd->cfg->name); 534 535 ret = regmap_attach_dev(&client->dev, regmap, sd->cfg); 536 if (ret) 537 return dev_err_probe(&client->dev, ret, 538 "regmap attach of '%s' failed\n", 539 sd->cfg->name); 540 541 if (sd->id == MAX77759_I2C_SUBDEV_ID_MAXQ) 542 max77759->regmap_maxq = regmap; 543 else if (sd->id == MAX77759_I2C_SUBDEV_ID_CHARGER) 544 max77759->regmap_charger = regmap; 545 546 return 0; 547 } 548 549 static int max77759_add_chained_irq_chip(struct device *dev, 550 struct regmap *regmap, 551 int pirq, 552 struct regmap_irq_chip_data *parent, 553 const struct regmap_irq_chip *chip, 554 struct regmap_irq_chip_data **data) 555 { 556 int irq, ret; 557 558 irq = regmap_irq_get_virq(parent, pirq); 559 if (irq < 0) 560 return dev_err_probe(dev, irq, 561 "failed to get parent vIRQ(%d) for chip %s\n", 562 pirq, chip->name); 563 564 ret = devm_regmap_add_irq_chip(dev, regmap, irq, 565 IRQF_ONESHOT | IRQF_SHARED, 0, chip, 566 data); 567 if (ret) 568 return dev_err_probe(dev, ret, "failed to add %s IRQ chip\n", 569 chip->name); 570 571 return 0; 572 } 573 574 static int max77759_add_chained_maxq(struct i2c_client *client, 575 struct max77759 *max77759, 576 struct regmap_irq_chip_data *parent) 577 { 578 struct regmap_irq_chip_data *irq_chip_data; 579 int apcmdres_irq; 580 int ret; 581 582 ret = max77759_add_chained_irq_chip(&client->dev, 583 max77759->regmap_maxq, 584 MAX77759_INT_MAXQ, 585 parent, 586 &max77759_maxq_irq_chip, 587 &irq_chip_data); 588 if (ret) 589 return ret; 590 591 init_completion(&max77759->cmd_done); 592 apcmdres_irq = regmap_irq_get_virq(irq_chip_data, 593 MAX77759_MAXQ_INT_APCMDRESI); 594 595 ret = devm_request_threaded_irq(&client->dev, apcmdres_irq, 596 NULL, apcmdres_irq_handler, 597 IRQF_ONESHOT | IRQF_SHARED, 598 dev_name(&client->dev), max77759); 599 if (ret) 600 return dev_err_probe(&client->dev, ret, 601 "MAX77759_MAXQ_INT_APCMDRESI failed\n"); 602 603 ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO, 604 max77759_maxq_cells, 605 ARRAY_SIZE(max77759_maxq_cells), 606 NULL, 0, 607 regmap_irq_get_domain(irq_chip_data)); 608 if (ret) 609 return dev_err_probe(&client->dev, ret, 610 "failed to add child devices (MaxQ)\n"); 611 612 return 0; 613 } 614 615 static int max77759_add_chained_topsys(struct i2c_client *client, 616 struct max77759 *max77759, 617 struct regmap_irq_chip_data *parent) 618 { 619 struct regmap_irq_chip_data *irq_chip_data; 620 int ret; 621 622 ret = max77759_add_chained_irq_chip(&client->dev, 623 max77759->regmap_top, 624 MAX77759_INT_TOPSYS, 625 parent, 626 &max77759_topsys_irq_chip, 627 &irq_chip_data); 628 if (ret) 629 return ret; 630 631 return 0; 632 } 633 634 static int max77759_add_chained_charger(struct i2c_client *client, 635 struct max77759 *max77759, 636 struct regmap_irq_chip_data *parent) 637 { 638 struct regmap_irq_chip_data *irq_chip_data; 639 int ret; 640 641 ret = max77759_add_chained_irq_chip(&client->dev, 642 max77759->regmap_charger, 643 MAX77759_INT_CHGR, 644 parent, 645 &max77759_chgr_irq_chip, 646 &irq_chip_data); 647 if (ret) 648 return ret; 649 650 ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO, 651 max77759_charger_cells, 652 ARRAY_SIZE(max77759_charger_cells), 653 NULL, 0, 654 regmap_irq_get_domain(irq_chip_data)); 655 if (ret) 656 return dev_err_probe(&client->dev, ret, 657 "failed to add child devices (charger)\n"); 658 659 return 0; 660 } 661 662 static int max77759_probe(struct i2c_client *client) 663 { 664 struct regmap_irq_chip_data *irq_chip_data_pmic; 665 struct max77759 *max77759; 666 unsigned int pmic_id; 667 int ret; 668 669 max77759 = devm_kzalloc(&client->dev, sizeof(*max77759), GFP_KERNEL); 670 if (!max77759) 671 return -ENOMEM; 672 673 i2c_set_clientdata(client, max77759); 674 675 max77759->regmap_top = devm_regmap_init_i2c(client, 676 &max77759_regmap_config_top); 677 if (IS_ERR(max77759->regmap_top)) 678 return dev_err_probe(&client->dev, PTR_ERR(max77759->regmap_top), 679 "regmap init for '%s' failed\n", 680 max77759_regmap_config_top.name); 681 682 ret = regmap_read(max77759->regmap_top, 683 MAX77759_PMIC_REG_PMIC_ID, &pmic_id); 684 if (ret) 685 return dev_err_probe(&client->dev, ret, 686 "unable to read device ID\n"); 687 688 if (pmic_id != MAX77759_CHIP_ID) 689 return dev_err_probe(&client->dev, -ENODEV, 690 "unsupported device ID %#.2x (%d)\n", 691 pmic_id, pmic_id); 692 693 ret = devm_mutex_init(&client->dev, &max77759->maxq_lock); 694 if (ret) 695 return ret; 696 697 for (int i = 0; i < ARRAY_SIZE(max77759_i2c_subdevs); i++) { 698 ret = max77759_create_i2c_subdev(client, max77759, 699 &max77759_i2c_subdevs[i]); 700 if (ret) 701 return ret; 702 } 703 704 ret = devm_regmap_add_irq_chip(&client->dev, max77759->regmap_top, 705 client->irq, IRQF_ONESHOT | IRQF_SHARED, 0, 706 &max77759_pmic_irq_chip, 707 &irq_chip_data_pmic); 708 if (ret) 709 return dev_err_probe(&client->dev, ret, 710 "failed to add IRQ chip '%s'\n", 711 max77759_pmic_irq_chip.name); 712 713 ret = max77759_add_chained_maxq(client, max77759, irq_chip_data_pmic); 714 if (ret) 715 return ret; 716 717 ret = max77759_add_chained_topsys(client, max77759, irq_chip_data_pmic); 718 if (ret) 719 return ret; 720 721 ret = max77759_add_chained_charger(client, max77759, irq_chip_data_pmic); 722 if (ret) 723 return ret; 724 725 return devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO, 726 max77759_cells, ARRAY_SIZE(max77759_cells), 727 NULL, 0, 728 regmap_irq_get_domain(irq_chip_data_pmic)); 729 } 730 731 static const struct i2c_device_id max77759_i2c_id[] = { 732 { "max77759" }, 733 { } 734 }; 735 MODULE_DEVICE_TABLE(i2c, max77759_i2c_id); 736 737 static const struct of_device_id max77759_of_id[] = { 738 { .compatible = "maxim,max77759", }, 739 { } 740 }; 741 MODULE_DEVICE_TABLE(of, max77759_of_id); 742 743 static struct i2c_driver max77759_i2c_driver = { 744 .driver = { 745 .name = "max77759", 746 .of_match_table = max77759_of_id, 747 }, 748 .probe = max77759_probe, 749 .id_table = max77759_i2c_id, 750 }; 751 module_i2c_driver(max77759_i2c_driver); 752 753 MODULE_AUTHOR("André Draszik <andre.draszik@linaro.org>"); 754 MODULE_DESCRIPTION("Maxim MAX77759 core driver"); 755 MODULE_LICENSE("GPL"); 756