1 /* 2 * lpc_ich.c - LPC interface for Intel ICH 3 * 4 * LPC bridge function of the Intel ICH contains many other 5 * functional units, such as Interrupt controllers, Timers, 6 * Power Management, System Management, GPIO, RTC, and LPC 7 * Configuration Registers. 8 * 9 * This driver is derived from lpc_sch. 10 11 * Copyright (c) 2011 Extreme Engineering Solution, Inc. 12 * Author: Aaron Sierra <asierra@xes-inc.com> 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License 2 as published 16 * by the Free Software Foundation. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; see the file COPYING. If not, write to 25 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 26 * 27 * This driver supports the following I/O Controller hubs: 28 * (See the intel documentation on http://developer.intel.com.) 29 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO) 30 * document number 290687-002, 298242-027: 82801BA (ICH2) 31 * document number 290733-003, 290739-013: 82801CA (ICH3-S) 32 * document number 290716-001, 290718-007: 82801CAM (ICH3-M) 33 * document number 290744-001, 290745-025: 82801DB (ICH4) 34 * document number 252337-001, 252663-008: 82801DBM (ICH4-M) 35 * document number 273599-001, 273645-002: 82801E (C-ICH) 36 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R) 37 * document number 300641-004, 300884-013: 6300ESB 38 * document number 301473-002, 301474-026: 82801F (ICH6) 39 * document number 313082-001, 313075-006: 631xESB, 632xESB 40 * document number 307013-003, 307014-024: 82801G (ICH7) 41 * document number 322896-001, 322897-001: NM10 42 * document number 313056-003, 313057-017: 82801H (ICH8) 43 * document number 316972-004, 316973-012: 82801I (ICH9) 44 * document number 319973-002, 319974-002: 82801J (ICH10) 45 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH) 46 * document number 320066-003, 320257-008: EP80597 (IICH) 47 * document number 324645-001, 324646-001: Cougar Point (CPT) 48 * document number TBD : Patsburg (PBG) 49 * document number TBD : DH89xxCC 50 * document number TBD : Panther Point 51 * document number TBD : Lynx Point 52 * document number TBD : Lynx Point-LP 53 * document number TBD : Wellsburg 54 * document number TBD : Avoton SoC 55 * document number TBD : Coleto Creek 56 * document number TBD : Wildcat Point-LP 57 * document number TBD : 9 Series 58 * document number TBD : Lewisburg 59 * document number TBD : Apollo Lake SoC 60 */ 61 62 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 63 64 #include <linux/kernel.h> 65 #include <linux/module.h> 66 #include <linux/errno.h> 67 #include <linux/acpi.h> 68 #include <linux/pci.h> 69 #include <linux/mfd/core.h> 70 #include <linux/mfd/lpc_ich.h> 71 #include <linux/platform_data/itco_wdt.h> 72 73 #define ACPIBASE 0x40 74 #define ACPIBASE_GPE_OFF 0x28 75 #define ACPIBASE_GPE_END 0x2f 76 #define ACPIBASE_SMI_OFF 0x30 77 #define ACPIBASE_SMI_END 0x33 78 #define ACPIBASE_PMC_OFF 0x08 79 #define ACPIBASE_PMC_END 0x0c 80 #define ACPIBASE_TCO_OFF 0x60 81 #define ACPIBASE_TCO_END 0x7f 82 #define ACPICTRL_PMCBASE 0x44 83 84 #define ACPIBASE_GCS_OFF 0x3410 85 #define ACPIBASE_GCS_END 0x3414 86 87 #define SPIBASE_BYT 0x54 88 #define SPIBASE_BYT_SZ 512 89 #define SPIBASE_BYT_EN BIT(1) 90 91 #define SPIBASE_LPT 0x3800 92 #define SPIBASE_LPT_SZ 512 93 #define BCR 0xdc 94 #define BCR_WPD BIT(0) 95 96 #define SPIBASE_APL_SZ 4096 97 98 #define GPIOBASE_ICH0 0x58 99 #define GPIOCTRL_ICH0 0x5C 100 #define GPIOBASE_ICH6 0x48 101 #define GPIOCTRL_ICH6 0x4C 102 103 #define RCBABASE 0xf0 104 105 #define wdt_io_res(i) wdt_res(0, i) 106 #define wdt_mem_res(i) wdt_res(ICH_RES_MEM_OFF, i) 107 #define wdt_res(b, i) (&wdt_ich_res[(b) + (i)]) 108 109 struct lpc_ich_priv { 110 int chipset; 111 112 int abase; /* ACPI base */ 113 int actrl_pbase; /* ACPI control or PMC base */ 114 int gbase; /* GPIO base */ 115 int gctrl; /* GPIO control */ 116 117 int abase_save; /* Cached ACPI base value */ 118 int actrl_pbase_save; /* Cached ACPI control or PMC base value */ 119 int gctrl_save; /* Cached GPIO control value */ 120 }; 121 122 static struct resource wdt_ich_res[] = { 123 /* ACPI - TCO */ 124 { 125 .flags = IORESOURCE_IO, 126 }, 127 /* ACPI - SMI */ 128 { 129 .flags = IORESOURCE_IO, 130 }, 131 /* GCS or PMC */ 132 { 133 .flags = IORESOURCE_MEM, 134 }, 135 }; 136 137 static struct resource gpio_ich_res[] = { 138 /* GPIO */ 139 { 140 .flags = IORESOURCE_IO, 141 }, 142 /* ACPI - GPE0 */ 143 { 144 .flags = IORESOURCE_IO, 145 }, 146 }; 147 148 static struct resource intel_spi_res[] = { 149 { 150 .flags = IORESOURCE_MEM, 151 } 152 }; 153 154 static struct mfd_cell lpc_ich_wdt_cell = { 155 .name = "iTCO_wdt", 156 .num_resources = ARRAY_SIZE(wdt_ich_res), 157 .resources = wdt_ich_res, 158 .ignore_resource_conflicts = true, 159 }; 160 161 static struct mfd_cell lpc_ich_gpio_cell = { 162 .name = "gpio_ich", 163 .num_resources = ARRAY_SIZE(gpio_ich_res), 164 .resources = gpio_ich_res, 165 .ignore_resource_conflicts = true, 166 }; 167 168 169 static struct mfd_cell lpc_ich_spi_cell = { 170 .name = "intel-spi", 171 .num_resources = ARRAY_SIZE(intel_spi_res), 172 .resources = intel_spi_res, 173 .ignore_resource_conflicts = true, 174 }; 175 176 /* chipset related info */ 177 enum lpc_chipsets { 178 LPC_ICH = 0, /* ICH */ 179 LPC_ICH0, /* ICH0 */ 180 LPC_ICH2, /* ICH2 */ 181 LPC_ICH2M, /* ICH2-M */ 182 LPC_ICH3, /* ICH3-S */ 183 LPC_ICH3M, /* ICH3-M */ 184 LPC_ICH4, /* ICH4 */ 185 LPC_ICH4M, /* ICH4-M */ 186 LPC_CICH, /* C-ICH */ 187 LPC_ICH5, /* ICH5 & ICH5R */ 188 LPC_6300ESB, /* 6300ESB */ 189 LPC_ICH6, /* ICH6 & ICH6R */ 190 LPC_ICH6M, /* ICH6-M */ 191 LPC_ICH6W, /* ICH6W & ICH6RW */ 192 LPC_631XESB, /* 631xESB/632xESB */ 193 LPC_ICH7, /* ICH7 & ICH7R */ 194 LPC_ICH7DH, /* ICH7DH */ 195 LPC_ICH7M, /* ICH7-M & ICH7-U */ 196 LPC_ICH7MDH, /* ICH7-M DH */ 197 LPC_NM10, /* NM10 */ 198 LPC_ICH8, /* ICH8 & ICH8R */ 199 LPC_ICH8DH, /* ICH8DH */ 200 LPC_ICH8DO, /* ICH8DO */ 201 LPC_ICH8M, /* ICH8M */ 202 LPC_ICH8ME, /* ICH8M-E */ 203 LPC_ICH9, /* ICH9 */ 204 LPC_ICH9R, /* ICH9R */ 205 LPC_ICH9DH, /* ICH9DH */ 206 LPC_ICH9DO, /* ICH9DO */ 207 LPC_ICH9M, /* ICH9M */ 208 LPC_ICH9ME, /* ICH9M-E */ 209 LPC_ICH10, /* ICH10 */ 210 LPC_ICH10R, /* ICH10R */ 211 LPC_ICH10D, /* ICH10D */ 212 LPC_ICH10DO, /* ICH10DO */ 213 LPC_PCH, /* PCH Desktop Full Featured */ 214 LPC_PCHM, /* PCH Mobile Full Featured */ 215 LPC_P55, /* P55 */ 216 LPC_PM55, /* PM55 */ 217 LPC_H55, /* H55 */ 218 LPC_QM57, /* QM57 */ 219 LPC_H57, /* H57 */ 220 LPC_HM55, /* HM55 */ 221 LPC_Q57, /* Q57 */ 222 LPC_HM57, /* HM57 */ 223 LPC_PCHMSFF, /* PCH Mobile SFF Full Featured */ 224 LPC_QS57, /* QS57 */ 225 LPC_3400, /* 3400 */ 226 LPC_3420, /* 3420 */ 227 LPC_3450, /* 3450 */ 228 LPC_EP80579, /* EP80579 */ 229 LPC_CPT, /* Cougar Point */ 230 LPC_CPTD, /* Cougar Point Desktop */ 231 LPC_CPTM, /* Cougar Point Mobile */ 232 LPC_PBG, /* Patsburg */ 233 LPC_DH89XXCC, /* DH89xxCC */ 234 LPC_PPT, /* Panther Point */ 235 LPC_LPT, /* Lynx Point */ 236 LPC_LPT_LP, /* Lynx Point-LP */ 237 LPC_WBG, /* Wellsburg */ 238 LPC_AVN, /* Avoton SoC */ 239 LPC_BAYTRAIL, /* Bay Trail SoC */ 240 LPC_COLETO, /* Coleto Creek */ 241 LPC_WPT_LP, /* Wildcat Point-LP */ 242 LPC_BRASWELL, /* Braswell SoC */ 243 LPC_LEWISBURG, /* Lewisburg */ 244 LPC_9S, /* 9 Series */ 245 LPC_APL, /* Apollo Lake SoC */ 246 }; 247 248 static struct lpc_ich_info lpc_chipset_info[] = { 249 [LPC_ICH] = { 250 .name = "ICH", 251 .iTCO_version = 1, 252 }, 253 [LPC_ICH0] = { 254 .name = "ICH0", 255 .iTCO_version = 1, 256 }, 257 [LPC_ICH2] = { 258 .name = "ICH2", 259 .iTCO_version = 1, 260 }, 261 [LPC_ICH2M] = { 262 .name = "ICH2-M", 263 .iTCO_version = 1, 264 }, 265 [LPC_ICH3] = { 266 .name = "ICH3-S", 267 .iTCO_version = 1, 268 }, 269 [LPC_ICH3M] = { 270 .name = "ICH3-M", 271 .iTCO_version = 1, 272 }, 273 [LPC_ICH4] = { 274 .name = "ICH4", 275 .iTCO_version = 1, 276 }, 277 [LPC_ICH4M] = { 278 .name = "ICH4-M", 279 .iTCO_version = 1, 280 }, 281 [LPC_CICH] = { 282 .name = "C-ICH", 283 .iTCO_version = 1, 284 }, 285 [LPC_ICH5] = { 286 .name = "ICH5 or ICH5R", 287 .iTCO_version = 1, 288 }, 289 [LPC_6300ESB] = { 290 .name = "6300ESB", 291 .iTCO_version = 1, 292 }, 293 [LPC_ICH6] = { 294 .name = "ICH6 or ICH6R", 295 .iTCO_version = 2, 296 .gpio_version = ICH_V6_GPIO, 297 }, 298 [LPC_ICH6M] = { 299 .name = "ICH6-M", 300 .iTCO_version = 2, 301 .gpio_version = ICH_V6_GPIO, 302 }, 303 [LPC_ICH6W] = { 304 .name = "ICH6W or ICH6RW", 305 .iTCO_version = 2, 306 .gpio_version = ICH_V6_GPIO, 307 }, 308 [LPC_631XESB] = { 309 .name = "631xESB/632xESB", 310 .iTCO_version = 2, 311 .gpio_version = ICH_V6_GPIO, 312 }, 313 [LPC_ICH7] = { 314 .name = "ICH7 or ICH7R", 315 .iTCO_version = 2, 316 .gpio_version = ICH_V7_GPIO, 317 }, 318 [LPC_ICH7DH] = { 319 .name = "ICH7DH", 320 .iTCO_version = 2, 321 .gpio_version = ICH_V7_GPIO, 322 }, 323 [LPC_ICH7M] = { 324 .name = "ICH7-M or ICH7-U", 325 .iTCO_version = 2, 326 .gpio_version = ICH_V7_GPIO, 327 }, 328 [LPC_ICH7MDH] = { 329 .name = "ICH7-M DH", 330 .iTCO_version = 2, 331 .gpio_version = ICH_V7_GPIO, 332 }, 333 [LPC_NM10] = { 334 .name = "NM10", 335 .iTCO_version = 2, 336 .gpio_version = ICH_V7_GPIO, 337 }, 338 [LPC_ICH8] = { 339 .name = "ICH8 or ICH8R", 340 .iTCO_version = 2, 341 .gpio_version = ICH_V7_GPIO, 342 }, 343 [LPC_ICH8DH] = { 344 .name = "ICH8DH", 345 .iTCO_version = 2, 346 .gpio_version = ICH_V7_GPIO, 347 }, 348 [LPC_ICH8DO] = { 349 .name = "ICH8DO", 350 .iTCO_version = 2, 351 .gpio_version = ICH_V7_GPIO, 352 }, 353 [LPC_ICH8M] = { 354 .name = "ICH8M", 355 .iTCO_version = 2, 356 .gpio_version = ICH_V7_GPIO, 357 }, 358 [LPC_ICH8ME] = { 359 .name = "ICH8M-E", 360 .iTCO_version = 2, 361 .gpio_version = ICH_V7_GPIO, 362 }, 363 [LPC_ICH9] = { 364 .name = "ICH9", 365 .iTCO_version = 2, 366 .gpio_version = ICH_V9_GPIO, 367 }, 368 [LPC_ICH9R] = { 369 .name = "ICH9R", 370 .iTCO_version = 2, 371 .gpio_version = ICH_V9_GPIO, 372 }, 373 [LPC_ICH9DH] = { 374 .name = "ICH9DH", 375 .iTCO_version = 2, 376 .gpio_version = ICH_V9_GPIO, 377 }, 378 [LPC_ICH9DO] = { 379 .name = "ICH9DO", 380 .iTCO_version = 2, 381 .gpio_version = ICH_V9_GPIO, 382 }, 383 [LPC_ICH9M] = { 384 .name = "ICH9M", 385 .iTCO_version = 2, 386 .gpio_version = ICH_V9_GPIO, 387 }, 388 [LPC_ICH9ME] = { 389 .name = "ICH9M-E", 390 .iTCO_version = 2, 391 .gpio_version = ICH_V9_GPIO, 392 }, 393 [LPC_ICH10] = { 394 .name = "ICH10", 395 .iTCO_version = 2, 396 .gpio_version = ICH_V10CONS_GPIO, 397 }, 398 [LPC_ICH10R] = { 399 .name = "ICH10R", 400 .iTCO_version = 2, 401 .gpio_version = ICH_V10CONS_GPIO, 402 }, 403 [LPC_ICH10D] = { 404 .name = "ICH10D", 405 .iTCO_version = 2, 406 .gpio_version = ICH_V10CORP_GPIO, 407 }, 408 [LPC_ICH10DO] = { 409 .name = "ICH10DO", 410 .iTCO_version = 2, 411 .gpio_version = ICH_V10CORP_GPIO, 412 }, 413 [LPC_PCH] = { 414 .name = "PCH Desktop Full Featured", 415 .iTCO_version = 2, 416 .gpio_version = ICH_V5_GPIO, 417 }, 418 [LPC_PCHM] = { 419 .name = "PCH Mobile Full Featured", 420 .iTCO_version = 2, 421 .gpio_version = ICH_V5_GPIO, 422 }, 423 [LPC_P55] = { 424 .name = "P55", 425 .iTCO_version = 2, 426 .gpio_version = ICH_V5_GPIO, 427 }, 428 [LPC_PM55] = { 429 .name = "PM55", 430 .iTCO_version = 2, 431 .gpio_version = ICH_V5_GPIO, 432 }, 433 [LPC_H55] = { 434 .name = "H55", 435 .iTCO_version = 2, 436 .gpio_version = ICH_V5_GPIO, 437 }, 438 [LPC_QM57] = { 439 .name = "QM57", 440 .iTCO_version = 2, 441 .gpio_version = ICH_V5_GPIO, 442 }, 443 [LPC_H57] = { 444 .name = "H57", 445 .iTCO_version = 2, 446 .gpio_version = ICH_V5_GPIO, 447 }, 448 [LPC_HM55] = { 449 .name = "HM55", 450 .iTCO_version = 2, 451 .gpio_version = ICH_V5_GPIO, 452 }, 453 [LPC_Q57] = { 454 .name = "Q57", 455 .iTCO_version = 2, 456 .gpio_version = ICH_V5_GPIO, 457 }, 458 [LPC_HM57] = { 459 .name = "HM57", 460 .iTCO_version = 2, 461 .gpio_version = ICH_V5_GPIO, 462 }, 463 [LPC_PCHMSFF] = { 464 .name = "PCH Mobile SFF Full Featured", 465 .iTCO_version = 2, 466 .gpio_version = ICH_V5_GPIO, 467 }, 468 [LPC_QS57] = { 469 .name = "QS57", 470 .iTCO_version = 2, 471 .gpio_version = ICH_V5_GPIO, 472 }, 473 [LPC_3400] = { 474 .name = "3400", 475 .iTCO_version = 2, 476 .gpio_version = ICH_V5_GPIO, 477 }, 478 [LPC_3420] = { 479 .name = "3420", 480 .iTCO_version = 2, 481 .gpio_version = ICH_V5_GPIO, 482 }, 483 [LPC_3450] = { 484 .name = "3450", 485 .iTCO_version = 2, 486 .gpio_version = ICH_V5_GPIO, 487 }, 488 [LPC_EP80579] = { 489 .name = "EP80579", 490 .iTCO_version = 2, 491 }, 492 [LPC_CPT] = { 493 .name = "Cougar Point", 494 .iTCO_version = 2, 495 .gpio_version = ICH_V5_GPIO, 496 }, 497 [LPC_CPTD] = { 498 .name = "Cougar Point Desktop", 499 .iTCO_version = 2, 500 .gpio_version = ICH_V5_GPIO, 501 }, 502 [LPC_CPTM] = { 503 .name = "Cougar Point Mobile", 504 .iTCO_version = 2, 505 .gpio_version = ICH_V5_GPIO, 506 }, 507 [LPC_PBG] = { 508 .name = "Patsburg", 509 .iTCO_version = 2, 510 }, 511 [LPC_DH89XXCC] = { 512 .name = "DH89xxCC", 513 .iTCO_version = 2, 514 }, 515 [LPC_PPT] = { 516 .name = "Panther Point", 517 .iTCO_version = 2, 518 .gpio_version = ICH_V5_GPIO, 519 }, 520 [LPC_LPT] = { 521 .name = "Lynx Point", 522 .iTCO_version = 2, 523 .gpio_version = ICH_V5_GPIO, 524 .spi_type = INTEL_SPI_LPT, 525 }, 526 [LPC_LPT_LP] = { 527 .name = "Lynx Point_LP", 528 .iTCO_version = 2, 529 .spi_type = INTEL_SPI_LPT, 530 }, 531 [LPC_WBG] = { 532 .name = "Wellsburg", 533 .iTCO_version = 2, 534 }, 535 [LPC_AVN] = { 536 .name = "Avoton SoC", 537 .iTCO_version = 3, 538 .gpio_version = AVOTON_GPIO, 539 }, 540 [LPC_BAYTRAIL] = { 541 .name = "Bay Trail SoC", 542 .iTCO_version = 3, 543 .spi_type = INTEL_SPI_BYT, 544 }, 545 [LPC_COLETO] = { 546 .name = "Coleto Creek", 547 .iTCO_version = 2, 548 }, 549 [LPC_WPT_LP] = { 550 .name = "Wildcat Point_LP", 551 .iTCO_version = 2, 552 .spi_type = INTEL_SPI_LPT, 553 }, 554 [LPC_BRASWELL] = { 555 .name = "Braswell SoC", 556 .iTCO_version = 3, 557 .spi_type = INTEL_SPI_BYT, 558 }, 559 [LPC_LEWISBURG] = { 560 .name = "Lewisburg", 561 .iTCO_version = 2, 562 }, 563 [LPC_9S] = { 564 .name = "9 Series", 565 .iTCO_version = 2, 566 .gpio_version = ICH_V5_GPIO, 567 }, 568 [LPC_APL] = { 569 .name = "Apollo Lake SoC", 570 .spi_type = INTEL_SPI_BXT, 571 }, 572 }; 573 574 /* 575 * This data only exists for exporting the supported PCI ids 576 * via MODULE_DEVICE_TABLE. We do not actually register a 577 * pci_driver, because the I/O Controller Hub has also other 578 * functions that probably will be registered by other drivers. 579 */ 580 static const struct pci_device_id lpc_ich_ids[] = { 581 { PCI_VDEVICE(INTEL, 0x0f1c), LPC_BAYTRAIL}, 582 { PCI_VDEVICE(INTEL, 0x1c41), LPC_CPT}, 583 { PCI_VDEVICE(INTEL, 0x1c42), LPC_CPTD}, 584 { PCI_VDEVICE(INTEL, 0x1c43), LPC_CPTM}, 585 { PCI_VDEVICE(INTEL, 0x1c44), LPC_CPT}, 586 { PCI_VDEVICE(INTEL, 0x1c45), LPC_CPT}, 587 { PCI_VDEVICE(INTEL, 0x1c46), LPC_CPT}, 588 { PCI_VDEVICE(INTEL, 0x1c47), LPC_CPT}, 589 { PCI_VDEVICE(INTEL, 0x1c48), LPC_CPT}, 590 { PCI_VDEVICE(INTEL, 0x1c49), LPC_CPT}, 591 { PCI_VDEVICE(INTEL, 0x1c4a), LPC_CPT}, 592 { PCI_VDEVICE(INTEL, 0x1c4b), LPC_CPT}, 593 { PCI_VDEVICE(INTEL, 0x1c4c), LPC_CPT}, 594 { PCI_VDEVICE(INTEL, 0x1c4d), LPC_CPT}, 595 { PCI_VDEVICE(INTEL, 0x1c4e), LPC_CPT}, 596 { PCI_VDEVICE(INTEL, 0x1c4f), LPC_CPT}, 597 { PCI_VDEVICE(INTEL, 0x1c50), LPC_CPT}, 598 { PCI_VDEVICE(INTEL, 0x1c51), LPC_CPT}, 599 { PCI_VDEVICE(INTEL, 0x1c52), LPC_CPT}, 600 { PCI_VDEVICE(INTEL, 0x1c53), LPC_CPT}, 601 { PCI_VDEVICE(INTEL, 0x1c54), LPC_CPT}, 602 { PCI_VDEVICE(INTEL, 0x1c55), LPC_CPT}, 603 { PCI_VDEVICE(INTEL, 0x1c56), LPC_CPT}, 604 { PCI_VDEVICE(INTEL, 0x1c57), LPC_CPT}, 605 { PCI_VDEVICE(INTEL, 0x1c58), LPC_CPT}, 606 { PCI_VDEVICE(INTEL, 0x1c59), LPC_CPT}, 607 { PCI_VDEVICE(INTEL, 0x1c5a), LPC_CPT}, 608 { PCI_VDEVICE(INTEL, 0x1c5b), LPC_CPT}, 609 { PCI_VDEVICE(INTEL, 0x1c5c), LPC_CPT}, 610 { PCI_VDEVICE(INTEL, 0x1c5d), LPC_CPT}, 611 { PCI_VDEVICE(INTEL, 0x1c5e), LPC_CPT}, 612 { PCI_VDEVICE(INTEL, 0x1c5f), LPC_CPT}, 613 { PCI_VDEVICE(INTEL, 0x1d40), LPC_PBG}, 614 { PCI_VDEVICE(INTEL, 0x1d41), LPC_PBG}, 615 { PCI_VDEVICE(INTEL, 0x1e40), LPC_PPT}, 616 { PCI_VDEVICE(INTEL, 0x1e41), LPC_PPT}, 617 { PCI_VDEVICE(INTEL, 0x1e42), LPC_PPT}, 618 { PCI_VDEVICE(INTEL, 0x1e43), LPC_PPT}, 619 { PCI_VDEVICE(INTEL, 0x1e44), LPC_PPT}, 620 { PCI_VDEVICE(INTEL, 0x1e45), LPC_PPT}, 621 { PCI_VDEVICE(INTEL, 0x1e46), LPC_PPT}, 622 { PCI_VDEVICE(INTEL, 0x1e47), LPC_PPT}, 623 { PCI_VDEVICE(INTEL, 0x1e48), LPC_PPT}, 624 { PCI_VDEVICE(INTEL, 0x1e49), LPC_PPT}, 625 { PCI_VDEVICE(INTEL, 0x1e4a), LPC_PPT}, 626 { PCI_VDEVICE(INTEL, 0x1e4b), LPC_PPT}, 627 { PCI_VDEVICE(INTEL, 0x1e4c), LPC_PPT}, 628 { PCI_VDEVICE(INTEL, 0x1e4d), LPC_PPT}, 629 { PCI_VDEVICE(INTEL, 0x1e4e), LPC_PPT}, 630 { PCI_VDEVICE(INTEL, 0x1e4f), LPC_PPT}, 631 { PCI_VDEVICE(INTEL, 0x1e50), LPC_PPT}, 632 { PCI_VDEVICE(INTEL, 0x1e51), LPC_PPT}, 633 { PCI_VDEVICE(INTEL, 0x1e52), LPC_PPT}, 634 { PCI_VDEVICE(INTEL, 0x1e53), LPC_PPT}, 635 { PCI_VDEVICE(INTEL, 0x1e54), LPC_PPT}, 636 { PCI_VDEVICE(INTEL, 0x1e55), LPC_PPT}, 637 { PCI_VDEVICE(INTEL, 0x1e56), LPC_PPT}, 638 { PCI_VDEVICE(INTEL, 0x1e57), LPC_PPT}, 639 { PCI_VDEVICE(INTEL, 0x1e58), LPC_PPT}, 640 { PCI_VDEVICE(INTEL, 0x1e59), LPC_PPT}, 641 { PCI_VDEVICE(INTEL, 0x1e5a), LPC_PPT}, 642 { PCI_VDEVICE(INTEL, 0x1e5b), LPC_PPT}, 643 { PCI_VDEVICE(INTEL, 0x1e5c), LPC_PPT}, 644 { PCI_VDEVICE(INTEL, 0x1e5d), LPC_PPT}, 645 { PCI_VDEVICE(INTEL, 0x1e5e), LPC_PPT}, 646 { PCI_VDEVICE(INTEL, 0x1e5f), LPC_PPT}, 647 { PCI_VDEVICE(INTEL, 0x1f38), LPC_AVN}, 648 { PCI_VDEVICE(INTEL, 0x1f39), LPC_AVN}, 649 { PCI_VDEVICE(INTEL, 0x1f3a), LPC_AVN}, 650 { PCI_VDEVICE(INTEL, 0x1f3b), LPC_AVN}, 651 { PCI_VDEVICE(INTEL, 0x229c), LPC_BRASWELL}, 652 { PCI_VDEVICE(INTEL, 0x2310), LPC_DH89XXCC}, 653 { PCI_VDEVICE(INTEL, 0x2390), LPC_COLETO}, 654 { PCI_VDEVICE(INTEL, 0x2410), LPC_ICH}, 655 { PCI_VDEVICE(INTEL, 0x2420), LPC_ICH0}, 656 { PCI_VDEVICE(INTEL, 0x2440), LPC_ICH2}, 657 { PCI_VDEVICE(INTEL, 0x244c), LPC_ICH2M}, 658 { PCI_VDEVICE(INTEL, 0x2450), LPC_CICH}, 659 { PCI_VDEVICE(INTEL, 0x2480), LPC_ICH3}, 660 { PCI_VDEVICE(INTEL, 0x248c), LPC_ICH3M}, 661 { PCI_VDEVICE(INTEL, 0x24c0), LPC_ICH4}, 662 { PCI_VDEVICE(INTEL, 0x24cc), LPC_ICH4M}, 663 { PCI_VDEVICE(INTEL, 0x24d0), LPC_ICH5}, 664 { PCI_VDEVICE(INTEL, 0x25a1), LPC_6300ESB}, 665 { PCI_VDEVICE(INTEL, 0x2640), LPC_ICH6}, 666 { PCI_VDEVICE(INTEL, 0x2641), LPC_ICH6M}, 667 { PCI_VDEVICE(INTEL, 0x2642), LPC_ICH6W}, 668 { PCI_VDEVICE(INTEL, 0x2670), LPC_631XESB}, 669 { PCI_VDEVICE(INTEL, 0x2671), LPC_631XESB}, 670 { PCI_VDEVICE(INTEL, 0x2672), LPC_631XESB}, 671 { PCI_VDEVICE(INTEL, 0x2673), LPC_631XESB}, 672 { PCI_VDEVICE(INTEL, 0x2674), LPC_631XESB}, 673 { PCI_VDEVICE(INTEL, 0x2675), LPC_631XESB}, 674 { PCI_VDEVICE(INTEL, 0x2676), LPC_631XESB}, 675 { PCI_VDEVICE(INTEL, 0x2677), LPC_631XESB}, 676 { PCI_VDEVICE(INTEL, 0x2678), LPC_631XESB}, 677 { PCI_VDEVICE(INTEL, 0x2679), LPC_631XESB}, 678 { PCI_VDEVICE(INTEL, 0x267a), LPC_631XESB}, 679 { PCI_VDEVICE(INTEL, 0x267b), LPC_631XESB}, 680 { PCI_VDEVICE(INTEL, 0x267c), LPC_631XESB}, 681 { PCI_VDEVICE(INTEL, 0x267d), LPC_631XESB}, 682 { PCI_VDEVICE(INTEL, 0x267e), LPC_631XESB}, 683 { PCI_VDEVICE(INTEL, 0x267f), LPC_631XESB}, 684 { PCI_VDEVICE(INTEL, 0x27b0), LPC_ICH7DH}, 685 { PCI_VDEVICE(INTEL, 0x27b8), LPC_ICH7}, 686 { PCI_VDEVICE(INTEL, 0x27b9), LPC_ICH7M}, 687 { PCI_VDEVICE(INTEL, 0x27bc), LPC_NM10}, 688 { PCI_VDEVICE(INTEL, 0x27bd), LPC_ICH7MDH}, 689 { PCI_VDEVICE(INTEL, 0x2810), LPC_ICH8}, 690 { PCI_VDEVICE(INTEL, 0x2811), LPC_ICH8ME}, 691 { PCI_VDEVICE(INTEL, 0x2812), LPC_ICH8DH}, 692 { PCI_VDEVICE(INTEL, 0x2814), LPC_ICH8DO}, 693 { PCI_VDEVICE(INTEL, 0x2815), LPC_ICH8M}, 694 { PCI_VDEVICE(INTEL, 0x2912), LPC_ICH9DH}, 695 { PCI_VDEVICE(INTEL, 0x2914), LPC_ICH9DO}, 696 { PCI_VDEVICE(INTEL, 0x2916), LPC_ICH9R}, 697 { PCI_VDEVICE(INTEL, 0x2917), LPC_ICH9ME}, 698 { PCI_VDEVICE(INTEL, 0x2918), LPC_ICH9}, 699 { PCI_VDEVICE(INTEL, 0x2919), LPC_ICH9M}, 700 { PCI_VDEVICE(INTEL, 0x3a14), LPC_ICH10DO}, 701 { PCI_VDEVICE(INTEL, 0x3a16), LPC_ICH10R}, 702 { PCI_VDEVICE(INTEL, 0x3a18), LPC_ICH10}, 703 { PCI_VDEVICE(INTEL, 0x3a1a), LPC_ICH10D}, 704 { PCI_VDEVICE(INTEL, 0x3b00), LPC_PCH}, 705 { PCI_VDEVICE(INTEL, 0x3b01), LPC_PCHM}, 706 { PCI_VDEVICE(INTEL, 0x3b02), LPC_P55}, 707 { PCI_VDEVICE(INTEL, 0x3b03), LPC_PM55}, 708 { PCI_VDEVICE(INTEL, 0x3b06), LPC_H55}, 709 { PCI_VDEVICE(INTEL, 0x3b07), LPC_QM57}, 710 { PCI_VDEVICE(INTEL, 0x3b08), LPC_H57}, 711 { PCI_VDEVICE(INTEL, 0x3b09), LPC_HM55}, 712 { PCI_VDEVICE(INTEL, 0x3b0a), LPC_Q57}, 713 { PCI_VDEVICE(INTEL, 0x3b0b), LPC_HM57}, 714 { PCI_VDEVICE(INTEL, 0x3b0d), LPC_PCHMSFF}, 715 { PCI_VDEVICE(INTEL, 0x3b0f), LPC_QS57}, 716 { PCI_VDEVICE(INTEL, 0x3b12), LPC_3400}, 717 { PCI_VDEVICE(INTEL, 0x3b14), LPC_3420}, 718 { PCI_VDEVICE(INTEL, 0x3b16), LPC_3450}, 719 { PCI_VDEVICE(INTEL, 0x5031), LPC_EP80579}, 720 { PCI_VDEVICE(INTEL, 0x5ae8), LPC_APL}, 721 { PCI_VDEVICE(INTEL, 0x8c40), LPC_LPT}, 722 { PCI_VDEVICE(INTEL, 0x8c41), LPC_LPT}, 723 { PCI_VDEVICE(INTEL, 0x8c42), LPC_LPT}, 724 { PCI_VDEVICE(INTEL, 0x8c43), LPC_LPT}, 725 { PCI_VDEVICE(INTEL, 0x8c44), LPC_LPT}, 726 { PCI_VDEVICE(INTEL, 0x8c45), LPC_LPT}, 727 { PCI_VDEVICE(INTEL, 0x8c46), LPC_LPT}, 728 { PCI_VDEVICE(INTEL, 0x8c47), LPC_LPT}, 729 { PCI_VDEVICE(INTEL, 0x8c48), LPC_LPT}, 730 { PCI_VDEVICE(INTEL, 0x8c49), LPC_LPT}, 731 { PCI_VDEVICE(INTEL, 0x8c4a), LPC_LPT}, 732 { PCI_VDEVICE(INTEL, 0x8c4b), LPC_LPT}, 733 { PCI_VDEVICE(INTEL, 0x8c4c), LPC_LPT}, 734 { PCI_VDEVICE(INTEL, 0x8c4d), LPC_LPT}, 735 { PCI_VDEVICE(INTEL, 0x8c4e), LPC_LPT}, 736 { PCI_VDEVICE(INTEL, 0x8c4f), LPC_LPT}, 737 { PCI_VDEVICE(INTEL, 0x8c50), LPC_LPT}, 738 { PCI_VDEVICE(INTEL, 0x8c51), LPC_LPT}, 739 { PCI_VDEVICE(INTEL, 0x8c52), LPC_LPT}, 740 { PCI_VDEVICE(INTEL, 0x8c53), LPC_LPT}, 741 { PCI_VDEVICE(INTEL, 0x8c54), LPC_LPT}, 742 { PCI_VDEVICE(INTEL, 0x8c55), LPC_LPT}, 743 { PCI_VDEVICE(INTEL, 0x8c56), LPC_LPT}, 744 { PCI_VDEVICE(INTEL, 0x8c57), LPC_LPT}, 745 { PCI_VDEVICE(INTEL, 0x8c58), LPC_LPT}, 746 { PCI_VDEVICE(INTEL, 0x8c59), LPC_LPT}, 747 { PCI_VDEVICE(INTEL, 0x8c5a), LPC_LPT}, 748 { PCI_VDEVICE(INTEL, 0x8c5b), LPC_LPT}, 749 { PCI_VDEVICE(INTEL, 0x8c5c), LPC_LPT}, 750 { PCI_VDEVICE(INTEL, 0x8c5d), LPC_LPT}, 751 { PCI_VDEVICE(INTEL, 0x8c5e), LPC_LPT}, 752 { PCI_VDEVICE(INTEL, 0x8c5f), LPC_LPT}, 753 { PCI_VDEVICE(INTEL, 0x8cc1), LPC_9S}, 754 { PCI_VDEVICE(INTEL, 0x8cc2), LPC_9S}, 755 { PCI_VDEVICE(INTEL, 0x8cc3), LPC_9S}, 756 { PCI_VDEVICE(INTEL, 0x8cc4), LPC_9S}, 757 { PCI_VDEVICE(INTEL, 0x8cc6), LPC_9S}, 758 { PCI_VDEVICE(INTEL, 0x8d40), LPC_WBG}, 759 { PCI_VDEVICE(INTEL, 0x8d41), LPC_WBG}, 760 { PCI_VDEVICE(INTEL, 0x8d42), LPC_WBG}, 761 { PCI_VDEVICE(INTEL, 0x8d43), LPC_WBG}, 762 { PCI_VDEVICE(INTEL, 0x8d44), LPC_WBG}, 763 { PCI_VDEVICE(INTEL, 0x8d45), LPC_WBG}, 764 { PCI_VDEVICE(INTEL, 0x8d46), LPC_WBG}, 765 { PCI_VDEVICE(INTEL, 0x8d47), LPC_WBG}, 766 { PCI_VDEVICE(INTEL, 0x8d48), LPC_WBG}, 767 { PCI_VDEVICE(INTEL, 0x8d49), LPC_WBG}, 768 { PCI_VDEVICE(INTEL, 0x8d4a), LPC_WBG}, 769 { PCI_VDEVICE(INTEL, 0x8d4b), LPC_WBG}, 770 { PCI_VDEVICE(INTEL, 0x8d4c), LPC_WBG}, 771 { PCI_VDEVICE(INTEL, 0x8d4d), LPC_WBG}, 772 { PCI_VDEVICE(INTEL, 0x8d4e), LPC_WBG}, 773 { PCI_VDEVICE(INTEL, 0x8d4f), LPC_WBG}, 774 { PCI_VDEVICE(INTEL, 0x8d50), LPC_WBG}, 775 { PCI_VDEVICE(INTEL, 0x8d51), LPC_WBG}, 776 { PCI_VDEVICE(INTEL, 0x8d52), LPC_WBG}, 777 { PCI_VDEVICE(INTEL, 0x8d53), LPC_WBG}, 778 { PCI_VDEVICE(INTEL, 0x8d54), LPC_WBG}, 779 { PCI_VDEVICE(INTEL, 0x8d55), LPC_WBG}, 780 { PCI_VDEVICE(INTEL, 0x8d56), LPC_WBG}, 781 { PCI_VDEVICE(INTEL, 0x8d57), LPC_WBG}, 782 { PCI_VDEVICE(INTEL, 0x8d58), LPC_WBG}, 783 { PCI_VDEVICE(INTEL, 0x8d59), LPC_WBG}, 784 { PCI_VDEVICE(INTEL, 0x8d5a), LPC_WBG}, 785 { PCI_VDEVICE(INTEL, 0x8d5b), LPC_WBG}, 786 { PCI_VDEVICE(INTEL, 0x8d5c), LPC_WBG}, 787 { PCI_VDEVICE(INTEL, 0x8d5d), LPC_WBG}, 788 { PCI_VDEVICE(INTEL, 0x8d5e), LPC_WBG}, 789 { PCI_VDEVICE(INTEL, 0x8d5f), LPC_WBG}, 790 { PCI_VDEVICE(INTEL, 0x9c40), LPC_LPT_LP}, 791 { PCI_VDEVICE(INTEL, 0x9c41), LPC_LPT_LP}, 792 { PCI_VDEVICE(INTEL, 0x9c42), LPC_LPT_LP}, 793 { PCI_VDEVICE(INTEL, 0x9c43), LPC_LPT_LP}, 794 { PCI_VDEVICE(INTEL, 0x9c44), LPC_LPT_LP}, 795 { PCI_VDEVICE(INTEL, 0x9c45), LPC_LPT_LP}, 796 { PCI_VDEVICE(INTEL, 0x9c46), LPC_LPT_LP}, 797 { PCI_VDEVICE(INTEL, 0x9c47), LPC_LPT_LP}, 798 { PCI_VDEVICE(INTEL, 0x9cc1), LPC_WPT_LP}, 799 { PCI_VDEVICE(INTEL, 0x9cc2), LPC_WPT_LP}, 800 { PCI_VDEVICE(INTEL, 0x9cc3), LPC_WPT_LP}, 801 { PCI_VDEVICE(INTEL, 0x9cc5), LPC_WPT_LP}, 802 { PCI_VDEVICE(INTEL, 0x9cc6), LPC_WPT_LP}, 803 { PCI_VDEVICE(INTEL, 0x9cc7), LPC_WPT_LP}, 804 { PCI_VDEVICE(INTEL, 0x9cc9), LPC_WPT_LP}, 805 { PCI_VDEVICE(INTEL, 0xa1c1), LPC_LEWISBURG}, 806 { PCI_VDEVICE(INTEL, 0xa1c2), LPC_LEWISBURG}, 807 { PCI_VDEVICE(INTEL, 0xa1c3), LPC_LEWISBURG}, 808 { PCI_VDEVICE(INTEL, 0xa1c4), LPC_LEWISBURG}, 809 { PCI_VDEVICE(INTEL, 0xa1c5), LPC_LEWISBURG}, 810 { PCI_VDEVICE(INTEL, 0xa1c6), LPC_LEWISBURG}, 811 { PCI_VDEVICE(INTEL, 0xa1c7), LPC_LEWISBURG}, 812 { PCI_VDEVICE(INTEL, 0xa242), LPC_LEWISBURG}, 813 { PCI_VDEVICE(INTEL, 0xa243), LPC_LEWISBURG}, 814 { 0, }, /* End of list */ 815 }; 816 MODULE_DEVICE_TABLE(pci, lpc_ich_ids); 817 818 static void lpc_ich_restore_config_space(struct pci_dev *dev) 819 { 820 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 821 822 if (priv->abase_save >= 0) { 823 pci_write_config_byte(dev, priv->abase, priv->abase_save); 824 priv->abase_save = -1; 825 } 826 827 if (priv->actrl_pbase_save >= 0) { 828 pci_write_config_byte(dev, priv->actrl_pbase, 829 priv->actrl_pbase_save); 830 priv->actrl_pbase_save = -1; 831 } 832 833 if (priv->gctrl_save >= 0) { 834 pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save); 835 priv->gctrl_save = -1; 836 } 837 } 838 839 static void lpc_ich_enable_acpi_space(struct pci_dev *dev) 840 { 841 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 842 u8 reg_save; 843 844 switch (lpc_chipset_info[priv->chipset].iTCO_version) { 845 case 3: 846 /* 847 * Some chipsets (eg Avoton) enable the ACPI space in the 848 * ACPI BASE register. 849 */ 850 pci_read_config_byte(dev, priv->abase, ®_save); 851 pci_write_config_byte(dev, priv->abase, reg_save | 0x2); 852 priv->abase_save = reg_save; 853 break; 854 default: 855 /* 856 * Most chipsets enable the ACPI space in the ACPI control 857 * register. 858 */ 859 pci_read_config_byte(dev, priv->actrl_pbase, ®_save); 860 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80); 861 priv->actrl_pbase_save = reg_save; 862 break; 863 } 864 } 865 866 static void lpc_ich_enable_gpio_space(struct pci_dev *dev) 867 { 868 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 869 u8 reg_save; 870 871 pci_read_config_byte(dev, priv->gctrl, ®_save); 872 pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10); 873 priv->gctrl_save = reg_save; 874 } 875 876 static void lpc_ich_enable_pmc_space(struct pci_dev *dev) 877 { 878 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 879 u8 reg_save; 880 881 pci_read_config_byte(dev, priv->actrl_pbase, ®_save); 882 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2); 883 884 priv->actrl_pbase_save = reg_save; 885 } 886 887 static int lpc_ich_finalize_wdt_cell(struct pci_dev *dev) 888 { 889 struct itco_wdt_platform_data *pdata; 890 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 891 struct lpc_ich_info *info; 892 struct mfd_cell *cell = &lpc_ich_wdt_cell; 893 894 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL); 895 if (!pdata) 896 return -ENOMEM; 897 898 info = &lpc_chipset_info[priv->chipset]; 899 900 pdata->version = info->iTCO_version; 901 strlcpy(pdata->name, info->name, sizeof(pdata->name)); 902 903 cell->platform_data = pdata; 904 cell->pdata_size = sizeof(*pdata); 905 return 0; 906 } 907 908 static void lpc_ich_finalize_gpio_cell(struct pci_dev *dev) 909 { 910 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 911 struct mfd_cell *cell = &lpc_ich_gpio_cell; 912 913 cell->platform_data = &lpc_chipset_info[priv->chipset]; 914 cell->pdata_size = sizeof(struct lpc_ich_info); 915 } 916 917 /* 918 * We don't check for resource conflict globally. There are 2 or 3 independent 919 * GPIO groups and it's enough to have access to one of these to instantiate 920 * the device. 921 */ 922 static int lpc_ich_check_conflict_gpio(struct resource *res) 923 { 924 int ret; 925 u8 use_gpio = 0; 926 927 if (resource_size(res) >= 0x50 && 928 !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3")) 929 use_gpio |= 1 << 2; 930 931 if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2")) 932 use_gpio |= 1 << 1; 933 934 ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1"); 935 if (!ret) 936 use_gpio |= 1 << 0; 937 938 return use_gpio ? use_gpio : ret; 939 } 940 941 static int lpc_ich_init_gpio(struct pci_dev *dev) 942 { 943 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 944 u32 base_addr_cfg; 945 u32 base_addr; 946 int ret; 947 bool acpi_conflict = false; 948 struct resource *res; 949 950 /* Setup power management base register */ 951 pci_read_config_dword(dev, priv->abase, &base_addr_cfg); 952 base_addr = base_addr_cfg & 0x0000ff80; 953 if (!base_addr) { 954 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n"); 955 lpc_ich_gpio_cell.num_resources--; 956 goto gpe0_done; 957 } 958 959 res = &gpio_ich_res[ICH_RES_GPE0]; 960 res->start = base_addr + ACPIBASE_GPE_OFF; 961 res->end = base_addr + ACPIBASE_GPE_END; 962 ret = acpi_check_resource_conflict(res); 963 if (ret) { 964 /* 965 * This isn't fatal for the GPIO, but we have to make sure that 966 * the platform_device subsystem doesn't see this resource 967 * or it will register an invalid region. 968 */ 969 lpc_ich_gpio_cell.num_resources--; 970 acpi_conflict = true; 971 } else { 972 lpc_ich_enable_acpi_space(dev); 973 } 974 975 gpe0_done: 976 /* Setup GPIO base register */ 977 pci_read_config_dword(dev, priv->gbase, &base_addr_cfg); 978 base_addr = base_addr_cfg & 0x0000ff80; 979 if (!base_addr) { 980 dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n"); 981 ret = -ENODEV; 982 goto gpio_done; 983 } 984 985 /* Older devices provide fewer GPIO and have a smaller resource size. */ 986 res = &gpio_ich_res[ICH_RES_GPIO]; 987 res->start = base_addr; 988 switch (lpc_chipset_info[priv->chipset].gpio_version) { 989 case ICH_V5_GPIO: 990 case ICH_V10CORP_GPIO: 991 res->end = res->start + 128 - 1; 992 break; 993 default: 994 res->end = res->start + 64 - 1; 995 break; 996 } 997 998 ret = lpc_ich_check_conflict_gpio(res); 999 if (ret < 0) { 1000 /* this isn't necessarily fatal for the GPIO */ 1001 acpi_conflict = true; 1002 goto gpio_done; 1003 } 1004 lpc_chipset_info[priv->chipset].use_gpio = ret; 1005 lpc_ich_enable_gpio_space(dev); 1006 1007 lpc_ich_finalize_gpio_cell(dev); 1008 ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO, 1009 &lpc_ich_gpio_cell, 1, NULL, 0, NULL); 1010 1011 gpio_done: 1012 if (acpi_conflict) 1013 pr_warn("Resource conflict(s) found affecting %s\n", 1014 lpc_ich_gpio_cell.name); 1015 return ret; 1016 } 1017 1018 static int lpc_ich_init_wdt(struct pci_dev *dev) 1019 { 1020 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 1021 u32 base_addr_cfg; 1022 u32 base_addr; 1023 int ret; 1024 struct resource *res; 1025 1026 /* If we have ACPI based watchdog use that instead */ 1027 if (acpi_has_watchdog()) 1028 return -ENODEV; 1029 1030 /* Setup power management base register */ 1031 pci_read_config_dword(dev, priv->abase, &base_addr_cfg); 1032 base_addr = base_addr_cfg & 0x0000ff80; 1033 if (!base_addr) { 1034 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n"); 1035 ret = -ENODEV; 1036 goto wdt_done; 1037 } 1038 1039 res = wdt_io_res(ICH_RES_IO_TCO); 1040 res->start = base_addr + ACPIBASE_TCO_OFF; 1041 res->end = base_addr + ACPIBASE_TCO_END; 1042 1043 res = wdt_io_res(ICH_RES_IO_SMI); 1044 res->start = base_addr + ACPIBASE_SMI_OFF; 1045 res->end = base_addr + ACPIBASE_SMI_END; 1046 1047 lpc_ich_enable_acpi_space(dev); 1048 1049 /* 1050 * iTCO v2: 1051 * Get the Memory-Mapped GCS register. To get access to it 1052 * we have to read RCBA from PCI Config space 0xf0 and use 1053 * it as base. GCS = RCBA + ICH6_GCS(0x3410). 1054 * 1055 * iTCO v3: 1056 * Get the Power Management Configuration register. To get access 1057 * to it we have to read the PMC BASE from config space and address 1058 * the register at offset 0x8. 1059 */ 1060 if (lpc_chipset_info[priv->chipset].iTCO_version == 1) { 1061 /* Don't register iomem for TCO ver 1 */ 1062 lpc_ich_wdt_cell.num_resources--; 1063 } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) { 1064 pci_read_config_dword(dev, RCBABASE, &base_addr_cfg); 1065 base_addr = base_addr_cfg & 0xffffc000; 1066 if (!(base_addr_cfg & 1)) { 1067 dev_notice(&dev->dev, "RCBA is disabled by " 1068 "hardware/BIOS, device disabled\n"); 1069 ret = -ENODEV; 1070 goto wdt_done; 1071 } 1072 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC); 1073 res->start = base_addr + ACPIBASE_GCS_OFF; 1074 res->end = base_addr + ACPIBASE_GCS_END; 1075 } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) { 1076 lpc_ich_enable_pmc_space(dev); 1077 pci_read_config_dword(dev, ACPICTRL_PMCBASE, &base_addr_cfg); 1078 base_addr = base_addr_cfg & 0xfffffe00; 1079 1080 res = wdt_mem_res(ICH_RES_MEM_GCS_PMC); 1081 res->start = base_addr + ACPIBASE_PMC_OFF; 1082 res->end = base_addr + ACPIBASE_PMC_END; 1083 } 1084 1085 ret = lpc_ich_finalize_wdt_cell(dev); 1086 if (ret) 1087 goto wdt_done; 1088 1089 ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO, 1090 &lpc_ich_wdt_cell, 1, NULL, 0, NULL); 1091 1092 wdt_done: 1093 return ret; 1094 } 1095 1096 static int lpc_ich_init_spi(struct pci_dev *dev) 1097 { 1098 struct lpc_ich_priv *priv = pci_get_drvdata(dev); 1099 struct resource *res = &intel_spi_res[0]; 1100 struct intel_spi_boardinfo *info; 1101 u32 spi_base, rcba, bcr; 1102 1103 info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL); 1104 if (!info) 1105 return -ENOMEM; 1106 1107 info->type = lpc_chipset_info[priv->chipset].spi_type; 1108 1109 switch (info->type) { 1110 case INTEL_SPI_BYT: 1111 pci_read_config_dword(dev, SPIBASE_BYT, &spi_base); 1112 if (spi_base & SPIBASE_BYT_EN) { 1113 res->start = spi_base & ~(SPIBASE_BYT_SZ - 1); 1114 res->end = res->start + SPIBASE_BYT_SZ - 1; 1115 } 1116 break; 1117 1118 case INTEL_SPI_LPT: 1119 pci_read_config_dword(dev, RCBABASE, &rcba); 1120 if (rcba & 1) { 1121 spi_base = round_down(rcba, SPIBASE_LPT_SZ); 1122 res->start = spi_base + SPIBASE_LPT; 1123 res->end = res->start + SPIBASE_LPT_SZ - 1; 1124 1125 /* 1126 * Try to make the flash chip writeable now by 1127 * setting BCR_WPD. It it fails we tell the driver 1128 * that it can only read the chip. 1129 */ 1130 pci_read_config_dword(dev, BCR, &bcr); 1131 if (!(bcr & BCR_WPD)) { 1132 bcr |= BCR_WPD; 1133 pci_write_config_dword(dev, BCR, bcr); 1134 pci_read_config_dword(dev, BCR, &bcr); 1135 } 1136 info->writeable = !!(bcr & BCR_WPD); 1137 } 1138 break; 1139 1140 case INTEL_SPI_BXT: { 1141 unsigned int p2sb = PCI_DEVFN(13, 0); 1142 unsigned int spi = PCI_DEVFN(13, 2); 1143 struct pci_bus *bus = dev->bus; 1144 1145 /* 1146 * The P2SB is hidden by BIOS and we need to unhide it in 1147 * order to read BAR of the SPI flash device. Once that is 1148 * done we hide it again. 1149 */ 1150 pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x0); 1151 pci_bus_read_config_dword(bus, spi, PCI_BASE_ADDRESS_0, 1152 &spi_base); 1153 if (spi_base != ~0) { 1154 res->start = spi_base & 0xfffffff0; 1155 res->end = res->start + SPIBASE_APL_SZ - 1; 1156 1157 pci_bus_read_config_dword(bus, spi, BCR, &bcr); 1158 if (!(bcr & BCR_WPD)) { 1159 bcr |= BCR_WPD; 1160 pci_bus_write_config_dword(bus, spi, BCR, bcr); 1161 pci_bus_read_config_dword(bus, spi, BCR, &bcr); 1162 } 1163 info->writeable = !!(bcr & BCR_WPD); 1164 } 1165 1166 pci_bus_write_config_byte(bus, p2sb, 0xe1, 0x1); 1167 break; 1168 } 1169 1170 default: 1171 return -EINVAL; 1172 } 1173 1174 if (!res->start) 1175 return -ENODEV; 1176 1177 lpc_ich_spi_cell.platform_data = info; 1178 lpc_ich_spi_cell.pdata_size = sizeof(*info); 1179 1180 return mfd_add_devices(&dev->dev, PLATFORM_DEVID_NONE, 1181 &lpc_ich_spi_cell, 1, NULL, 0, NULL); 1182 } 1183 1184 static int lpc_ich_probe(struct pci_dev *dev, 1185 const struct pci_device_id *id) 1186 { 1187 struct lpc_ich_priv *priv; 1188 int ret; 1189 bool cell_added = false; 1190 1191 priv = devm_kzalloc(&dev->dev, 1192 sizeof(struct lpc_ich_priv), GFP_KERNEL); 1193 if (!priv) 1194 return -ENOMEM; 1195 1196 priv->chipset = id->driver_data; 1197 1198 priv->actrl_pbase_save = -1; 1199 priv->abase_save = -1; 1200 1201 priv->abase = ACPIBASE; 1202 priv->actrl_pbase = ACPICTRL_PMCBASE; 1203 1204 priv->gctrl_save = -1; 1205 if (priv->chipset <= LPC_ICH5) { 1206 priv->gbase = GPIOBASE_ICH0; 1207 priv->gctrl = GPIOCTRL_ICH0; 1208 } else { 1209 priv->gbase = GPIOBASE_ICH6; 1210 priv->gctrl = GPIOCTRL_ICH6; 1211 } 1212 1213 pci_set_drvdata(dev, priv); 1214 1215 if (lpc_chipset_info[priv->chipset].iTCO_version) { 1216 ret = lpc_ich_init_wdt(dev); 1217 if (!ret) 1218 cell_added = true; 1219 } 1220 1221 if (lpc_chipset_info[priv->chipset].gpio_version) { 1222 ret = lpc_ich_init_gpio(dev); 1223 if (!ret) 1224 cell_added = true; 1225 } 1226 1227 if (lpc_chipset_info[priv->chipset].spi_type) { 1228 ret = lpc_ich_init_spi(dev); 1229 if (!ret) 1230 cell_added = true; 1231 } 1232 1233 /* 1234 * We only care if at least one or none of the cells registered 1235 * successfully. 1236 */ 1237 if (!cell_added) { 1238 dev_warn(&dev->dev, "No MFD cells added\n"); 1239 lpc_ich_restore_config_space(dev); 1240 return -ENODEV; 1241 } 1242 1243 return 0; 1244 } 1245 1246 static void lpc_ich_remove(struct pci_dev *dev) 1247 { 1248 mfd_remove_devices(&dev->dev); 1249 lpc_ich_restore_config_space(dev); 1250 } 1251 1252 static struct pci_driver lpc_ich_driver = { 1253 .name = "lpc_ich", 1254 .id_table = lpc_ich_ids, 1255 .probe = lpc_ich_probe, 1256 .remove = lpc_ich_remove, 1257 }; 1258 1259 module_pci_driver(lpc_ich_driver); 1260 1261 MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>"); 1262 MODULE_DESCRIPTION("LPC interface for Intel ICH"); 1263 MODULE_LICENSE("GPL"); 1264