1b9a801dfSAndy Shevchenko // SPDX-License-Identifier: GPL-2.0 2b9a801dfSAndy Shevchenko /* 3b9a801dfSAndy Shevchenko * Device access for Basin Cove PMIC 4b9a801dfSAndy Shevchenko * 5b9a801dfSAndy Shevchenko * Copyright (c) 2019, Intel Corporation. 6b9a801dfSAndy Shevchenko * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 7b9a801dfSAndy Shevchenko */ 8b9a801dfSAndy Shevchenko 9b9a801dfSAndy Shevchenko #include <linux/acpi.h> 10b9a801dfSAndy Shevchenko #include <linux/interrupt.h> 11b9a801dfSAndy Shevchenko #include <linux/mfd/core.h> 12b9a801dfSAndy Shevchenko #include <linux/mfd/intel_soc_pmic.h> 13b9a801dfSAndy Shevchenko #include <linux/mfd/intel_soc_pmic_mrfld.h> 14b9a801dfSAndy Shevchenko #include <linux/module.h> 15*c912ac66SMika Westerberg #include <linux/platform_data/x86/intel_scu_ipc.h> 16b9a801dfSAndy Shevchenko #include <linux/platform_device.h> 17b9a801dfSAndy Shevchenko #include <linux/regmap.h> 18b9a801dfSAndy Shevchenko 19b9a801dfSAndy Shevchenko /* 20b9a801dfSAndy Shevchenko * Level 2 IRQs 21b9a801dfSAndy Shevchenko * 22b9a801dfSAndy Shevchenko * Firmware on the systems with Basin Cove PMIC services Level 1 IRQs 23b9a801dfSAndy Shevchenko * without an assistance. Thus, each of the Level 1 IRQ is represented 24b9a801dfSAndy Shevchenko * as a separate RTE in IOAPIC. 25b9a801dfSAndy Shevchenko */ 26b9a801dfSAndy Shevchenko static struct resource irq_level2_resources[] = { 27b9a801dfSAndy Shevchenko DEFINE_RES_IRQ(0), /* power button */ 28b9a801dfSAndy Shevchenko DEFINE_RES_IRQ(0), /* TMU */ 29b9a801dfSAndy Shevchenko DEFINE_RES_IRQ(0), /* thermal */ 30b9a801dfSAndy Shevchenko DEFINE_RES_IRQ(0), /* BCU */ 31b9a801dfSAndy Shevchenko DEFINE_RES_IRQ(0), /* ADC */ 32b9a801dfSAndy Shevchenko DEFINE_RES_IRQ(0), /* charger */ 33b9a801dfSAndy Shevchenko DEFINE_RES_IRQ(0), /* GPIO */ 34b9a801dfSAndy Shevchenko }; 35b9a801dfSAndy Shevchenko 36b9a801dfSAndy Shevchenko static const struct mfd_cell bcove_dev[] = { 37b9a801dfSAndy Shevchenko { 38b9a801dfSAndy Shevchenko .name = "mrfld_bcove_pwrbtn", 39b9a801dfSAndy Shevchenko .num_resources = 1, 40b9a801dfSAndy Shevchenko .resources = &irq_level2_resources[0], 41b9a801dfSAndy Shevchenko }, { 42b9a801dfSAndy Shevchenko .name = "mrfld_bcove_tmu", 43b9a801dfSAndy Shevchenko .num_resources = 1, 44b9a801dfSAndy Shevchenko .resources = &irq_level2_resources[1], 45b9a801dfSAndy Shevchenko }, { 46b9a801dfSAndy Shevchenko .name = "mrfld_bcove_thermal", 47b9a801dfSAndy Shevchenko .num_resources = 1, 48b9a801dfSAndy Shevchenko .resources = &irq_level2_resources[2], 49b9a801dfSAndy Shevchenko }, { 50b9a801dfSAndy Shevchenko .name = "mrfld_bcove_bcu", 51b9a801dfSAndy Shevchenko .num_resources = 1, 52b9a801dfSAndy Shevchenko .resources = &irq_level2_resources[3], 53b9a801dfSAndy Shevchenko }, { 54b9a801dfSAndy Shevchenko .name = "mrfld_bcove_adc", 55b9a801dfSAndy Shevchenko .num_resources = 1, 56b9a801dfSAndy Shevchenko .resources = &irq_level2_resources[4], 57b9a801dfSAndy Shevchenko }, { 58b9a801dfSAndy Shevchenko .name = "mrfld_bcove_charger", 59b9a801dfSAndy Shevchenko .num_resources = 1, 60b9a801dfSAndy Shevchenko .resources = &irq_level2_resources[5], 61b9a801dfSAndy Shevchenko }, { 62b9a801dfSAndy Shevchenko .name = "mrfld_bcove_pwrsrc", 63b9a801dfSAndy Shevchenko .num_resources = 1, 64b9a801dfSAndy Shevchenko .resources = &irq_level2_resources[5], 65b9a801dfSAndy Shevchenko }, { 66b9a801dfSAndy Shevchenko .name = "mrfld_bcove_gpio", 67b9a801dfSAndy Shevchenko .num_resources = 1, 68b9a801dfSAndy Shevchenko .resources = &irq_level2_resources[6], 69b9a801dfSAndy Shevchenko }, 70b9a801dfSAndy Shevchenko { .name = "mrfld_bcove_region", }, 71b9a801dfSAndy Shevchenko }; 72b9a801dfSAndy Shevchenko 73b9a801dfSAndy Shevchenko static int bcove_ipc_byte_reg_read(void *context, unsigned int reg, 74b9a801dfSAndy Shevchenko unsigned int *val) 75b9a801dfSAndy Shevchenko { 7650362083SMika Westerberg struct intel_soc_pmic *pmic = context; 77b9a801dfSAndy Shevchenko u8 ipc_out; 78b9a801dfSAndy Shevchenko int ret; 79b9a801dfSAndy Shevchenko 8050362083SMika Westerberg ret = intel_scu_ipc_dev_ioread8(pmic->scu, reg, &ipc_out); 81b9a801dfSAndy Shevchenko if (ret) 82b9a801dfSAndy Shevchenko return ret; 83b9a801dfSAndy Shevchenko 84b9a801dfSAndy Shevchenko *val = ipc_out; 85b9a801dfSAndy Shevchenko return 0; 86b9a801dfSAndy Shevchenko } 87b9a801dfSAndy Shevchenko 88b9a801dfSAndy Shevchenko static int bcove_ipc_byte_reg_write(void *context, unsigned int reg, 89b9a801dfSAndy Shevchenko unsigned int val) 90b9a801dfSAndy Shevchenko { 9150362083SMika Westerberg struct intel_soc_pmic *pmic = context; 92b9a801dfSAndy Shevchenko u8 ipc_in = val; 93b9a801dfSAndy Shevchenko 944ee1d9dcSXu Wang return intel_scu_ipc_dev_iowrite8(pmic->scu, reg, ipc_in); 95b9a801dfSAndy Shevchenko } 96b9a801dfSAndy Shevchenko 97b9a801dfSAndy Shevchenko static const struct regmap_config bcove_regmap_config = { 98b9a801dfSAndy Shevchenko .reg_bits = 16, 99b9a801dfSAndy Shevchenko .val_bits = 8, 100b9a801dfSAndy Shevchenko .max_register = 0xff, 101b9a801dfSAndy Shevchenko .reg_write = bcove_ipc_byte_reg_write, 102b9a801dfSAndy Shevchenko .reg_read = bcove_ipc_byte_reg_read, 103b9a801dfSAndy Shevchenko }; 104b9a801dfSAndy Shevchenko 105b9a801dfSAndy Shevchenko static int bcove_probe(struct platform_device *pdev) 106b9a801dfSAndy Shevchenko { 107b9a801dfSAndy Shevchenko struct device *dev = &pdev->dev; 108b9a801dfSAndy Shevchenko struct intel_soc_pmic *pmic; 109b9a801dfSAndy Shevchenko unsigned int i; 110b9a801dfSAndy Shevchenko int ret; 111b9a801dfSAndy Shevchenko 112b9a801dfSAndy Shevchenko pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL); 113b9a801dfSAndy Shevchenko if (!pmic) 114b9a801dfSAndy Shevchenko return -ENOMEM; 115b9a801dfSAndy Shevchenko 11650362083SMika Westerberg pmic->scu = devm_intel_scu_ipc_dev_get(dev); 11750362083SMika Westerberg if (!pmic->scu) 11850362083SMika Westerberg return -ENOMEM; 11950362083SMika Westerberg 120b9a801dfSAndy Shevchenko platform_set_drvdata(pdev, pmic); 121b9a801dfSAndy Shevchenko pmic->dev = &pdev->dev; 122b9a801dfSAndy Shevchenko 123b9a801dfSAndy Shevchenko pmic->regmap = devm_regmap_init(dev, NULL, pmic, &bcove_regmap_config); 124b9a801dfSAndy Shevchenko if (IS_ERR(pmic->regmap)) 125b9a801dfSAndy Shevchenko return PTR_ERR(pmic->regmap); 126b9a801dfSAndy Shevchenko 127b9a801dfSAndy Shevchenko for (i = 0; i < ARRAY_SIZE(irq_level2_resources); i++) { 128b9a801dfSAndy Shevchenko ret = platform_get_irq(pdev, i); 129b9a801dfSAndy Shevchenko if (ret < 0) 130b9a801dfSAndy Shevchenko return ret; 131b9a801dfSAndy Shevchenko 132b9a801dfSAndy Shevchenko irq_level2_resources[i].start = ret; 133b9a801dfSAndy Shevchenko irq_level2_resources[i].end = ret; 134b9a801dfSAndy Shevchenko } 135b9a801dfSAndy Shevchenko 136b9a801dfSAndy Shevchenko return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, 137b9a801dfSAndy Shevchenko bcove_dev, ARRAY_SIZE(bcove_dev), 138b9a801dfSAndy Shevchenko NULL, 0, NULL); 139b9a801dfSAndy Shevchenko } 140b9a801dfSAndy Shevchenko 141b9a801dfSAndy Shevchenko static const struct acpi_device_id bcove_acpi_ids[] = { 142b9a801dfSAndy Shevchenko { "INTC100E" }, 143b9a801dfSAndy Shevchenko {} 144b9a801dfSAndy Shevchenko }; 145b9a801dfSAndy Shevchenko MODULE_DEVICE_TABLE(acpi, bcove_acpi_ids); 146b9a801dfSAndy Shevchenko 147b9a801dfSAndy Shevchenko static struct platform_driver bcove_driver = { 148b9a801dfSAndy Shevchenko .driver = { 149b9a801dfSAndy Shevchenko .name = "intel_soc_pmic_mrfld", 150b9a801dfSAndy Shevchenko .acpi_match_table = bcove_acpi_ids, 151b9a801dfSAndy Shevchenko }, 152b9a801dfSAndy Shevchenko .probe = bcove_probe, 153b9a801dfSAndy Shevchenko }; 154b9a801dfSAndy Shevchenko module_platform_driver(bcove_driver); 155b9a801dfSAndy Shevchenko 156b9a801dfSAndy Shevchenko MODULE_DESCRIPTION("IPC driver for Intel SoC Basin Cove PMIC"); 157b9a801dfSAndy Shevchenko MODULE_LICENSE("GPL v2"); 158