1 /* 2 * intel_soc_pmic_crc.c - Device access for Crystal Cove PMIC 3 * 4 * Copyright (C) 2013, 2014 Intel Corporation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License version 8 * 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * Author: Yang, Bin <bin.yang@intel.com> 16 * Author: Zhu, Lejun <lejun.zhu@linux.intel.com> 17 */ 18 19 #include <linux/mfd/core.h> 20 #include <linux/interrupt.h> 21 #include <linux/regmap.h> 22 #include <linux/mfd/intel_soc_pmic.h> 23 #include "intel_soc_pmic_core.h" 24 25 #define CRYSTAL_COVE_MAX_REGISTER 0xC6 26 27 #define CRYSTAL_COVE_REG_IRQLVL1 0x02 28 #define CRYSTAL_COVE_REG_MIRQLVL1 0x0E 29 30 #define CRYSTAL_COVE_IRQ_PWRSRC 0 31 #define CRYSTAL_COVE_IRQ_THRM 1 32 #define CRYSTAL_COVE_IRQ_BCU 2 33 #define CRYSTAL_COVE_IRQ_ADC 3 34 #define CRYSTAL_COVE_IRQ_CHGR 4 35 #define CRYSTAL_COVE_IRQ_GPIO 5 36 #define CRYSTAL_COVE_IRQ_VHDMIOCP 6 37 38 static struct resource gpio_resources[] = { 39 { 40 .name = "GPIO", 41 .start = CRYSTAL_COVE_IRQ_GPIO, 42 .end = CRYSTAL_COVE_IRQ_GPIO, 43 .flags = IORESOURCE_IRQ, 44 }, 45 }; 46 47 static struct resource pwrsrc_resources[] = { 48 { 49 .name = "PWRSRC", 50 .start = CRYSTAL_COVE_IRQ_PWRSRC, 51 .end = CRYSTAL_COVE_IRQ_PWRSRC, 52 .flags = IORESOURCE_IRQ, 53 }, 54 }; 55 56 static struct resource adc_resources[] = { 57 { 58 .name = "ADC", 59 .start = CRYSTAL_COVE_IRQ_ADC, 60 .end = CRYSTAL_COVE_IRQ_ADC, 61 .flags = IORESOURCE_IRQ, 62 }, 63 }; 64 65 static struct resource thermal_resources[] = { 66 { 67 .name = "THERMAL", 68 .start = CRYSTAL_COVE_IRQ_THRM, 69 .end = CRYSTAL_COVE_IRQ_THRM, 70 .flags = IORESOURCE_IRQ, 71 }, 72 }; 73 74 static struct resource bcu_resources[] = { 75 { 76 .name = "BCU", 77 .start = CRYSTAL_COVE_IRQ_BCU, 78 .end = CRYSTAL_COVE_IRQ_BCU, 79 .flags = IORESOURCE_IRQ, 80 }, 81 }; 82 83 static struct mfd_cell crystal_cove_dev[] = { 84 { 85 .name = "crystal_cove_pwrsrc", 86 .num_resources = ARRAY_SIZE(pwrsrc_resources), 87 .resources = pwrsrc_resources, 88 }, 89 { 90 .name = "crystal_cove_adc", 91 .num_resources = ARRAY_SIZE(adc_resources), 92 .resources = adc_resources, 93 }, 94 { 95 .name = "crystal_cove_thermal", 96 .num_resources = ARRAY_SIZE(thermal_resources), 97 .resources = thermal_resources, 98 }, 99 { 100 .name = "crystal_cove_bcu", 101 .num_resources = ARRAY_SIZE(bcu_resources), 102 .resources = bcu_resources, 103 }, 104 { 105 .name = "crystal_cove_gpio", 106 .num_resources = ARRAY_SIZE(gpio_resources), 107 .resources = gpio_resources, 108 }, 109 { 110 .name = "crystal_cove_pmic", 111 }, 112 { 113 .name = "crystal_cove_pwm", 114 }, 115 }; 116 117 static const struct regmap_config crystal_cove_regmap_config = { 118 .reg_bits = 8, 119 .val_bits = 8, 120 121 .max_register = CRYSTAL_COVE_MAX_REGISTER, 122 .cache_type = REGCACHE_NONE, 123 }; 124 125 static const struct regmap_irq crystal_cove_irqs[] = { 126 [CRYSTAL_COVE_IRQ_PWRSRC] = { 127 .mask = BIT(CRYSTAL_COVE_IRQ_PWRSRC), 128 }, 129 [CRYSTAL_COVE_IRQ_THRM] = { 130 .mask = BIT(CRYSTAL_COVE_IRQ_THRM), 131 }, 132 [CRYSTAL_COVE_IRQ_BCU] = { 133 .mask = BIT(CRYSTAL_COVE_IRQ_BCU), 134 }, 135 [CRYSTAL_COVE_IRQ_ADC] = { 136 .mask = BIT(CRYSTAL_COVE_IRQ_ADC), 137 }, 138 [CRYSTAL_COVE_IRQ_CHGR] = { 139 .mask = BIT(CRYSTAL_COVE_IRQ_CHGR), 140 }, 141 [CRYSTAL_COVE_IRQ_GPIO] = { 142 .mask = BIT(CRYSTAL_COVE_IRQ_GPIO), 143 }, 144 [CRYSTAL_COVE_IRQ_VHDMIOCP] = { 145 .mask = BIT(CRYSTAL_COVE_IRQ_VHDMIOCP), 146 }, 147 }; 148 149 static const struct regmap_irq_chip crystal_cove_irq_chip = { 150 .name = "Crystal Cove", 151 .irqs = crystal_cove_irqs, 152 .num_irqs = ARRAY_SIZE(crystal_cove_irqs), 153 .num_regs = 1, 154 .status_base = CRYSTAL_COVE_REG_IRQLVL1, 155 .mask_base = CRYSTAL_COVE_REG_MIRQLVL1, 156 }; 157 158 struct intel_soc_pmic_config intel_soc_pmic_config_crc = { 159 .irq_flags = IRQF_TRIGGER_RISING, 160 .cell_dev = crystal_cove_dev, 161 .n_cell_devs = ARRAY_SIZE(crystal_cove_dev), 162 .regmap_config = &crystal_cove_regmap_config, 163 .irq_chip = &crystal_cove_irq_chip, 164 }; 165