1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Device access for Crystal Cove PMIC 4 * 5 * Copyright (C) 2013, 2014 Intel Corporation. All rights reserved. 6 * 7 * Author: Yang, Bin <bin.yang@intel.com> 8 * Author: Zhu, Lejun <lejun.zhu@linux.intel.com> 9 */ 10 11 #include <linux/interrupt.h> 12 #include <linux/regmap.h> 13 #include <linux/mfd/core.h> 14 #include <linux/mfd/intel_soc_pmic.h> 15 16 #include "intel_soc_pmic_core.h" 17 18 #define CRYSTAL_COVE_MAX_REGISTER 0xC6 19 20 #define CRYSTAL_COVE_REG_IRQLVL1 0x02 21 #define CRYSTAL_COVE_REG_MIRQLVL1 0x0E 22 23 #define CRYSTAL_COVE_IRQ_PWRSRC 0 24 #define CRYSTAL_COVE_IRQ_THRM 1 25 #define CRYSTAL_COVE_IRQ_BCU 2 26 #define CRYSTAL_COVE_IRQ_ADC 3 27 #define CRYSTAL_COVE_IRQ_CHGR 4 28 #define CRYSTAL_COVE_IRQ_GPIO 5 29 #define CRYSTAL_COVE_IRQ_VHDMIOCP 6 30 31 static struct resource gpio_resources[] = { 32 DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_GPIO, "GPIO"), 33 }; 34 35 static struct resource pwrsrc_resources[] = { 36 DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_PWRSRC, "PWRSRC"), 37 }; 38 39 static struct resource adc_resources[] = { 40 DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_ADC, "ADC"), 41 }; 42 43 static struct resource thermal_resources[] = { 44 DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_THRM, "THERMAL"), 45 }; 46 47 static struct resource bcu_resources[] = { 48 DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_BCU, "BCU"), 49 }; 50 51 static struct mfd_cell crystal_cove_byt_dev[] = { 52 { 53 .name = "crystal_cove_pwrsrc", 54 .num_resources = ARRAY_SIZE(pwrsrc_resources), 55 .resources = pwrsrc_resources, 56 }, 57 { 58 .name = "crystal_cove_adc", 59 .num_resources = ARRAY_SIZE(adc_resources), 60 .resources = adc_resources, 61 }, 62 { 63 .name = "crystal_cove_thermal", 64 .num_resources = ARRAY_SIZE(thermal_resources), 65 .resources = thermal_resources, 66 }, 67 { 68 .name = "crystal_cove_bcu", 69 .num_resources = ARRAY_SIZE(bcu_resources), 70 .resources = bcu_resources, 71 }, 72 { 73 .name = "crystal_cove_gpio", 74 .num_resources = ARRAY_SIZE(gpio_resources), 75 .resources = gpio_resources, 76 }, 77 { 78 .name = "byt_crystal_cove_pmic", 79 }, 80 { 81 .name = "crystal_cove_pwm", 82 }, 83 }; 84 85 static struct mfd_cell crystal_cove_cht_dev[] = { 86 { 87 .name = "crystal_cove_gpio", 88 .num_resources = ARRAY_SIZE(gpio_resources), 89 .resources = gpio_resources, 90 }, 91 { 92 .name = "cht_crystal_cove_pmic", 93 }, 94 { 95 .name = "crystal_cove_pwm", 96 }, 97 }; 98 99 static const struct regmap_config crystal_cove_regmap_config = { 100 .reg_bits = 8, 101 .val_bits = 8, 102 103 .max_register = CRYSTAL_COVE_MAX_REGISTER, 104 .cache_type = REGCACHE_NONE, 105 }; 106 107 static const struct regmap_irq crystal_cove_irqs[] = { 108 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_PWRSRC, 0, BIT(CRYSTAL_COVE_IRQ_PWRSRC)), 109 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_THRM, 0, BIT(CRYSTAL_COVE_IRQ_THRM)), 110 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_BCU, 0, BIT(CRYSTAL_COVE_IRQ_BCU)), 111 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_ADC, 0, BIT(CRYSTAL_COVE_IRQ_ADC)), 112 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_CHGR, 0, BIT(CRYSTAL_COVE_IRQ_CHGR)), 113 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_GPIO, 0, BIT(CRYSTAL_COVE_IRQ_GPIO)), 114 REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_VHDMIOCP, 0, BIT(CRYSTAL_COVE_IRQ_VHDMIOCP)), 115 }; 116 117 static const struct regmap_irq_chip crystal_cove_irq_chip = { 118 .name = "Crystal Cove", 119 .irqs = crystal_cove_irqs, 120 .num_irqs = ARRAY_SIZE(crystal_cove_irqs), 121 .num_regs = 1, 122 .status_base = CRYSTAL_COVE_REG_IRQLVL1, 123 .mask_base = CRYSTAL_COVE_REG_MIRQLVL1, 124 }; 125 126 struct intel_soc_pmic_config intel_soc_pmic_config_byt_crc = { 127 .irq_flags = IRQF_TRIGGER_RISING, 128 .cell_dev = crystal_cove_byt_dev, 129 .n_cell_devs = ARRAY_SIZE(crystal_cove_byt_dev), 130 .regmap_config = &crystal_cove_regmap_config, 131 .irq_chip = &crystal_cove_irq_chip, 132 }; 133 134 struct intel_soc_pmic_config intel_soc_pmic_config_cht_crc = { 135 .irq_flags = IRQF_TRIGGER_RISING, 136 .cell_dev = crystal_cove_cht_dev, 137 .n_cell_devs = ARRAY_SIZE(crystal_cove_cht_dev), 138 .regmap_config = &crystal_cove_regmap_config, 139 .irq_chip = &crystal_cove_irq_chip, 140 }; 141