1*4b45efe8SAndy Shevchenko /* 2*4b45efe8SAndy Shevchenko * Intel Sunrisepoint LPSS core support. 3*4b45efe8SAndy Shevchenko * 4*4b45efe8SAndy Shevchenko * Copyright (C) 2015, Intel Corporation 5*4b45efe8SAndy Shevchenko * 6*4b45efe8SAndy Shevchenko * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 7*4b45efe8SAndy Shevchenko * Mika Westerberg <mika.westerberg@linux.intel.com> 8*4b45efe8SAndy Shevchenko * Heikki Krogerus <heikki.krogerus@linux.intel.com> 9*4b45efe8SAndy Shevchenko * Jarkko Nikula <jarkko.nikula@linux.intel.com> 10*4b45efe8SAndy Shevchenko * 11*4b45efe8SAndy Shevchenko * This program is free software; you can redistribute it and/or modify 12*4b45efe8SAndy Shevchenko * it under the terms of the GNU General Public License version 2 as 13*4b45efe8SAndy Shevchenko * published by the Free Software Foundation. 14*4b45efe8SAndy Shevchenko */ 15*4b45efe8SAndy Shevchenko 16*4b45efe8SAndy Shevchenko #include <linux/clk.h> 17*4b45efe8SAndy Shevchenko #include <linux/clkdev.h> 18*4b45efe8SAndy Shevchenko #include <linux/clk-provider.h> 19*4b45efe8SAndy Shevchenko #include <linux/debugfs.h> 20*4b45efe8SAndy Shevchenko #include <linux/idr.h> 21*4b45efe8SAndy Shevchenko #include <linux/ioport.h> 22*4b45efe8SAndy Shevchenko #include <linux/kernel.h> 23*4b45efe8SAndy Shevchenko #include <linux/module.h> 24*4b45efe8SAndy Shevchenko #include <linux/mfd/core.h> 25*4b45efe8SAndy Shevchenko #include <linux/pm_qos.h> 26*4b45efe8SAndy Shevchenko #include <linux/pm_runtime.h> 27*4b45efe8SAndy Shevchenko #include <linux/seq_file.h> 28*4b45efe8SAndy Shevchenko 29*4b45efe8SAndy Shevchenko #include "intel-lpss.h" 30*4b45efe8SAndy Shevchenko 31*4b45efe8SAndy Shevchenko #define LPSS_DEV_OFFSET 0x000 32*4b45efe8SAndy Shevchenko #define LPSS_DEV_SIZE 0x200 33*4b45efe8SAndy Shevchenko #define LPSS_PRIV_OFFSET 0x200 34*4b45efe8SAndy Shevchenko #define LPSS_PRIV_SIZE 0x100 35*4b45efe8SAndy Shevchenko #define LPSS_IDMA64_OFFSET 0x800 36*4b45efe8SAndy Shevchenko #define LPSS_IDMA64_SIZE 0x800 37*4b45efe8SAndy Shevchenko 38*4b45efe8SAndy Shevchenko /* Offsets from lpss->priv */ 39*4b45efe8SAndy Shevchenko #define LPSS_PRIV_RESETS 0x04 40*4b45efe8SAndy Shevchenko #define LPSS_PRIV_RESETS_FUNC BIT(2) 41*4b45efe8SAndy Shevchenko #define LPSS_PRIV_RESETS_IDMA 0x3 42*4b45efe8SAndy Shevchenko 43*4b45efe8SAndy Shevchenko #define LPSS_PRIV_ACTIVELTR 0x10 44*4b45efe8SAndy Shevchenko #define LPSS_PRIV_IDLELTR 0x14 45*4b45efe8SAndy Shevchenko 46*4b45efe8SAndy Shevchenko #define LPSS_PRIV_LTR_REQ BIT(15) 47*4b45efe8SAndy Shevchenko #define LPSS_PRIV_LTR_SCALE_MASK 0xc00 48*4b45efe8SAndy Shevchenko #define LPSS_PRIV_LTR_SCALE_1US 0x800 49*4b45efe8SAndy Shevchenko #define LPSS_PRIV_LTR_SCALE_32US 0xc00 50*4b45efe8SAndy Shevchenko #define LPSS_PRIV_LTR_VALUE_MASK 0x3ff 51*4b45efe8SAndy Shevchenko 52*4b45efe8SAndy Shevchenko #define LPSS_PRIV_SSP_REG 0x20 53*4b45efe8SAndy Shevchenko #define LPSS_PRIV_SSP_REG_DIS_DMA_FIN BIT(0) 54*4b45efe8SAndy Shevchenko 55*4b45efe8SAndy Shevchenko #define LPSS_PRIV_REMAP_ADDR_LO 0x40 56*4b45efe8SAndy Shevchenko #define LPSS_PRIV_REMAP_ADDR_HI 0x44 57*4b45efe8SAndy Shevchenko 58*4b45efe8SAndy Shevchenko #define LPSS_PRIV_CAPS 0xfc 59*4b45efe8SAndy Shevchenko #define LPSS_PRIV_CAPS_NO_IDMA BIT(8) 60*4b45efe8SAndy Shevchenko #define LPSS_PRIV_CAPS_TYPE_SHIFT 4 61*4b45efe8SAndy Shevchenko #define LPSS_PRIV_CAPS_TYPE_MASK (0xf << LPSS_PRIV_CAPS_TYPE_SHIFT) 62*4b45efe8SAndy Shevchenko 63*4b45efe8SAndy Shevchenko /* This matches the type field in CAPS register */ 64*4b45efe8SAndy Shevchenko enum intel_lpss_dev_type { 65*4b45efe8SAndy Shevchenko LPSS_DEV_I2C = 0, 66*4b45efe8SAndy Shevchenko LPSS_DEV_UART, 67*4b45efe8SAndy Shevchenko LPSS_DEV_SPI, 68*4b45efe8SAndy Shevchenko }; 69*4b45efe8SAndy Shevchenko 70*4b45efe8SAndy Shevchenko struct intel_lpss { 71*4b45efe8SAndy Shevchenko const struct intel_lpss_platform_info *info; 72*4b45efe8SAndy Shevchenko enum intel_lpss_dev_type type; 73*4b45efe8SAndy Shevchenko struct clk *clk; 74*4b45efe8SAndy Shevchenko struct clk_lookup *clock; 75*4b45efe8SAndy Shevchenko const struct mfd_cell *cell; 76*4b45efe8SAndy Shevchenko struct device *dev; 77*4b45efe8SAndy Shevchenko void __iomem *priv; 78*4b45efe8SAndy Shevchenko int devid; 79*4b45efe8SAndy Shevchenko u32 caps; 80*4b45efe8SAndy Shevchenko u32 active_ltr; 81*4b45efe8SAndy Shevchenko u32 idle_ltr; 82*4b45efe8SAndy Shevchenko struct dentry *debugfs; 83*4b45efe8SAndy Shevchenko }; 84*4b45efe8SAndy Shevchenko 85*4b45efe8SAndy Shevchenko static const struct resource intel_lpss_dev_resources[] = { 86*4b45efe8SAndy Shevchenko DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET, LPSS_DEV_SIZE, "lpss_dev"), 87*4b45efe8SAndy Shevchenko DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET, LPSS_PRIV_SIZE, "lpss_priv"), 88*4b45efe8SAndy Shevchenko DEFINE_RES_IRQ(0), 89*4b45efe8SAndy Shevchenko }; 90*4b45efe8SAndy Shevchenko 91*4b45efe8SAndy Shevchenko static const struct resource intel_lpss_idma64_resources[] = { 92*4b45efe8SAndy Shevchenko DEFINE_RES_MEM(LPSS_IDMA64_OFFSET, LPSS_IDMA64_SIZE), 93*4b45efe8SAndy Shevchenko DEFINE_RES_IRQ(0), 94*4b45efe8SAndy Shevchenko }; 95*4b45efe8SAndy Shevchenko 96*4b45efe8SAndy Shevchenko #define LPSS_IDMA64_DRIVER_NAME "idma64" 97*4b45efe8SAndy Shevchenko 98*4b45efe8SAndy Shevchenko /* 99*4b45efe8SAndy Shevchenko * Cells needs to be ordered so that the iDMA is created first. This is 100*4b45efe8SAndy Shevchenko * because we need to be sure the DMA is available when the host controller 101*4b45efe8SAndy Shevchenko * driver is probed. 102*4b45efe8SAndy Shevchenko */ 103*4b45efe8SAndy Shevchenko static const struct mfd_cell intel_lpss_idma64_cell = { 104*4b45efe8SAndy Shevchenko .name = LPSS_IDMA64_DRIVER_NAME, 105*4b45efe8SAndy Shevchenko .num_resources = ARRAY_SIZE(intel_lpss_idma64_resources), 106*4b45efe8SAndy Shevchenko .resources = intel_lpss_idma64_resources, 107*4b45efe8SAndy Shevchenko }; 108*4b45efe8SAndy Shevchenko 109*4b45efe8SAndy Shevchenko static const struct mfd_cell intel_lpss_i2c_cell = { 110*4b45efe8SAndy Shevchenko .name = "i2c_designware", 111*4b45efe8SAndy Shevchenko .num_resources = ARRAY_SIZE(intel_lpss_dev_resources), 112*4b45efe8SAndy Shevchenko .resources = intel_lpss_dev_resources, 113*4b45efe8SAndy Shevchenko }; 114*4b45efe8SAndy Shevchenko 115*4b45efe8SAndy Shevchenko static const struct mfd_cell intel_lpss_uart_cell = { 116*4b45efe8SAndy Shevchenko .name = "dw-apb-uart", 117*4b45efe8SAndy Shevchenko .num_resources = ARRAY_SIZE(intel_lpss_dev_resources), 118*4b45efe8SAndy Shevchenko .resources = intel_lpss_dev_resources, 119*4b45efe8SAndy Shevchenko }; 120*4b45efe8SAndy Shevchenko 121*4b45efe8SAndy Shevchenko static const struct mfd_cell intel_lpss_spi_cell = { 122*4b45efe8SAndy Shevchenko .name = "pxa2xx-spi", 123*4b45efe8SAndy Shevchenko .num_resources = ARRAY_SIZE(intel_lpss_dev_resources), 124*4b45efe8SAndy Shevchenko .resources = intel_lpss_dev_resources, 125*4b45efe8SAndy Shevchenko }; 126*4b45efe8SAndy Shevchenko 127*4b45efe8SAndy Shevchenko static DEFINE_IDA(intel_lpss_devid_ida); 128*4b45efe8SAndy Shevchenko static struct dentry *intel_lpss_debugfs; 129*4b45efe8SAndy Shevchenko 130*4b45efe8SAndy Shevchenko static int intel_lpss_request_dma_module(const char *name) 131*4b45efe8SAndy Shevchenko { 132*4b45efe8SAndy Shevchenko static bool intel_lpss_dma_requested; 133*4b45efe8SAndy Shevchenko 134*4b45efe8SAndy Shevchenko if (intel_lpss_dma_requested) 135*4b45efe8SAndy Shevchenko return 0; 136*4b45efe8SAndy Shevchenko 137*4b45efe8SAndy Shevchenko intel_lpss_dma_requested = true; 138*4b45efe8SAndy Shevchenko return request_module("%s", name); 139*4b45efe8SAndy Shevchenko } 140*4b45efe8SAndy Shevchenko 141*4b45efe8SAndy Shevchenko static void intel_lpss_cache_ltr(struct intel_lpss *lpss) 142*4b45efe8SAndy Shevchenko { 143*4b45efe8SAndy Shevchenko lpss->active_ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR); 144*4b45efe8SAndy Shevchenko lpss->idle_ltr = readl(lpss->priv + LPSS_PRIV_IDLELTR); 145*4b45efe8SAndy Shevchenko } 146*4b45efe8SAndy Shevchenko 147*4b45efe8SAndy Shevchenko static int intel_lpss_debugfs_add(struct intel_lpss *lpss) 148*4b45efe8SAndy Shevchenko { 149*4b45efe8SAndy Shevchenko struct dentry *dir; 150*4b45efe8SAndy Shevchenko 151*4b45efe8SAndy Shevchenko dir = debugfs_create_dir(dev_name(lpss->dev), intel_lpss_debugfs); 152*4b45efe8SAndy Shevchenko if (IS_ERR(dir)) 153*4b45efe8SAndy Shevchenko return PTR_ERR(dir); 154*4b45efe8SAndy Shevchenko 155*4b45efe8SAndy Shevchenko /* Cache the values into lpss structure */ 156*4b45efe8SAndy Shevchenko intel_lpss_cache_ltr(lpss); 157*4b45efe8SAndy Shevchenko 158*4b45efe8SAndy Shevchenko debugfs_create_x32("capabilities", S_IRUGO, dir, &lpss->caps); 159*4b45efe8SAndy Shevchenko debugfs_create_x32("active_ltr", S_IRUGO, dir, &lpss->active_ltr); 160*4b45efe8SAndy Shevchenko debugfs_create_x32("idle_ltr", S_IRUGO, dir, &lpss->idle_ltr); 161*4b45efe8SAndy Shevchenko 162*4b45efe8SAndy Shevchenko lpss->debugfs = dir; 163*4b45efe8SAndy Shevchenko return 0; 164*4b45efe8SAndy Shevchenko } 165*4b45efe8SAndy Shevchenko 166*4b45efe8SAndy Shevchenko static void intel_lpss_debugfs_remove(struct intel_lpss *lpss) 167*4b45efe8SAndy Shevchenko { 168*4b45efe8SAndy Shevchenko debugfs_remove_recursive(lpss->debugfs); 169*4b45efe8SAndy Shevchenko } 170*4b45efe8SAndy Shevchenko 171*4b45efe8SAndy Shevchenko static void intel_lpss_ltr_set(struct device *dev, s32 val) 172*4b45efe8SAndy Shevchenko { 173*4b45efe8SAndy Shevchenko struct intel_lpss *lpss = dev_get_drvdata(dev); 174*4b45efe8SAndy Shevchenko u32 ltr; 175*4b45efe8SAndy Shevchenko 176*4b45efe8SAndy Shevchenko /* 177*4b45efe8SAndy Shevchenko * Program latency tolerance (LTR) accordingly what has been asked 178*4b45efe8SAndy Shevchenko * by the PM QoS layer or disable it in case we were passed 179*4b45efe8SAndy Shevchenko * negative value or PM_QOS_LATENCY_ANY. 180*4b45efe8SAndy Shevchenko */ 181*4b45efe8SAndy Shevchenko ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR); 182*4b45efe8SAndy Shevchenko 183*4b45efe8SAndy Shevchenko if (val == PM_QOS_LATENCY_ANY || val < 0) { 184*4b45efe8SAndy Shevchenko ltr &= ~LPSS_PRIV_LTR_REQ; 185*4b45efe8SAndy Shevchenko } else { 186*4b45efe8SAndy Shevchenko ltr |= LPSS_PRIV_LTR_REQ; 187*4b45efe8SAndy Shevchenko ltr &= ~LPSS_PRIV_LTR_SCALE_MASK; 188*4b45efe8SAndy Shevchenko ltr &= ~LPSS_PRIV_LTR_VALUE_MASK; 189*4b45efe8SAndy Shevchenko 190*4b45efe8SAndy Shevchenko if (val > LPSS_PRIV_LTR_VALUE_MASK) 191*4b45efe8SAndy Shevchenko ltr |= LPSS_PRIV_LTR_SCALE_32US | val >> 5; 192*4b45efe8SAndy Shevchenko else 193*4b45efe8SAndy Shevchenko ltr |= LPSS_PRIV_LTR_SCALE_1US | val; 194*4b45efe8SAndy Shevchenko } 195*4b45efe8SAndy Shevchenko 196*4b45efe8SAndy Shevchenko if (ltr == lpss->active_ltr) 197*4b45efe8SAndy Shevchenko return; 198*4b45efe8SAndy Shevchenko 199*4b45efe8SAndy Shevchenko writel(ltr, lpss->priv + LPSS_PRIV_ACTIVELTR); 200*4b45efe8SAndy Shevchenko writel(ltr, lpss->priv + LPSS_PRIV_IDLELTR); 201*4b45efe8SAndy Shevchenko 202*4b45efe8SAndy Shevchenko /* Cache the values into lpss structure */ 203*4b45efe8SAndy Shevchenko intel_lpss_cache_ltr(lpss); 204*4b45efe8SAndy Shevchenko } 205*4b45efe8SAndy Shevchenko 206*4b45efe8SAndy Shevchenko static void intel_lpss_ltr_expose(struct intel_lpss *lpss) 207*4b45efe8SAndy Shevchenko { 208*4b45efe8SAndy Shevchenko lpss->dev->power.set_latency_tolerance = intel_lpss_ltr_set; 209*4b45efe8SAndy Shevchenko dev_pm_qos_expose_latency_tolerance(lpss->dev); 210*4b45efe8SAndy Shevchenko } 211*4b45efe8SAndy Shevchenko 212*4b45efe8SAndy Shevchenko static void intel_lpss_ltr_hide(struct intel_lpss *lpss) 213*4b45efe8SAndy Shevchenko { 214*4b45efe8SAndy Shevchenko dev_pm_qos_hide_latency_tolerance(lpss->dev); 215*4b45efe8SAndy Shevchenko lpss->dev->power.set_latency_tolerance = NULL; 216*4b45efe8SAndy Shevchenko } 217*4b45efe8SAndy Shevchenko 218*4b45efe8SAndy Shevchenko static int intel_lpss_assign_devs(struct intel_lpss *lpss) 219*4b45efe8SAndy Shevchenko { 220*4b45efe8SAndy Shevchenko unsigned int type; 221*4b45efe8SAndy Shevchenko 222*4b45efe8SAndy Shevchenko type = lpss->caps & LPSS_PRIV_CAPS_TYPE_MASK; 223*4b45efe8SAndy Shevchenko type >>= LPSS_PRIV_CAPS_TYPE_SHIFT; 224*4b45efe8SAndy Shevchenko 225*4b45efe8SAndy Shevchenko switch (type) { 226*4b45efe8SAndy Shevchenko case LPSS_DEV_I2C: 227*4b45efe8SAndy Shevchenko lpss->cell = &intel_lpss_i2c_cell; 228*4b45efe8SAndy Shevchenko break; 229*4b45efe8SAndy Shevchenko case LPSS_DEV_UART: 230*4b45efe8SAndy Shevchenko lpss->cell = &intel_lpss_uart_cell; 231*4b45efe8SAndy Shevchenko break; 232*4b45efe8SAndy Shevchenko case LPSS_DEV_SPI: 233*4b45efe8SAndy Shevchenko lpss->cell = &intel_lpss_spi_cell; 234*4b45efe8SAndy Shevchenko break; 235*4b45efe8SAndy Shevchenko default: 236*4b45efe8SAndy Shevchenko return -ENODEV; 237*4b45efe8SAndy Shevchenko } 238*4b45efe8SAndy Shevchenko 239*4b45efe8SAndy Shevchenko lpss->type = type; 240*4b45efe8SAndy Shevchenko 241*4b45efe8SAndy Shevchenko return 0; 242*4b45efe8SAndy Shevchenko } 243*4b45efe8SAndy Shevchenko 244*4b45efe8SAndy Shevchenko static bool intel_lpss_has_idma(const struct intel_lpss *lpss) 245*4b45efe8SAndy Shevchenko { 246*4b45efe8SAndy Shevchenko return (lpss->caps & LPSS_PRIV_CAPS_NO_IDMA) == 0; 247*4b45efe8SAndy Shevchenko } 248*4b45efe8SAndy Shevchenko 249*4b45efe8SAndy Shevchenko static void intel_lpss_set_remap_addr(const struct intel_lpss *lpss) 250*4b45efe8SAndy Shevchenko { 251*4b45efe8SAndy Shevchenko resource_size_t addr = lpss->info->mem->start; 252*4b45efe8SAndy Shevchenko 253*4b45efe8SAndy Shevchenko writel(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR_LO); 254*4b45efe8SAndy Shevchenko #if BITS_PER_LONG > 32 255*4b45efe8SAndy Shevchenko writel(addr >> 32, lpss->priv + LPSS_PRIV_REMAP_ADDR_HI); 256*4b45efe8SAndy Shevchenko #else 257*4b45efe8SAndy Shevchenko writel(0, lpss->priv + LPSS_PRIV_REMAP_ADDR_HI); 258*4b45efe8SAndy Shevchenko #endif 259*4b45efe8SAndy Shevchenko } 260*4b45efe8SAndy Shevchenko 261*4b45efe8SAndy Shevchenko static void intel_lpss_deassert_reset(const struct intel_lpss *lpss) 262*4b45efe8SAndy Shevchenko { 263*4b45efe8SAndy Shevchenko u32 value = LPSS_PRIV_RESETS_FUNC | LPSS_PRIV_RESETS_IDMA; 264*4b45efe8SAndy Shevchenko 265*4b45efe8SAndy Shevchenko /* Bring out the device from reset */ 266*4b45efe8SAndy Shevchenko writel(value, lpss->priv + LPSS_PRIV_RESETS); 267*4b45efe8SAndy Shevchenko } 268*4b45efe8SAndy Shevchenko 269*4b45efe8SAndy Shevchenko static void intel_lpss_init_dev(const struct intel_lpss *lpss) 270*4b45efe8SAndy Shevchenko { 271*4b45efe8SAndy Shevchenko u32 value = LPSS_PRIV_SSP_REG_DIS_DMA_FIN; 272*4b45efe8SAndy Shevchenko 273*4b45efe8SAndy Shevchenko intel_lpss_deassert_reset(lpss); 274*4b45efe8SAndy Shevchenko 275*4b45efe8SAndy Shevchenko if (!intel_lpss_has_idma(lpss)) 276*4b45efe8SAndy Shevchenko return; 277*4b45efe8SAndy Shevchenko 278*4b45efe8SAndy Shevchenko intel_lpss_set_remap_addr(lpss); 279*4b45efe8SAndy Shevchenko 280*4b45efe8SAndy Shevchenko /* Make sure that SPI multiblock DMA transfers are re-enabled */ 281*4b45efe8SAndy Shevchenko if (lpss->type == LPSS_DEV_SPI) 282*4b45efe8SAndy Shevchenko writel(value, lpss->priv + LPSS_PRIV_SSP_REG); 283*4b45efe8SAndy Shevchenko } 284*4b45efe8SAndy Shevchenko 285*4b45efe8SAndy Shevchenko static void intel_lpss_unregister_clock_tree(struct clk *clk) 286*4b45efe8SAndy Shevchenko { 287*4b45efe8SAndy Shevchenko struct clk *parent; 288*4b45efe8SAndy Shevchenko 289*4b45efe8SAndy Shevchenko while (clk) { 290*4b45efe8SAndy Shevchenko parent = clk_get_parent(clk); 291*4b45efe8SAndy Shevchenko clk_unregister(clk); 292*4b45efe8SAndy Shevchenko clk = parent; 293*4b45efe8SAndy Shevchenko } 294*4b45efe8SAndy Shevchenko } 295*4b45efe8SAndy Shevchenko 296*4b45efe8SAndy Shevchenko static int intel_lpss_register_clock_divider(struct intel_lpss *lpss, 297*4b45efe8SAndy Shevchenko const char *devname, 298*4b45efe8SAndy Shevchenko struct clk **clk) 299*4b45efe8SAndy Shevchenko { 300*4b45efe8SAndy Shevchenko char name[32]; 301*4b45efe8SAndy Shevchenko struct clk *tmp = *clk; 302*4b45efe8SAndy Shevchenko 303*4b45efe8SAndy Shevchenko snprintf(name, sizeof(name), "%s-enable", devname); 304*4b45efe8SAndy Shevchenko tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0, 305*4b45efe8SAndy Shevchenko lpss->priv, 0, 0, NULL); 306*4b45efe8SAndy Shevchenko if (IS_ERR(tmp)) 307*4b45efe8SAndy Shevchenko return PTR_ERR(tmp); 308*4b45efe8SAndy Shevchenko 309*4b45efe8SAndy Shevchenko snprintf(name, sizeof(name), "%s-div", devname); 310*4b45efe8SAndy Shevchenko tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp), 311*4b45efe8SAndy Shevchenko 0, lpss->priv, 1, 15, 16, 15, 0, 312*4b45efe8SAndy Shevchenko NULL); 313*4b45efe8SAndy Shevchenko if (IS_ERR(tmp)) 314*4b45efe8SAndy Shevchenko return PTR_ERR(tmp); 315*4b45efe8SAndy Shevchenko *clk = tmp; 316*4b45efe8SAndy Shevchenko 317*4b45efe8SAndy Shevchenko snprintf(name, sizeof(name), "%s-update", devname); 318*4b45efe8SAndy Shevchenko tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 319*4b45efe8SAndy Shevchenko CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL); 320*4b45efe8SAndy Shevchenko if (IS_ERR(tmp)) 321*4b45efe8SAndy Shevchenko return PTR_ERR(tmp); 322*4b45efe8SAndy Shevchenko *clk = tmp; 323*4b45efe8SAndy Shevchenko 324*4b45efe8SAndy Shevchenko return 0; 325*4b45efe8SAndy Shevchenko } 326*4b45efe8SAndy Shevchenko 327*4b45efe8SAndy Shevchenko static int intel_lpss_register_clock(struct intel_lpss *lpss) 328*4b45efe8SAndy Shevchenko { 329*4b45efe8SAndy Shevchenko const struct mfd_cell *cell = lpss->cell; 330*4b45efe8SAndy Shevchenko struct clk *clk; 331*4b45efe8SAndy Shevchenko char devname[24]; 332*4b45efe8SAndy Shevchenko int ret; 333*4b45efe8SAndy Shevchenko 334*4b45efe8SAndy Shevchenko if (!lpss->info->clk_rate) 335*4b45efe8SAndy Shevchenko return 0; 336*4b45efe8SAndy Shevchenko 337*4b45efe8SAndy Shevchenko /* Root clock */ 338*4b45efe8SAndy Shevchenko clk = clk_register_fixed_rate(NULL, dev_name(lpss->dev), NULL, 339*4b45efe8SAndy Shevchenko CLK_IS_ROOT, lpss->info->clk_rate); 340*4b45efe8SAndy Shevchenko if (IS_ERR(clk)) 341*4b45efe8SAndy Shevchenko return PTR_ERR(clk); 342*4b45efe8SAndy Shevchenko 343*4b45efe8SAndy Shevchenko snprintf(devname, sizeof(devname), "%s.%d", cell->name, lpss->devid); 344*4b45efe8SAndy Shevchenko 345*4b45efe8SAndy Shevchenko /* 346*4b45efe8SAndy Shevchenko * Support for clock divider only if it has some preset value. 347*4b45efe8SAndy Shevchenko * Otherwise we assume that the divider is not used. 348*4b45efe8SAndy Shevchenko */ 349*4b45efe8SAndy Shevchenko if (lpss->type != LPSS_DEV_I2C) { 350*4b45efe8SAndy Shevchenko ret = intel_lpss_register_clock_divider(lpss, devname, &clk); 351*4b45efe8SAndy Shevchenko if (ret) 352*4b45efe8SAndy Shevchenko goto err_clk_register; 353*4b45efe8SAndy Shevchenko } 354*4b45efe8SAndy Shevchenko 355*4b45efe8SAndy Shevchenko ret = -ENOMEM; 356*4b45efe8SAndy Shevchenko 357*4b45efe8SAndy Shevchenko /* Clock for the host controller */ 358*4b45efe8SAndy Shevchenko lpss->clock = clkdev_create(clk, lpss->info->clk_con_id, "%s", devname); 359*4b45efe8SAndy Shevchenko if (!lpss->clock) 360*4b45efe8SAndy Shevchenko goto err_clk_register; 361*4b45efe8SAndy Shevchenko 362*4b45efe8SAndy Shevchenko lpss->clk = clk; 363*4b45efe8SAndy Shevchenko 364*4b45efe8SAndy Shevchenko return 0; 365*4b45efe8SAndy Shevchenko 366*4b45efe8SAndy Shevchenko err_clk_register: 367*4b45efe8SAndy Shevchenko intel_lpss_unregister_clock_tree(clk); 368*4b45efe8SAndy Shevchenko 369*4b45efe8SAndy Shevchenko return ret; 370*4b45efe8SAndy Shevchenko } 371*4b45efe8SAndy Shevchenko 372*4b45efe8SAndy Shevchenko static void intel_lpss_unregister_clock(struct intel_lpss *lpss) 373*4b45efe8SAndy Shevchenko { 374*4b45efe8SAndy Shevchenko if (IS_ERR_OR_NULL(lpss->clk)) 375*4b45efe8SAndy Shevchenko return; 376*4b45efe8SAndy Shevchenko 377*4b45efe8SAndy Shevchenko clkdev_drop(lpss->clock); 378*4b45efe8SAndy Shevchenko intel_lpss_unregister_clock_tree(lpss->clk); 379*4b45efe8SAndy Shevchenko } 380*4b45efe8SAndy Shevchenko 381*4b45efe8SAndy Shevchenko int intel_lpss_probe(struct device *dev, 382*4b45efe8SAndy Shevchenko const struct intel_lpss_platform_info *info) 383*4b45efe8SAndy Shevchenko { 384*4b45efe8SAndy Shevchenko struct intel_lpss *lpss; 385*4b45efe8SAndy Shevchenko int ret; 386*4b45efe8SAndy Shevchenko 387*4b45efe8SAndy Shevchenko if (!info || !info->mem || info->irq <= 0) 388*4b45efe8SAndy Shevchenko return -EINVAL; 389*4b45efe8SAndy Shevchenko 390*4b45efe8SAndy Shevchenko lpss = devm_kzalloc(dev, sizeof(*lpss), GFP_KERNEL); 391*4b45efe8SAndy Shevchenko if (!lpss) 392*4b45efe8SAndy Shevchenko return -ENOMEM; 393*4b45efe8SAndy Shevchenko 394*4b45efe8SAndy Shevchenko lpss->priv = devm_ioremap(dev, info->mem->start + LPSS_PRIV_OFFSET, 395*4b45efe8SAndy Shevchenko LPSS_PRIV_SIZE); 396*4b45efe8SAndy Shevchenko if (!lpss->priv) 397*4b45efe8SAndy Shevchenko return -ENOMEM; 398*4b45efe8SAndy Shevchenko 399*4b45efe8SAndy Shevchenko lpss->info = info; 400*4b45efe8SAndy Shevchenko lpss->dev = dev; 401*4b45efe8SAndy Shevchenko lpss->caps = readl(lpss->priv + LPSS_PRIV_CAPS); 402*4b45efe8SAndy Shevchenko 403*4b45efe8SAndy Shevchenko dev_set_drvdata(dev, lpss); 404*4b45efe8SAndy Shevchenko 405*4b45efe8SAndy Shevchenko ret = intel_lpss_assign_devs(lpss); 406*4b45efe8SAndy Shevchenko if (ret) 407*4b45efe8SAndy Shevchenko return ret; 408*4b45efe8SAndy Shevchenko 409*4b45efe8SAndy Shevchenko intel_lpss_init_dev(lpss); 410*4b45efe8SAndy Shevchenko 411*4b45efe8SAndy Shevchenko lpss->devid = ida_simple_get(&intel_lpss_devid_ida, 0, 0, GFP_KERNEL); 412*4b45efe8SAndy Shevchenko if (lpss->devid < 0) 413*4b45efe8SAndy Shevchenko return lpss->devid; 414*4b45efe8SAndy Shevchenko 415*4b45efe8SAndy Shevchenko ret = intel_lpss_register_clock(lpss); 416*4b45efe8SAndy Shevchenko if (ret) 417*4b45efe8SAndy Shevchenko goto err_clk_register; 418*4b45efe8SAndy Shevchenko 419*4b45efe8SAndy Shevchenko intel_lpss_ltr_expose(lpss); 420*4b45efe8SAndy Shevchenko 421*4b45efe8SAndy Shevchenko ret = intel_lpss_debugfs_add(lpss); 422*4b45efe8SAndy Shevchenko if (ret) 423*4b45efe8SAndy Shevchenko dev_warn(dev, "Failed to create debugfs entries\n"); 424*4b45efe8SAndy Shevchenko 425*4b45efe8SAndy Shevchenko if (intel_lpss_has_idma(lpss)) { 426*4b45efe8SAndy Shevchenko /* 427*4b45efe8SAndy Shevchenko * Ensure the DMA driver is loaded before the host 428*4b45efe8SAndy Shevchenko * controller device appears, so that the host controller 429*4b45efe8SAndy Shevchenko * driver can request its DMA channels as early as 430*4b45efe8SAndy Shevchenko * possible. 431*4b45efe8SAndy Shevchenko * 432*4b45efe8SAndy Shevchenko * If the DMA module is not there that's OK as well. 433*4b45efe8SAndy Shevchenko */ 434*4b45efe8SAndy Shevchenko intel_lpss_request_dma_module(LPSS_IDMA64_DRIVER_NAME); 435*4b45efe8SAndy Shevchenko 436*4b45efe8SAndy Shevchenko ret = mfd_add_devices(dev, lpss->devid, &intel_lpss_idma64_cell, 437*4b45efe8SAndy Shevchenko 1, info->mem, info->irq, NULL); 438*4b45efe8SAndy Shevchenko if (ret) 439*4b45efe8SAndy Shevchenko dev_warn(dev, "Failed to add %s, fallback to PIO\n", 440*4b45efe8SAndy Shevchenko LPSS_IDMA64_DRIVER_NAME); 441*4b45efe8SAndy Shevchenko } 442*4b45efe8SAndy Shevchenko 443*4b45efe8SAndy Shevchenko ret = mfd_add_devices(dev, lpss->devid, lpss->cell, 444*4b45efe8SAndy Shevchenko 1, info->mem, info->irq, NULL); 445*4b45efe8SAndy Shevchenko if (ret) 446*4b45efe8SAndy Shevchenko goto err_remove_ltr; 447*4b45efe8SAndy Shevchenko 448*4b45efe8SAndy Shevchenko return 0; 449*4b45efe8SAndy Shevchenko 450*4b45efe8SAndy Shevchenko err_remove_ltr: 451*4b45efe8SAndy Shevchenko intel_lpss_debugfs_remove(lpss); 452*4b45efe8SAndy Shevchenko intel_lpss_ltr_hide(lpss); 453*4b45efe8SAndy Shevchenko 454*4b45efe8SAndy Shevchenko err_clk_register: 455*4b45efe8SAndy Shevchenko ida_simple_remove(&intel_lpss_devid_ida, lpss->devid); 456*4b45efe8SAndy Shevchenko 457*4b45efe8SAndy Shevchenko return ret; 458*4b45efe8SAndy Shevchenko } 459*4b45efe8SAndy Shevchenko EXPORT_SYMBOL_GPL(intel_lpss_probe); 460*4b45efe8SAndy Shevchenko 461*4b45efe8SAndy Shevchenko void intel_lpss_remove(struct device *dev) 462*4b45efe8SAndy Shevchenko { 463*4b45efe8SAndy Shevchenko struct intel_lpss *lpss = dev_get_drvdata(dev); 464*4b45efe8SAndy Shevchenko 465*4b45efe8SAndy Shevchenko mfd_remove_devices(dev); 466*4b45efe8SAndy Shevchenko intel_lpss_debugfs_remove(lpss); 467*4b45efe8SAndy Shevchenko intel_lpss_ltr_hide(lpss); 468*4b45efe8SAndy Shevchenko intel_lpss_unregister_clock(lpss); 469*4b45efe8SAndy Shevchenko ida_simple_remove(&intel_lpss_devid_ida, lpss->devid); 470*4b45efe8SAndy Shevchenko } 471*4b45efe8SAndy Shevchenko EXPORT_SYMBOL_GPL(intel_lpss_remove); 472*4b45efe8SAndy Shevchenko 473*4b45efe8SAndy Shevchenko static int resume_lpss_device(struct device *dev, void *data) 474*4b45efe8SAndy Shevchenko { 475*4b45efe8SAndy Shevchenko pm_runtime_resume(dev); 476*4b45efe8SAndy Shevchenko return 0; 477*4b45efe8SAndy Shevchenko } 478*4b45efe8SAndy Shevchenko 479*4b45efe8SAndy Shevchenko int intel_lpss_prepare(struct device *dev) 480*4b45efe8SAndy Shevchenko { 481*4b45efe8SAndy Shevchenko /* 482*4b45efe8SAndy Shevchenko * Resume both child devices before entering system sleep. This 483*4b45efe8SAndy Shevchenko * ensures that they are in proper state before they get suspended. 484*4b45efe8SAndy Shevchenko */ 485*4b45efe8SAndy Shevchenko device_for_each_child_reverse(dev, NULL, resume_lpss_device); 486*4b45efe8SAndy Shevchenko return 0; 487*4b45efe8SAndy Shevchenko } 488*4b45efe8SAndy Shevchenko EXPORT_SYMBOL_GPL(intel_lpss_prepare); 489*4b45efe8SAndy Shevchenko 490*4b45efe8SAndy Shevchenko int intel_lpss_suspend(struct device *dev) 491*4b45efe8SAndy Shevchenko { 492*4b45efe8SAndy Shevchenko return 0; 493*4b45efe8SAndy Shevchenko } 494*4b45efe8SAndy Shevchenko EXPORT_SYMBOL_GPL(intel_lpss_suspend); 495*4b45efe8SAndy Shevchenko 496*4b45efe8SAndy Shevchenko int intel_lpss_resume(struct device *dev) 497*4b45efe8SAndy Shevchenko { 498*4b45efe8SAndy Shevchenko struct intel_lpss *lpss = dev_get_drvdata(dev); 499*4b45efe8SAndy Shevchenko 500*4b45efe8SAndy Shevchenko intel_lpss_init_dev(lpss); 501*4b45efe8SAndy Shevchenko 502*4b45efe8SAndy Shevchenko return 0; 503*4b45efe8SAndy Shevchenko } 504*4b45efe8SAndy Shevchenko EXPORT_SYMBOL_GPL(intel_lpss_resume); 505*4b45efe8SAndy Shevchenko 506*4b45efe8SAndy Shevchenko static int __init intel_lpss_init(void) 507*4b45efe8SAndy Shevchenko { 508*4b45efe8SAndy Shevchenko intel_lpss_debugfs = debugfs_create_dir("intel_lpss", NULL); 509*4b45efe8SAndy Shevchenko return 0; 510*4b45efe8SAndy Shevchenko } 511*4b45efe8SAndy Shevchenko module_init(intel_lpss_init); 512*4b45efe8SAndy Shevchenko 513*4b45efe8SAndy Shevchenko static void __exit intel_lpss_exit(void) 514*4b45efe8SAndy Shevchenko { 515*4b45efe8SAndy Shevchenko debugfs_remove(intel_lpss_debugfs); 516*4b45efe8SAndy Shevchenko } 517*4b45efe8SAndy Shevchenko module_exit(intel_lpss_exit); 518*4b45efe8SAndy Shevchenko 519*4b45efe8SAndy Shevchenko MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); 520*4b45efe8SAndy Shevchenko MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 521*4b45efe8SAndy Shevchenko MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>"); 522*4b45efe8SAndy Shevchenko MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>"); 523*4b45efe8SAndy Shevchenko MODULE_DESCRIPTION("Intel LPSS core driver"); 524*4b45efe8SAndy Shevchenko MODULE_LICENSE("GPL v2"); 525