1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2015 Pengutronix, Markus Pargmann <mpa@pengutronix.de> 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/interrupt.h> 8 #include <linux/irqchip/chained_irq.h> 9 #include <linux/irqdesc.h> 10 #include <linux/irqdomain.h> 11 #include <linux/irq.h> 12 #include <linux/mfd/imx25-tsadc.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_platform.h> 16 #include <linux/platform_device.h> 17 #include <linux/regmap.h> 18 19 static const struct regmap_config mx25_tsadc_regmap_config = { 20 .fast_io = true, 21 .max_register = 8, 22 .reg_bits = 32, 23 .val_bits = 32, 24 .reg_stride = 4, 25 }; 26 27 static void mx25_tsadc_irq_handler(struct irq_desc *desc) 28 { 29 struct mx25_tsadc *tsadc = irq_desc_get_handler_data(desc); 30 struct irq_chip *chip = irq_desc_get_chip(desc); 31 u32 status; 32 33 chained_irq_enter(chip, desc); 34 35 regmap_read(tsadc->regs, MX25_TSC_TGSR, &status); 36 37 if (status & MX25_TGSR_GCQ_INT) 38 generic_handle_domain_irq(tsadc->domain, 1); 39 40 if (status & MX25_TGSR_TCQ_INT) 41 generic_handle_domain_irq(tsadc->domain, 0); 42 43 chained_irq_exit(chip, desc); 44 } 45 46 static int mx25_tsadc_domain_map(struct irq_domain *d, unsigned int irq, 47 irq_hw_number_t hwirq) 48 { 49 struct mx25_tsadc *tsadc = d->host_data; 50 51 irq_set_chip_data(irq, tsadc); 52 irq_set_chip_and_handler(irq, &dummy_irq_chip, 53 handle_level_irq); 54 irq_modify_status(irq, IRQ_NOREQUEST, IRQ_NOPROBE); 55 56 return 0; 57 } 58 59 static const struct irq_domain_ops mx25_tsadc_domain_ops = { 60 .map = mx25_tsadc_domain_map, 61 .xlate = irq_domain_xlate_onecell, 62 }; 63 64 static int mx25_tsadc_setup_irq(struct platform_device *pdev, 65 struct mx25_tsadc *tsadc) 66 { 67 struct device *dev = &pdev->dev; 68 int irq; 69 70 irq = platform_get_irq(pdev, 0); 71 if (irq < 0) 72 return irq; 73 74 tsadc->domain = irq_domain_create_simple(dev_fwnode(dev), 2, 0, &mx25_tsadc_domain_ops, 75 tsadc); 76 if (!tsadc->domain) { 77 dev_err(dev, "Failed to add irq domain\n"); 78 return -ENOMEM; 79 } 80 81 irq_set_chained_handler_and_data(irq, mx25_tsadc_irq_handler, tsadc); 82 83 return 0; 84 } 85 86 static int mx25_tsadc_unset_irq(struct platform_device *pdev) 87 { 88 struct mx25_tsadc *tsadc = platform_get_drvdata(pdev); 89 int irq = platform_get_irq(pdev, 0); 90 91 if (irq >= 0) { 92 irq_set_chained_handler_and_data(irq, NULL, NULL); 93 irq_domain_remove(tsadc->domain); 94 } 95 96 return 0; 97 } 98 99 static void mx25_tsadc_setup_clk(struct platform_device *pdev, 100 struct mx25_tsadc *tsadc) 101 { 102 unsigned clk_div; 103 104 /* 105 * According to the datasheet the ADC clock should never 106 * exceed 1,75 MHz. Base clock is the IPG and the ADC unit uses 107 * a funny clock divider. To keep the ADC conversion time constant 108 * adapt the ADC internal clock divider to the IPG clock rate. 109 */ 110 111 dev_dbg(&pdev->dev, "Found master clock at %lu Hz\n", 112 clk_get_rate(tsadc->clk)); 113 114 clk_div = DIV_ROUND_UP(clk_get_rate(tsadc->clk), 1750000); 115 dev_dbg(&pdev->dev, "Setting up ADC clock divider to %u\n", clk_div); 116 117 /* adc clock = IPG clock / (2 * div + 2) */ 118 clk_div -= 2; 119 clk_div /= 2; 120 121 /* 122 * the ADC clock divider changes its behaviour when values below 4 123 * are used: it is fixed to "/ 10" in this case 124 */ 125 clk_div = max_t(unsigned, 4, clk_div); 126 127 dev_dbg(&pdev->dev, "Resulting ADC conversion clock at %lu Hz\n", 128 clk_get_rate(tsadc->clk) / (2 * clk_div + 2)); 129 130 regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, 131 MX25_TGCR_ADCCLKCFG(0x1f), 132 MX25_TGCR_ADCCLKCFG(clk_div)); 133 } 134 135 static int mx25_tsadc_probe(struct platform_device *pdev) 136 { 137 struct device *dev = &pdev->dev; 138 struct mx25_tsadc *tsadc; 139 int ret; 140 void __iomem *iomem; 141 142 tsadc = devm_kzalloc(dev, sizeof(*tsadc), GFP_KERNEL); 143 if (!tsadc) 144 return -ENOMEM; 145 146 iomem = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 147 if (IS_ERR(iomem)) 148 return PTR_ERR(iomem); 149 150 tsadc->regs = devm_regmap_init_mmio(dev, iomem, 151 &mx25_tsadc_regmap_config); 152 if (IS_ERR(tsadc->regs)) { 153 dev_err(dev, "Failed to initialize regmap\n"); 154 return PTR_ERR(tsadc->regs); 155 } 156 157 tsadc->clk = devm_clk_get(dev, "ipg"); 158 if (IS_ERR(tsadc->clk)) { 159 dev_err(dev, "Failed to get ipg clock\n"); 160 return PTR_ERR(tsadc->clk); 161 } 162 163 /* setup clock according to the datasheet */ 164 mx25_tsadc_setup_clk(pdev, tsadc); 165 166 /* Enable clock and reset the component */ 167 regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_CLK_EN, 168 MX25_TGCR_CLK_EN); 169 regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_TSC_RST, 170 MX25_TGCR_TSC_RST); 171 172 /* Setup powersaving mode, but enable internal reference voltage */ 173 regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_POWERMODE_MASK, 174 MX25_TGCR_POWERMODE_SAVE); 175 regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_INTREFEN, 176 MX25_TGCR_INTREFEN); 177 178 ret = mx25_tsadc_setup_irq(pdev, tsadc); 179 if (ret) 180 return ret; 181 182 platform_set_drvdata(pdev, tsadc); 183 184 ret = devm_of_platform_populate(dev); 185 if (ret) 186 goto err_irq; 187 188 return 0; 189 190 err_irq: 191 mx25_tsadc_unset_irq(pdev); 192 193 return ret; 194 } 195 196 static void mx25_tsadc_remove(struct platform_device *pdev) 197 { 198 mx25_tsadc_unset_irq(pdev); 199 } 200 201 static const struct of_device_id mx25_tsadc_ids[] = { 202 { .compatible = "fsl,imx25-tsadc" }, 203 { /* Sentinel */ } 204 }; 205 MODULE_DEVICE_TABLE(of, mx25_tsadc_ids); 206 207 static struct platform_driver mx25_tsadc_driver = { 208 .driver = { 209 .name = "mx25-tsadc", 210 .of_match_table = mx25_tsadc_ids, 211 }, 212 .probe = mx25_tsadc_probe, 213 .remove = mx25_tsadc_remove, 214 }; 215 module_platform_driver(mx25_tsadc_driver); 216 217 MODULE_DESCRIPTION("MFD for ADC/TSC for Freescale mx25"); 218 MODULE_AUTHOR("Markus Pargmann <mpa@pengutronix.de>"); 219 MODULE_LICENSE("GPL v2"); 220 MODULE_ALIAS("platform:mx25-tsadc"); 221