1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2015 Pengutronix, Markus Pargmann <mpa@pengutronix.de> 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/interrupt.h> 8 #include <linux/irqchip/chained_irq.h> 9 #include <linux/irqdesc.h> 10 #include <linux/irqdomain.h> 11 #include <linux/irq.h> 12 #include <linux/mfd/imx25-tsadc.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_platform.h> 16 #include <linux/platform_device.h> 17 #include <linux/regmap.h> 18 19 static struct regmap_config mx25_tsadc_regmap_config = { 20 .fast_io = true, 21 .max_register = 8, 22 .reg_bits = 32, 23 .val_bits = 32, 24 .reg_stride = 4, 25 }; 26 27 static void mx25_tsadc_irq_handler(struct irq_desc *desc) 28 { 29 struct mx25_tsadc *tsadc = irq_desc_get_handler_data(desc); 30 struct irq_chip *chip = irq_desc_get_chip(desc); 31 u32 status; 32 33 chained_irq_enter(chip, desc); 34 35 regmap_read(tsadc->regs, MX25_TSC_TGSR, &status); 36 37 if (status & MX25_TGSR_GCQ_INT) 38 generic_handle_irq(irq_find_mapping(tsadc->domain, 1)); 39 40 if (status & MX25_TGSR_TCQ_INT) 41 generic_handle_irq(irq_find_mapping(tsadc->domain, 0)); 42 43 chained_irq_exit(chip, desc); 44 } 45 46 static int mx25_tsadc_domain_map(struct irq_domain *d, unsigned int irq, 47 irq_hw_number_t hwirq) 48 { 49 struct mx25_tsadc *tsadc = d->host_data; 50 51 irq_set_chip_data(irq, tsadc); 52 irq_set_chip_and_handler(irq, &dummy_irq_chip, 53 handle_level_irq); 54 irq_modify_status(irq, IRQ_NOREQUEST, IRQ_NOPROBE); 55 56 return 0; 57 } 58 59 static const struct irq_domain_ops mx25_tsadc_domain_ops = { 60 .map = mx25_tsadc_domain_map, 61 .xlate = irq_domain_xlate_onecell, 62 }; 63 64 static int mx25_tsadc_setup_irq(struct platform_device *pdev, 65 struct mx25_tsadc *tsadc) 66 { 67 struct device *dev = &pdev->dev; 68 struct device_node *np = dev->of_node; 69 int irq; 70 71 irq = platform_get_irq(pdev, 0); 72 if (irq <= 0) 73 return irq; 74 75 tsadc->domain = irq_domain_add_simple(np, 2, 0, &mx25_tsadc_domain_ops, 76 tsadc); 77 if (!tsadc->domain) { 78 dev_err(dev, "Failed to add irq domain\n"); 79 return -ENOMEM; 80 } 81 82 irq_set_chained_handler_and_data(irq, mx25_tsadc_irq_handler, tsadc); 83 84 return 0; 85 } 86 87 static void mx25_tsadc_setup_clk(struct platform_device *pdev, 88 struct mx25_tsadc *tsadc) 89 { 90 unsigned clk_div; 91 92 /* 93 * According to the datasheet the ADC clock should never 94 * exceed 1,75 MHz. Base clock is the IPG and the ADC unit uses 95 * a funny clock divider. To keep the ADC conversion time constant 96 * adapt the ADC internal clock divider to the IPG clock rate. 97 */ 98 99 dev_dbg(&pdev->dev, "Found master clock at %lu Hz\n", 100 clk_get_rate(tsadc->clk)); 101 102 clk_div = DIV_ROUND_UP(clk_get_rate(tsadc->clk), 1750000); 103 dev_dbg(&pdev->dev, "Setting up ADC clock divider to %u\n", clk_div); 104 105 /* adc clock = IPG clock / (2 * div + 2) */ 106 clk_div -= 2; 107 clk_div /= 2; 108 109 /* 110 * the ADC clock divider changes its behaviour when values below 4 111 * are used: it is fixed to "/ 10" in this case 112 */ 113 clk_div = max_t(unsigned, 4, clk_div); 114 115 dev_dbg(&pdev->dev, "Resulting ADC conversion clock at %lu Hz\n", 116 clk_get_rate(tsadc->clk) / (2 * clk_div + 2)); 117 118 regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, 119 MX25_TGCR_ADCCLKCFG(0x1f), 120 MX25_TGCR_ADCCLKCFG(clk_div)); 121 } 122 123 static int mx25_tsadc_probe(struct platform_device *pdev) 124 { 125 struct device *dev = &pdev->dev; 126 struct mx25_tsadc *tsadc; 127 struct resource *res; 128 int ret; 129 void __iomem *iomem; 130 131 tsadc = devm_kzalloc(dev, sizeof(*tsadc), GFP_KERNEL); 132 if (!tsadc) 133 return -ENOMEM; 134 135 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 136 iomem = devm_ioremap_resource(dev, res); 137 if (IS_ERR(iomem)) 138 return PTR_ERR(iomem); 139 140 tsadc->regs = devm_regmap_init_mmio(dev, iomem, 141 &mx25_tsadc_regmap_config); 142 if (IS_ERR(tsadc->regs)) { 143 dev_err(dev, "Failed to initialize regmap\n"); 144 return PTR_ERR(tsadc->regs); 145 } 146 147 tsadc->clk = devm_clk_get(dev, "ipg"); 148 if (IS_ERR(tsadc->clk)) { 149 dev_err(dev, "Failed to get ipg clock\n"); 150 return PTR_ERR(tsadc->clk); 151 } 152 153 /* setup clock according to the datasheet */ 154 mx25_tsadc_setup_clk(pdev, tsadc); 155 156 /* Enable clock and reset the component */ 157 regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_CLK_EN, 158 MX25_TGCR_CLK_EN); 159 regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_TSC_RST, 160 MX25_TGCR_TSC_RST); 161 162 /* Setup powersaving mode, but enable internal reference voltage */ 163 regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_POWERMODE_MASK, 164 MX25_TGCR_POWERMODE_SAVE); 165 regmap_update_bits(tsadc->regs, MX25_TSC_TGCR, MX25_TGCR_INTREFEN, 166 MX25_TGCR_INTREFEN); 167 168 ret = mx25_tsadc_setup_irq(pdev, tsadc); 169 if (ret) 170 return ret; 171 172 platform_set_drvdata(pdev, tsadc); 173 174 return devm_of_platform_populate(dev); 175 } 176 177 static int mx25_tsadc_remove(struct platform_device *pdev) 178 { 179 struct mx25_tsadc *tsadc = platform_get_drvdata(pdev); 180 int irq = platform_get_irq(pdev, 0); 181 182 if (irq) { 183 irq_set_chained_handler_and_data(irq, NULL, NULL); 184 irq_domain_remove(tsadc->domain); 185 } 186 187 return 0; 188 } 189 190 static const struct of_device_id mx25_tsadc_ids[] = { 191 { .compatible = "fsl,imx25-tsadc" }, 192 { /* Sentinel */ } 193 }; 194 MODULE_DEVICE_TABLE(of, mx25_tsadc_ids); 195 196 static struct platform_driver mx25_tsadc_driver = { 197 .driver = { 198 .name = "mx25-tsadc", 199 .of_match_table = of_match_ptr(mx25_tsadc_ids), 200 }, 201 .probe = mx25_tsadc_probe, 202 .remove = mx25_tsadc_remove, 203 }; 204 module_platform_driver(mx25_tsadc_driver); 205 206 MODULE_DESCRIPTION("MFD for ADC/TSC for Freescale mx25"); 207 MODULE_AUTHOR("Markus Pargmann <mpa@pengutronix.de>"); 208 MODULE_LICENSE("GPL v2"); 209 MODULE_ALIAS("platform:mx25-tsadc"); 210