1 /* 2 * Copyright (C) STMicroelectronics 2009 3 * Copyright (C) ST-Ericsson SA 2010 4 * 5 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com> 6 * Author: Sundar Iyer <sundar.iyer@stericsson.com> 7 * 8 * License Terms: GNU General Public License v2 9 * 10 * PRCM Unit registers 11 */ 12 13 #ifndef __MACH_PRCMU_REGS_H 14 #define __MACH_PRCMU_REGS_H 15 16 #include <mach/hardware.h> 17 18 #define PRCM_ARM_PLLDIVPS (_PRCMU_BASE + 0x118) 19 #define PRCM_ARM_CHGCLKREQ (_PRCMU_BASE + 0x114) 20 #define PRCM_PLLARM_ENABLE (_PRCMU_BASE + 0x98) 21 #define PRCM_ARMCLKFIX_MGT (_PRCMU_BASE + 0x0) 22 #define PRCM_A9_RESETN_CLR (_PRCMU_BASE + 0x1f4) 23 #define PRCM_A9_RESETN_SET (_PRCMU_BASE + 0x1f0) 24 #define PRCM_ARM_LS_CLAMP (_PRCMU_BASE + 0x30c) 25 #define PRCM_SRAM_A9 (_PRCMU_BASE + 0x308) 26 27 /* ARM WFI Standby signal register */ 28 #define PRCM_ARM_WFI_STANDBY (_PRCMU_BASE + 0x130) 29 #define PRCMU_IOCR (_PRCMU_BASE + 0x310) 30 31 /* CPU mailbox registers */ 32 #define PRCM_MBOX_CPU_VAL (_PRCMU_BASE + 0x0fc) 33 #define PRCM_MBOX_CPU_SET (_PRCMU_BASE + 0x100) 34 #define PRCM_MBOX_CPU_CLR (_PRCMU_BASE + 0x104) 35 36 /* Dual A9 core interrupt management unit registers */ 37 #define PRCM_A9_MASK_REQ (_PRCMU_BASE + 0x328) 38 #define PRCM_A9_MASK_ACK (_PRCMU_BASE + 0x32c) 39 #define PRCM_ARMITMSK31TO0 (_PRCMU_BASE + 0x11c) 40 #define PRCM_ARMITMSK63TO32 (_PRCMU_BASE + 0x120) 41 #define PRCM_ARMITMSK95TO64 (_PRCMU_BASE + 0x124) 42 #define PRCM_ARMITMSK127TO96 (_PRCMU_BASE + 0x128) 43 #define PRCM_POWER_STATE_VAL (_PRCMU_BASE + 0x25C) 44 #define PRCM_ARMITVAL31TO0 (_PRCMU_BASE + 0x260) 45 #define PRCM_ARMITVAL63TO32 (_PRCMU_BASE + 0x264) 46 #define PRCM_ARMITVAL95TO64 (_PRCMU_BASE + 0x268) 47 #define PRCM_ARMITVAL127TO96 (_PRCMU_BASE + 0x26C) 48 49 #define PRCM_HOSTACCESS_REQ (_PRCMU_BASE + 0x334) 50 #define ARM_WAKEUP_MODEM 0x1 51 52 #define PRCM_ARM_IT1_CLEAR (_PRCMU_BASE + 0x48C) 53 #define PRCM_ARM_IT1_VAL (_PRCMU_BASE + 0x494) 54 #define PRCM_HOLD_EVT (_PRCMU_BASE + 0x174) 55 56 #define PRCM_ITSTATUS0 (_PRCMU_BASE + 0x148) 57 #define PRCM_ITSTATUS1 (_PRCMU_BASE + 0x150) 58 #define PRCM_ITSTATUS2 (_PRCMU_BASE + 0x158) 59 #define PRCM_ITSTATUS3 (_PRCMU_BASE + 0x160) 60 #define PRCM_ITSTATUS4 (_PRCMU_BASE + 0x168) 61 #define PRCM_ITSTATUS5 (_PRCMU_BASE + 0x484) 62 #define PRCM_ITCLEAR5 (_PRCMU_BASE + 0x488) 63 #define PRCM_ARMIT_MASKXP70_IT (_PRCMU_BASE + 0x1018) 64 65 /* System reset register */ 66 #define PRCM_APE_SOFTRST (_PRCMU_BASE + 0x228) 67 68 /* Level shifter and clamp control registers */ 69 #define PRCM_MMIP_LS_CLAMP_SET (_PRCMU_BASE + 0x420) 70 #define PRCM_MMIP_LS_CLAMP_CLR (_PRCMU_BASE + 0x424) 71 72 /* PRCMU clock/PLL/reset registers */ 73 #define PRCM_PLLDSI_FREQ (_PRCMU_BASE + 0x500) 74 #define PRCM_PLLDSI_ENABLE (_PRCMU_BASE + 0x504) 75 #define PRCM_LCDCLK_MGT (_PRCMU_BASE + 0x044) 76 #define PRCM_MCDECLK_MGT (_PRCMU_BASE + 0x064) 77 #define PRCM_HDMICLK_MGT (_PRCMU_BASE + 0x058) 78 #define PRCM_TVCLK_MGT (_PRCMU_BASE + 0x07c) 79 #define PRCM_DSI_PLLOUT_SEL (_PRCMU_BASE + 0x530) 80 #define PRCM_DSITVCLK_DIV (_PRCMU_BASE + 0x52C) 81 #define PRCM_APE_RESETN_SET (_PRCMU_BASE + 0x1E4) 82 #define PRCM_APE_RESETN_CLR (_PRCMU_BASE + 0x1E8) 83 84 /* ePOD and memory power signal control registers */ 85 #define PRCM_EPOD_C_SET (_PRCMU_BASE + 0x410) 86 #define PRCM_SRAM_LS_SLEEP (_PRCMU_BASE + 0x304) 87 88 /* Debug power control unit registers */ 89 #define PRCM_POWER_STATE_SET (_PRCMU_BASE + 0x254) 90 91 /* Miscellaneous unit registers */ 92 #define PRCM_DSI_SW_RESET (_PRCMU_BASE + 0x324) 93 94 #endif /* __MACH_PRCMU_REGS_H */ 95