1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * CS42L43 core driver 4 * 5 * Copyright (C) 2022-2023 Cirrus Logic, Inc. and 6 * Cirrus Logic International Semiconductor Ltd. 7 */ 8 9 #include <linux/array_size.h> 10 #include <linux/bitops.h> 11 #include <linux/build_bug.h> 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/err.h> 15 #include <linux/firmware.h> 16 #include <linux/gpio/consumer.h> 17 #include <linux/jiffies.h> 18 #include <linux/mfd/core.h> 19 #include <linux/mfd/cs42l43.h> 20 #include <linux/mfd/cs42l43-regs.h> 21 #include <linux/module.h> 22 #include <linux/pm.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/regmap.h> 25 #include <linux/soundwire/sdw.h> 26 #include <linux/types.h> 27 28 #include "cs42l43.h" 29 30 #define CS42L43_RESET_DELAY_MS 20 31 32 #define CS42L43_SDW_ATTACH_TIMEOUT_MS 5000 33 #define CS42L43_SDW_DETACH_TIMEOUT_MS 100 34 35 #define CS42L43_MCU_BOOT_STAGE1 1 36 #define CS42L43_MCU_BOOT_STAGE2 2 37 #define CS42L43_MCU_BOOT_STAGE3 3 38 #define CS42L43_MCU_BOOT_STAGE4 4 39 #define CS42L43_MCU_POLL_US 5000 40 #define CS42L43_MCU_CMD_TIMEOUT_US 20000 41 #define CS42L43_MCU_UPDATE_FORMAT 3 42 #define CS42L43_MCU_UPDATE_OFFSET 0x100000 43 #define CS42L43_MCU_UPDATE_TIMEOUT_US 500000 44 #define CS42L43_MCU_UPDATE_RETRIES 5 45 46 #define CS42L43_MCU_ROM_REV 0x2001 47 #define CS42L43_MCU_ROM_BIOS_REV 0x0000 48 49 #define CS42L43_MCU_SUPPORTED_REV 0x2105 50 #define CS42L43_MCU_SHADOW_REGS_REQUIRED_REV 0x2200 51 #define CS42L43_BIOS_SHADOW_REGS_REQUIRED_REV 0x1002 52 #define CS42L43_MCU_SUPPORTED_BIOS_REV 0x0001 53 54 #define CS42L43_VDDP_DELAY_US 50 55 #define CS42L43_VDDD_DELAY_US 1000 56 57 #define CS42L43_AUTOSUSPEND_TIME_MS 250 58 59 struct cs42l43_patch_header { 60 __le16 version; 61 __le16 size; 62 __u8 reserved; 63 __u8 secure; 64 __le16 bss_size; 65 __le32 apply_addr; 66 __le32 checksum; 67 __le32 sha; 68 __le16 swrev; 69 __le16 patchid; 70 __le16 ipxid; 71 __le16 romver; 72 __le32 load_addr; 73 } __packed; 74 75 static const struct reg_sequence cs42l43_reva_patch[] = { 76 { 0x4000, 0x00000055 }, 77 { 0x4000, 0x000000AA }, 78 { 0x10084, 0x00000000 }, 79 { 0x1741C, 0x00CD2000 }, 80 { 0x1718C, 0x00000003 }, 81 { 0x4000, 0x00000000 }, 82 { CS42L43_CCM_BLK_CLK_CONTROL, 0x00000002 }, 83 { CS42L43_HPPATHVOL, 0x011B011B }, 84 { CS42L43_OSC_DIV_SEL, 0x00000001 }, 85 { CS42L43_DACCNFG2, 0x00000005 }, 86 { CS42L43_MIC_DETECT_CONTROL_ANDROID, 0x80790079 }, 87 { CS42L43_RELID, 0x0000000F }, 88 }; 89 90 const struct reg_default cs42l43_reg_default[CS42L43_N_DEFAULTS] = { 91 { CS42L43_DRV_CTRL1, 0x000186C0 }, 92 { CS42L43_DRV_CTRL3, 0x286DB018 }, 93 { CS42L43_DRV_CTRL4, 0x000006D8 }, 94 { CS42L43_DRV_CTRL_5, 0x136C00C0 }, 95 { CS42L43_GPIO_CTRL1, 0x00000707 }, 96 { CS42L43_GPIO_CTRL2, 0x00000000 }, 97 { CS42L43_GPIO_FN_SEL, 0x00000004 }, 98 { CS42L43_MCLK_SRC_SEL, 0x00000000 }, 99 { CS42L43_SAMPLE_RATE1, 0x00000003 }, 100 { CS42L43_SAMPLE_RATE2, 0x00000003 }, 101 { CS42L43_SAMPLE_RATE3, 0x00000003 }, 102 { CS42L43_SAMPLE_RATE4, 0x00000003 }, 103 { CS42L43_PLL_CONTROL, 0x00000000 }, 104 { CS42L43_FS_SELECT1, 0x00000000 }, 105 { CS42L43_FS_SELECT2, 0x00000000 }, 106 { CS42L43_FS_SELECT3, 0x00000000 }, 107 { CS42L43_FS_SELECT4, 0x00000000 }, 108 { CS42L43_PDM_CONTROL, 0x00000000 }, 109 { CS42L43_ASP_CLK_CONFIG1, 0x00010001 }, 110 { CS42L43_ASP_CLK_CONFIG2, 0x00000000 }, 111 { CS42L43_OSC_DIV_SEL, 0x00000001 }, 112 { CS42L43_ADC_B_CTRL1, 0x00000000 }, 113 { CS42L43_ADC_B_CTRL2, 0x00000000 }, 114 { CS42L43_DECIM_HPF_WNF_CTRL1, 0x00000001 }, 115 { CS42L43_DECIM_HPF_WNF_CTRL2, 0x00000001 }, 116 { CS42L43_DECIM_HPF_WNF_CTRL3, 0x00000001 }, 117 { CS42L43_DECIM_HPF_WNF_CTRL4, 0x00000001 }, 118 { CS42L43B_DECIM_HPF_WNF_CTRL5, 0x00000001 }, 119 { CS42L43B_DECIM_HPF_WNF_CTRL6, 0x00000001 }, 120 { CS42L43_DMIC_PDM_CTRL, 0x00000000 }, 121 { CS42L43_DECIM_VOL_CTRL_CH1_CH2, 0x20122012 }, 122 { CS42L43_DECIM_VOL_CTRL_CH3_CH4, 0x20122012 }, 123 { CS42L43B_DECIM_VOL_CTRL_CH1_CH2, 0x20122012 }, 124 { CS42L43B_DECIM_VOL_CTRL_CH3_CH4, 0x20122012 }, 125 { CS42L43B_DECIM_VOL_CTRL_CH5_CH6, 0x20122012 }, 126 { CS42L43_INTP_VOLUME_CTRL1, 0x00000180 }, 127 { CS42L43_INTP_VOLUME_CTRL2, 0x00000180 }, 128 { CS42L43_AMP1_2_VOL_RAMP, 0x00000022 }, 129 { CS42L43_ASP_CTRL, 0x00000004 }, 130 { CS42L43_ASP_FSYNC_CTRL1, 0x000000FA }, 131 { CS42L43_ASP_FSYNC_CTRL2, 0x00000001 }, 132 { CS42L43_ASP_FSYNC_CTRL3, 0x00000000 }, 133 { CS42L43_ASP_FSYNC_CTRL4, 0x000001F4 }, 134 { CS42L43_ASP_DATA_CTRL, 0x0000003A }, 135 { CS42L43_ASP_RX_EN, 0x00000000 }, 136 { CS42L43_ASP_TX_EN, 0x00000000 }, 137 { CS42L43_ASP_RX_CH1_CTRL, 0x00170001 }, 138 { CS42L43_ASP_RX_CH2_CTRL, 0x00170031 }, 139 { CS42L43_ASP_RX_CH3_CTRL, 0x00170061 }, 140 { CS42L43_ASP_RX_CH4_CTRL, 0x00170091 }, 141 { CS42L43_ASP_RX_CH5_CTRL, 0x001700C1 }, 142 { CS42L43_ASP_RX_CH6_CTRL, 0x001700F1 }, 143 { CS42L43_ASP_TX_CH1_CTRL, 0x00170001 }, 144 { CS42L43_ASP_TX_CH2_CTRL, 0x00170031 }, 145 { CS42L43_ASP_TX_CH3_CTRL, 0x00170061 }, 146 { CS42L43_ASP_TX_CH4_CTRL, 0x00170091 }, 147 { CS42L43_ASP_TX_CH5_CTRL, 0x001700C1 }, 148 { CS42L43_ASP_TX_CH6_CTRL, 0x001700F1 }, 149 { CS42L43_ASPTX1_INPUT, 0x00000000 }, 150 { CS42L43_ASPTX2_INPUT, 0x00000000 }, 151 { CS42L43_ASPTX3_INPUT, 0x00000000 }, 152 { CS42L43_ASPTX4_INPUT, 0x00000000 }, 153 { CS42L43_ASPTX5_INPUT, 0x00000000 }, 154 { CS42L43_ASPTX6_INPUT, 0x00000000 }, 155 { CS42L43_SWIRE_DP1_CH1_INPUT, 0x00000000 }, 156 { CS42L43_SWIRE_DP1_CH2_INPUT, 0x00000000 }, 157 { CS42L43_SWIRE_DP1_CH3_INPUT, 0x00000000 }, 158 { CS42L43_SWIRE_DP1_CH4_INPUT, 0x00000000 }, 159 { CS42L43_SWIRE_DP2_CH1_INPUT, 0x00000000 }, 160 { CS42L43_SWIRE_DP2_CH2_INPUT, 0x00000000 }, 161 { CS42L43_SWIRE_DP3_CH1_INPUT, 0x00000000 }, 162 { CS42L43_SWIRE_DP3_CH2_INPUT, 0x00000000 }, 163 { CS42L43B_SWIRE_DP3_CH3_INPUT, 0x00000000 }, 164 { CS42L43B_SWIRE_DP3_CH4_INPUT, 0x00000000 }, 165 { CS42L43_SWIRE_DP4_CH1_INPUT, 0x00000000 }, 166 { CS42L43_SWIRE_DP4_CH2_INPUT, 0x00000000 }, 167 { CS42L43B_SWIRE_DP4_CH3_INPUT, 0x00000000 }, 168 { CS42L43B_SWIRE_DP4_CH4_INPUT, 0x00000000 }, 169 { CS42L43_ASRC_INT1_INPUT1, 0x00000000 }, 170 { CS42L43_ASRC_INT2_INPUT1, 0x00000000 }, 171 { CS42L43_ASRC_INT3_INPUT1, 0x00000000 }, 172 { CS42L43_ASRC_INT4_INPUT1, 0x00000000 }, 173 { CS42L43_ASRC_DEC1_INPUT1, 0x00000000 }, 174 { CS42L43_ASRC_DEC2_INPUT1, 0x00000000 }, 175 { CS42L43_ASRC_DEC3_INPUT1, 0x00000000 }, 176 { CS42L43_ASRC_DEC4_INPUT1, 0x00000000 }, 177 { CS42L43_ISRC1INT1_INPUT1, 0x00000000 }, 178 { CS42L43_ISRC1INT2_INPUT1, 0x00000000 }, 179 { CS42L43_ISRC1DEC1_INPUT1, 0x00000000 }, 180 { CS42L43_ISRC1DEC2_INPUT1, 0x00000000 }, 181 { CS42L43B_ISRC1DEC3_INPUT1, 0x00000000 }, 182 { CS42L43B_ISRC1DEC4_INPUT1, 0x00000000 }, 183 { CS42L43_ISRC2INT1_INPUT1, 0x00000000 }, 184 { CS42L43_ISRC2INT2_INPUT1, 0x00000000 }, 185 { CS42L43_ISRC2DEC1_INPUT1, 0x00000000 }, 186 { CS42L43_ISRC2DEC2_INPUT1, 0x00000000 }, 187 { CS42L43B_ISRC2DEC3_INPUT1, 0x00000000 }, 188 { CS42L43B_ISRC2DEC4_INPUT1, 0x00000000 }, 189 { CS42L43_EQ1MIX_INPUT1, 0x00800000 }, 190 { CS42L43_EQ1MIX_INPUT2, 0x00800000 }, 191 { CS42L43_EQ1MIX_INPUT3, 0x00800000 }, 192 { CS42L43_EQ1MIX_INPUT4, 0x00800000 }, 193 { CS42L43_EQ2MIX_INPUT1, 0x00800000 }, 194 { CS42L43_EQ2MIX_INPUT2, 0x00800000 }, 195 { CS42L43_EQ2MIX_INPUT3, 0x00800000 }, 196 { CS42L43_EQ2MIX_INPUT4, 0x00800000 }, 197 { CS42L43_SPDIF1_INPUT1, 0x00000000 }, 198 { CS42L43_SPDIF2_INPUT1, 0x00000000 }, 199 { CS42L43_AMP1MIX_INPUT1, 0x00800000 }, 200 { CS42L43_AMP1MIX_INPUT2, 0x00800000 }, 201 { CS42L43_AMP1MIX_INPUT3, 0x00800000 }, 202 { CS42L43_AMP1MIX_INPUT4, 0x00800000 }, 203 { CS42L43_AMP2MIX_INPUT1, 0x00800000 }, 204 { CS42L43_AMP2MIX_INPUT2, 0x00800000 }, 205 { CS42L43_AMP2MIX_INPUT3, 0x00800000 }, 206 { CS42L43_AMP2MIX_INPUT4, 0x00800000 }, 207 { CS42L43_AMP3MIX_INPUT1, 0x00800000 }, 208 { CS42L43_AMP3MIX_INPUT2, 0x00800000 }, 209 { CS42L43_AMP3MIX_INPUT3, 0x00800000 }, 210 { CS42L43_AMP3MIX_INPUT4, 0x00800000 }, 211 { CS42L43_AMP4MIX_INPUT1, 0x00800000 }, 212 { CS42L43_AMP4MIX_INPUT2, 0x00800000 }, 213 { CS42L43_AMP4MIX_INPUT3, 0x00800000 }, 214 { CS42L43_AMP4MIX_INPUT4, 0x00800000 }, 215 { CS42L43_ASRC_INT_ENABLES, 0x00000100 }, 216 { CS42L43_ASRC_DEC_ENABLES, 0x00000100 }, 217 { CS42L43_PDNCNTL, 0x00000000 }, 218 { CS42L43_RINGSENSE_DEB_CTRL, 0x0000001B }, 219 { CS42L43_TIPSENSE_DEB_CTRL, 0x0000001B }, 220 { CS42L43_HS2, 0x050106F3 }, 221 { CS42L43_STEREO_MIC_CTRL, 0x00000000 }, 222 { CS42L43_STEREO_MIC_CLAMP_CTRL, 0x00000001 }, 223 { CS42L43_BLOCK_EN2, 0x00000000 }, 224 { CS42L43_BLOCK_EN3, 0x00000000 }, 225 { CS42L43_BLOCK_EN4, 0x00000000 }, 226 { CS42L43_BLOCK_EN5, 0x00000000 }, 227 { CS42L43_BLOCK_EN6, 0x00000000 }, 228 { CS42L43_BLOCK_EN7, 0x00000000 }, 229 { CS42L43_BLOCK_EN8, 0x00000000 }, 230 { CS42L43_BLOCK_EN9, 0x00000000 }, 231 { CS42L43_BLOCK_EN10, 0x00000000 }, 232 { CS42L43_BLOCK_EN11, 0x00000000 }, 233 { CS42L43_TONE_CH1_CTRL, 0x00000000 }, 234 { CS42L43_TONE_CH2_CTRL, 0x00000000 }, 235 { CS42L43_MIC_DETECT_CONTROL_1, 0x00000003 }, 236 { CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL, 0x02000003 }, 237 { CS42L43_MIC_DETECT_CONTROL_ANDROID, 0x80790079 }, 238 { CS42L43_ISRC1_CTRL, 0x00000000 }, 239 { CS42L43_ISRC2_CTRL, 0x00000000 }, 240 { CS42L43_CTRL_REG, 0x00000006 }, 241 { CS42L43_FDIV_FRAC, 0x40000000 }, 242 { CS42L43_CAL_RATIO, 0x00000080 }, 243 { CS42L43_SPI_CLK_CONFIG1, 0x00000001 }, 244 { CS42L43_SPI_CONFIG1, 0x00000000 }, 245 { CS42L43_SPI_CONFIG2, 0x00000000 }, 246 { CS42L43_SPI_CONFIG3, 0x00000001 }, 247 { CS42L43_SPI_CONFIG4, 0x00000000 }, 248 { CS42L43_TRAN_CONFIG3, 0x00000000 }, 249 { CS42L43_TRAN_CONFIG4, 0x00000000 }, 250 { CS42L43_TRAN_CONFIG5, 0x00000000 }, 251 { CS42L43_TRAN_CONFIG6, 0x00000000 }, 252 { CS42L43_TRAN_CONFIG7, 0x00000000 }, 253 { CS42L43_TRAN_CONFIG8, 0x00000000 }, 254 { CS42L43_DACCNFG1, 0x00000008 }, 255 { CS42L43_DACCNFG2, 0x00000005 }, 256 { CS42L43_HPPATHVOL, 0x011B011B }, 257 { CS42L43_PGAVOL, 0x00003470 }, 258 { CS42L43_LOADDETENA, 0x00000000 }, 259 { CS42L43_CTRL, 0x00000037 }, 260 { CS42L43_COEFF_DATA_IN0, 0x00000000 }, 261 { CS42L43_COEFF_RD_WR0, 0x00000000 }, 262 { CS42L43_START_EQZ0, 0x00000000 }, 263 { CS42L43_MUTE_EQ_IN0, 0x00000000 }, 264 { CS42L43_DECIM_MASK, 0x0000000F }, 265 { CS42L43_EQ_MIX_MASK, 0x0000000F }, 266 { CS42L43_ASP_MASK, 0x000000FF }, 267 { CS42L43_PLL_MASK, 0x00000003 }, 268 { CS42L43_SOFT_MASK, 0x0000FFFF }, 269 { CS42L43_SWIRE_MASK, 0x00007FFF }, 270 { CS42L43_MSM_MASK, 0x00000FFF }, 271 { CS42L43_ACC_DET_MASK, 0x00000FFF }, 272 { CS42L43_I2C_TGT_MASK, 0x00000003 }, 273 { CS42L43_SPI_MSTR_MASK, 0x00000007 }, 274 { CS42L43_SW_TO_SPI_BRIDGE_MASK, 0x00000001 }, 275 { CS42L43_OTP_MASK, 0x00000007 }, 276 { CS42L43_CLASS_D_AMP_MASK, 0x00003FFF }, 277 { CS42L43_GPIO_INT_MASK, 0x0000003F }, 278 { CS42L43_ASRC_MASK, 0x0000000F }, 279 { CS42L43_HPOUT_MASK, 0x00000003 }, 280 }; 281 EXPORT_SYMBOL_NS_GPL(cs42l43_reg_default, "MFD_CS42L43"); 282 283 bool cs42l43_readable_register(struct device *dev, unsigned int reg) 284 { 285 struct cs42l43 *cs42l43 = dev_get_drvdata(dev); 286 287 switch (reg) { 288 case CS42L43_DEVID: 289 case CS42L43_REVID: 290 case CS42L43_RELID: 291 case CS42L43_SFT_RESET: 292 case CS42L43_DRV_CTRL1: 293 case CS42L43_DRV_CTRL3: 294 case CS42L43_DRV_CTRL4: 295 case CS42L43_DRV_CTRL_5: 296 case CS42L43_GPIO_CTRL1: 297 case CS42L43_GPIO_CTRL2: 298 case CS42L43_GPIO_STS: 299 case CS42L43_GPIO_FN_SEL: 300 case CS42L43_MCLK_SRC_SEL: 301 case CS42L43_SAMPLE_RATE1 ... CS42L43_SAMPLE_RATE4: 302 case CS42L43_PLL_CONTROL: 303 case CS42L43_FS_SELECT1 ... CS42L43_FS_SELECT4: 304 case CS42L43_PDM_CONTROL: 305 case CS42L43_ASP_CLK_CONFIG1 ... CS42L43_ASP_CLK_CONFIG2: 306 case CS42L43_OSC_DIV_SEL: 307 case CS42L43_ADC_B_CTRL1 ... CS42L43_ADC_B_CTRL2: 308 case CS42L43_DECIM_HPF_WNF_CTRL1 ... CS42L43_DECIM_HPF_WNF_CTRL4: 309 case CS42L43_DMIC_PDM_CTRL: 310 case CS42L43_INTP_VOLUME_CTRL1 ... CS42L43_INTP_VOLUME_CTRL2: 311 case CS42L43_AMP1_2_VOL_RAMP: 312 case CS42L43_ASP_CTRL: 313 case CS42L43_ASP_FSYNC_CTRL1 ... CS42L43_ASP_FSYNC_CTRL4: 314 case CS42L43_ASP_DATA_CTRL: 315 case CS42L43_ASP_RX_EN ... CS42L43_ASP_TX_EN: 316 case CS42L43_ASP_RX_CH1_CTRL ... CS42L43_ASP_RX_CH6_CTRL: 317 case CS42L43_ASP_TX_CH1_CTRL ... CS42L43_ASP_TX_CH6_CTRL: 318 case CS42L43_OTP_REVISION_ID: 319 case CS42L43_ASPTX1_INPUT: 320 case CS42L43_ASPTX2_INPUT: 321 case CS42L43_ASPTX3_INPUT: 322 case CS42L43_ASPTX4_INPUT: 323 case CS42L43_ASPTX5_INPUT: 324 case CS42L43_ASPTX6_INPUT: 325 case CS42L43_SWIRE_DP1_CH1_INPUT: 326 case CS42L43_SWIRE_DP1_CH2_INPUT: 327 case CS42L43_SWIRE_DP1_CH3_INPUT: 328 case CS42L43_SWIRE_DP1_CH4_INPUT: 329 case CS42L43_SWIRE_DP2_CH1_INPUT: 330 case CS42L43_SWIRE_DP2_CH2_INPUT: 331 case CS42L43_SWIRE_DP3_CH1_INPUT: 332 case CS42L43_SWIRE_DP3_CH2_INPUT: 333 case CS42L43_SWIRE_DP4_CH1_INPUT: 334 case CS42L43_SWIRE_DP4_CH2_INPUT: 335 case CS42L43_ASRC_INT1_INPUT1: 336 case CS42L43_ASRC_INT2_INPUT1: 337 case CS42L43_ASRC_INT3_INPUT1: 338 case CS42L43_ASRC_INT4_INPUT1: 339 case CS42L43_ASRC_DEC1_INPUT1: 340 case CS42L43_ASRC_DEC2_INPUT1: 341 case CS42L43_ASRC_DEC3_INPUT1: 342 case CS42L43_ASRC_DEC4_INPUT1: 343 case CS42L43_ISRC1INT1_INPUT1: 344 case CS42L43_ISRC1INT2_INPUT1: 345 case CS42L43_ISRC1DEC1_INPUT1: 346 case CS42L43_ISRC1DEC2_INPUT1: 347 case CS42L43_ISRC2INT1_INPUT1: 348 case CS42L43_ISRC2INT2_INPUT1: 349 case CS42L43_ISRC2DEC1_INPUT1: 350 case CS42L43_ISRC2DEC2_INPUT1: 351 case CS42L43_EQ1MIX_INPUT1 ... CS42L43_EQ1MIX_INPUT4: 352 case CS42L43_EQ2MIX_INPUT1 ... CS42L43_EQ2MIX_INPUT4: 353 case CS42L43_SPDIF1_INPUT1: 354 case CS42L43_SPDIF2_INPUT1: 355 case CS42L43_AMP1MIX_INPUT1 ... CS42L43_AMP1MIX_INPUT4: 356 case CS42L43_AMP2MIX_INPUT1 ... CS42L43_AMP2MIX_INPUT4: 357 case CS42L43_AMP3MIX_INPUT1 ... CS42L43_AMP3MIX_INPUT4: 358 case CS42L43_AMP4MIX_INPUT1 ... CS42L43_AMP4MIX_INPUT4: 359 case CS42L43_ASRC_INT_ENABLES ... CS42L43_ASRC_DEC_ENABLES: 360 case CS42L43_PDNCNTL: 361 case CS42L43_RINGSENSE_DEB_CTRL: 362 case CS42L43_TIPSENSE_DEB_CTRL: 363 case CS42L43_TIP_RING_SENSE_INTERRUPT_STATUS: 364 case CS42L43_HS2: 365 case CS42L43_HS_STAT: 366 case CS42L43_MCU_SW_INTERRUPT: 367 case CS42L43_STEREO_MIC_CTRL: 368 case CS42L43_STEREO_MIC_CLAMP_CTRL: 369 case CS42L43_BLOCK_EN2 ... CS42L43_BLOCK_EN11: 370 case CS42L43_TONE_CH1_CTRL ... CS42L43_TONE_CH2_CTRL: 371 case CS42L43_MIC_DETECT_CONTROL_1: 372 case CS42L43_DETECT_STATUS_1: 373 case CS42L43_HS_BIAS_SENSE_AND_CLAMP_AUTOCONTROL: 374 case CS42L43_MIC_DETECT_CONTROL_ANDROID: 375 case CS42L43_ISRC1_CTRL: 376 case CS42L43_ISRC2_CTRL: 377 case CS42L43_CTRL_REG: 378 case CS42L43_FDIV_FRAC: 379 case CS42L43_CAL_RATIO: 380 case CS42L43_SPI_CLK_CONFIG1: 381 case CS42L43_SPI_CONFIG1 ... CS42L43_SPI_CONFIG4: 382 case CS42L43_SPI_STATUS1 ... CS42L43_SPI_STATUS2: 383 case CS42L43_TRAN_CONFIG1 ... CS42L43_TRAN_CONFIG8: 384 case CS42L43_TRAN_STATUS1 ... CS42L43_TRAN_STATUS3: 385 case CS42L43_TX_DATA: 386 case CS42L43_RX_DATA: 387 case CS42L43_DACCNFG1 ... CS42L43_DACCNFG2: 388 case CS42L43_HPPATHVOL: 389 case CS42L43_PGAVOL: 390 case CS42L43_LOADDETRESULTS: 391 case CS42L43_LOADDETENA: 392 case CS42L43_CTRL: 393 case CS42L43_COEFF_DATA_IN0: 394 case CS42L43_COEFF_RD_WR0: 395 case CS42L43_INIT_DONE0: 396 case CS42L43_START_EQZ0: 397 case CS42L43_MUTE_EQ_IN0: 398 case CS42L43_DECIM_INT ... CS42L43_HPOUT_INT: 399 case CS42L43_DECIM_MASK ... CS42L43_HPOUT_MASK: 400 case CS42L43_DECIM_INT_SHADOW ... CS42L43_HP_OUT_SHADOW: 401 case CS42L43_BOOT_CONTROL: 402 case CS42L43_BLOCK_EN: 403 case CS42L43_SHUTTER_CONTROL: 404 case CS42L43B_MCU_SW_REV ... CS42L43B_MCU_RAM_MAX: 405 return true; // registers present on all variants 406 case CS42L43_MCU_SW_REV ... CS42L43B_MCU_SW_REV - 1: 407 case CS42L43B_MCU_RAM_MAX + 1 ... CS42L43_MCU_RAM_MAX: 408 case CS42L43_DECIM_VOL_CTRL_CH1_CH2 ... CS42L43_DECIM_VOL_CTRL_CH3_CH4: 409 return cs42l43->variant_id == CS42L43_DEVID_VAL; // regs only in CS42L43 variant 410 case CS42L43B_DECIM_VOL_CTRL_CH1_CH2 ... CS42L43B_DECIM_HPF_WNF_CTRL6: 411 case CS42L43B_SWIRE_DP3_CH3_INPUT ... CS42L43B_SWIRE_DP4_CH4_INPUT: 412 case CS42L43B_ISRC1DEC3_INPUT1 ... CS42L43B_ISRC2DEC4_INPUT1: 413 return cs42l43->variant_id == CS42L43B_DEVID_VAL; // regs only in CS42L43B variant 414 default: 415 return false; 416 } 417 } 418 EXPORT_SYMBOL_NS_GPL(cs42l43_readable_register, "MFD_CS42L43"); 419 420 bool cs42l43_precious_register(struct device *dev, unsigned int reg) 421 { 422 switch (reg) { 423 case CS42L43_SFT_RESET: 424 case CS42L43_TX_DATA: 425 case CS42L43_RX_DATA: 426 case CS42L43_DECIM_INT ... CS42L43_HPOUT_INT: 427 case CS42L43_MCU_SW_REV ... CS42L43_MCU_RAM_MAX: 428 return true; 429 default: 430 return false; 431 } 432 } 433 EXPORT_SYMBOL_NS_GPL(cs42l43_precious_register, "MFD_CS42L43"); 434 435 bool cs42l43_volatile_register(struct device *dev, unsigned int reg) 436 { 437 switch (reg) { 438 case CS42L43_DEVID: 439 case CS42L43_REVID: 440 case CS42L43_RELID: 441 case CS42L43_GPIO_STS: 442 case CS42L43_OTP_REVISION_ID: 443 case CS42L43_TIP_RING_SENSE_INTERRUPT_STATUS: 444 case CS42L43_HS_STAT: 445 case CS42L43_MCU_SW_INTERRUPT: 446 case CS42L43_DETECT_STATUS_1: 447 case CS42L43_SPI_STATUS1 ... CS42L43_SPI_STATUS2: 448 case CS42L43_TRAN_CONFIG1 ... CS42L43_TRAN_CONFIG2: 449 case CS42L43_TRAN_CONFIG8: 450 case CS42L43_TRAN_STATUS1 ... CS42L43_TRAN_STATUS3: 451 case CS42L43_LOADDETRESULTS: 452 case CS42L43_INIT_DONE0: 453 case CS42L43_DECIM_INT_SHADOW ... CS42L43_HP_OUT_SHADOW: 454 case CS42L43_BOOT_CONTROL: 455 case CS42L43_BLOCK_EN: 456 return true; 457 default: 458 return cs42l43_precious_register(dev, reg); 459 } 460 } 461 EXPORT_SYMBOL_NS_GPL(cs42l43_volatile_register, "MFD_CS42L43"); 462 463 #define CS42L43_IRQ_OFFSET(reg) ((CS42L43_##reg##_INT) - CS42L43_DECIM_INT) 464 465 #define CS42L43_IRQ_REG(name, reg) REGMAP_IRQ_REG(CS42L43_##name, \ 466 CS42L43_IRQ_OFFSET(reg), \ 467 CS42L43_##name##_INT_MASK) 468 469 static const struct regmap_irq cs42l43_regmap_irqs[] = { 470 CS42L43_IRQ_REG(PLL_LOST_LOCK, PLL), 471 CS42L43_IRQ_REG(PLL_READY, PLL), 472 473 CS42L43_IRQ_REG(HP_STARTUP_DONE, MSM), 474 CS42L43_IRQ_REG(HP_SHUTDOWN_DONE, MSM), 475 CS42L43_IRQ_REG(HSDET_DONE, MSM), 476 CS42L43_IRQ_REG(TIPSENSE_UNPLUG_DB, MSM), 477 CS42L43_IRQ_REG(TIPSENSE_PLUG_DB, MSM), 478 CS42L43_IRQ_REG(RINGSENSE_UNPLUG_DB, MSM), 479 CS42L43_IRQ_REG(RINGSENSE_PLUG_DB, MSM), 480 CS42L43_IRQ_REG(TIPSENSE_UNPLUG_PDET, MSM), 481 CS42L43_IRQ_REG(TIPSENSE_PLUG_PDET, MSM), 482 CS42L43_IRQ_REG(RINGSENSE_UNPLUG_PDET, MSM), 483 CS42L43_IRQ_REG(RINGSENSE_PLUG_PDET, MSM), 484 485 CS42L43_IRQ_REG(HS2_BIAS_SENSE, ACC_DET), 486 CS42L43_IRQ_REG(HS1_BIAS_SENSE, ACC_DET), 487 CS42L43_IRQ_REG(DC_DETECT1_FALSE, ACC_DET), 488 CS42L43_IRQ_REG(DC_DETECT1_TRUE, ACC_DET), 489 CS42L43_IRQ_REG(HSBIAS_CLAMPED, ACC_DET), 490 CS42L43_IRQ_REG(HS3_4_BIAS_SENSE, ACC_DET), 491 492 CS42L43_IRQ_REG(AMP2_CLK_STOP_FAULT, CLASS_D_AMP), 493 CS42L43_IRQ_REG(AMP1_CLK_STOP_FAULT, CLASS_D_AMP), 494 CS42L43_IRQ_REG(AMP2_VDDSPK_FAULT, CLASS_D_AMP), 495 CS42L43_IRQ_REG(AMP1_VDDSPK_FAULT, CLASS_D_AMP), 496 CS42L43_IRQ_REG(AMP2_SHUTDOWN_DONE, CLASS_D_AMP), 497 CS42L43_IRQ_REG(AMP1_SHUTDOWN_DONE, CLASS_D_AMP), 498 CS42L43_IRQ_REG(AMP2_STARTUP_DONE, CLASS_D_AMP), 499 CS42L43_IRQ_REG(AMP1_STARTUP_DONE, CLASS_D_AMP), 500 CS42L43_IRQ_REG(AMP2_THERM_SHDN, CLASS_D_AMP), 501 CS42L43_IRQ_REG(AMP1_THERM_SHDN, CLASS_D_AMP), 502 CS42L43_IRQ_REG(AMP2_THERM_WARN, CLASS_D_AMP), 503 CS42L43_IRQ_REG(AMP1_THERM_WARN, CLASS_D_AMP), 504 CS42L43_IRQ_REG(AMP2_SCDET, CLASS_D_AMP), 505 CS42L43_IRQ_REG(AMP1_SCDET, CLASS_D_AMP), 506 507 CS42L43_IRQ_REG(GPIO3_FALL, GPIO), 508 CS42L43_IRQ_REG(GPIO3_RISE, GPIO), 509 CS42L43_IRQ_REG(GPIO2_FALL, GPIO), 510 CS42L43_IRQ_REG(GPIO2_RISE, GPIO), 511 CS42L43_IRQ_REG(GPIO1_FALL, GPIO), 512 CS42L43_IRQ_REG(GPIO1_RISE, GPIO), 513 514 CS42L43_IRQ_REG(HP_ILIMIT, HPOUT), 515 CS42L43_IRQ_REG(HP_LOADDET_DONE, HPOUT), 516 }; 517 518 static const struct regmap_irq_chip cs42l43_irq_chip = { 519 .name = "cs42l43", 520 521 .status_base = CS42L43_DECIM_INT, 522 .mask_base = CS42L43_DECIM_MASK, 523 .num_regs = 16, 524 525 .irqs = cs42l43_regmap_irqs, 526 .num_irqs = ARRAY_SIZE(cs42l43_regmap_irqs), 527 528 .runtime_pm = true, 529 }; 530 531 static const char * const cs42l43_core_supplies[] = { 532 "vdd-a", "vdd-io", "vdd-cp", 533 }; 534 535 static const char * const cs42l43_parent_supplies[] = { "vdd-amp" }; 536 537 static const struct mfd_cell cs42l43_devs[] = { 538 { .name = "cs42l43-pinctrl", }, 539 { .name = "cs42l43-spi", }, 540 { 541 .name = "cs42l43-codec", 542 .parent_supplies = cs42l43_parent_supplies, 543 .num_parent_supplies = ARRAY_SIZE(cs42l43_parent_supplies), 544 }, 545 }; 546 547 /* 548 * If the device is connected over Soundwire, as well as soft resetting the 549 * device, this function will also way for the device to detach from the bus 550 * before returning. 551 */ 552 static int cs42l43_soft_reset(struct cs42l43 *cs42l43) 553 { 554 static const struct reg_sequence reset[] = { 555 { CS42L43_SFT_RESET, CS42L43_SFT_RESET_VAL }, 556 }; 557 558 reinit_completion(&cs42l43->device_detach); 559 560 /* 561 * Apply cache only because the soft reset will cause the device to 562 * detach from the soundwire bus. 563 */ 564 regcache_cache_only(cs42l43->regmap, true); 565 regmap_multi_reg_write_bypassed(cs42l43->regmap, reset, ARRAY_SIZE(reset)); 566 567 msleep(CS42L43_RESET_DELAY_MS); 568 569 if (cs42l43->sdw) { 570 unsigned long timeout = msecs_to_jiffies(CS42L43_SDW_DETACH_TIMEOUT_MS); 571 unsigned long time; 572 573 time = wait_for_completion_timeout(&cs42l43->device_detach, timeout); 574 if (!time) { 575 dev_err(cs42l43->dev, "Timed out waiting for device detach\n"); 576 return -ETIMEDOUT; 577 } 578 } 579 580 return -EAGAIN; 581 } 582 583 /* 584 * This function is essentially a no-op on I2C, but will wait for the device to 585 * attach when the device is used on a SoundWire bus. 586 */ 587 static int cs42l43_wait_for_attach(struct cs42l43 *cs42l43) 588 { 589 if (!cs42l43->attached) { 590 unsigned long timeout = msecs_to_jiffies(CS42L43_SDW_ATTACH_TIMEOUT_MS); 591 unsigned long time; 592 593 time = wait_for_completion_timeout(&cs42l43->device_attach, timeout); 594 if (!time) { 595 dev_err(cs42l43->dev, "Timed out waiting for device re-attach\n"); 596 return -ETIMEDOUT; 597 } 598 } 599 600 regcache_cache_only(cs42l43->regmap, false); 601 602 /* The hardware requires enabling OSC_DIV before doing any SoundWire reads. */ 603 if (cs42l43->sdw) 604 regmap_write(cs42l43->regmap, CS42L43_OSC_DIV_SEL, 605 CS42L43_OSC_DIV2_EN_MASK); 606 607 return 0; 608 } 609 610 /* 611 * This function will advance the firmware into boot stage 3 from boot stage 2. 612 * Boot stage 3 is required to send commands to the firmware. This is achieved 613 * by setting the firmware NEED configuration register to zero, this indicates 614 * no configuration is required forcing the firmware to advance to boot stage 3. 615 * 616 * Later revisions of the firmware require the use of an alternative register 617 * for this purpose, which is indicated through the shadow flag. 618 */ 619 static int cs42l43_mcu_stage_2_3(struct cs42l43 *cs42l43, bool shadow) 620 { 621 unsigned int need_reg = CS42L43_NEED_CONFIGS; 622 unsigned int boot_reg; 623 unsigned int val; 624 int ret; 625 626 switch (cs42l43->variant_id) { 627 case CS42L43_DEVID_VAL: 628 if (shadow) 629 need_reg = CS42L43_FW_SH_BOOT_CFG_NEED_CONFIGS; 630 boot_reg = CS42L43_BOOT_STATUS; 631 break; 632 case CS42L43B_DEVID_VAL: 633 need_reg = CS42L43B_NEED_CONFIGS; 634 boot_reg = CS42L43B_BOOT_STATUS; 635 break; 636 default: 637 return -EINVAL; 638 } 639 640 regmap_write(cs42l43->regmap, need_reg, 0); 641 642 ret = regmap_read_poll_timeout(cs42l43->regmap, boot_reg, 643 val, (val == CS42L43_MCU_BOOT_STAGE3), 644 CS42L43_MCU_POLL_US, CS42L43_MCU_CMD_TIMEOUT_US); 645 if (ret) { 646 dev_err(cs42l43->dev, "Failed to move to stage 3: %d, 0x%x\n", ret, val); 647 return ret; 648 } 649 650 return -EAGAIN; 651 } 652 653 /* 654 * This function will return the firmware to boot stage 2 from boot stage 3. 655 * Boot stage 2 is required to apply updates to the firmware. This is achieved 656 * by setting the firmware NEED configuration register to FW_PATCH_NEED_CFG, 657 * setting the HAVE configuration register to 0, and soft resetting. The 658 * firmware will see it is missing a patch configuration and will pause in boot 659 * stage 2. 660 * 661 * Note: Unlike cs42l43_mcu_stage_2_3 there is no need to consider the shadow 662 * register here as the driver will only return to boot stage 2 if the firmware 663 * requires update which means the revision does not include shadow register 664 * support. 665 */ 666 static int cs42l43_mcu_stage_3_2(struct cs42l43 *cs42l43) 667 { 668 regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_NEED_CONFIGS, 669 CS42L43_FW_PATCH_NEED_CFG_MASK); 670 regmap_write(cs42l43->regmap, CS42L43_FW_MISSION_CTRL_HAVE_CONFIGS, 0); 671 672 return cs42l43_soft_reset(cs42l43); 673 } 674 675 /* 676 * Disable the firmware running on the device such that the driver can access 677 * the registers without fear of the MCU changing them under it. 678 */ 679 static int cs42l43_mcu_disable(struct cs42l43 *cs42l43) 680 { 681 unsigned int val, cfg_reg, ctrl_reg; 682 int ret; 683 684 switch (cs42l43->variant_id) { 685 case CS42L43_DEVID_VAL: 686 cfg_reg = CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_REG; 687 ctrl_reg = CS42L43_FW_MISSION_CTRL_MM_CTRL_SELECTION; 688 break; 689 case CS42L43B_DEVID_VAL: 690 cfg_reg = CS42L43B_FW_MISSION_CTRL_MM_MCU_CFG_REG; 691 ctrl_reg = CS42L43B_FW_MISSION_CTRL_MM_CTRL_SELECTION; 692 break; 693 default: 694 return -EINVAL; 695 } 696 697 regmap_write(cs42l43->regmap, cfg_reg, CS42L43_FW_MISSION_CTRL_MM_MCU_CFG_DISABLE_VAL); 698 regmap_write(cs42l43->regmap, ctrl_reg, CS42L43_FW_MM_CTRL_MCU_SEL_MASK); 699 700 regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, CS42L43_CONTROL_IND_MASK); 701 regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, 0); 702 703 ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_SOFT_INT_SHADOW, val, 704 (val & CS42L43_CONTROL_APPLIED_INT_MASK), 705 CS42L43_MCU_POLL_US, CS42L43_MCU_CMD_TIMEOUT_US); 706 if (ret) { 707 dev_err(cs42l43->dev, "Failed to disable firmware: %d, 0x%x\n", ret, val); 708 return ret; 709 } 710 711 /* Soft reset to clear any register state the firmware left behind. */ 712 return cs42l43_soft_reset(cs42l43); 713 } 714 715 /* 716 * Callback to load firmware updates. 717 */ 718 static void cs42l43_mcu_load_firmware(const struct firmware *firmware, void *context) 719 { 720 struct cs42l43 *cs42l43 = context; 721 const struct cs42l43_patch_header *hdr; 722 unsigned int loadaddr, val; 723 int ret; 724 725 if (!firmware) { 726 dev_err(cs42l43->dev, "Failed to load firmware\n"); 727 cs42l43->firmware_error = -ENODEV; 728 goto err; 729 } 730 731 hdr = (const struct cs42l43_patch_header *)&firmware->data[0]; 732 loadaddr = le32_to_cpu(hdr->load_addr); 733 734 if (le16_to_cpu(hdr->version) != CS42L43_MCU_UPDATE_FORMAT) { 735 dev_err(cs42l43->dev, "Bad firmware file format: %d\n", hdr->version); 736 cs42l43->firmware_error = -EINVAL; 737 goto err_release; 738 } 739 740 regmap_write(cs42l43->regmap, CS42L43_PATCH_START_ADDR, loadaddr); 741 regmap_bulk_write(cs42l43->regmap, loadaddr + CS42L43_MCU_UPDATE_OFFSET, 742 &firmware->data[0], firmware->size / sizeof(u32)); 743 744 regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, CS42L43_PATCH_IND_MASK); 745 regmap_write(cs42l43->regmap, CS42L43_MCU_SW_INTERRUPT, 0); 746 747 ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_SOFT_INT_SHADOW, val, 748 (val & CS42L43_PATCH_APPLIED_INT_MASK), 749 CS42L43_MCU_POLL_US, CS42L43_MCU_UPDATE_TIMEOUT_US); 750 if (ret) { 751 dev_err(cs42l43->dev, "Failed to update firmware: %d, 0x%x\n", ret, val); 752 cs42l43->firmware_error = ret; 753 goto err_release; 754 } 755 756 err_release: 757 release_firmware(firmware); 758 err: 759 complete(&cs42l43->firmware_download); 760 } 761 762 static int cs42l43_mcu_is_hw_compatible(struct cs42l43 *cs42l43, 763 unsigned int mcu_rev, 764 unsigned int bios_rev) 765 { 766 /* 767 * The firmware has two revision numbers bringing either of them up to a 768 * supported version will provide the disable the driver requires. 769 */ 770 if (mcu_rev < CS42L43_MCU_SUPPORTED_REV && 771 bios_rev < CS42L43_MCU_SUPPORTED_BIOS_REV) { 772 dev_err(cs42l43->dev, "Firmware too old to support disable\n"); 773 return -EINVAL; 774 } 775 776 return 0; 777 } 778 779 /* 780 * The process of updating the firmware is split into a series of steps, at the 781 * end of each step a soft reset of the device might be required which will 782 * require the driver to wait for the device to re-attach on the SoundWire bus, 783 * if that control bus is being used. 784 */ 785 static int cs42l43_mcu_update_step(struct cs42l43 *cs42l43) 786 { 787 unsigned int mcu_rev, bios_rev, boot_status, secure_cfg; 788 bool patched, shadow; 789 int boot_status_reg, mcu_sw_rev_reg; 790 int ret; 791 792 switch (cs42l43->variant_id) { 793 case CS42L43_DEVID_VAL: 794 boot_status_reg = CS42L43_BOOT_STATUS; 795 mcu_sw_rev_reg = CS42L43_MCU_SW_REV; 796 break; 797 case CS42L43B_DEVID_VAL: 798 boot_status_reg = CS42L43B_BOOT_STATUS; 799 mcu_sw_rev_reg = CS42L43B_MCU_SW_REV; 800 break; 801 default: 802 return -EINVAL; 803 } 804 805 /* Clear any stale software interrupt bits. */ 806 regmap_read(cs42l43->regmap, CS42L43_SOFT_INT, &mcu_rev); 807 808 ret = regmap_read(cs42l43->regmap, boot_status_reg, &boot_status); 809 if (ret) { 810 dev_err(cs42l43->dev, "Failed to read boot status: %d\n", ret); 811 return ret; 812 } 813 814 ret = regmap_read(cs42l43->regmap, mcu_sw_rev_reg, &mcu_rev); 815 if (ret) { 816 dev_err(cs42l43->dev, "Failed to read firmware revision: %d\n", ret); 817 return ret; 818 } 819 820 bios_rev = (((mcu_rev & CS42L43_BIOS_MAJOR_REV_MASK) << 12) | 821 ((mcu_rev & CS42L43_BIOS_MINOR_REV_MASK) << 4) | 822 ((mcu_rev & CS42L43_BIOS_SUBMINOR_REV_MASK) >> 8)) >> 823 CS42L43_BIOS_MAJOR_REV_SHIFT; 824 mcu_rev = ((mcu_rev & CS42L43_FW_MAJOR_REV_MASK) << 12) | 825 ((mcu_rev & CS42L43_FW_MINOR_REV_MASK) << 4) | 826 ((mcu_rev & CS42L43_FW_SUBMINOR_REV_MASK) >> 8); 827 828 /* 829 * The firmware has two revision numbers both of them being at the ROM 830 * revision indicates no patch has been applied. 831 */ 832 patched = mcu_rev != CS42L43_MCU_ROM_REV || bios_rev != CS42L43_MCU_ROM_BIOS_REV; 833 /* 834 * Later versions of the firmwware require the driver to access some 835 * features through a set of shadow registers. 836 */ 837 shadow = (mcu_rev >= CS42L43_MCU_SHADOW_REGS_REQUIRED_REV) || 838 (bios_rev >= CS42L43_BIOS_SHADOW_REGS_REQUIRED_REV); 839 840 ret = regmap_read(cs42l43->regmap, CS42L43_BOOT_CONTROL, &secure_cfg); 841 if (ret) { 842 dev_err(cs42l43->dev, "Failed to read security settings: %d\n", ret); 843 return ret; 844 } 845 846 cs42l43->hw_lock = secure_cfg & CS42L43_LOCK_HW_STS_MASK; 847 848 if (!patched && cs42l43->hw_lock) { 849 dev_err(cs42l43->dev, "Unpatched secure device\n"); 850 return -EPERM; 851 } 852 853 dev_dbg(cs42l43->dev, "Firmware(0x%x, 0x%x) in boot stage %d\n", 854 mcu_rev, bios_rev, boot_status); 855 856 switch (boot_status) { 857 case CS42L43_MCU_BOOT_STAGE2: 858 if (!patched) { 859 ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_UEVENT, 860 "cs42l43.bin", cs42l43->dev, 861 GFP_KERNEL, cs42l43, 862 cs42l43_mcu_load_firmware); 863 if (ret) { 864 dev_err(cs42l43->dev, "Failed to request firmware: %d\n", ret); 865 return ret; 866 } 867 868 wait_for_completion(&cs42l43->firmware_download); 869 870 if (cs42l43->firmware_error) 871 return cs42l43->firmware_error; 872 873 return -EAGAIN; 874 } else { 875 return cs42l43_mcu_stage_2_3(cs42l43, shadow); 876 } 877 case CS42L43_MCU_BOOT_STAGE3: 878 if (patched) { 879 ret = cs42l43_mcu_is_hw_compatible(cs42l43, mcu_rev, bios_rev); 880 if (ret) 881 return ret; 882 883 return cs42l43_mcu_disable(cs42l43); 884 } else { 885 return cs42l43_mcu_stage_3_2(cs42l43); 886 } 887 case CS42L43_MCU_BOOT_STAGE4: 888 return 0; 889 default: 890 dev_err(cs42l43->dev, "Invalid boot status: %d\n", boot_status); 891 return -EINVAL; 892 } 893 } 894 895 /* 896 * Update the firmware running on the device. 897 */ 898 static int cs42l43_mcu_update(struct cs42l43 *cs42l43) 899 { 900 int i, ret; 901 902 for (i = 0; i < CS42L43_MCU_UPDATE_RETRIES; i++) { 903 ret = cs42l43_mcu_update_step(cs42l43); 904 if (ret != -EAGAIN) 905 return ret; 906 907 ret = cs42l43_wait_for_attach(cs42l43); 908 if (ret) 909 return ret; 910 } 911 912 dev_err(cs42l43->dev, "Failed retrying update\n"); 913 return -ETIMEDOUT; 914 } 915 916 static int cs42l43_irq_config(struct cs42l43 *cs42l43) 917 { 918 struct irq_data *irq_data; 919 unsigned long irq_flags; 920 int ret; 921 922 if (cs42l43->sdw) 923 cs42l43->irq = cs42l43->sdw->irq; 924 925 cs42l43->irq_chip = cs42l43_irq_chip; 926 cs42l43->irq_chip.irq_drv_data = cs42l43; 927 928 irq_data = irq_get_irq_data(cs42l43->irq); 929 if (!irq_data) { 930 dev_err(cs42l43->dev, "Invalid IRQ: %d\n", cs42l43->irq); 931 return -EINVAL; 932 } 933 934 irq_flags = irqd_get_trigger_type(irq_data); 935 switch (irq_flags) { 936 case IRQF_TRIGGER_LOW: 937 case IRQF_TRIGGER_HIGH: 938 case IRQF_TRIGGER_RISING: 939 case IRQF_TRIGGER_FALLING: 940 break; 941 case IRQ_TYPE_NONE: 942 default: 943 irq_flags = IRQF_TRIGGER_LOW; 944 break; 945 } 946 947 irq_flags |= IRQF_ONESHOT; 948 949 ret = devm_regmap_add_irq_chip(cs42l43->dev, cs42l43->regmap, 950 cs42l43->irq, irq_flags, 0, 951 &cs42l43->irq_chip, &cs42l43->irq_data); 952 if (ret) { 953 dev_err(cs42l43->dev, "Failed to add IRQ chip: %d\n", ret); 954 return ret; 955 } 956 957 dev_dbg(cs42l43->dev, "Configured IRQ %d with flags 0x%lx\n", 958 cs42l43->irq, irq_flags); 959 960 return 0; 961 } 962 963 static void cs42l43_boot_work(struct work_struct *work) 964 { 965 struct cs42l43 *cs42l43 = container_of(work, struct cs42l43, boot_work); 966 unsigned int devid, revid, otp; 967 int ret; 968 969 ret = cs42l43_wait_for_attach(cs42l43); 970 if (ret) 971 goto err; 972 973 ret = regmap_read(cs42l43->regmap, CS42L43_DEVID, &devid); 974 if (ret) { 975 dev_err(cs42l43->dev, "Failed to read devid: %d\n", ret); 976 goto err; 977 } 978 979 switch (devid) { 980 case CS42L43_DEVID_VAL: 981 case CS42L43B_DEVID_VAL: 982 if (devid != cs42l43->variant_id) { 983 dev_err(cs42l43->dev, 984 "Device ID (0x%06x) does not match variant ID (0x%06lx)\n", 985 devid, cs42l43->variant_id); 986 goto err; 987 } 988 break; 989 default: 990 dev_err(cs42l43->dev, "Unrecognised devid: 0x%06x\n", devid); 991 goto err; 992 } 993 994 ret = regmap_read(cs42l43->regmap, CS42L43_REVID, &revid); 995 if (ret) { 996 dev_err(cs42l43->dev, "Failed to read rev: %d\n", ret); 997 goto err; 998 } 999 1000 ret = regmap_read(cs42l43->regmap, CS42L43_OTP_REVISION_ID, &otp); 1001 if (ret) { 1002 dev_err(cs42l43->dev, "Failed to read otp rev: %d\n", ret); 1003 goto err; 1004 } 1005 1006 dev_info(cs42l43->dev, 1007 "devid: 0x%06x, rev: 0x%02x, otp: 0x%02x\n", devid, revid, otp); 1008 1009 ret = cs42l43_mcu_update(cs42l43); 1010 if (ret) 1011 goto err; 1012 1013 ret = regmap_register_patch(cs42l43->regmap, cs42l43_reva_patch, 1014 ARRAY_SIZE(cs42l43_reva_patch)); 1015 if (ret) { 1016 dev_err(cs42l43->dev, "Failed to apply register patch: %d\n", ret); 1017 goto err; 1018 } 1019 1020 ret = cs42l43_irq_config(cs42l43); 1021 if (ret) 1022 goto err; 1023 1024 ret = devm_mfd_add_devices(cs42l43->dev, PLATFORM_DEVID_NONE, 1025 cs42l43_devs, ARRAY_SIZE(cs42l43_devs), 1026 NULL, 0, NULL); 1027 if (ret) { 1028 dev_err(cs42l43->dev, "Failed to add subdevices: %d\n", ret); 1029 goto err; 1030 } 1031 1032 pm_runtime_put_autosuspend(cs42l43->dev); 1033 1034 return; 1035 1036 err: 1037 pm_runtime_put_sync(cs42l43->dev); 1038 } 1039 1040 static int cs42l43_power_up(struct cs42l43 *cs42l43) 1041 { 1042 int ret; 1043 1044 ret = regulator_enable(cs42l43->vdd_p); 1045 if (ret) { 1046 dev_err(cs42l43->dev, "Failed to enable vdd-p: %d\n", ret); 1047 return ret; 1048 } 1049 1050 /* vdd-p must be on for 50uS before any other supply */ 1051 usleep_range(CS42L43_VDDP_DELAY_US, 2 * CS42L43_VDDP_DELAY_US); 1052 1053 gpiod_set_raw_value_cansleep(cs42l43->reset, 1); 1054 1055 ret = regulator_bulk_enable(CS42L43_N_SUPPLIES, cs42l43->core_supplies); 1056 if (ret) { 1057 dev_err(cs42l43->dev, "Failed to enable core supplies: %d\n", ret); 1058 goto err_reset; 1059 } 1060 1061 ret = regulator_enable(cs42l43->vdd_d); 1062 if (ret) { 1063 dev_err(cs42l43->dev, "Failed to enable vdd-d: %d\n", ret); 1064 goto err_core_supplies; 1065 } 1066 1067 usleep_range(CS42L43_VDDD_DELAY_US, 2 * CS42L43_VDDD_DELAY_US); 1068 1069 return 0; 1070 1071 err_core_supplies: 1072 regulator_bulk_disable(CS42L43_N_SUPPLIES, cs42l43->core_supplies); 1073 err_reset: 1074 gpiod_set_raw_value_cansleep(cs42l43->reset, 0); 1075 regulator_disable(cs42l43->vdd_p); 1076 1077 return ret; 1078 } 1079 1080 static int cs42l43_power_down(struct cs42l43 *cs42l43) 1081 { 1082 int ret; 1083 1084 ret = regulator_disable(cs42l43->vdd_d); 1085 if (ret) { 1086 dev_err(cs42l43->dev, "Failed to disable vdd-d: %d\n", ret); 1087 return ret; 1088 } 1089 1090 ret = regulator_bulk_disable(CS42L43_N_SUPPLIES, cs42l43->core_supplies); 1091 if (ret) { 1092 dev_err(cs42l43->dev, "Failed to disable core supplies: %d\n", ret); 1093 return ret; 1094 } 1095 1096 gpiod_set_raw_value_cansleep(cs42l43->reset, 0); 1097 1098 ret = regulator_disable(cs42l43->vdd_p); 1099 if (ret) { 1100 dev_err(cs42l43->dev, "Failed to disable vdd-p: %d\n", ret); 1101 return ret; 1102 } 1103 1104 return 0; 1105 } 1106 1107 static void cs42l43_dev_remove(void *data) 1108 { 1109 struct cs42l43 *cs42l43 = data; 1110 1111 cancel_work_sync(&cs42l43->boot_work); 1112 1113 cs42l43_power_down(cs42l43); 1114 } 1115 1116 int cs42l43_dev_probe(struct cs42l43 *cs42l43) 1117 { 1118 int i, ret; 1119 1120 dev_set_drvdata(cs42l43->dev, cs42l43); 1121 1122 mutex_init(&cs42l43->pll_lock); 1123 init_completion(&cs42l43->device_attach); 1124 init_completion(&cs42l43->device_detach); 1125 init_completion(&cs42l43->firmware_download); 1126 INIT_WORK(&cs42l43->boot_work, cs42l43_boot_work); 1127 1128 regcache_cache_only(cs42l43->regmap, true); 1129 1130 cs42l43->reset = devm_gpiod_get_optional(cs42l43->dev, "reset", GPIOD_OUT_HIGH); 1131 if (IS_ERR(cs42l43->reset)) 1132 return dev_err_probe(cs42l43->dev, PTR_ERR(cs42l43->reset), 1133 "Failed to get reset\n"); 1134 1135 gpiod_set_raw_value_cansleep(cs42l43->reset, 0); 1136 1137 cs42l43->vdd_p = devm_regulator_get(cs42l43->dev, "vdd-p"); 1138 if (IS_ERR(cs42l43->vdd_p)) 1139 return dev_err_probe(cs42l43->dev, PTR_ERR(cs42l43->vdd_p), 1140 "Failed to get vdd-p\n"); 1141 1142 cs42l43->vdd_d = devm_regulator_get(cs42l43->dev, "vdd-d"); 1143 if (IS_ERR(cs42l43->vdd_d)) 1144 return dev_err_probe(cs42l43->dev, PTR_ERR(cs42l43->vdd_d), 1145 "Failed to get vdd-d\n"); 1146 1147 BUILD_BUG_ON(ARRAY_SIZE(cs42l43_core_supplies) != CS42L43_N_SUPPLIES); 1148 1149 for (i = 0; i < CS42L43_N_SUPPLIES; i++) 1150 cs42l43->core_supplies[i].supply = cs42l43_core_supplies[i]; 1151 1152 ret = devm_regulator_bulk_get(cs42l43->dev, CS42L43_N_SUPPLIES, 1153 cs42l43->core_supplies); 1154 if (ret) 1155 return dev_err_probe(cs42l43->dev, ret, 1156 "Failed to get core supplies\n"); 1157 1158 ret = cs42l43_power_up(cs42l43); 1159 if (ret) 1160 return ret; 1161 1162 ret = devm_add_action_or_reset(cs42l43->dev, cs42l43_dev_remove, cs42l43); 1163 if (ret) 1164 return ret; 1165 1166 pm_runtime_set_autosuspend_delay(cs42l43->dev, CS42L43_AUTOSUSPEND_TIME_MS); 1167 pm_runtime_use_autosuspend(cs42l43->dev); 1168 pm_runtime_set_active(cs42l43->dev); 1169 /* 1170 * The device is already powered up, but keep it from suspending until 1171 * the boot work runs. 1172 */ 1173 pm_runtime_get_noresume(cs42l43->dev); 1174 ret = devm_pm_runtime_enable(cs42l43->dev); 1175 if (ret) 1176 return ret; 1177 1178 queue_work(system_long_wq, &cs42l43->boot_work); 1179 1180 return 0; 1181 } 1182 EXPORT_SYMBOL_NS_GPL(cs42l43_dev_probe, "MFD_CS42L43"); 1183 1184 static int cs42l43_suspend(struct device *dev) 1185 { 1186 struct cs42l43 *cs42l43 = dev_get_drvdata(dev); 1187 int ret; 1188 1189 ret = pm_runtime_resume_and_get(dev); 1190 if (ret) { 1191 dev_err(cs42l43->dev, "Failed to resume for suspend: %d\n", ret); 1192 return ret; 1193 } 1194 1195 disable_irq(cs42l43->irq); 1196 1197 ret = pm_runtime_force_suspend(dev); 1198 if (ret) { 1199 dev_err(cs42l43->dev, "Failed to force suspend: %d\n", ret); 1200 pm_runtime_put_noidle(dev); 1201 return ret; 1202 } 1203 1204 pm_runtime_put_noidle(dev); 1205 1206 ret = cs42l43_power_down(cs42l43); 1207 if (ret) 1208 return ret; 1209 1210 return 0; 1211 } 1212 1213 static int cs42l43_suspend_noirq(struct device *dev) 1214 { 1215 struct cs42l43 *cs42l43 = dev_get_drvdata(dev); 1216 1217 enable_irq(cs42l43->irq); 1218 1219 return 0; 1220 } 1221 1222 static int cs42l43_resume_noirq(struct device *dev) 1223 { 1224 struct cs42l43 *cs42l43 = dev_get_drvdata(dev); 1225 1226 disable_irq(cs42l43->irq); 1227 1228 return 0; 1229 } 1230 1231 static int cs42l43_resume(struct device *dev) 1232 { 1233 struct cs42l43 *cs42l43 = dev_get_drvdata(dev); 1234 int ret; 1235 1236 ret = cs42l43_power_up(cs42l43); 1237 if (ret) 1238 return ret; 1239 1240 ret = pm_runtime_force_resume(dev); 1241 if (ret) { 1242 dev_err(cs42l43->dev, "Failed to force resume: %d\n", ret); 1243 return ret; 1244 } 1245 1246 enable_irq(cs42l43->irq); 1247 1248 return 0; 1249 } 1250 1251 static int cs42l43_runtime_suspend(struct device *dev) 1252 { 1253 struct cs42l43 *cs42l43 = dev_get_drvdata(dev); 1254 1255 /* 1256 * Whilst the driver doesn't power the chip down here, going into runtime 1257 * suspend lets the SoundWire bus power down, which means the driver 1258 * can't communicate with the device any more. 1259 */ 1260 regcache_cache_only(cs42l43->regmap, true); 1261 1262 return 0; 1263 } 1264 1265 static int cs42l43_runtime_resume(struct device *dev) 1266 { 1267 struct cs42l43 *cs42l43 = dev_get_drvdata(dev); 1268 unsigned int reset_canary; 1269 int ret; 1270 1271 ret = cs42l43_wait_for_attach(cs42l43); 1272 if (ret) 1273 return ret; 1274 1275 ret = regmap_read(cs42l43->regmap, CS42L43_RELID, &reset_canary); 1276 if (ret) { 1277 dev_err(cs42l43->dev, "Failed to check reset canary: %d\n", ret); 1278 goto err; 1279 } 1280 1281 if (!reset_canary) { 1282 /* 1283 * If the canary has cleared the chip has reset, re-handle the 1284 * MCU and mark the cache as dirty to indicate the chip reset. 1285 */ 1286 ret = cs42l43_mcu_update(cs42l43); 1287 if (ret) 1288 goto err; 1289 1290 regcache_mark_dirty(cs42l43->regmap); 1291 } 1292 1293 ret = regcache_sync(cs42l43->regmap); 1294 if (ret) { 1295 dev_err(cs42l43->dev, "Failed to restore register cache: %d\n", ret); 1296 goto err; 1297 } 1298 1299 return 0; 1300 1301 err: 1302 regcache_cache_only(cs42l43->regmap, true); 1303 1304 return ret; 1305 } 1306 1307 EXPORT_NS_GPL_DEV_PM_OPS(cs42l43_pm_ops, MFD_CS42L43) = { 1308 SYSTEM_SLEEP_PM_OPS(cs42l43_suspend, cs42l43_resume) 1309 NOIRQ_SYSTEM_SLEEP_PM_OPS(cs42l43_suspend_noirq, cs42l43_resume_noirq) 1310 RUNTIME_PM_OPS(cs42l43_runtime_suspend, cs42l43_runtime_resume, NULL) 1311 }; 1312 1313 MODULE_DESCRIPTION("CS42L43 Core Driver"); 1314 MODULE_AUTHOR("Charles Keepax <ckeepax@opensource.cirrus.com>"); 1315 MODULE_LICENSE("GPL"); 1316 MODULE_FIRMWARE("cs42l43.bin"); 1317