1 /* 2 * Copyright (C) ST-Ericsson SA 2010 3 * 4 * License Terms: GNU General Public License v2 5 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> 6 * Author: Rabin Vincent <rabin.vincent@stericsson.com> 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/slab.h> 11 #include <linux/init.h> 12 #include <linux/irq.h> 13 #include <linux/delay.h> 14 #include <linux/interrupt.h> 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <linux/mfd/core.h> 18 #include <linux/mfd/ab8500.h> 19 #include <linux/regulator/ab8500.h> 20 21 /* 22 * Interrupt register offsets 23 * Bank : 0x0E 24 */ 25 #define AB8500_IT_SOURCE1_REG 0x0E00 26 #define AB8500_IT_SOURCE2_REG 0x0E01 27 #define AB8500_IT_SOURCE3_REG 0x0E02 28 #define AB8500_IT_SOURCE4_REG 0x0E03 29 #define AB8500_IT_SOURCE5_REG 0x0E04 30 #define AB8500_IT_SOURCE6_REG 0x0E05 31 #define AB8500_IT_SOURCE7_REG 0x0E06 32 #define AB8500_IT_SOURCE8_REG 0x0E07 33 #define AB8500_IT_SOURCE19_REG 0x0E12 34 #define AB8500_IT_SOURCE20_REG 0x0E13 35 #define AB8500_IT_SOURCE21_REG 0x0E14 36 #define AB8500_IT_SOURCE22_REG 0x0E15 37 #define AB8500_IT_SOURCE23_REG 0x0E16 38 #define AB8500_IT_SOURCE24_REG 0x0E17 39 40 /* 41 * latch registers 42 */ 43 #define AB8500_IT_LATCH1_REG 0x0E20 44 #define AB8500_IT_LATCH2_REG 0x0E21 45 #define AB8500_IT_LATCH3_REG 0x0E22 46 #define AB8500_IT_LATCH4_REG 0x0E23 47 #define AB8500_IT_LATCH5_REG 0x0E24 48 #define AB8500_IT_LATCH6_REG 0x0E25 49 #define AB8500_IT_LATCH7_REG 0x0E26 50 #define AB8500_IT_LATCH8_REG 0x0E27 51 #define AB8500_IT_LATCH9_REG 0x0E28 52 #define AB8500_IT_LATCH10_REG 0x0E29 53 #define AB8500_IT_LATCH19_REG 0x0E32 54 #define AB8500_IT_LATCH20_REG 0x0E33 55 #define AB8500_IT_LATCH21_REG 0x0E34 56 #define AB8500_IT_LATCH22_REG 0x0E35 57 #define AB8500_IT_LATCH23_REG 0x0E36 58 #define AB8500_IT_LATCH24_REG 0x0E37 59 60 /* 61 * mask registers 62 */ 63 64 #define AB8500_IT_MASK1_REG 0x0E40 65 #define AB8500_IT_MASK2_REG 0x0E41 66 #define AB8500_IT_MASK3_REG 0x0E42 67 #define AB8500_IT_MASK4_REG 0x0E43 68 #define AB8500_IT_MASK5_REG 0x0E44 69 #define AB8500_IT_MASK6_REG 0x0E45 70 #define AB8500_IT_MASK7_REG 0x0E46 71 #define AB8500_IT_MASK8_REG 0x0E47 72 #define AB8500_IT_MASK9_REG 0x0E48 73 #define AB8500_IT_MASK10_REG 0x0E49 74 #define AB8500_IT_MASK11_REG 0x0E4A 75 #define AB8500_IT_MASK12_REG 0x0E4B 76 #define AB8500_IT_MASK13_REG 0x0E4C 77 #define AB8500_IT_MASK14_REG 0x0E4D 78 #define AB8500_IT_MASK15_REG 0x0E4E 79 #define AB8500_IT_MASK16_REG 0x0E4F 80 #define AB8500_IT_MASK17_REG 0x0E50 81 #define AB8500_IT_MASK18_REG 0x0E51 82 #define AB8500_IT_MASK19_REG 0x0E52 83 #define AB8500_IT_MASK20_REG 0x0E53 84 #define AB8500_IT_MASK21_REG 0x0E54 85 #define AB8500_IT_MASK22_REG 0x0E55 86 #define AB8500_IT_MASK23_REG 0x0E56 87 #define AB8500_IT_MASK24_REG 0x0E57 88 89 #define AB8500_REV_REG 0x1080 90 91 /* 92 * Map interrupt numbers to the LATCH and MASK register offsets, Interrupt 93 * numbers are indexed into this array with (num / 8). 94 * 95 * This is one off from the register names, i.e. AB8500_IT_MASK1_REG is at 96 * offset 0. 97 */ 98 static const int ab8500_irq_regoffset[AB8500_NUM_IRQ_REGS] = { 99 0, 1, 2, 3, 4, 6, 7, 8, 9, 18, 19, 20, 21, 100 }; 101 102 static int __ab8500_write(struct ab8500 *ab8500, u16 addr, u8 data) 103 { 104 int ret; 105 106 dev_vdbg(ab8500->dev, "wr: addr %#x <= %#x\n", addr, data); 107 108 ret = ab8500->write(ab8500, addr, data); 109 if (ret < 0) 110 dev_err(ab8500->dev, "failed to write reg %#x: %d\n", 111 addr, ret); 112 113 return ret; 114 } 115 116 /** 117 * ab8500_write() - write an AB8500 register 118 * @ab8500: device to write to 119 * @addr: address of the register 120 * @data: value to write 121 */ 122 int ab8500_write(struct ab8500 *ab8500, u16 addr, u8 data) 123 { 124 int ret; 125 126 mutex_lock(&ab8500->lock); 127 ret = __ab8500_write(ab8500, addr, data); 128 mutex_unlock(&ab8500->lock); 129 130 return ret; 131 } 132 EXPORT_SYMBOL_GPL(ab8500_write); 133 134 static int __ab8500_read(struct ab8500 *ab8500, u16 addr) 135 { 136 int ret; 137 138 ret = ab8500->read(ab8500, addr); 139 if (ret < 0) 140 dev_err(ab8500->dev, "failed to read reg %#x: %d\n", 141 addr, ret); 142 143 dev_vdbg(ab8500->dev, "rd: addr %#x => data %#x\n", addr, ret); 144 145 return ret; 146 } 147 148 /** 149 * ab8500_read() - read an AB8500 register 150 * @ab8500: device to read from 151 * @addr: address of the register 152 */ 153 int ab8500_read(struct ab8500 *ab8500, u16 addr) 154 { 155 int ret; 156 157 mutex_lock(&ab8500->lock); 158 ret = __ab8500_read(ab8500, addr); 159 mutex_unlock(&ab8500->lock); 160 161 return ret; 162 } 163 EXPORT_SYMBOL_GPL(ab8500_read); 164 165 /** 166 * ab8500_set_bits() - set a bitfield in an AB8500 register 167 * @ab8500: device to read from 168 * @addr: address of the register 169 * @mask: mask of the bitfield to modify 170 * @data: value to set to the bitfield 171 */ 172 int ab8500_set_bits(struct ab8500 *ab8500, u16 addr, u8 mask, u8 data) 173 { 174 int ret; 175 176 mutex_lock(&ab8500->lock); 177 178 ret = __ab8500_read(ab8500, addr); 179 if (ret < 0) 180 goto out; 181 182 ret &= ~mask; 183 ret |= data; 184 185 ret = __ab8500_write(ab8500, addr, ret); 186 187 out: 188 mutex_unlock(&ab8500->lock); 189 return ret; 190 } 191 EXPORT_SYMBOL_GPL(ab8500_set_bits); 192 193 static void ab8500_irq_lock(unsigned int irq) 194 { 195 struct ab8500 *ab8500 = get_irq_chip_data(irq); 196 197 mutex_lock(&ab8500->irq_lock); 198 } 199 200 static void ab8500_irq_sync_unlock(unsigned int irq) 201 { 202 struct ab8500 *ab8500 = get_irq_chip_data(irq); 203 int i; 204 205 for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) { 206 u8 old = ab8500->oldmask[i]; 207 u8 new = ab8500->mask[i]; 208 int reg; 209 210 if (new == old) 211 continue; 212 213 ab8500->oldmask[i] = new; 214 215 reg = AB8500_IT_MASK1_REG + ab8500_irq_regoffset[i]; 216 ab8500_write(ab8500, reg, new); 217 } 218 219 mutex_unlock(&ab8500->irq_lock); 220 } 221 222 static void ab8500_irq_mask(unsigned int irq) 223 { 224 struct ab8500 *ab8500 = get_irq_chip_data(irq); 225 int offset = irq - ab8500->irq_base; 226 int index = offset / 8; 227 int mask = 1 << (offset % 8); 228 229 ab8500->mask[index] |= mask; 230 } 231 232 static void ab8500_irq_unmask(unsigned int irq) 233 { 234 struct ab8500 *ab8500 = get_irq_chip_data(irq); 235 int offset = irq - ab8500->irq_base; 236 int index = offset / 8; 237 int mask = 1 << (offset % 8); 238 239 ab8500->mask[index] &= ~mask; 240 } 241 242 static struct irq_chip ab8500_irq_chip = { 243 .name = "ab8500", 244 .bus_lock = ab8500_irq_lock, 245 .bus_sync_unlock = ab8500_irq_sync_unlock, 246 .mask = ab8500_irq_mask, 247 .unmask = ab8500_irq_unmask, 248 }; 249 250 static irqreturn_t ab8500_irq(int irq, void *dev) 251 { 252 struct ab8500 *ab8500 = dev; 253 int i; 254 255 dev_vdbg(ab8500->dev, "interrupt\n"); 256 257 for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) { 258 int regoffset = ab8500_irq_regoffset[i]; 259 int status; 260 261 status = ab8500_read(ab8500, AB8500_IT_LATCH1_REG + regoffset); 262 if (status <= 0) 263 continue; 264 265 do { 266 int bit = __ffs(status); 267 int line = i * 8 + bit; 268 269 handle_nested_irq(ab8500->irq_base + line); 270 status &= ~(1 << bit); 271 } while (status); 272 } 273 274 return IRQ_HANDLED; 275 } 276 277 static int ab8500_irq_init(struct ab8500 *ab8500) 278 { 279 int base = ab8500->irq_base; 280 int irq; 281 282 for (irq = base; irq < base + AB8500_NR_IRQS; irq++) { 283 set_irq_chip_data(irq, ab8500); 284 set_irq_chip_and_handler(irq, &ab8500_irq_chip, 285 handle_simple_irq); 286 set_irq_nested_thread(irq, 1); 287 #ifdef CONFIG_ARM 288 set_irq_flags(irq, IRQF_VALID); 289 #else 290 set_irq_noprobe(irq); 291 #endif 292 } 293 294 return 0; 295 } 296 297 static void ab8500_irq_remove(struct ab8500 *ab8500) 298 { 299 int base = ab8500->irq_base; 300 int irq; 301 302 for (irq = base; irq < base + AB8500_NR_IRQS; irq++) { 303 #ifdef CONFIG_ARM 304 set_irq_flags(irq, 0); 305 #endif 306 set_irq_chip_and_handler(irq, NULL, NULL); 307 set_irq_chip_data(irq, NULL); 308 } 309 } 310 311 static struct resource ab8500_gpadc_resources[] = { 312 { 313 .name = "HW_CONV_END", 314 .start = AB8500_INT_GP_HW_ADC_CONV_END, 315 .end = AB8500_INT_GP_HW_ADC_CONV_END, 316 .flags = IORESOURCE_IRQ, 317 }, 318 { 319 .name = "SW_CONV_END", 320 .start = AB8500_INT_GP_SW_ADC_CONV_END, 321 .end = AB8500_INT_GP_SW_ADC_CONV_END, 322 .flags = IORESOURCE_IRQ, 323 }, 324 }; 325 326 static struct resource ab8500_rtc_resources[] = { 327 { 328 .name = "60S", 329 .start = AB8500_INT_RTC_60S, 330 .end = AB8500_INT_RTC_60S, 331 .flags = IORESOURCE_IRQ, 332 }, 333 { 334 .name = "ALARM", 335 .start = AB8500_INT_RTC_ALARM, 336 .end = AB8500_INT_RTC_ALARM, 337 .flags = IORESOURCE_IRQ, 338 }, 339 }; 340 341 static struct mfd_cell ab8500_devs[] = { 342 { 343 .name = "ab8500-gpadc", 344 .num_resources = ARRAY_SIZE(ab8500_gpadc_resources), 345 .resources = ab8500_gpadc_resources, 346 }, 347 { 348 .name = "ab8500-rtc", 349 .num_resources = ARRAY_SIZE(ab8500_rtc_resources), 350 .resources = ab8500_rtc_resources, 351 }, 352 { .name = "ab8500-charger", }, 353 { .name = "ab8500-audio", }, 354 { .name = "ab8500-usb", }, 355 { .name = "ab8500-pwm", }, 356 { .name = "ab8500-regulator", }, 357 }; 358 359 int __devinit ab8500_init(struct ab8500 *ab8500) 360 { 361 struct ab8500_platform_data *plat = dev_get_platdata(ab8500->dev); 362 int ret; 363 int i; 364 365 if (plat) 366 ab8500->irq_base = plat->irq_base; 367 368 mutex_init(&ab8500->lock); 369 mutex_init(&ab8500->irq_lock); 370 371 ret = ab8500_read(ab8500, AB8500_REV_REG); 372 if (ret < 0) 373 return ret; 374 375 /* 376 * 0x0 - Early Drop 377 * 0x10 - Cut 1.0 378 * 0x11 - Cut 1.1 379 */ 380 if (ret == 0x0 || ret == 0x10 || ret == 0x11) { 381 ab8500->revision = ret; 382 dev_info(ab8500->dev, "detected chip, revision: %#x\n", ret); 383 } else { 384 dev_err(ab8500->dev, "unknown chip, revision: %#x\n", ret); 385 return -EINVAL; 386 } 387 388 if (plat && plat->init) 389 plat->init(ab8500); 390 391 /* Clear and mask all interrupts */ 392 for (i = 0; i < 10; i++) { 393 ab8500_read(ab8500, AB8500_IT_LATCH1_REG + i); 394 ab8500_write(ab8500, AB8500_IT_MASK1_REG + i, 0xff); 395 } 396 397 for (i = 18; i < 24; i++) { 398 ab8500_read(ab8500, AB8500_IT_LATCH1_REG + i); 399 ab8500_write(ab8500, AB8500_IT_MASK1_REG + i, 0xff); 400 } 401 402 for (i = 0; i < AB8500_NUM_IRQ_REGS; i++) 403 ab8500->mask[i] = ab8500->oldmask[i] = 0xff; 404 405 if (ab8500->irq_base) { 406 ret = ab8500_irq_init(ab8500); 407 if (ret) 408 return ret; 409 410 ret = request_threaded_irq(ab8500->irq, NULL, ab8500_irq, 411 IRQF_ONESHOT, "ab8500", ab8500); 412 if (ret) 413 goto out_removeirq; 414 } 415 416 ret = mfd_add_devices(ab8500->dev, 0, ab8500_devs, 417 ARRAY_SIZE(ab8500_devs), NULL, 418 ab8500->irq_base); 419 if (ret) 420 goto out_freeirq; 421 422 return ret; 423 424 out_freeirq: 425 if (ab8500->irq_base) { 426 free_irq(ab8500->irq, ab8500); 427 out_removeirq: 428 ab8500_irq_remove(ab8500); 429 } 430 return ret; 431 } 432 433 int __devexit ab8500_exit(struct ab8500 *ab8500) 434 { 435 mfd_remove_devices(ab8500->dev); 436 if (ab8500->irq_base) { 437 free_irq(ab8500->irq, ab8500); 438 ab8500_irq_remove(ab8500); 439 } 440 441 return 0; 442 } 443 444 MODULE_AUTHOR("Srinidhi Kasagar, Rabin Vincent"); 445 MODULE_DESCRIPTION("AB8500 MFD core"); 446 MODULE_LICENSE("GPL v2"); 447