1 /* 2 * Copyright (c) 2000-2006 LSI Logic Corporation. 3 * 4 * 5 * Name: mpi_cnfg.h 6 * Title: MPI Config message, structures, and Pages 7 * Creation Date: July 27, 2000 8 * 9 * mpi_cnfg.h Version: 01.05.13 10 * 11 * Version History 12 * --------------- 13 * 14 * Date Version Description 15 * -------- -------- ------------------------------------------------------ 16 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 17 * 06-06-00 01.00.01 Update version number for 1.0 release. 18 * 06-08-00 01.00.02 Added _PAGEVERSION definitions for all pages. 19 * Added FcPhLowestVersion, FcPhHighestVersion, Reserved2 20 * fields to FC_DEVICE_0 page, updated the page version. 21 * Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in 22 * SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages 23 * and updated the page versions. 24 * Added _RESPONSE_ID_MASK definition to SCSI_PORT_1 25 * page and updated the page version. 26 * Added Information field and _INFO_PARAMS_NEGOTIATED 27 * definitionto SCSI_DEVICE_0 page. 28 * 06-22-00 01.00.03 Removed batch controls from LAN_0 page and updated the 29 * page version. 30 * Added BucketsRemaining to LAN_1 page, redefined the 31 * state values, and updated the page version. 32 * Revised bus width definitions in SCSI_PORT_0, 33 * SCSI_DEVICE_0 and SCSI_DEVICE_1 pages. 34 * 06-30-00 01.00.04 Added MaxReplySize to LAN_1 page and updated the page 35 * version. 36 * Moved FC_DEVICE_0 PageAddress description to spec. 37 * 07-27-00 01.00.05 Corrected the SubsystemVendorID and SubsystemID field 38 * widths in IOC_0 page and updated the page version. 39 * 11-02-00 01.01.01 Original release for post 1.0 work 40 * Added Manufacturing pages, IO Unit Page 2, SCSI SPI 41 * Port Page 2, FC Port Page 4, FC Port Page 5 42 * 11-15-00 01.01.02 Interim changes to match proposals 43 * 12-04-00 01.01.03 Config page changes to match MPI rev 1.00.01. 44 * 12-05-00 01.01.04 Modified config page actions. 45 * 01-09-01 01.01.05 Added defines for page address formats. 46 * Data size for Manufacturing pages 2 and 3 no longer 47 * defined here. 48 * Io Unit Page 2 size is fixed at 4 adapters and some 49 * flags were changed. 50 * SCSI Port Page 2 Device Settings modified. 51 * New fields added to FC Port Page 0 and some flags 52 * cleaned up. 53 * Removed impedance flash from FC Port Page 1. 54 * Added FC Port pages 6 and 7. 55 * 01-25-01 01.01.06 Added MaxInitiators field to FcPortPage0. 56 * 01-29-01 01.01.07 Changed some defines to make them 32 character unique. 57 * Added some LinkType defines for FcPortPage0. 58 * 02-20-01 01.01.08 Started using MPI_POINTER. 59 * 02-27-01 01.01.09 Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with 60 * MPI_CONFIG_PAGETYPE_RAID_VOLUME. 61 * Added definitions and structures for IOC Page 2 and 62 * RAID Volume Page 2. 63 * 03-27-01 01.01.10 Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9. 64 * CONFIG_PAGE_FC_PORT_3 now supports persistent by DID. 65 * Added VendorId and ProductRevLevel fields to 66 * RAIDVOL2_IM_PHYS_ID struct. 67 * Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_ 68 * defines to make them compatible to MPI version 1.0. 69 * Added structure offset comments. 70 * 04-09-01 01.01.11 Added some new defines for the PageAddress field and 71 * removed some obsolete ones. 72 * Added IO Unit Page 3. 73 * Modified defines for Scsi Port Page 2. 74 * Modified RAID Volume Pages. 75 * 08-08-01 01.02.01 Original release for v1.2 work. 76 * Added SepID and SepBus to RVP2 IMPhysicalDisk struct. 77 * Added defines for the SEP bits in RVP2 VolumeSettings. 78 * Modified the DeviceSettings field in RVP2 to use the 79 * proper structure. 80 * Added defines for SES, SAF-TE, and cross channel for 81 * IOCPage2 CapabilitiesFlags. 82 * Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE. 83 * Removed define for 84 * MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE. 85 * Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT. 86 * 08-29-01 01.02.02 Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035. 87 * Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY 88 * and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY. 89 * Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS, 90 * MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and 91 * MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and 92 * MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED. 93 * Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED 94 * and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED. 95 * Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1. 96 * Added rejected bits to SCSI Device Page 0 Information. 97 * Increased size of ALPA array in FC Port Page 2 by one 98 * and removed a one byte reserved field. 99 * 09-28-01 01.02.03 Swapped NegWireSpeedLow and NegWireSpeedLow in 100 * CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering. 101 * Added structures for Manufacturing Page 4, IO Unit 102 * Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and 103 * RAID PhysDisk Page 0. 104 * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK. 105 * Modified some of the new defines to make them 32 106 * character unique. 107 * Modified how variable length pages (arrays) are defined. 108 * Added generic defines for hot spare pools and RAID 109 * volume types. 110 * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR. 111 * 03-14-02 01.02.06 Added PCISlotNum field to CONFIG_PAGE_IOC_1 along with 112 * related define, and bumped the page version define. 113 * 05-31-02 01.02.07 Added a Flags field to CONFIG_PAGE_IOC_2_RAID_VOL in a 114 * reserved byte and added a define. 115 * Added define for 116 * MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE. 117 * Added new config page: CONFIG_PAGE_IOC_5. 118 * Added MaxAliases, MaxHardAliases, and NumCurrentAliases 119 * fields to CONFIG_PAGE_FC_PORT_0. 120 * Added AltConnector and NumRequestedAliases fields to 121 * CONFIG_PAGE_FC_PORT_1. 122 * Added new config page: CONFIG_PAGE_FC_PORT_10. 123 * 07-12-02 01.02.08 Added more MPI_MANUFACTPAGE_DEVID_ defines. 124 * Added additional MPI_SCSIDEVPAGE0_NP_ defines. 125 * Added more MPI_SCSIDEVPAGE1_RP_ defines. 126 * Added define for 127 * MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE. 128 * Added new config page: CONFIG_PAGE_SCSI_DEVICE_3. 129 * Modified MPI_FCPORTPAGE5_FLAGS_ defines. 130 * 09-16-02 01.02.09 Added MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG define. 131 * 11-15-02 01.02.10 Added ConnectedID defines for CONFIG_PAGE_SCSI_PORT_0. 132 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1. 133 * Added more Flags defines for CONFIG_PAGE_FC_DEVICE_0. 134 * 04-01-03 01.02.11 Added RR_TOV field and additional Flags defines for 135 * CONFIG_PAGE_FC_PORT_1. 136 * Added define MPI_FCPORTPAGE5_FLAGS_DISABLE to disable 137 * an alias. 138 * Added more device id defines. 139 * 06-26-03 01.02.12 Added MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID define. 140 * Added TargetConfig and IDConfig fields to 141 * CONFIG_PAGE_SCSI_PORT_1. 142 * Added more PortFlags defines for CONFIG_PAGE_SCSI_PORT_2 143 * to control DV. 144 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1. 145 * In CONFIG_PAGE_FC_DEVICE_0, replaced Reserved1 field 146 * with ADISCHardALPA. 147 * Added MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY define. 148 * 01-16-04 01.02.13 Added InitiatorDeviceTimeout and InitiatorIoPendTimeout 149 * fields and related defines to CONFIG_PAGE_FC_PORT_1. 150 * Added define for 151 * MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK. 152 * Added new fields to the substructures of 153 * CONFIG_PAGE_FC_PORT_10. 154 * 04-29-04 01.02.14 Added define for IDP bit for CONFIG_PAGE_SCSI_PORT_0, 155 * CONFIG_PAGE_SCSI_DEVICE_0, and 156 * CONFIG_PAGE_SCSI_DEVICE_1. Also bumped Page Version for 157 * these pages. 158 * 05-11-04 01.03.01 Added structure for CONFIG_PAGE_INBAND_0. 159 * 08-19-04 01.05.01 Modified MSG_CONFIG request to support extended config 160 * pages. 161 * Added a new structure for extended config page header. 162 * Added new extended config pages types and structures for 163 * SAS IO Unit, SAS Expander, SAS Device, and SAS PHY. 164 * Replaced a reserved byte in CONFIG_PAGE_MANUFACTURING_4 165 * to add a Flags field. 166 * Two new Manufacturing config pages (5 and 6). 167 * Two new bits defined for IO Unit Page 1 Flags field. 168 * Modified CONFIG_PAGE_IO_UNIT_2 to add three new fields 169 * to specify the BIOS boot device. 170 * Four new Flags bits defined for IO Unit Page 2. 171 * Added IO Unit Page 4. 172 * Added EEDP Flags settings to IOC Page 1. 173 * Added new BIOS Page 1 config page. 174 * 10-05-04 01.05.02 Added define for 175 * MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE. 176 * Added new Flags field to CONFIG_PAGE_MANUFACTURING_5 and 177 * associated defines. 178 * Added more defines for SAS IO Unit Page 0 179 * DiscoveryStatus field. 180 * Added define for MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK 181 * and MPI_SAS_IOUNIT0_DS_TABLE_LINK. 182 * Added defines for Physical Mapping Modes to SAS IO Unit 183 * Page 2. 184 * Added define for 185 * MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH. 186 * 10-27-04 01.05.03 Added defines for new SAS PHY page addressing mode. 187 * Added defines for MaxTargetSpinUp to BIOS Page 1. 188 * Added 5 new ControlFlags defines for SAS IO Unit 189 * Page 1. 190 * Added MaxNumPhysicalMappedIDs field to SAS IO Unit 191 * Page 2. 192 * Added AccessStatus field to SAS Device Page 0 and added 193 * new Flags bits for supported SATA features. 194 * 12-07-04 01.05.04 Added config page structures for BIOS Page 2, RAID 195 * Volume Page 1, and RAID Physical Disk Page 1. 196 * Replaced IO Unit Page 1 BootTargetID,BootBus, and 197 * BootAdapterNum with reserved field. 198 * Added DataScrubRate and ResyncRate to RAID Volume 199 * Page 0. 200 * Added MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT 201 * define. 202 * 12-09-04 01.05.05 Added Target Mode Large CDB Enable to FC Port Page 1 203 * Flags field. 204 * Added Auto Port Config flag define for SAS IOUNIT 205 * Page 1 ControlFlags. 206 * Added Disabled bad Phy define to Expander Page 1 207 * Discovery Info field. 208 * Added SAS/SATA device support to SAS IOUnit Page 1 209 * ControlFlags. 210 * Added Unsupported device to SAS Dev Page 0 Flags field 211 * Added disable use SATA Hash Address for SAS IOUNIT 212 * page 1 in ControlFields. 213 * 01-15-05 01.05.06 Added defaults for data scrub rate and resync rate to 214 * Manufacturing Page 4. 215 * Added new defines for BIOS Page 1 IOCSettings field. 216 * Added ExtDiskIdentifier field to RAID Physical Disk 217 * Page 0. 218 * Added new defines for SAS IO Unit Page 1 ControlFlags 219 * and to SAS Device Page 0 Flags to control SATA devices. 220 * Added defines and structures for the new Log Page 0, a 221 * new type of configuration page. 222 * 02-09-05 01.05.07 Added InactiveStatus field to RAID Volume Page 0. 223 * Added WWID field to RAID Volume Page 1. 224 * Added PhysicalPort field to SAS Expander pages 0 and 1. 225 * 03-11-05 01.05.08 Removed the EEDP flags from IOC Page 1. 226 * Added Enclosure/Slot boot device format to BIOS Page 2. 227 * New status value for RAID Volume Page 0 VolumeStatus 228 * (VolumeState subfield). 229 * New value for RAID Physical Page 0 InactiveStatus. 230 * Added Inactive Volume Member flag RAID Physical Disk 231 * Page 0 PhysDiskStatus field. 232 * New physical mapping mode in SAS IO Unit Page 2. 233 * Added CONFIG_PAGE_SAS_ENCLOSURE_0. 234 * Added Slot and Enclosure fields to SAS Device Page 0. 235 * 06-24-05 01.05.09 Added EEDP defines to IOC Page 1. 236 * Added more RAID type defines to IOC Page 2. 237 * Added Port Enable Delay settings to BIOS Page 1. 238 * Added Bad Block Table Full define to RAID Volume Page 0. 239 * Added Previous State defines to RAID Physical Disk 240 * Page 0. 241 * Added Max Sata Targets define for DiscoveryStatus field 242 * of SAS IO Unit Page 0. 243 * Added Device Self Test to Control Flags of SAS IO Unit 244 * Page 1. 245 * Added Direct Attach Starting Slot Number define for SAS 246 * IO Unit Page 2. 247 * Added new fields in SAS Device Page 2 for enclosure 248 * mapping. 249 * Added OwnerDevHandle and Flags field to SAS PHY Page 0. 250 * Added IOC GPIO Flags define to SAS Enclosure Page 0. 251 * Fixed the value for MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT. 252 * 08-03-05 01.05.10 Removed ISDataScrubRate and ISResyncRate from 253 * Manufacturing Page 4. 254 * Added MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE bit. 255 * Added NumDevsPerEnclosure field to SAS IO Unit page 2. 256 * Added MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP 257 * define. 258 * Added EnclosureHandle field to SAS Expander page 0. 259 * Removed redundant NumTableEntriesProg field from SAS 260 * Expander Page 1. 261 * 08-30-05 01.05.11 Added DeviceID for FC949E and changed the DeviceID for 262 * SAS1078. 263 * Added more defines for Manufacturing Page 4 Flags field. 264 * Added more defines for IOCSettings and added 265 * ExpanderSpinup field to Bios Page 1. 266 * Added postpone SATA Init bit to SAS IO Unit Page 1 267 * ControlFlags. 268 * Changed LogEntry format for Log Page 0. 269 * 03-27-06 01.05.12 Added two new Flags defines for Manufacturing Page 4. 270 * Added Manufacturing Page 7. 271 * Added MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING. 272 * Added IOC Page 6. 273 * Added PrevBootDeviceForm field to CONFIG_PAGE_BIOS_2. 274 * Added MaxLBAHigh field to RAID Volume Page 0. 275 * Added Nvdata version fields to SAS IO Unit Page 0. 276 * Added AdditionalControlFlags, MaxTargetPortConnectTime, 277 * ReportDeviceMissingDelay, and IODeviceMissingDelay 278 * fields to SAS IO Unit Page 1. 279 * 10-11-06 01.05.13 Added NumForceWWID field and ForceWWID array to 280 * Manufacturing Page 5. 281 * Added Manufacturing pages 8 through 10. 282 * Added defines for supported metadata size bits in 283 * CapabilitiesFlags field of IOC Page 6. 284 * Added defines for metadata size bits in VolumeSettings 285 * field of RAID Volume Page 0. 286 * Added SATA Link Reset settings, Enable SATA Asynchronous 287 * Notification bit, and HideNonZeroAttachedPhyIdentifiers 288 * bit to AdditionalControlFlags field of SAS IO Unit 289 * Page 1. 290 * Added defines for Enclosure Devices Unmapped and 291 * Device Limit Exceeded bits in Status field of SAS IO 292 * Unit Page 2. 293 * Added more AccessStatus values for SAS Device Page 0. 294 * Added bit for SATA Asynchronous Notification Support in 295 * Flags field of SAS Device Page 0. 296 * -------------------------------------------------------------------------- 297 */ 298 299 #ifndef MPI_CNFG_H 300 #define MPI_CNFG_H 301 302 303 /***************************************************************************** 304 * 305 * C o n f i g M e s s a g e a n d S t r u c t u r e s 306 * 307 *****************************************************************************/ 308 309 typedef struct _CONFIG_PAGE_HEADER 310 { 311 U8 PageVersion; /* 00h */ 312 U8 PageLength; /* 01h */ 313 U8 PageNumber; /* 02h */ 314 U8 PageType; /* 03h */ 315 } CONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER, 316 ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t; 317 318 typedef union _CONFIG_PAGE_HEADER_UNION 319 { 320 ConfigPageHeader_t Struct; 321 U8 Bytes[4]; 322 U16 Word16[2]; 323 U32 Word32; 324 } ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion, 325 CONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION; 326 327 typedef struct _CONFIG_EXTENDED_PAGE_HEADER 328 { 329 U8 PageVersion; /* 00h */ 330 U8 Reserved1; /* 01h */ 331 U8 PageNumber; /* 02h */ 332 U8 PageType; /* 03h */ 333 U16 ExtPageLength; /* 04h */ 334 U8 ExtPageType; /* 06h */ 335 U8 Reserved2; /* 07h */ 336 } CONFIG_EXTENDED_PAGE_HEADER, MPI_POINTER PTR_CONFIG_EXTENDED_PAGE_HEADER, 337 ConfigExtendedPageHeader_t, MPI_POINTER pConfigExtendedPageHeader_t; 338 339 340 341 /**************************************************************************** 342 * PageType field values 343 ****************************************************************************/ 344 #define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00) 345 #define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10) 346 #define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20) 347 #define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30) 348 #define MPI_CONFIG_PAGEATTR_MASK (0xF0) 349 350 #define MPI_CONFIG_PAGETYPE_IO_UNIT (0x00) 351 #define MPI_CONFIG_PAGETYPE_IOC (0x01) 352 #define MPI_CONFIG_PAGETYPE_BIOS (0x02) 353 #define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03) 354 #define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04) 355 #define MPI_CONFIG_PAGETYPE_FC_PORT (0x05) 356 #define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06) 357 #define MPI_CONFIG_PAGETYPE_LAN (0x07) 358 #define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 359 #define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09) 360 #define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 361 #define MPI_CONFIG_PAGETYPE_INBAND (0x0B) 362 #define MPI_CONFIG_PAGETYPE_EXTENDED (0x0F) 363 #define MPI_CONFIG_PAGETYPE_MASK (0x0F) 364 365 #define MPI_CONFIG_TYPENUM_MASK (0x0FFF) 366 367 368 /**************************************************************************** 369 * ExtPageType field values 370 ****************************************************************************/ 371 #define MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 372 #define MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 373 #define MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 374 #define MPI_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 375 #define MPI_CONFIG_EXTPAGETYPE_LOG (0x14) 376 #define MPI_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 377 378 379 /**************************************************************************** 380 * PageAddress field values 381 ****************************************************************************/ 382 #define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF) 383 384 #define MPI_SCSI_DEVICE_FORM_MASK (0xF0000000) 385 #define MPI_SCSI_DEVICE_FORM_BUS_TID (0x00000000) 386 #define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF) 387 #define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0) 388 #define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00) 389 #define MPI_SCSI_DEVICE_BUS_SHIFT (8) 390 #define MPI_SCSI_DEVICE_FORM_TARGET_MODE (0x10000000) 391 #define MPI_SCSI_DEVICE_TM_RESPOND_ID_MASK (0x000000FF) 392 #define MPI_SCSI_DEVICE_TM_RESPOND_ID_SHIFT (0) 393 #define MPI_SCSI_DEVICE_TM_BUS_MASK (0x0000FF00) 394 #define MPI_SCSI_DEVICE_TM_BUS_SHIFT (8) 395 #define MPI_SCSI_DEVICE_TM_INIT_ID_MASK (0x00FF0000) 396 #define MPI_SCSI_DEVICE_TM_INIT_ID_SHIFT (16) 397 398 #define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000) 399 #define MPI_FC_PORT_PGAD_PORT_SHIFT (28) 400 #define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000) 401 #define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000) 402 #define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF) 403 #define MPI_FC_PORT_PGAD_INDEX_SHIFT (0) 404 405 #define MPI_FC_DEVICE_PGAD_PORT_MASK (0xF0000000) 406 #define MPI_FC_DEVICE_PGAD_PORT_SHIFT (28) 407 #define MPI_FC_DEVICE_PGAD_FORM_MASK (0x0F000000) 408 #define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID (0x00000000) 409 #define MPI_FC_DEVICE_PGAD_ND_PORT_MASK (0xF0000000) 410 #define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT (28) 411 #define MPI_FC_DEVICE_PGAD_ND_DID_MASK (0x00FFFFFF) 412 #define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT (0) 413 #define MPI_FC_DEVICE_PGAD_FORM_BUS_TID (0x01000000) 414 #define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00) 415 #define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8) 416 #define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF) 417 #define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0) 418 419 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 420 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0) 421 422 #define MPI_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 423 #define MPI_SAS_EXPAND_PGAD_FORM_SHIFT (28) 424 #define MPI_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 425 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x00000001) 426 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE (0x00000002) 427 #define MPI_SAS_EXPAND_PGAD_GNH_MASK_HANDLE (0x0000FFFF) 428 #define MPI_SAS_EXPAND_PGAD_GNH_SHIFT_HANDLE (0) 429 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_PHY (0x00FF0000) 430 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_PHY (16) 431 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_HANDLE (0x0000FFFF) 432 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_HANDLE (0) 433 #define MPI_SAS_EXPAND_PGAD_H_MASK_HANDLE (0x0000FFFF) 434 #define MPI_SAS_EXPAND_PGAD_H_SHIFT_HANDLE (0) 435 436 #define MPI_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 437 #define MPI_SAS_DEVICE_PGAD_FORM_SHIFT (28) 438 #define MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 439 #define MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID (0x00000001) 440 #define MPI_SAS_DEVICE_PGAD_FORM_HANDLE (0x00000002) 441 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_MASK (0x0000FFFF) 442 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_SHIFT (0) 443 #define MPI_SAS_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00) 444 #define MPI_SAS_DEVICE_PGAD_BT_BUS_SHIFT (8) 445 #define MPI_SAS_DEVICE_PGAD_BT_TID_MASK (0x000000FF) 446 #define MPI_SAS_DEVICE_PGAD_BT_TID_SHIFT (0) 447 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_MASK (0x0000FFFF) 448 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_SHIFT (0) 449 450 #define MPI_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 451 #define MPI_SAS_PHY_PGAD_FORM_SHIFT (28) 452 #define MPI_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x0) 453 #define MPI_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x1) 454 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 455 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_SHIFT (0) 456 #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 457 #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_SHIFT (0) 458 459 #define MPI_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 460 #define MPI_SAS_ENCLOS_PGAD_FORM_SHIFT (28) 461 #define MPI_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 462 #define MPI_SAS_ENCLOS_PGAD_FORM_HANDLE (0x00000001) 463 #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_MASK (0x0000FFFF) 464 #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_SHIFT (0) 465 #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_MASK (0x0000FFFF) 466 #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_SHIFT (0) 467 468 469 470 /**************************************************************************** 471 * Config Request Message 472 ****************************************************************************/ 473 typedef struct _MSG_CONFIG 474 { 475 U8 Action; /* 00h */ 476 U8 Reserved; /* 01h */ 477 U8 ChainOffset; /* 02h */ 478 U8 Function; /* 03h */ 479 U16 ExtPageLength; /* 04h */ 480 U8 ExtPageType; /* 06h */ 481 U8 MsgFlags; /* 07h */ 482 U32 MsgContext; /* 08h */ 483 U8 Reserved2[8]; /* 0Ch */ 484 CONFIG_PAGE_HEADER Header; /* 14h */ 485 U32 PageAddress; /* 18h */ 486 SGE_IO_UNION PageBufferSGE; /* 1Ch */ 487 } MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG, 488 Config_t, MPI_POINTER pConfig_t; 489 490 491 /**************************************************************************** 492 * Action field values 493 ****************************************************************************/ 494 #define MPI_CONFIG_ACTION_PAGE_HEADER (0x00) 495 #define MPI_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 496 #define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 497 #define MPI_CONFIG_ACTION_PAGE_DEFAULT (0x03) 498 #define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 499 #define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 500 #define MPI_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 501 502 503 /* Config Reply Message */ 504 typedef struct _MSG_CONFIG_REPLY 505 { 506 U8 Action; /* 00h */ 507 U8 Reserved; /* 01h */ 508 U8 MsgLength; /* 02h */ 509 U8 Function; /* 03h */ 510 U16 ExtPageLength; /* 04h */ 511 U8 ExtPageType; /* 06h */ 512 U8 MsgFlags; /* 07h */ 513 U32 MsgContext; /* 08h */ 514 U8 Reserved2[2]; /* 0Ch */ 515 U16 IOCStatus; /* 0Eh */ 516 U32 IOCLogInfo; /* 10h */ 517 CONFIG_PAGE_HEADER Header; /* 14h */ 518 } MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY, 519 ConfigReply_t, MPI_POINTER pConfigReply_t; 520 521 522 523 /***************************************************************************** 524 * 525 * C o n f i g u r a t i o n P a g e s 526 * 527 *****************************************************************************/ 528 529 /**************************************************************************** 530 * Manufacturing Config pages 531 ****************************************************************************/ 532 #define MPI_MANUFACTPAGE_VENDORID_LSILOGIC (0x1000) 533 /* Fibre Channel */ 534 #define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621) 535 #define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624) 536 #define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622) 537 #define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628) 538 #define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626) 539 #define MPI_MANUFACTPAGE_DEVICEID_FC939X (0x0642) 540 #define MPI_MANUFACTPAGE_DEVICEID_FC949X (0x0640) 541 #define MPI_MANUFACTPAGE_DEVICEID_FC949E (0x0646) 542 /* SCSI */ 543 #define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030) 544 #define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031) 545 #define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032) 546 #define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033) 547 #define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040) 548 #define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041) 549 /* SAS */ 550 #define MPI_MANUFACTPAGE_DEVID_SAS1064 (0x0050) 551 #define MPI_MANUFACTPAGE_DEVID_SAS1064A (0x005C) 552 #define MPI_MANUFACTPAGE_DEVID_SAS1064E (0x0056) 553 #define MPI_MANUFACTPAGE_DEVID_SAS1066 (0x005E) 554 #define MPI_MANUFACTPAGE_DEVID_SAS1066E (0x005A) 555 #define MPI_MANUFACTPAGE_DEVID_SAS1068 (0x0054) 556 #define MPI_MANUFACTPAGE_DEVID_SAS1068E (0x0058) 557 #define MPI_MANUFACTPAGE_DEVID_SAS1078 (0x0062) 558 559 560 typedef struct _CONFIG_PAGE_MANUFACTURING_0 561 { 562 CONFIG_PAGE_HEADER Header; /* 00h */ 563 U8 ChipName[16]; /* 04h */ 564 U8 ChipRevision[8]; /* 14h */ 565 U8 BoardName[16]; /* 1Ch */ 566 U8 BoardAssembly[16]; /* 2Ch */ 567 U8 BoardTracerNumber[16]; /* 3Ch */ 568 569 } CONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0, 570 ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t; 571 572 #define MPI_MANUFACTURING0_PAGEVERSION (0x00) 573 574 575 typedef struct _CONFIG_PAGE_MANUFACTURING_1 576 { 577 CONFIG_PAGE_HEADER Header; /* 00h */ 578 U8 VPD[256]; /* 04h */ 579 } CONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1, 580 ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t; 581 582 #define MPI_MANUFACTURING1_PAGEVERSION (0x00) 583 584 585 typedef struct _MPI_CHIP_REVISION_ID 586 { 587 U16 DeviceID; /* 00h */ 588 U8 PCIRevisionID; /* 02h */ 589 U8 Reserved; /* 03h */ 590 } MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID, 591 MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t; 592 593 594 /* 595 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 596 * one and check Header.PageLength at runtime. 597 */ 598 #ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS 599 #define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 600 #endif 601 602 typedef struct _CONFIG_PAGE_MANUFACTURING_2 603 { 604 CONFIG_PAGE_HEADER Header; /* 00h */ 605 MPI_CHIP_REVISION_ID ChipId; /* 04h */ 606 U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */ 607 } CONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2, 608 ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t; 609 610 #define MPI_MANUFACTURING2_PAGEVERSION (0x00) 611 612 613 /* 614 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 615 * one and check Header.PageLength at runtime. 616 */ 617 #ifndef MPI_MAN_PAGE_3_INFO_WORDS 618 #define MPI_MAN_PAGE_3_INFO_WORDS (1) 619 #endif 620 621 typedef struct _CONFIG_PAGE_MANUFACTURING_3 622 { 623 CONFIG_PAGE_HEADER Header; /* 00h */ 624 MPI_CHIP_REVISION_ID ChipId; /* 04h */ 625 U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */ 626 } CONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3, 627 ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t; 628 629 #define MPI_MANUFACTURING3_PAGEVERSION (0x00) 630 631 632 typedef struct _CONFIG_PAGE_MANUFACTURING_4 633 { 634 CONFIG_PAGE_HEADER Header; /* 00h */ 635 U32 Reserved1; /* 04h */ 636 U8 InfoOffset0; /* 08h */ 637 U8 InfoSize0; /* 09h */ 638 U8 InfoOffset1; /* 0Ah */ 639 U8 InfoSize1; /* 0Bh */ 640 U8 InquirySize; /* 0Ch */ 641 U8 Flags; /* 0Dh */ 642 U16 Reserved2; /* 0Eh */ 643 U8 InquiryData[56]; /* 10h */ 644 U32 ISVolumeSettings; /* 48h */ 645 U32 IMEVolumeSettings; /* 4Ch */ 646 U32 IMVolumeSettings; /* 50h */ 647 U32 Reserved3; /* 54h */ 648 U32 Reserved4; /* 58h */ 649 U32 Reserved5; /* 5Ch */ 650 U8 IMEDataScrubRate; /* 60h */ 651 U8 IMEResyncRate; /* 61h */ 652 U16 Reserved6; /* 62h */ 653 U8 IMDataScrubRate; /* 64h */ 654 U8 IMResyncRate; /* 65h */ 655 U16 Reserved7; /* 66h */ 656 U32 Reserved8; /* 68h */ 657 U32 Reserved9; /* 6Ch */ 658 } CONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4, 659 ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t; 660 661 #define MPI_MANUFACTURING4_PAGEVERSION (0x04) 662 663 /* defines for the Flags field */ 664 #define MPI_MANPAGE4_FORCE_BAD_BLOCK_TABLE (0x80) 665 #define MPI_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x40) 666 #define MPI_MANPAGE4_IME_DISABLE (0x20) 667 #define MPI_MANPAGE4_IM_DISABLE (0x10) 668 #define MPI_MANPAGE4_IS_DISABLE (0x08) 669 #define MPI_MANPAGE4_IR_MODEPAGE8_DISABLE (0x04) 670 #define MPI_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x02) 671 #define MPI_MANPAGE4_IR_NO_MIX_SAS_SATA (0x01) 672 673 674 #ifndef MPI_MANPAGE5_NUM_FORCEWWID 675 #define MPI_MANPAGE5_NUM_FORCEWWID (1) 676 #endif 677 678 typedef struct _CONFIG_PAGE_MANUFACTURING_5 679 { 680 CONFIG_PAGE_HEADER Header; /* 00h */ 681 U64 BaseWWID; /* 04h */ 682 U8 Flags; /* 0Ch */ 683 U8 NumForceWWID; /* 0Dh */ 684 U16 Reserved2; /* 0Eh */ 685 U32 Reserved3; /* 10h */ 686 U32 Reserved4; /* 14h */ 687 U64 ForceWWID[MPI_MANPAGE5_NUM_FORCEWWID]; /* 18h */ 688 } CONFIG_PAGE_MANUFACTURING_5, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_5, 689 ManufacturingPage5_t, MPI_POINTER pManufacturingPage5_t; 690 691 #define MPI_MANUFACTURING5_PAGEVERSION (0x02) 692 693 /* defines for the Flags field */ 694 #define MPI_MANPAGE5_TWO_WWID_PER_PHY (0x01) 695 696 697 typedef struct _CONFIG_PAGE_MANUFACTURING_6 698 { 699 CONFIG_PAGE_HEADER Header; /* 00h */ 700 U32 ProductSpecificInfo;/* 04h */ 701 } CONFIG_PAGE_MANUFACTURING_6, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_6, 702 ManufacturingPage6_t, MPI_POINTER pManufacturingPage6_t; 703 704 #define MPI_MANUFACTURING6_PAGEVERSION (0x00) 705 706 707 typedef struct _MPI_MANPAGE7_CONNECTOR_INFO 708 { 709 U32 Pinout; /* 00h */ 710 U8 Connector[16]; /* 04h */ 711 U8 Location; /* 14h */ 712 U8 Reserved1; /* 15h */ 713 U16 Slot; /* 16h */ 714 U32 Reserved2; /* 18h */ 715 } MPI_MANPAGE7_CONNECTOR_INFO, MPI_POINTER PTR_MPI_MANPAGE7_CONNECTOR_INFO, 716 MpiManPage7ConnectorInfo_t, MPI_POINTER pMpiManPage7ConnectorInfo_t; 717 718 /* defines for the Pinout field */ 719 #define MPI_MANPAGE7_PINOUT_SFF_8484_L4 (0x00080000) 720 #define MPI_MANPAGE7_PINOUT_SFF_8484_L3 (0x00040000) 721 #define MPI_MANPAGE7_PINOUT_SFF_8484_L2 (0x00020000) 722 #define MPI_MANPAGE7_PINOUT_SFF_8484_L1 (0x00010000) 723 #define MPI_MANPAGE7_PINOUT_SFF_8470_L4 (0x00000800) 724 #define MPI_MANPAGE7_PINOUT_SFF_8470_L3 (0x00000400) 725 #define MPI_MANPAGE7_PINOUT_SFF_8470_L2 (0x00000200) 726 #define MPI_MANPAGE7_PINOUT_SFF_8470_L1 (0x00000100) 727 #define MPI_MANPAGE7_PINOUT_SFF_8482 (0x00000002) 728 #define MPI_MANPAGE7_PINOUT_CONNECTION_UNKNOWN (0x00000001) 729 730 /* defines for the Location field */ 731 #define MPI_MANPAGE7_LOCATION_UNKNOWN (0x01) 732 #define MPI_MANPAGE7_LOCATION_INTERNAL (0x02) 733 #define MPI_MANPAGE7_LOCATION_EXTERNAL (0x04) 734 #define MPI_MANPAGE7_LOCATION_SWITCHABLE (0x08) 735 #define MPI_MANPAGE7_LOCATION_AUTO (0x10) 736 #define MPI_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 737 #define MPI_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 738 739 /* 740 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 741 * one and check NumPhys at runtime. 742 */ 743 #ifndef MPI_MANPAGE7_CONNECTOR_INFO_MAX 744 #define MPI_MANPAGE7_CONNECTOR_INFO_MAX (1) 745 #endif 746 747 typedef struct _CONFIG_PAGE_MANUFACTURING_7 748 { 749 CONFIG_PAGE_HEADER Header; /* 00h */ 750 U32 Reserved1; /* 04h */ 751 U32 Reserved2; /* 08h */ 752 U32 Flags; /* 0Ch */ 753 U8 EnclosureName[16]; /* 10h */ 754 U8 NumPhys; /* 20h */ 755 U8 Reserved3; /* 21h */ 756 U16 Reserved4; /* 22h */ 757 MPI_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI_MANPAGE7_CONNECTOR_INFO_MAX]; /* 24h */ 758 } CONFIG_PAGE_MANUFACTURING_7, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_7, 759 ManufacturingPage7_t, MPI_POINTER pManufacturingPage7_t; 760 761 #define MPI_MANUFACTURING7_PAGEVERSION (0x00) 762 763 /* defines for the Flags field */ 764 #define MPI_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 765 766 767 typedef struct _CONFIG_PAGE_MANUFACTURING_8 768 { 769 CONFIG_PAGE_HEADER Header; /* 00h */ 770 U32 ProductSpecificInfo;/* 04h */ 771 } CONFIG_PAGE_MANUFACTURING_8, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_8, 772 ManufacturingPage8_t, MPI_POINTER pManufacturingPage8_t; 773 774 #define MPI_MANUFACTURING8_PAGEVERSION (0x00) 775 776 777 typedef struct _CONFIG_PAGE_MANUFACTURING_9 778 { 779 CONFIG_PAGE_HEADER Header; /* 00h */ 780 U32 ProductSpecificInfo;/* 04h */ 781 } CONFIG_PAGE_MANUFACTURING_9, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_9, 782 ManufacturingPage9_t, MPI_POINTER pManufacturingPage9_t; 783 784 #define MPI_MANUFACTURING6_PAGEVERSION (0x00) 785 786 787 typedef struct _CONFIG_PAGE_MANUFACTURING_10 788 { 789 CONFIG_PAGE_HEADER Header; /* 00h */ 790 U32 ProductSpecificInfo;/* 04h */ 791 } CONFIG_PAGE_MANUFACTURING_10, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_10, 792 ManufacturingPage10_t, MPI_POINTER pManufacturingPage10_t; 793 794 #define MPI_MANUFACTURING10_PAGEVERSION (0x00) 795 796 797 /**************************************************************************** 798 * IO Unit Config Pages 799 ****************************************************************************/ 800 801 typedef struct _CONFIG_PAGE_IO_UNIT_0 802 { 803 CONFIG_PAGE_HEADER Header; /* 00h */ 804 U64 UniqueValue; /* 04h */ 805 } CONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0, 806 IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t; 807 808 #define MPI_IOUNITPAGE0_PAGEVERSION (0x00) 809 810 811 typedef struct _CONFIG_PAGE_IO_UNIT_1 812 { 813 CONFIG_PAGE_HEADER Header; /* 00h */ 814 U32 Flags; /* 04h */ 815 } CONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1, 816 IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t; 817 818 #define MPI_IOUNITPAGE1_PAGEVERSION (0x02) 819 820 /* IO Unit Page 1 Flags defines */ 821 #define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000) 822 #define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001) 823 #define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002) 824 #define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000) 825 #define MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 826 #define MPI_IOUNITPAGE1_DISABLE_QUEUE_FULL_HANDLING (0x00000020) 827 #define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040) 828 #define MPI_IOUNITPAGE1_FORCE_32 (0x00000080) 829 #define MPI_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 830 #define MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE (0x00000200) 831 832 typedef struct _MPI_ADAPTER_INFO 833 { 834 U8 PciBusNumber; /* 00h */ 835 U8 PciDeviceAndFunctionNumber; /* 01h */ 836 U16 AdapterFlags; /* 02h */ 837 } MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO, 838 MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t; 839 840 #define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 841 #define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 842 843 typedef struct _CONFIG_PAGE_IO_UNIT_2 844 { 845 CONFIG_PAGE_HEADER Header; /* 00h */ 846 U32 Flags; /* 04h */ 847 U32 BiosVersion; /* 08h */ 848 MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */ 849 U32 Reserved1; /* 1Ch */ 850 } CONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2, 851 IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t; 852 853 #define MPI_IOUNITPAGE2_PAGEVERSION (0x02) 854 855 #define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002) 856 #define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004) 857 #define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008) 858 #define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010) 859 860 #define MPI_IOUNITPAGE2_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 861 #define MPI_IOUNITPAGE2_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 862 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DISPLAY (0x00000020) 863 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 864 865 866 /* 867 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 868 * one and check Header.PageLength at runtime. 869 */ 870 #ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX 871 #define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 872 #endif 873 874 typedef struct _CONFIG_PAGE_IO_UNIT_3 875 { 876 CONFIG_PAGE_HEADER Header; /* 00h */ 877 U8 GPIOCount; /* 04h */ 878 U8 Reserved1; /* 05h */ 879 U16 Reserved2; /* 06h */ 880 U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */ 881 } CONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3, 882 IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t; 883 884 #define MPI_IOUNITPAGE3_PAGEVERSION (0x01) 885 886 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC) 887 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 888 #define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00) 889 #define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01) 890 891 892 typedef struct _CONFIG_PAGE_IO_UNIT_4 893 { 894 CONFIG_PAGE_HEADER Header; /* 00h */ 895 U32 Reserved1; /* 04h */ 896 SGE_SIMPLE_UNION FWImageSGE; /* 08h */ 897 } CONFIG_PAGE_IO_UNIT_4, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_4, 898 IOUnitPage4_t, MPI_POINTER pIOUnitPage4_t; 899 900 #define MPI_IOUNITPAGE4_PAGEVERSION (0x00) 901 902 903 /**************************************************************************** 904 * IOC Config Pages 905 ****************************************************************************/ 906 907 typedef struct _CONFIG_PAGE_IOC_0 908 { 909 CONFIG_PAGE_HEADER Header; /* 00h */ 910 U32 TotalNVStore; /* 04h */ 911 U32 FreeNVStore; /* 08h */ 912 U16 VendorID; /* 0Ch */ 913 U16 DeviceID; /* 0Eh */ 914 U8 RevisionID; /* 10h */ 915 U8 Reserved[3]; /* 11h */ 916 U32 ClassCode; /* 14h */ 917 U16 SubsystemVendorID; /* 18h */ 918 U16 SubsystemID; /* 1Ah */ 919 } CONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0, 920 IOCPage0_t, MPI_POINTER pIOCPage0_t; 921 922 #define MPI_IOCPAGE0_PAGEVERSION (0x01) 923 924 925 typedef struct _CONFIG_PAGE_IOC_1 926 { 927 CONFIG_PAGE_HEADER Header; /* 00h */ 928 U32 Flags; /* 04h */ 929 U32 CoalescingTimeout; /* 08h */ 930 U8 CoalescingDepth; /* 0Ch */ 931 U8 PCISlotNum; /* 0Dh */ 932 U8 Reserved[2]; /* 0Eh */ 933 } CONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1, 934 IOCPage1_t, MPI_POINTER pIOCPage1_t; 935 936 #define MPI_IOCPAGE1_PAGEVERSION (0x03) 937 938 /* defines for the Flags field */ 939 #define MPI_IOCPAGE1_EEDP_MODE_MASK (0x07000000) 940 #define MPI_IOCPAGE1_EEDP_MODE_OFF (0x00000000) 941 #define MPI_IOCPAGE1_EEDP_MODE_T10 (0x01000000) 942 #define MPI_IOCPAGE1_EEDP_MODE_LSI_1 (0x02000000) 943 #define MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE (0x00000010) 944 #define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001) 945 946 #define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 947 948 949 typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL 950 { 951 U8 VolumeID; /* 00h */ 952 U8 VolumeBus; /* 01h */ 953 U8 VolumeIOC; /* 02h */ 954 U8 VolumePageNumber; /* 03h */ 955 U8 VolumeType; /* 04h */ 956 U8 Flags; /* 05h */ 957 U16 Reserved3; /* 06h */ 958 } CONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL, 959 ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t; 960 961 /* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */ 962 963 #define MPI_RAID_VOL_TYPE_IS (0x00) 964 #define MPI_RAID_VOL_TYPE_IME (0x01) 965 #define MPI_RAID_VOL_TYPE_IM (0x02) 966 #define MPI_RAID_VOL_TYPE_RAID_5 (0x03) 967 #define MPI_RAID_VOL_TYPE_RAID_6 (0x04) 968 #define MPI_RAID_VOL_TYPE_RAID_10 (0x05) 969 #define MPI_RAID_VOL_TYPE_RAID_50 (0x06) 970 #define MPI_RAID_VOL_TYPE_UNKNOWN (0xFF) 971 972 /* IOC Page 2 Volume Flags values */ 973 974 #define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE (0x08) 975 976 /* 977 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 978 * one and check Header.PageLength at runtime. 979 */ 980 #ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX 981 #define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1) 982 #endif 983 984 typedef struct _CONFIG_PAGE_IOC_2 985 { 986 CONFIG_PAGE_HEADER Header; /* 00h */ 987 U32 CapabilitiesFlags; /* 04h */ 988 U8 NumActiveVolumes; /* 08h */ 989 U8 MaxVolumes; /* 09h */ 990 U8 NumActivePhysDisks; /* 0Ah */ 991 U8 MaxPhysDisks; /* 0Bh */ 992 CONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */ 993 } CONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2, 994 IOCPage2_t, MPI_POINTER pIOCPage2_t; 995 996 #define MPI_IOCPAGE2_PAGEVERSION (0x04) 997 998 /* IOC Page 2 Capabilities flags */ 999 1000 #define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001) 1001 #define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002) 1002 #define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004) 1003 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_5_SUPPORT (0x00000008) 1004 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_6_SUPPORT (0x00000010) 1005 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_10_SUPPORT (0x00000020) 1006 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_50_SUPPORT (0x00000040) 1007 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING (0x10000000) 1008 #define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000) 1009 #define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000) 1010 #define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000) 1011 1012 1013 typedef struct _IOC_3_PHYS_DISK 1014 { 1015 U8 PhysDiskID; /* 00h */ 1016 U8 PhysDiskBus; /* 01h */ 1017 U8 PhysDiskIOC; /* 02h */ 1018 U8 PhysDiskNum; /* 03h */ 1019 } IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK, 1020 Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t; 1021 1022 /* 1023 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1024 * one and check Header.PageLength at runtime. 1025 */ 1026 #ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX 1027 #define MPI_IOC_PAGE_3_PHYSDISK_MAX (1) 1028 #endif 1029 1030 typedef struct _CONFIG_PAGE_IOC_3 1031 { 1032 CONFIG_PAGE_HEADER Header; /* 00h */ 1033 U8 NumPhysDisks; /* 04h */ 1034 U8 Reserved1; /* 05h */ 1035 U16 Reserved2; /* 06h */ 1036 IOC_3_PHYS_DISK PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */ 1037 } CONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3, 1038 IOCPage3_t, MPI_POINTER pIOCPage3_t; 1039 1040 #define MPI_IOCPAGE3_PAGEVERSION (0x00) 1041 1042 1043 typedef struct _IOC_4_SEP 1044 { 1045 U8 SEPTargetID; /* 00h */ 1046 U8 SEPBus; /* 01h */ 1047 U16 Reserved; /* 02h */ 1048 } IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP, 1049 Ioc4Sep_t, MPI_POINTER pIoc4Sep_t; 1050 1051 /* 1052 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1053 * one and check Header.PageLength at runtime. 1054 */ 1055 #ifndef MPI_IOC_PAGE_4_SEP_MAX 1056 #define MPI_IOC_PAGE_4_SEP_MAX (1) 1057 #endif 1058 1059 typedef struct _CONFIG_PAGE_IOC_4 1060 { 1061 CONFIG_PAGE_HEADER Header; /* 00h */ 1062 U8 ActiveSEP; /* 04h */ 1063 U8 MaxSEP; /* 05h */ 1064 U16 Reserved1; /* 06h */ 1065 IOC_4_SEP SEP[MPI_IOC_PAGE_4_SEP_MAX]; /* 08h */ 1066 } CONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4, 1067 IOCPage4_t, MPI_POINTER pIOCPage4_t; 1068 1069 #define MPI_IOCPAGE4_PAGEVERSION (0x00) 1070 1071 1072 typedef struct _IOC_5_HOT_SPARE 1073 { 1074 U8 PhysDiskNum; /* 00h */ 1075 U8 Reserved; /* 01h */ 1076 U8 HotSparePool; /* 02h */ 1077 U8 Flags; /* 03h */ 1078 } IOC_5_HOT_SPARE, MPI_POINTER PTR_IOC_5_HOT_SPARE, 1079 Ioc5HotSpare_t, MPI_POINTER pIoc5HotSpare_t; 1080 1081 /* IOC Page 5 HotSpare Flags */ 1082 #define MPI_IOC_PAGE_5_HOT_SPARE_ACTIVE (0x01) 1083 1084 /* 1085 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1086 * one and check Header.PageLength at runtime. 1087 */ 1088 #ifndef MPI_IOC_PAGE_5_HOT_SPARE_MAX 1089 #define MPI_IOC_PAGE_5_HOT_SPARE_MAX (1) 1090 #endif 1091 1092 typedef struct _CONFIG_PAGE_IOC_5 1093 { 1094 CONFIG_PAGE_HEADER Header; /* 00h */ 1095 U32 Reserved1; /* 04h */ 1096 U8 NumHotSpares; /* 08h */ 1097 U8 Reserved2; /* 09h */ 1098 U16 Reserved3; /* 0Ah */ 1099 IOC_5_HOT_SPARE HotSpare[MPI_IOC_PAGE_5_HOT_SPARE_MAX]; /* 0Ch */ 1100 } CONFIG_PAGE_IOC_5, MPI_POINTER PTR_CONFIG_PAGE_IOC_5, 1101 IOCPage5_t, MPI_POINTER pIOCPage5_t; 1102 1103 #define MPI_IOCPAGE5_PAGEVERSION (0x00) 1104 1105 typedef struct _CONFIG_PAGE_IOC_6 1106 { 1107 CONFIG_PAGE_HEADER Header; /* 00h */ 1108 U32 CapabilitiesFlags; /* 04h */ 1109 U8 MaxDrivesIS; /* 08h */ 1110 U8 MaxDrivesIM; /* 09h */ 1111 U8 MaxDrivesIME; /* 0Ah */ 1112 U8 Reserved1; /* 0Bh */ 1113 U8 MinDrivesIS; /* 0Ch */ 1114 U8 MinDrivesIM; /* 0Dh */ 1115 U8 MinDrivesIME; /* 0Eh */ 1116 U8 Reserved2; /* 0Fh */ 1117 U8 MaxGlobalHotSpares; /* 10h */ 1118 U8 Reserved3; /* 11h */ 1119 U16 Reserved4; /* 12h */ 1120 U32 Reserved5; /* 14h */ 1121 U32 SupportedStripeSizeMapIS; /* 18h */ 1122 U32 SupportedStripeSizeMapIME; /* 1Ch */ 1123 U32 Reserved6; /* 20h */ 1124 U8 MetadataSize; /* 24h */ 1125 U8 Reserved7; /* 25h */ 1126 U16 Reserved8; /* 26h */ 1127 U16 MaxBadBlockTableEntries; /* 28h */ 1128 U16 Reserved9; /* 2Ah */ 1129 U16 IRNvsramUsage; /* 2Ch */ 1130 U16 Reserved10; /* 2Eh */ 1131 U32 IRNvsramVersion; /* 30h */ 1132 U32 Reserved11; /* 34h */ 1133 U32 Reserved12; /* 38h */ 1134 } CONFIG_PAGE_IOC_6, MPI_POINTER PTR_CONFIG_PAGE_IOC_6, 1135 IOCPage6_t, MPI_POINTER pIOCPage6_t; 1136 1137 #define MPI_IOCPAGE6_PAGEVERSION (0x01) 1138 1139 /* IOC Page 6 Capabilities Flags */ 1140 1141 #define MPI_IOCPAGE6_CAP_FLAGS_MASK_METADATA_SIZE (0x00000006) 1142 #define MPI_IOCPAGE6_CAP_FLAGS_64MB_METADATA_SIZE (0x00000000) 1143 #define MPI_IOCPAGE6_CAP_FLAGS_512MB_METADATA_SIZE (0x00000002) 1144 1145 #define MPI_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1146 1147 1148 /**************************************************************************** 1149 * BIOS Config Pages 1150 ****************************************************************************/ 1151 1152 typedef struct _CONFIG_PAGE_BIOS_1 1153 { 1154 CONFIG_PAGE_HEADER Header; /* 00h */ 1155 U32 BiosOptions; /* 04h */ 1156 U32 IOCSettings; /* 08h */ 1157 U32 Reserved1; /* 0Ch */ 1158 U32 DeviceSettings; /* 10h */ 1159 U16 NumberOfDevices; /* 14h */ 1160 U8 ExpanderSpinup; /* 16h */ 1161 U8 Reserved2; /* 17h */ 1162 U16 IOTimeoutBlockDevicesNonRM; /* 18h */ 1163 U16 IOTimeoutSequential; /* 1Ah */ 1164 U16 IOTimeoutOther; /* 1Ch */ 1165 U16 IOTimeoutBlockDevicesRM; /* 1Eh */ 1166 } CONFIG_PAGE_BIOS_1, MPI_POINTER PTR_CONFIG_PAGE_BIOS_1, 1167 BIOSPage1_t, MPI_POINTER pBIOSPage1_t; 1168 1169 #define MPI_BIOSPAGE1_PAGEVERSION (0x03) 1170 1171 /* values for the BiosOptions field */ 1172 #define MPI_BIOSPAGE1_OPTIONS_SPI_ENABLE (0x00000400) 1173 #define MPI_BIOSPAGE1_OPTIONS_FC_ENABLE (0x00000200) 1174 #define MPI_BIOSPAGE1_OPTIONS_SAS_ENABLE (0x00000100) 1175 #define MPI_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1176 1177 /* values for the IOCSettings field */ 1178 #define MPI_BIOSPAGE1_IOCSET_MASK_INITIAL_SPINUP_DELAY (0x0F000000) 1179 #define MPI_BIOSPAGE1_IOCSET_SHIFT_INITIAL_SPINUP_DELAY (24) 1180 1181 #define MPI_BIOSPAGE1_IOCSET_MASK_PORT_ENABLE_DELAY (0x00F00000) 1182 #define MPI_BIOSPAGE1_IOCSET_SHIFT_PORT_ENABLE_DELAY (20) 1183 1184 #define MPI_BIOSPAGE1_IOCSET_AUTO_PORT_ENABLE (0x00080000) 1185 #define MPI_BIOSPAGE1_IOCSET_DIRECT_ATTACH_SPINUP_MODE (0x00040000) 1186 1187 #define MPI_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1188 #define MPI_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1189 #define MPI_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1190 1191 #define MPI_BIOSPAGE1_IOCSET_MASK_MAX_TARGET_SPIN_UP (0x0000F000) 1192 #define MPI_BIOSPAGE1_IOCSET_SHIFT_MAX_TARGET_SPIN_UP (12) 1193 1194 #define MPI_BIOSPAGE1_IOCSET_MASK_SPINUP_DELAY (0x00000F00) 1195 #define MPI_BIOSPAGE1_IOCSET_SHIFT_SPINUP_DELAY (8) 1196 1197 #define MPI_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1198 #define MPI_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1199 #define MPI_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1200 #define MPI_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1201 1202 #define MPI_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1203 #define MPI_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1204 #define MPI_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1205 #define MPI_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1206 #define MPI_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1207 1208 #define MPI_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1209 1210 /* values for the DeviceSettings field */ 1211 #define MPI_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1212 #define MPI_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1213 #define MPI_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1214 #define MPI_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1215 1216 /* defines for the ExpanderSpinup field */ 1217 #define MPI_BIOSPAGE1_EXPSPINUP_MASK_MAX_TARGET (0xF0) 1218 #define MPI_BIOSPAGE1_EXPSPINUP_SHIFT_MAX_TARGET (4) 1219 #define MPI_BIOSPAGE1_EXPSPINUP_MASK_DELAY (0x0F) 1220 1221 typedef struct _MPI_BOOT_DEVICE_ADAPTER_ORDER 1222 { 1223 U32 Reserved1; /* 00h */ 1224 U32 Reserved2; /* 04h */ 1225 U32 Reserved3; /* 08h */ 1226 U32 Reserved4; /* 0Ch */ 1227 U32 Reserved5; /* 10h */ 1228 U32 Reserved6; /* 14h */ 1229 U32 Reserved7; /* 18h */ 1230 U32 Reserved8; /* 1Ch */ 1231 U32 Reserved9; /* 20h */ 1232 U32 Reserved10; /* 24h */ 1233 U32 Reserved11; /* 28h */ 1234 U32 Reserved12; /* 2Ch */ 1235 U32 Reserved13; /* 30h */ 1236 U32 Reserved14; /* 34h */ 1237 U32 Reserved15; /* 38h */ 1238 U32 Reserved16; /* 3Ch */ 1239 U32 Reserved17; /* 40h */ 1240 } MPI_BOOT_DEVICE_ADAPTER_ORDER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_ORDER; 1241 1242 typedef struct _MPI_BOOT_DEVICE_ADAPTER_NUMBER 1243 { 1244 U8 TargetID; /* 00h */ 1245 U8 Bus; /* 01h */ 1246 U8 AdapterNumber; /* 02h */ 1247 U8 Reserved1; /* 03h */ 1248 U32 Reserved2; /* 04h */ 1249 U32 Reserved3; /* 08h */ 1250 U32 Reserved4; /* 0Ch */ 1251 U8 LUN[8]; /* 10h */ 1252 U32 Reserved5; /* 18h */ 1253 U32 Reserved6; /* 1Ch */ 1254 U32 Reserved7; /* 20h */ 1255 U32 Reserved8; /* 24h */ 1256 U32 Reserved9; /* 28h */ 1257 U32 Reserved10; /* 2Ch */ 1258 U32 Reserved11; /* 30h */ 1259 U32 Reserved12; /* 34h */ 1260 U32 Reserved13; /* 38h */ 1261 U32 Reserved14; /* 3Ch */ 1262 U32 Reserved15; /* 40h */ 1263 } MPI_BOOT_DEVICE_ADAPTER_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_NUMBER; 1264 1265 typedef struct _MPI_BOOT_DEVICE_PCI_ADDRESS 1266 { 1267 U8 TargetID; /* 00h */ 1268 U8 Bus; /* 01h */ 1269 U16 PCIAddress; /* 02h */ 1270 U32 Reserved1; /* 04h */ 1271 U32 Reserved2; /* 08h */ 1272 U32 Reserved3; /* 0Ch */ 1273 U8 LUN[8]; /* 10h */ 1274 U32 Reserved4; /* 18h */ 1275 U32 Reserved5; /* 1Ch */ 1276 U32 Reserved6; /* 20h */ 1277 U32 Reserved7; /* 24h */ 1278 U32 Reserved8; /* 28h */ 1279 U32 Reserved9; /* 2Ch */ 1280 U32 Reserved10; /* 30h */ 1281 U32 Reserved11; /* 34h */ 1282 U32 Reserved12; /* 38h */ 1283 U32 Reserved13; /* 3Ch */ 1284 U32 Reserved14; /* 40h */ 1285 } MPI_BOOT_DEVICE_PCI_ADDRESS, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_ADDRESS; 1286 1287 typedef struct _MPI_BOOT_DEVICE_SLOT_NUMBER 1288 { 1289 U8 TargetID; /* 00h */ 1290 U8 Bus; /* 01h */ 1291 U8 PCISlotNumber; /* 02h */ 1292 U8 Reserved1; /* 03h */ 1293 U32 Reserved2; /* 04h */ 1294 U32 Reserved3; /* 08h */ 1295 U32 Reserved4; /* 0Ch */ 1296 U8 LUN[8]; /* 10h */ 1297 U32 Reserved5; /* 18h */ 1298 U32 Reserved6; /* 1Ch */ 1299 U32 Reserved7; /* 20h */ 1300 U32 Reserved8; /* 24h */ 1301 U32 Reserved9; /* 28h */ 1302 U32 Reserved10; /* 2Ch */ 1303 U32 Reserved11; /* 30h */ 1304 U32 Reserved12; /* 34h */ 1305 U32 Reserved13; /* 38h */ 1306 U32 Reserved14; /* 3Ch */ 1307 U32 Reserved15; /* 40h */ 1308 } MPI_BOOT_DEVICE_PCI_SLOT_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_SLOT_NUMBER; 1309 1310 typedef struct _MPI_BOOT_DEVICE_FC_WWN 1311 { 1312 U64 WWPN; /* 00h */ 1313 U32 Reserved1; /* 08h */ 1314 U32 Reserved2; /* 0Ch */ 1315 U8 LUN[8]; /* 10h */ 1316 U32 Reserved3; /* 18h */ 1317 U32 Reserved4; /* 1Ch */ 1318 U32 Reserved5; /* 20h */ 1319 U32 Reserved6; /* 24h */ 1320 U32 Reserved7; /* 28h */ 1321 U32 Reserved8; /* 2Ch */ 1322 U32 Reserved9; /* 30h */ 1323 U32 Reserved10; /* 34h */ 1324 U32 Reserved11; /* 38h */ 1325 U32 Reserved12; /* 3Ch */ 1326 U32 Reserved13; /* 40h */ 1327 } MPI_BOOT_DEVICE_FC_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_FC_WWN; 1328 1329 typedef struct _MPI_BOOT_DEVICE_SAS_WWN 1330 { 1331 U64 SASAddress; /* 00h */ 1332 U32 Reserved1; /* 08h */ 1333 U32 Reserved2; /* 0Ch */ 1334 U8 LUN[8]; /* 10h */ 1335 U32 Reserved3; /* 18h */ 1336 U32 Reserved4; /* 1Ch */ 1337 U32 Reserved5; /* 20h */ 1338 U32 Reserved6; /* 24h */ 1339 U32 Reserved7; /* 28h */ 1340 U32 Reserved8; /* 2Ch */ 1341 U32 Reserved9; /* 30h */ 1342 U32 Reserved10; /* 34h */ 1343 U32 Reserved11; /* 38h */ 1344 U32 Reserved12; /* 3Ch */ 1345 U32 Reserved13; /* 40h */ 1346 } MPI_BOOT_DEVICE_SAS_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_SAS_WWN; 1347 1348 typedef struct _MPI_BOOT_DEVICE_ENCLOSURE_SLOT 1349 { 1350 U64 EnclosureLogicalID; /* 00h */ 1351 U32 Reserved1; /* 08h */ 1352 U32 Reserved2; /* 0Ch */ 1353 U8 LUN[8]; /* 10h */ 1354 U16 SlotNumber; /* 18h */ 1355 U16 Reserved3; /* 1Ah */ 1356 U32 Reserved4; /* 1Ch */ 1357 U32 Reserved5; /* 20h */ 1358 U32 Reserved6; /* 24h */ 1359 U32 Reserved7; /* 28h */ 1360 U32 Reserved8; /* 2Ch */ 1361 U32 Reserved9; /* 30h */ 1362 U32 Reserved10; /* 34h */ 1363 U32 Reserved11; /* 38h */ 1364 U32 Reserved12; /* 3Ch */ 1365 U32 Reserved13; /* 40h */ 1366 } MPI_BOOT_DEVICE_ENCLOSURE_SLOT, 1367 MPI_POINTER PTR_MPI_BOOT_DEVICE_ENCLOSURE_SLOT; 1368 1369 typedef union _MPI_BIOSPAGE2_BOOT_DEVICE 1370 { 1371 MPI_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1372 MPI_BOOT_DEVICE_ADAPTER_NUMBER AdapterNumber; 1373 MPI_BOOT_DEVICE_PCI_ADDRESS PCIAddress; 1374 MPI_BOOT_DEVICE_PCI_SLOT_NUMBER PCISlotNumber; 1375 MPI_BOOT_DEVICE_FC_WWN FcWwn; 1376 MPI_BOOT_DEVICE_SAS_WWN SasWwn; 1377 MPI_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1378 } MPI_BIOSPAGE2_BOOT_DEVICE, MPI_POINTER PTR_MPI_BIOSPAGE2_BOOT_DEVICE; 1379 1380 typedef struct _CONFIG_PAGE_BIOS_2 1381 { 1382 CONFIG_PAGE_HEADER Header; /* 00h */ 1383 U32 Reserved1; /* 04h */ 1384 U32 Reserved2; /* 08h */ 1385 U32 Reserved3; /* 0Ch */ 1386 U32 Reserved4; /* 10h */ 1387 U32 Reserved5; /* 14h */ 1388 U32 Reserved6; /* 18h */ 1389 U8 BootDeviceForm; /* 1Ch */ 1390 U8 PrevBootDeviceForm; /* 1Ch */ 1391 U16 Reserved8; /* 1Eh */ 1392 MPI_BIOSPAGE2_BOOT_DEVICE BootDevice; /* 20h */ 1393 } CONFIG_PAGE_BIOS_2, MPI_POINTER PTR_CONFIG_PAGE_BIOS_2, 1394 BIOSPage2_t, MPI_POINTER pBIOSPage2_t; 1395 1396 #define MPI_BIOSPAGE2_PAGEVERSION (0x02) 1397 1398 #define MPI_BIOSPAGE2_FORM_MASK (0x0F) 1399 #define MPI_BIOSPAGE2_FORM_ADAPTER_ORDER (0x00) 1400 #define MPI_BIOSPAGE2_FORM_ADAPTER_NUMBER (0x01) 1401 #define MPI_BIOSPAGE2_FORM_PCI_ADDRESS (0x02) 1402 #define MPI_BIOSPAGE2_FORM_PCI_SLOT_NUMBER (0x03) 1403 #define MPI_BIOSPAGE2_FORM_FC_WWN (0x04) 1404 #define MPI_BIOSPAGE2_FORM_SAS_WWN (0x05) 1405 #define MPI_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1406 1407 1408 /**************************************************************************** 1409 * SCSI Port Config Pages 1410 ****************************************************************************/ 1411 1412 typedef struct _CONFIG_PAGE_SCSI_PORT_0 1413 { 1414 CONFIG_PAGE_HEADER Header; /* 00h */ 1415 U32 Capabilities; /* 04h */ 1416 U32 PhysicalInterface; /* 08h */ 1417 } CONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0, 1418 SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t; 1419 1420 #define MPI_SCSIPORTPAGE0_PAGEVERSION (0x02) 1421 1422 #define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001) 1423 #define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002) 1424 #define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004) 1425 #define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 1426 #define MPI_SCSIPORTPAGE0_SYNC_ASYNC (0x00) 1427 #define MPI_SCSIPORTPAGE0_SYNC_5 (0x32) 1428 #define MPI_SCSIPORTPAGE0_SYNC_10 (0x19) 1429 #define MPI_SCSIPORTPAGE0_SYNC_20 (0x0C) 1430 #define MPI_SCSIPORTPAGE0_SYNC_33_33 (0x0B) 1431 #define MPI_SCSIPORTPAGE0_SYNC_40 (0x0A) 1432 #define MPI_SCSIPORTPAGE0_SYNC_80 (0x09) 1433 #define MPI_SCSIPORTPAGE0_SYNC_160 (0x08) 1434 #define MPI_SCSIPORTPAGE0_SYNC_UNKNOWN (0xFF) 1435 1436 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD (8) 1437 #define MPI_SCSIPORTPAGE0_CAP_GET_MIN_SYNC_PERIOD(Cap) \ 1438 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK) \ 1439 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD \ 1440 ) 1441 #define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 1442 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET (16) 1443 #define MPI_SCSIPORTPAGE0_CAP_GET_MAX_SYNC_OFFSET(Cap) \ 1444 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK) \ 1445 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET \ 1446 ) 1447 #define MPI_SCSIPORTPAGE0_CAP_IDP (0x08000000) 1448 #define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000) 1449 #define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000) 1450 1451 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003) 1452 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01) 1453 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02) 1454 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03) 1455 #define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID (0xFF000000) 1456 #define MPI_SCSIPORTPAGE0_PHY_SHIFT_CONNECTED_ID (24) 1457 #define MPI_SCSIPORTPAGE0_PHY_BUS_FREE_CONNECTED_ID (0xFE) 1458 #define MPI_SCSIPORTPAGE0_PHY_UNKNOWN_CONNECTED_ID (0xFF) 1459 1460 1461 typedef struct _CONFIG_PAGE_SCSI_PORT_1 1462 { 1463 CONFIG_PAGE_HEADER Header; /* 00h */ 1464 U32 Configuration; /* 04h */ 1465 U32 OnBusTimerValue; /* 08h */ 1466 U8 TargetConfig; /* 0Ch */ 1467 U8 Reserved1; /* 0Dh */ 1468 U16 IDConfig; /* 0Eh */ 1469 } CONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1, 1470 SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t; 1471 1472 #define MPI_SCSIPORTPAGE1_PAGEVERSION (0x03) 1473 1474 /* Configuration values */ 1475 #define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF) 1476 #define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000) 1477 #define MPI_SCSIPORTPAGE1_CFG_SHIFT_PORT_RESPONSE_ID (16) 1478 1479 /* TargetConfig values */ 1480 #define MPI_SCSIPORTPAGE1_TARGCONFIG_TARG_ONLY (0x01) 1481 #define MPI_SCSIPORTPAGE1_TARGCONFIG_INIT_TARG (0x02) 1482 1483 1484 typedef struct _MPI_DEVICE_INFO 1485 { 1486 U8 Timeout; /* 00h */ 1487 U8 SyncFactor; /* 01h */ 1488 U16 DeviceFlags; /* 02h */ 1489 } MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO, 1490 MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t; 1491 1492 typedef struct _CONFIG_PAGE_SCSI_PORT_2 1493 { 1494 CONFIG_PAGE_HEADER Header; /* 00h */ 1495 U32 PortFlags; /* 04h */ 1496 U32 PortSettings; /* 08h */ 1497 MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */ 1498 } CONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2, 1499 SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t; 1500 1501 #define MPI_SCSIPORTPAGE2_PAGEVERSION (0x02) 1502 1503 /* PortFlags values */ 1504 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001) 1505 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004) 1506 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 1507 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010) 1508 1509 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK (0x00000060) 1510 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_FULL_DV (0x00000000) 1511 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_BASIC_DV_ONLY (0x00000020) 1512 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_OFF_DV (0x00000060) 1513 1514 1515 /* PortSettings values */ 1516 #define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F) 1517 #define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030) 1518 #define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000) 1519 #define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010) 1520 #define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020) 1521 #define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030) 1522 #define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0) 1523 #define MPI_SCSIPORTPAGE2_PORT_RM_NONE (0x00000000) 1524 #define MPI_SCSIPORTPAGE2_PORT_RM_BOOT_ONLY (0x00000040) 1525 #define MPI_SCSIPORTPAGE2_PORT_RM_WITH_MEDIA (0x00000080) 1526 #define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00) 1527 #define MPI_SCSIPORTPAGE2_PORT_SHIFT_SPINUP_DELAY (8) 1528 #define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000) 1529 #define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000) 1530 #define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000) 1531 #define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000) 1532 1533 #define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001) 1534 #define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002) 1535 #define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004) 1536 #define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008) 1537 #define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010) 1538 #define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020) 1539 1540 1541 /**************************************************************************** 1542 * SCSI Target Device Config Pages 1543 ****************************************************************************/ 1544 1545 typedef struct _CONFIG_PAGE_SCSI_DEVICE_0 1546 { 1547 CONFIG_PAGE_HEADER Header; /* 00h */ 1548 U32 NegotiatedParameters; /* 04h */ 1549 U32 Information; /* 08h */ 1550 } CONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0, 1551 SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t; 1552 1553 #define MPI_SCSIDEVPAGE0_PAGEVERSION (0x04) 1554 1555 #define MPI_SCSIDEVPAGE0_NP_IU (0x00000001) 1556 #define MPI_SCSIDEVPAGE0_NP_DT (0x00000002) 1557 #define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004) 1558 #define MPI_SCSIDEVPAGE0_NP_HOLD_MCS (0x00000008) 1559 #define MPI_SCSIDEVPAGE0_NP_WR_FLOW (0x00000010) 1560 #define MPI_SCSIDEVPAGE0_NP_RD_STRM (0x00000020) 1561 #define MPI_SCSIDEVPAGE0_NP_RTI (0x00000040) 1562 #define MPI_SCSIDEVPAGE0_NP_PCOMP_EN (0x00000080) 1563 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00) 1564 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_PERIOD (8) 1565 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000) 1566 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_OFFSET (16) 1567 #define MPI_SCSIDEVPAGE0_NP_IDP (0x08000000) 1568 #define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000) 1569 #define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000) 1570 1571 #define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001) 1572 #define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002) 1573 #define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004) 1574 #define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008) 1575 1576 1577 typedef struct _CONFIG_PAGE_SCSI_DEVICE_1 1578 { 1579 CONFIG_PAGE_HEADER Header; /* 00h */ 1580 U32 RequestedParameters; /* 04h */ 1581 U32 Reserved; /* 08h */ 1582 U32 Configuration; /* 0Ch */ 1583 } CONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1, 1584 SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t; 1585 1586 #define MPI_SCSIDEVPAGE1_PAGEVERSION (0x05) 1587 1588 #define MPI_SCSIDEVPAGE1_RP_IU (0x00000001) 1589 #define MPI_SCSIDEVPAGE1_RP_DT (0x00000002) 1590 #define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004) 1591 #define MPI_SCSIDEVPAGE1_RP_HOLD_MCS (0x00000008) 1592 #define MPI_SCSIDEVPAGE1_RP_WR_FLOW (0x00000010) 1593 #define MPI_SCSIDEVPAGE1_RP_RD_STRM (0x00000020) 1594 #define MPI_SCSIDEVPAGE1_RP_RTI (0x00000040) 1595 #define MPI_SCSIDEVPAGE1_RP_PCOMP_EN (0x00000080) 1596 #define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 1597 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MIN_SYNC_PERIOD (8) 1598 #define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 1599 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MAX_SYNC_OFFSET (16) 1600 #define MPI_SCSIDEVPAGE1_RP_IDP (0x08000000) 1601 #define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000) 1602 #define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000) 1603 1604 #define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002) 1605 #define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004) 1606 #define MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE (0x00000008) 1607 #define MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG (0x00000010) 1608 1609 1610 typedef struct _CONFIG_PAGE_SCSI_DEVICE_2 1611 { 1612 CONFIG_PAGE_HEADER Header; /* 00h */ 1613 U32 DomainValidation; /* 04h */ 1614 U32 ParityPipeSelect; /* 08h */ 1615 U32 DataPipeSelect; /* 0Ch */ 1616 } CONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2, 1617 SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t; 1618 1619 #define MPI_SCSIDEVPAGE2_PAGEVERSION (0x01) 1620 1621 #define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010) 1622 #define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020) 1623 #define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380) 1624 #define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00) 1625 #define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000) 1626 #define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000) 1627 #define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000) 1628 #define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000) 1629 #define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000) 1630 1631 #define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003) 1632 1633 #define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003) 1634 #define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C) 1635 #define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030) 1636 #define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0) 1637 #define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300) 1638 #define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00) 1639 #define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000) 1640 #define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000) 1641 #define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000) 1642 #define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK (0x000C0000) 1643 #define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000) 1644 #define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000) 1645 #define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000) 1646 #define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000) 1647 #define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000) 1648 #define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000) 1649 1650 1651 typedef struct _CONFIG_PAGE_SCSI_DEVICE_3 1652 { 1653 CONFIG_PAGE_HEADER Header; /* 00h */ 1654 U16 MsgRejectCount; /* 04h */ 1655 U16 PhaseErrorCount; /* 06h */ 1656 U16 ParityErrorCount; /* 08h */ 1657 U16 Reserved; /* 0Ah */ 1658 } CONFIG_PAGE_SCSI_DEVICE_3, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_3, 1659 SCSIDevicePage3_t, MPI_POINTER pSCSIDevicePage3_t; 1660 1661 #define MPI_SCSIDEVPAGE3_PAGEVERSION (0x00) 1662 1663 #define MPI_SCSIDEVPAGE3_MAX_COUNTER (0xFFFE) 1664 #define MPI_SCSIDEVPAGE3_UNSUPPORTED_COUNTER (0xFFFF) 1665 1666 1667 /**************************************************************************** 1668 * FC Port Config Pages 1669 ****************************************************************************/ 1670 1671 typedef struct _CONFIG_PAGE_FC_PORT_0 1672 { 1673 CONFIG_PAGE_HEADER Header; /* 00h */ 1674 U32 Flags; /* 04h */ 1675 U8 MPIPortNumber; /* 08h */ 1676 U8 LinkType; /* 09h */ 1677 U8 PortState; /* 0Ah */ 1678 U8 Reserved; /* 0Bh */ 1679 U32 PortIdentifier; /* 0Ch */ 1680 U64 WWNN; /* 10h */ 1681 U64 WWPN; /* 18h */ 1682 U32 SupportedServiceClass; /* 20h */ 1683 U32 SupportedSpeeds; /* 24h */ 1684 U32 CurrentSpeed; /* 28h */ 1685 U32 MaxFrameSize; /* 2Ch */ 1686 U64 FabricWWNN; /* 30h */ 1687 U64 FabricWWPN; /* 38h */ 1688 U32 DiscoveredPortsCount; /* 40h */ 1689 U32 MaxInitiators; /* 44h */ 1690 U8 MaxAliasesSupported; /* 48h */ 1691 U8 MaxHardAliasesSupported; /* 49h */ 1692 U8 NumCurrentAliases; /* 4Ah */ 1693 U8 Reserved1; /* 4Bh */ 1694 } CONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0, 1695 FCPortPage0_t, MPI_POINTER pFCPortPage0_t; 1696 1697 #define MPI_FCPORTPAGE0_PAGEVERSION (0x02) 1698 1699 #define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F) 1700 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR) 1701 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET) 1702 #define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN) 1703 #define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR) 1704 1705 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010) 1706 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020) 1707 #define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000040) 1708 1709 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00) 1710 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000) 1711 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100) 1712 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200) 1713 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400) 1714 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800) 1715 1716 #define MPI_FCPORTPAGE0_LTYPE_RESERVED (0x00) 1717 #define MPI_FCPORTPAGE0_LTYPE_OTHER (0x01) 1718 #define MPI_FCPORTPAGE0_LTYPE_UNKNOWN (0x02) 1719 #define MPI_FCPORTPAGE0_LTYPE_COPPER (0x03) 1720 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 (0x04) 1721 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 (0x05) 1722 #define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI (0x06) 1723 #define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI (0x07) 1724 #define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI (0x08) 1725 #define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI (0x09) 1726 #define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE (0x0A) 1727 #define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE (0x0B) 1728 #define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE (0x0C) 1729 #define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE (0x0D) 1730 #define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE (0x0E) 1731 #define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE (0x0F) 1732 1733 #define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN (0x01) /*(SNIA)HBA_PORTSTATE_UNKNOWN 1 Unknown */ 1734 #define MPI_FCPORTPAGE0_PORTSTATE_ONLINE (0x02) /*(SNIA)HBA_PORTSTATE_ONLINE 2 Operational */ 1735 #define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE (0x03) /*(SNIA)HBA_PORTSTATE_OFFLINE 3 User Offline */ 1736 #define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED (0x04) /*(SNIA)HBA_PORTSTATE_BYPASSED 4 Bypassed */ 1737 #define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST (0x05) /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS 5 In diagnostics mode */ 1738 #define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */ 1739 #define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */ 1740 #define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */ 1741 1742 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001) 1743 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002) 1744 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004) 1745 1746 #define MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN (0x00000000) /* (SNIA)HBA_PORTSPEED_UNKNOWN 0 Unknown - transceiver incapable of reporting */ 1747 #define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */ 1748 #define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */ 1749 #define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */ 1750 #define MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED (0x00000008) /* (SNIA)HBA_PORTSPEED_4GBIT 8 4 GBit/sec */ 1751 1752 #define MPI_FCPORTPAGE0_CURRENT_SPEED_UKNOWN MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN 1753 #define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED 1754 #define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED 1755 #define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED 1756 #define MPI_FCPORTPAGE0_CURRENT_SPEED_4GBIT MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED 1757 #define MPI_FCPORTPAGE0_CURRENT_SPEED_NOT_NEGOTIATED (0x00008000) /* (SNIA)HBA_PORTSPEED_NOT_NEGOTIATED (1<<15) Speed not established */ 1758 1759 1760 typedef struct _CONFIG_PAGE_FC_PORT_1 1761 { 1762 CONFIG_PAGE_HEADER Header; /* 00h */ 1763 U32 Flags; /* 04h */ 1764 U64 NoSEEPROMWWNN; /* 08h */ 1765 U64 NoSEEPROMWWPN; /* 10h */ 1766 U8 HardALPA; /* 18h */ 1767 U8 LinkConfig; /* 19h */ 1768 U8 TopologyConfig; /* 1Ah */ 1769 U8 AltConnector; /* 1Bh */ 1770 U8 NumRequestedAliases; /* 1Ch */ 1771 U8 RR_TOV; /* 1Dh */ 1772 U8 InitiatorDeviceTimeout; /* 1Eh */ 1773 U8 InitiatorIoPendTimeout; /* 1Fh */ 1774 } CONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1, 1775 FCPortPage1_t, MPI_POINTER pFCPortPage1_t; 1776 1777 #define MPI_FCPORTPAGE1_PAGEVERSION (0x06) 1778 1779 #define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000) 1780 #define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000) 1781 #define MPI_FCPORTPAGE1_FLAGS_FORCE_USE_NOSEEPROM_WWNS (0x02000000) 1782 #define MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS (0x01000000) 1783 #define MPI_FCPORTPAGE1_FLAGS_TARGET_MODE_OXID (0x00800000) 1784 #define MPI_FCPORTPAGE1_FLAGS_PORT_OFFLINE (0x00400000) 1785 #define MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK (0x00200000) 1786 #define MPI_FCPORTPAGE1_FLAGS_TARGET_LARGE_CDB_ENABLE (0x00000080) 1787 #define MPI_FCPORTPAGE1_FLAGS_MASK_RR_TOV_UNITS (0x00000070) 1788 #define MPI_FCPORTPAGE1_FLAGS_SUPPRESS_PROT_REG (0x00000008) 1789 #define MPI_FCPORTPAGE1_FLAGS_PLOGI_ON_LOGO (0x00000004) 1790 #define MPI_FCPORTPAGE1_FLAGS_MAINTAIN_LOGINS (0x00000002) 1791 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001) 1792 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000) 1793 1794 #define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000) 1795 #define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28) 1796 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1797 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1798 #define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1799 #define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1800 1801 #define MPI_FCPORTPAGE1_FLAGS_NONE_RR_TOV_UNITS (0x00000000) 1802 #define MPI_FCPORTPAGE1_FLAGS_THOUSANDTH_RR_TOV_UNITS (0x00000010) 1803 #define MPI_FCPORTPAGE1_FLAGS_TENTH_RR_TOV_UNITS (0x00000030) 1804 #define MPI_FCPORTPAGE1_FLAGS_TEN_RR_TOV_UNITS (0x00000050) 1805 1806 #define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF) 1807 1808 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F) 1809 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00) 1810 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01) 1811 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02) 1812 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03) 1813 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F) 1814 1815 #define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F) 1816 #define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01) 1817 #define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02) 1818 #define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F) 1819 1820 #define MPI_FCPORTPAGE1_ALT_CONN_UNKNOWN (0x00) 1821 1822 #define MPI_FCPORTPAGE1_INITIATOR_DEV_TIMEOUT_MASK (0x7F) 1823 #define MPI_FCPORTPAGE1_INITIATOR_DEV_UNIT_16 (0x80) 1824 1825 1826 typedef struct _CONFIG_PAGE_FC_PORT_2 1827 { 1828 CONFIG_PAGE_HEADER Header; /* 00h */ 1829 U8 NumberActive; /* 04h */ 1830 U8 ALPA[127]; /* 05h */ 1831 } CONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2, 1832 FCPortPage2_t, MPI_POINTER pFCPortPage2_t; 1833 1834 #define MPI_FCPORTPAGE2_PAGEVERSION (0x01) 1835 1836 1837 typedef struct _WWN_FORMAT 1838 { 1839 U64 WWNN; /* 00h */ 1840 U64 WWPN; /* 08h */ 1841 } WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT, 1842 WWNFormat, MPI_POINTER pWWNFormat; 1843 1844 typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID 1845 { 1846 WWN_FORMAT WWN; 1847 U32 Did; 1848 } FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID, 1849 PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t; 1850 1851 typedef struct _FC_PORT_PERSISTENT 1852 { 1853 FC_PORT_PERSISTENT_PHYSICAL_ID PhysicalIdentifier; /* 00h */ 1854 U8 TargetID; /* 10h */ 1855 U8 Bus; /* 11h */ 1856 U16 Flags; /* 12h */ 1857 } FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT, 1858 PersistentData_t, MPI_POINTER pPersistentData_t; 1859 1860 #define MPI_PERSISTENT_FLAGS_SHIFT (16) 1861 #define MPI_PERSISTENT_FLAGS_ENTRY_VALID (0x0001) 1862 #define MPI_PERSISTENT_FLAGS_SCAN_ID (0x0002) 1863 #define MPI_PERSISTENT_FLAGS_SCAN_LUNS (0x0004) 1864 #define MPI_PERSISTENT_FLAGS_BOOT_DEVICE (0x0008) 1865 #define MPI_PERSISTENT_FLAGS_BY_DID (0x0080) 1866 1867 /* 1868 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1869 * one and check Header.PageLength at runtime. 1870 */ 1871 #ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX 1872 #define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1) 1873 #endif 1874 1875 typedef struct _CONFIG_PAGE_FC_PORT_3 1876 { 1877 CONFIG_PAGE_HEADER Header; /* 00h */ 1878 FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */ 1879 } CONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3, 1880 FCPortPage3_t, MPI_POINTER pFCPortPage3_t; 1881 1882 #define MPI_FCPORTPAGE3_PAGEVERSION (0x01) 1883 1884 1885 typedef struct _CONFIG_PAGE_FC_PORT_4 1886 { 1887 CONFIG_PAGE_HEADER Header; /* 00h */ 1888 U32 PortFlags; /* 04h */ 1889 U32 PortSettings; /* 08h */ 1890 } CONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4, 1891 FCPortPage4_t, MPI_POINTER pFCPortPage4_t; 1892 1893 #define MPI_FCPORTPAGE4_PAGEVERSION (0x00) 1894 1895 #define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 1896 1897 #define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030) 1898 #define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000) 1899 #define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA (0x00000010) 1900 #define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA (0x00000020) 1901 #define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA (0x00000030) 1902 #define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA (0x000000C0) 1903 #define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00) 1904 1905 1906 typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO 1907 { 1908 U8 Flags; /* 00h */ 1909 U8 AliasAlpa; /* 01h */ 1910 U16 Reserved; /* 02h */ 1911 U64 AliasWWNN; /* 04h */ 1912 U64 AliasWWPN; /* 0Ch */ 1913 } CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 1914 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 1915 FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t; 1916 1917 typedef struct _CONFIG_PAGE_FC_PORT_5 1918 { 1919 CONFIG_PAGE_HEADER Header; /* 00h */ 1920 CONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo; /* 04h */ 1921 } CONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5, 1922 FCPortPage5_t, MPI_POINTER pFCPortPage5_t; 1923 1924 #define MPI_FCPORTPAGE5_PAGEVERSION (0x02) 1925 1926 #define MPI_FCPORTPAGE5_FLAGS_ALPA_ACQUIRED (0x01) 1927 #define MPI_FCPORTPAGE5_FLAGS_HARD_ALPA (0x02) 1928 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWNN (0x04) 1929 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWPN (0x08) 1930 #define MPI_FCPORTPAGE5_FLAGS_DISABLE (0x10) 1931 1932 typedef struct _CONFIG_PAGE_FC_PORT_6 1933 { 1934 CONFIG_PAGE_HEADER Header; /* 00h */ 1935 U32 Reserved; /* 04h */ 1936 U64 TimeSinceReset; /* 08h */ 1937 U64 TxFrames; /* 10h */ 1938 U64 RxFrames; /* 18h */ 1939 U64 TxWords; /* 20h */ 1940 U64 RxWords; /* 28h */ 1941 U64 LipCount; /* 30h */ 1942 U64 NosCount; /* 38h */ 1943 U64 ErrorFrames; /* 40h */ 1944 U64 DumpedFrames; /* 48h */ 1945 U64 LinkFailureCount; /* 50h */ 1946 U64 LossOfSyncCount; /* 58h */ 1947 U64 LossOfSignalCount; /* 60h */ 1948 U64 PrimativeSeqErrCount; /* 68h */ 1949 U64 InvalidTxWordCount; /* 70h */ 1950 U64 InvalidCrcCount; /* 78h */ 1951 U64 FcpInitiatorIoCount; /* 80h */ 1952 } CONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6, 1953 FCPortPage6_t, MPI_POINTER pFCPortPage6_t; 1954 1955 #define MPI_FCPORTPAGE6_PAGEVERSION (0x00) 1956 1957 1958 typedef struct _CONFIG_PAGE_FC_PORT_7 1959 { 1960 CONFIG_PAGE_HEADER Header; /* 00h */ 1961 U32 Reserved; /* 04h */ 1962 U8 PortSymbolicName[256]; /* 08h */ 1963 } CONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7, 1964 FCPortPage7_t, MPI_POINTER pFCPortPage7_t; 1965 1966 #define MPI_FCPORTPAGE7_PAGEVERSION (0x00) 1967 1968 1969 typedef struct _CONFIG_PAGE_FC_PORT_8 1970 { 1971 CONFIG_PAGE_HEADER Header; /* 00h */ 1972 U32 BitVector[8]; /* 04h */ 1973 } CONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8, 1974 FCPortPage8_t, MPI_POINTER pFCPortPage8_t; 1975 1976 #define MPI_FCPORTPAGE8_PAGEVERSION (0x00) 1977 1978 1979 typedef struct _CONFIG_PAGE_FC_PORT_9 1980 { 1981 CONFIG_PAGE_HEADER Header; /* 00h */ 1982 U32 Reserved; /* 04h */ 1983 U64 GlobalWWPN; /* 08h */ 1984 U64 GlobalWWNN; /* 10h */ 1985 U32 UnitType; /* 18h */ 1986 U32 PhysicalPortNumber; /* 1Ch */ 1987 U32 NumAttachedNodes; /* 20h */ 1988 U16 IPVersion; /* 24h */ 1989 U16 UDPPortNumber; /* 26h */ 1990 U8 IPAddress[16]; /* 28h */ 1991 U16 Reserved1; /* 38h */ 1992 U16 TopologyDiscoveryFlags; /* 3Ah */ 1993 } CONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9, 1994 FCPortPage9_t, MPI_POINTER pFCPortPage9_t; 1995 1996 #define MPI_FCPORTPAGE9_PAGEVERSION (0x00) 1997 1998 1999 typedef struct _CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA 2000 { 2001 U8 Id; /* 10h */ 2002 U8 ExtId; /* 11h */ 2003 U8 Connector; /* 12h */ 2004 U8 Transceiver[8]; /* 13h */ 2005 U8 Encoding; /* 1Bh */ 2006 U8 BitRate_100mbs; /* 1Ch */ 2007 U8 Reserved1; /* 1Dh */ 2008 U8 Length9u_km; /* 1Eh */ 2009 U8 Length9u_100m; /* 1Fh */ 2010 U8 Length50u_10m; /* 20h */ 2011 U8 Length62p5u_10m; /* 21h */ 2012 U8 LengthCopper_m; /* 22h */ 2013 U8 Reseverved2; /* 22h */ 2014 U8 VendorName[16]; /* 24h */ 2015 U8 Reserved3; /* 34h */ 2016 U8 VendorOUI[3]; /* 35h */ 2017 U8 VendorPN[16]; /* 38h */ 2018 U8 VendorRev[4]; /* 48h */ 2019 U16 Wavelength; /* 4Ch */ 2020 U8 Reserved4; /* 4Eh */ 2021 U8 CC_BASE; /* 4Fh */ 2022 } CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA, 2023 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA, 2024 FCPortPage10BaseSfpData_t, MPI_POINTER pFCPortPage10BaseSfpData_t; 2025 2026 #define MPI_FCPORT10_BASE_ID_UNKNOWN (0x00) 2027 #define MPI_FCPORT10_BASE_ID_GBIC (0x01) 2028 #define MPI_FCPORT10_BASE_ID_FIXED (0x02) 2029 #define MPI_FCPORT10_BASE_ID_SFP (0x03) 2030 #define MPI_FCPORT10_BASE_ID_SFP_MIN (0x04) 2031 #define MPI_FCPORT10_BASE_ID_SFP_MAX (0x7F) 2032 #define MPI_FCPORT10_BASE_ID_VEND_SPEC_MASK (0x80) 2033 2034 #define MPI_FCPORT10_BASE_EXTID_UNKNOWN (0x00) 2035 #define MPI_FCPORT10_BASE_EXTID_MODDEF1 (0x01) 2036 #define MPI_FCPORT10_BASE_EXTID_MODDEF2 (0x02) 2037 #define MPI_FCPORT10_BASE_EXTID_MODDEF3 (0x03) 2038 #define MPI_FCPORT10_BASE_EXTID_SEEPROM (0x04) 2039 #define MPI_FCPORT10_BASE_EXTID_MODDEF5 (0x05) 2040 #define MPI_FCPORT10_BASE_EXTID_MODDEF6 (0x06) 2041 #define MPI_FCPORT10_BASE_EXTID_MODDEF7 (0x07) 2042 #define MPI_FCPORT10_BASE_EXTID_VNDSPC_MASK (0x80) 2043 2044 #define MPI_FCPORT10_BASE_CONN_UNKNOWN (0x00) 2045 #define MPI_FCPORT10_BASE_CONN_SC (0x01) 2046 #define MPI_FCPORT10_BASE_CONN_COPPER1 (0x02) 2047 #define MPI_FCPORT10_BASE_CONN_COPPER2 (0x03) 2048 #define MPI_FCPORT10_BASE_CONN_BNC_TNC (0x04) 2049 #define MPI_FCPORT10_BASE_CONN_COAXIAL (0x05) 2050 #define MPI_FCPORT10_BASE_CONN_FIBERJACK (0x06) 2051 #define MPI_FCPORT10_BASE_CONN_LC (0x07) 2052 #define MPI_FCPORT10_BASE_CONN_MT_RJ (0x08) 2053 #define MPI_FCPORT10_BASE_CONN_MU (0x09) 2054 #define MPI_FCPORT10_BASE_CONN_SG (0x0A) 2055 #define MPI_FCPORT10_BASE_CONN_OPT_PIGT (0x0B) 2056 #define MPI_FCPORT10_BASE_CONN_RSV1_MIN (0x0C) 2057 #define MPI_FCPORT10_BASE_CONN_RSV1_MAX (0x1F) 2058 #define MPI_FCPORT10_BASE_CONN_HSSDC_II (0x20) 2059 #define MPI_FCPORT10_BASE_CONN_CPR_PIGT (0x21) 2060 #define MPI_FCPORT10_BASE_CONN_RSV2_MIN (0x22) 2061 #define MPI_FCPORT10_BASE_CONN_RSV2_MAX (0x7F) 2062 #define MPI_FCPORT10_BASE_CONN_VNDSPC_MASK (0x80) 2063 2064 #define MPI_FCPORT10_BASE_ENCODE_UNSPEC (0x00) 2065 #define MPI_FCPORT10_BASE_ENCODE_8B10B (0x01) 2066 #define MPI_FCPORT10_BASE_ENCODE_4B5B (0x02) 2067 #define MPI_FCPORT10_BASE_ENCODE_NRZ (0x03) 2068 #define MPI_FCPORT10_BASE_ENCODE_MANCHESTER (0x04) 2069 2070 2071 typedef struct _CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA 2072 { 2073 U8 Options[2]; /* 50h */ 2074 U8 BitRateMax; /* 52h */ 2075 U8 BitRateMin; /* 53h */ 2076 U8 VendorSN[16]; /* 54h */ 2077 U8 DateCode[8]; /* 64h */ 2078 U8 DiagMonitoringType; /* 6Ch */ 2079 U8 EnhancedOptions; /* 6Dh */ 2080 U8 SFF8472Compliance; /* 6Eh */ 2081 U8 CC_EXT; /* 6Fh */ 2082 } CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA, 2083 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA, 2084 FCPortPage10ExtendedSfpData_t, MPI_POINTER pFCPortPage10ExtendedSfpData_t; 2085 2086 #define MPI_FCPORT10_EXT_OPTION1_RATESEL (0x20) 2087 #define MPI_FCPORT10_EXT_OPTION1_TX_DISABLE (0x10) 2088 #define MPI_FCPORT10_EXT_OPTION1_TX_FAULT (0x08) 2089 #define MPI_FCPORT10_EXT_OPTION1_LOS_INVERT (0x04) 2090 #define MPI_FCPORT10_EXT_OPTION1_LOS (0x02) 2091 2092 2093 typedef struct _CONFIG_PAGE_FC_PORT_10 2094 { 2095 CONFIG_PAGE_HEADER Header; /* 00h */ 2096 U8 Flags; /* 04h */ 2097 U8 Reserved1; /* 05h */ 2098 U16 Reserved2; /* 06h */ 2099 U32 HwConfig1; /* 08h */ 2100 U32 HwConfig2; /* 0Ch */ 2101 CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA Base; /* 10h */ 2102 CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA Extended; /* 50h */ 2103 U8 VendorSpecific[32]; /* 70h */ 2104 } CONFIG_PAGE_FC_PORT_10, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10, 2105 FCPortPage10_t, MPI_POINTER pFCPortPage10_t; 2106 2107 #define MPI_FCPORTPAGE10_PAGEVERSION (0x01) 2108 2109 /* standard MODDEF pin definitions (from GBIC spec.) */ 2110 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_MASK (0x00000007) 2111 #define MPI_FCPORTPAGE10_FLAGS_MODDEF2 (0x00000001) 2112 #define MPI_FCPORTPAGE10_FLAGS_MODDEF1 (0x00000002) 2113 #define MPI_FCPORTPAGE10_FLAGS_MODDEF0 (0x00000004) 2114 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_NOGBIC (0x00000007) 2115 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_CPR_IEEE_CX (0x00000006) 2116 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_COPPER (0x00000005) 2117 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_OPTICAL_LW (0x00000004) 2118 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SEEPROM (0x00000003) 2119 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SW_OPTICAL (0x00000002) 2120 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_LX_IEEE_OPT_LW (0x00000001) 2121 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SX_IEEE_OPT_SW (0x00000000) 2122 2123 #define MPI_FCPORTPAGE10_FLAGS_CC_BASE_OK (0x00000010) 2124 #define MPI_FCPORTPAGE10_FLAGS_CC_EXT_OK (0x00000020) 2125 2126 2127 /**************************************************************************** 2128 * FC Device Config Pages 2129 ****************************************************************************/ 2130 2131 typedef struct _CONFIG_PAGE_FC_DEVICE_0 2132 { 2133 CONFIG_PAGE_HEADER Header; /* 00h */ 2134 U64 WWNN; /* 04h */ 2135 U64 WWPN; /* 0Ch */ 2136 U32 PortIdentifier; /* 14h */ 2137 U8 Protocol; /* 18h */ 2138 U8 Flags; /* 19h */ 2139 U16 BBCredit; /* 1Ah */ 2140 U16 MaxRxFrameSize; /* 1Ch */ 2141 U8 ADISCHardALPA; /* 1Eh */ 2142 U8 PortNumber; /* 1Fh */ 2143 U8 FcPhLowestVersion; /* 20h */ 2144 U8 FcPhHighestVersion; /* 21h */ 2145 U8 CurrentTargetID; /* 22h */ 2146 U8 CurrentBus; /* 23h */ 2147 } CONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0, 2148 FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t; 2149 2150 #define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x03) 2151 2152 #define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01) 2153 #define MPI_FC_DEVICE_PAGE0_FLAGS_PLOGI_INVALID (0x02) 2154 #define MPI_FC_DEVICE_PAGE0_FLAGS_PRLI_INVALID (0x04) 2155 2156 #define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01) 2157 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02) 2158 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04) 2159 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY (0x08) 2160 2161 #define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK) 2162 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK) 2163 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID) 2164 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID) 2165 #define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK) 2166 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK) 2167 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT) 2168 #define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK) 2169 2170 #define MPI_FC_DEVICE_PAGE0_HARD_ALPA_UNKNOWN (0xFF) 2171 2172 /**************************************************************************** 2173 * RAID Volume Config Pages 2174 ****************************************************************************/ 2175 2176 typedef struct _RAID_VOL0_PHYS_DISK 2177 { 2178 U16 Reserved; /* 00h */ 2179 U8 PhysDiskMap; /* 02h */ 2180 U8 PhysDiskNum; /* 03h */ 2181 } RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK, 2182 RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t; 2183 2184 #define MPI_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 2185 #define MPI_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 2186 2187 typedef struct _RAID_VOL0_STATUS 2188 { 2189 U8 Flags; /* 00h */ 2190 U8 State; /* 01h */ 2191 U16 Reserved; /* 02h */ 2192 } RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS, 2193 RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t; 2194 2195 /* RAID Volume Page 0 VolumeStatus defines */ 2196 #define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01) 2197 #define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02) 2198 #define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04) 2199 #define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x08) 2200 #define MPI_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x10) 2201 2202 #define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00) 2203 #define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01) 2204 #define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02) 2205 #define MPI_RAIDVOL0_STATUS_STATE_MISSING (0x03) 2206 2207 typedef struct _RAID_VOL0_SETTINGS 2208 { 2209 U16 Settings; /* 00h */ 2210 U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 2211 U8 Reserved; /* 02h */ 2212 } RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS, 2213 RaidVol0Settings, MPI_POINTER pRaidVol0Settings; 2214 2215 /* RAID Volume Page 0 VolumeSettings defines */ 2216 #define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001) 2217 #define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002) 2218 #define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004) 2219 #define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008) 2220 #define MPI_RAIDVOL0_SETTING_FAST_DATA_SCRUBBING_0102 (0x0020) /* obsolete */ 2221 2222 #define MPI_RAIDVOL0_SETTING_MASK_METADATA_SIZE (0x00C0) 2223 #define MPI_RAIDVOL0_SETTING_64MB_METADATA_SIZE (0x0000) 2224 #define MPI_RAIDVOL0_SETTING_512MB_METADATA_SIZE (0x0040) 2225 2226 #define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010) 2227 #define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000) 2228 2229 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 2230 #define MPI_RAID_HOT_SPARE_POOL_0 (0x01) 2231 #define MPI_RAID_HOT_SPARE_POOL_1 (0x02) 2232 #define MPI_RAID_HOT_SPARE_POOL_2 (0x04) 2233 #define MPI_RAID_HOT_SPARE_POOL_3 (0x08) 2234 #define MPI_RAID_HOT_SPARE_POOL_4 (0x10) 2235 #define MPI_RAID_HOT_SPARE_POOL_5 (0x20) 2236 #define MPI_RAID_HOT_SPARE_POOL_6 (0x40) 2237 #define MPI_RAID_HOT_SPARE_POOL_7 (0x80) 2238 2239 /* 2240 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2241 * one and check Header.PageLength at runtime. 2242 */ 2243 #ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX 2244 #define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 2245 #endif 2246 2247 typedef struct _CONFIG_PAGE_RAID_VOL_0 2248 { 2249 CONFIG_PAGE_HEADER Header; /* 00h */ 2250 U8 VolumeID; /* 04h */ 2251 U8 VolumeBus; /* 05h */ 2252 U8 VolumeIOC; /* 06h */ 2253 U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */ 2254 RAID_VOL0_STATUS VolumeStatus; /* 08h */ 2255 RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */ 2256 U32 MaxLBA; /* 10h */ 2257 U32 MaxLBAHigh; /* 14h */ 2258 U32 StripeSize; /* 18h */ 2259 U32 Reserved2; /* 1Ch */ 2260 U32 Reserved3; /* 20h */ 2261 U8 NumPhysDisks; /* 24h */ 2262 U8 DataScrubRate; /* 25h */ 2263 U8 ResyncRate; /* 26h */ 2264 U8 InactiveStatus; /* 27h */ 2265 RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */ 2266 } CONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0, 2267 RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t; 2268 2269 #define MPI_RAIDVOLPAGE0_PAGEVERSION (0x07) 2270 2271 /* values for RAID Volume Page 0 InactiveStatus field */ 2272 #define MPI_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 2273 #define MPI_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 2274 #define MPI_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 2275 #define MPI_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 2276 #define MPI_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 2277 #define MPI_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 2278 #define MPI_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 2279 2280 2281 typedef struct _CONFIG_PAGE_RAID_VOL_1 2282 { 2283 CONFIG_PAGE_HEADER Header; /* 00h */ 2284 U8 VolumeID; /* 01h */ 2285 U8 VolumeBus; /* 02h */ 2286 U8 VolumeIOC; /* 03h */ 2287 U8 Reserved0; /* 04h */ 2288 U8 GUID[24]; /* 05h */ 2289 U8 Name[32]; /* 20h */ 2290 U64 WWID; /* 40h */ 2291 U32 Reserved1; /* 48h */ 2292 U32 Reserved2; /* 4Ch */ 2293 } CONFIG_PAGE_RAID_VOL_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_1, 2294 RaidVolumePage1_t, MPI_POINTER pRaidVolumePage1_t; 2295 2296 #define MPI_RAIDVOLPAGE1_PAGEVERSION (0x01) 2297 2298 2299 /**************************************************************************** 2300 * RAID Physical Disk Config Pages 2301 ****************************************************************************/ 2302 2303 typedef struct _RAID_PHYS_DISK0_ERROR_DATA 2304 { 2305 U8 ErrorCdbByte; /* 00h */ 2306 U8 ErrorSenseKey; /* 01h */ 2307 U16 Reserved; /* 02h */ 2308 U16 ErrorCount; /* 04h */ 2309 U8 ErrorASC; /* 06h */ 2310 U8 ErrorASCQ; /* 07h */ 2311 U16 SmartCount; /* 08h */ 2312 U8 SmartASC; /* 0Ah */ 2313 U8 SmartASCQ; /* 0Bh */ 2314 } RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA, 2315 RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t; 2316 2317 typedef struct _RAID_PHYS_DISK_INQUIRY_DATA 2318 { 2319 U8 VendorID[8]; /* 00h */ 2320 U8 ProductID[16]; /* 08h */ 2321 U8 ProductRevLevel[4]; /* 18h */ 2322 U8 Info[32]; /* 1Ch */ 2323 } RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA, 2324 RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData; 2325 2326 typedef struct _RAID_PHYS_DISK0_SETTINGS 2327 { 2328 U8 SepID; /* 00h */ 2329 U8 SepBus; /* 01h */ 2330 U8 HotSparePool; /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 2331 U8 PhysDiskSettings; /* 03h */ 2332 } RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS, 2333 RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t; 2334 2335 typedef struct _RAID_PHYS_DISK0_STATUS 2336 { 2337 U8 Flags; /* 00h */ 2338 U8 State; /* 01h */ 2339 U16 Reserved; /* 02h */ 2340 } RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS, 2341 RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t; 2342 2343 /* RAID Volume 2 IM Physical Disk DiskStatus flags */ 2344 2345 #define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01) 2346 #define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02) 2347 #define MPI_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x04) 2348 #define MPI_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00) 2349 #define MPI_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x08) 2350 2351 #define MPI_PHYSDISK0_STATUS_ONLINE (0x00) 2352 #define MPI_PHYSDISK0_STATUS_MISSING (0x01) 2353 #define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02) 2354 #define MPI_PHYSDISK0_STATUS_FAILED (0x03) 2355 #define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04) 2356 #define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05) 2357 #define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06) 2358 #define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF) 2359 2360 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0 2361 { 2362 CONFIG_PAGE_HEADER Header; /* 00h */ 2363 U8 PhysDiskID; /* 04h */ 2364 U8 PhysDiskBus; /* 05h */ 2365 U8 PhysDiskIOC; /* 06h */ 2366 U8 PhysDiskNum; /* 07h */ 2367 RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */ 2368 U32 Reserved1; /* 0Ch */ 2369 U8 ExtDiskIdentifier[8]; /* 10h */ 2370 U8 DiskIdentifier[16]; /* 18h */ 2371 RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */ 2372 RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */ 2373 U32 MaxLBA; /* 68h */ 2374 RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */ 2375 } CONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0, 2376 RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t; 2377 2378 #define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x02) 2379 2380 2381 typedef struct _RAID_PHYS_DISK1_PATH 2382 { 2383 U8 PhysDiskID; /* 00h */ 2384 U8 PhysDiskBus; /* 01h */ 2385 U16 Reserved1; /* 02h */ 2386 U64 WWID; /* 04h */ 2387 U64 OwnerWWID; /* 0Ch */ 2388 U8 OwnerIdentifier; /* 14h */ 2389 U8 Reserved2; /* 15h */ 2390 U16 Flags; /* 16h */ 2391 } RAID_PHYS_DISK1_PATH, MPI_POINTER PTR_RAID_PHYS_DISK1_PATH, 2392 RaidPhysDisk1Path_t, MPI_POINTER pRaidPhysDisk1Path_t; 2393 2394 /* RAID Physical Disk Page 1 Flags field defines */ 2395 #define MPI_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 2396 #define MPI_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 2397 2398 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_1 2399 { 2400 CONFIG_PAGE_HEADER Header; /* 00h */ 2401 U8 NumPhysDiskPaths; /* 04h */ 2402 U8 PhysDiskNum; /* 05h */ 2403 U16 Reserved2; /* 06h */ 2404 U32 Reserved1; /* 08h */ 2405 RAID_PHYS_DISK1_PATH Path[1]; /* 0Ch */ 2406 } CONFIG_PAGE_RAID_PHYS_DISK_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_1, 2407 RaidPhysDiskPage1_t, MPI_POINTER pRaidPhysDiskPage1_t; 2408 2409 #define MPI_RAIDPHYSDISKPAGE1_PAGEVERSION (0x00) 2410 2411 2412 /**************************************************************************** 2413 * LAN Config Pages 2414 ****************************************************************************/ 2415 2416 typedef struct _CONFIG_PAGE_LAN_0 2417 { 2418 ConfigPageHeader_t Header; /* 00h */ 2419 U16 TxRxModes; /* 04h */ 2420 U16 Reserved; /* 06h */ 2421 U32 PacketPrePad; /* 08h */ 2422 } CONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0, 2423 LANPage0_t, MPI_POINTER pLANPage0_t; 2424 2425 #define MPI_LAN_PAGE0_PAGEVERSION (0x01) 2426 2427 #define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000) 2428 #define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001) 2429 #define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001) 2430 2431 typedef struct _CONFIG_PAGE_LAN_1 2432 { 2433 ConfigPageHeader_t Header; /* 00h */ 2434 U16 Reserved; /* 04h */ 2435 U8 CurrentDeviceState; /* 06h */ 2436 U8 Reserved1; /* 07h */ 2437 U32 MinPacketSize; /* 08h */ 2438 U32 MaxPacketSize; /* 0Ch */ 2439 U32 HardwareAddressLow; /* 10h */ 2440 U32 HardwareAddressHigh; /* 14h */ 2441 U32 MaxWireSpeedLow; /* 18h */ 2442 U32 MaxWireSpeedHigh; /* 1Ch */ 2443 U32 BucketsRemaining; /* 20h */ 2444 U32 MaxReplySize; /* 24h */ 2445 U32 NegWireSpeedLow; /* 28h */ 2446 U32 NegWireSpeedHigh; /* 2Ch */ 2447 } CONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1, 2448 LANPage1_t, MPI_POINTER pLANPage1_t; 2449 2450 #define MPI_LAN_PAGE1_PAGEVERSION (0x03) 2451 2452 #define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00) 2453 #define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01) 2454 2455 2456 /**************************************************************************** 2457 * Inband Config Pages 2458 ****************************************************************************/ 2459 2460 typedef struct _CONFIG_PAGE_INBAND_0 2461 { 2462 CONFIG_PAGE_HEADER Header; /* 00h */ 2463 MPI_VERSION_FORMAT InbandVersion; /* 04h */ 2464 U16 MaximumBuffers; /* 08h */ 2465 U16 Reserved1; /* 0Ah */ 2466 } CONFIG_PAGE_INBAND_0, MPI_POINTER PTR_CONFIG_PAGE_INBAND_0, 2467 InbandPage0_t, MPI_POINTER pInbandPage0_t; 2468 2469 #define MPI_INBAND_PAGEVERSION (0x00) 2470 2471 2472 2473 /**************************************************************************** 2474 * SAS IO Unit Config Pages 2475 ****************************************************************************/ 2476 2477 typedef struct _MPI_SAS_IO_UNIT0_PHY_DATA 2478 { 2479 U8 Port; /* 00h */ 2480 U8 PortFlags; /* 01h */ 2481 U8 PhyFlags; /* 02h */ 2482 U8 NegotiatedLinkRate; /* 03h */ 2483 U32 ControllerPhyDeviceInfo;/* 04h */ 2484 U16 AttachedDeviceHandle; /* 08h */ 2485 U16 ControllerDevHandle; /* 0Ah */ 2486 U32 DiscoveryStatus; /* 0Ch */ 2487 } MPI_SAS_IO_UNIT0_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT0_PHY_DATA, 2488 SasIOUnit0PhyData, MPI_POINTER pSasIOUnit0PhyData; 2489 2490 /* 2491 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2492 * one and check Header.PageLength at runtime. 2493 */ 2494 #ifndef MPI_SAS_IOUNIT0_PHY_MAX 2495 #define MPI_SAS_IOUNIT0_PHY_MAX (1) 2496 #endif 2497 2498 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_0 2499 { 2500 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2501 U16 NvdataVersionDefault; /* 08h */ 2502 U16 NvdataVersionPersistent; /* 0Ah */ 2503 U8 NumPhys; /* 0Ch */ 2504 U8 Reserved2; /* 0Dh */ 2505 U16 Reserved3; /* 0Eh */ 2506 MPI_SAS_IO_UNIT0_PHY_DATA PhyData[MPI_SAS_IOUNIT0_PHY_MAX]; /* 10h */ 2507 } CONFIG_PAGE_SAS_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_0, 2508 SasIOUnitPage0_t, MPI_POINTER pSasIOUnitPage0_t; 2509 2510 #define MPI_SASIOUNITPAGE0_PAGEVERSION (0x04) 2511 2512 /* values for SAS IO Unit Page 0 PortFlags */ 2513 #define MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS (0x08) 2514 #define MPI_SAS_IOUNIT0_PORT_FLAGS_0_TARGET_IOC_NUM (0x00) 2515 #define MPI_SAS_IOUNIT0_PORT_FLAGS_1_TARGET_IOC_NUM (0x04) 2516 #define MPI_SAS_IOUNIT0_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2517 2518 /* values for SAS IO Unit Page 0 PhyFlags */ 2519 #define MPI_SAS_IOUNIT0_PHY_FLAGS_PHY_DISABLED (0x04) 2520 #define MPI_SAS_IOUNIT0_PHY_FLAGS_TX_INVERT (0x02) 2521 #define MPI_SAS_IOUNIT0_PHY_FLAGS_RX_INVERT (0x01) 2522 2523 /* values for SAS IO Unit Page 0 NegotiatedLinkRate */ 2524 #define MPI_SAS_IOUNIT0_RATE_UNKNOWN (0x00) 2525 #define MPI_SAS_IOUNIT0_RATE_PHY_DISABLED (0x01) 2526 #define MPI_SAS_IOUNIT0_RATE_FAILED_SPEED_NEGOTIATION (0x02) 2527 #define MPI_SAS_IOUNIT0_RATE_SATA_OOB_COMPLETE (0x03) 2528 #define MPI_SAS_IOUNIT0_RATE_1_5 (0x08) 2529 #define MPI_SAS_IOUNIT0_RATE_3_0 (0x09) 2530 2531 /* see mpi_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 2532 2533 /* values for SAS IO Unit Page 0 DiscoveryStatus */ 2534 #define MPI_SAS_IOUNIT0_DS_LOOP_DETECTED (0x00000001) 2535 #define MPI_SAS_IOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2536 #define MPI_SAS_IOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 2537 #define MPI_SAS_IOUNIT0_DS_EXPANDER_ERR (0x00000008) 2538 #define MPI_SAS_IOUNIT0_DS_SMP_TIMEOUT (0x00000010) 2539 #define MPI_SAS_IOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2540 #define MPI_SAS_IOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 2541 #define MPI_SAS_IOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 2542 #define MPI_SAS_IOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 2543 #define MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 2544 #define MPI_SAS_IOUNIT0_DS_TABLE_LINK (0x00000400) 2545 #define MPI_SAS_IOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 2546 #define MPI_SAS_IOUNIT0_DS_MAX_SATA_TARGETS (0x00001000) 2547 2548 2549 typedef struct _MPI_SAS_IO_UNIT1_PHY_DATA 2550 { 2551 U8 Port; /* 00h */ 2552 U8 PortFlags; /* 01h */ 2553 U8 PhyFlags; /* 02h */ 2554 U8 MaxMinLinkRate; /* 03h */ 2555 U32 ControllerPhyDeviceInfo; /* 04h */ 2556 U16 MaxTargetPortConnectTime; /* 08h */ 2557 U16 Reserved1; /* 0Ah */ 2558 } MPI_SAS_IO_UNIT1_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT1_PHY_DATA, 2559 SasIOUnit1PhyData, MPI_POINTER pSasIOUnit1PhyData; 2560 2561 /* 2562 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2563 * one and check Header.PageLength at runtime. 2564 */ 2565 #ifndef MPI_SAS_IOUNIT1_PHY_MAX 2566 #define MPI_SAS_IOUNIT1_PHY_MAX (1) 2567 #endif 2568 2569 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_1 2570 { 2571 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2572 U16 ControlFlags; /* 08h */ 2573 U16 MaxNumSATATargets; /* 0Ah */ 2574 U16 AdditionalControlFlags; /* 0Ch */ 2575 U16 Reserved1; /* 0Eh */ 2576 U8 NumPhys; /* 10h */ 2577 U8 SATAMaxQDepth; /* 11h */ 2578 U8 ReportDeviceMissingDelay; /* 12h */ 2579 U8 IODeviceMissingDelay; /* 13h */ 2580 MPI_SAS_IO_UNIT1_PHY_DATA PhyData[MPI_SAS_IOUNIT1_PHY_MAX]; /* 14h */ 2581 } CONFIG_PAGE_SAS_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_1, 2582 SasIOUnitPage1_t, MPI_POINTER pSasIOUnitPage1_t; 2583 2584 #define MPI_SASIOUNITPAGE1_PAGEVERSION (0x07) 2585 2586 /* values for SAS IO Unit Page 1 ControlFlags */ 2587 #define MPI_SAS_IOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 2588 #define MPI_SAS_IOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 2589 #define MPI_SAS_IOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 2590 #define MPI_SAS_IOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 2591 #define MPI_SAS_IOUNIT1_CONTROL_DISABLE_SAS_HASH (0x0800) 2592 2593 #define MPI_SAS_IOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 2594 #define MPI_SAS_IOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 2595 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x00) 2596 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x01) 2597 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x02) 2598 2599 #define MPI_SAS_IOUNIT1_CONTROL_POSTPONE_SATA_INIT (0x0100) 2600 #define MPI_SAS_IOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 2601 #define MPI_SAS_IOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 2602 #define MPI_SAS_IOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 2603 #define MPI_SAS_IOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 2604 #define MPI_SAS_IOUNIT1_CONTROL_PHY_ENABLE_ORDER_HIGH (0x0008) 2605 #define MPI_SAS_IOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 2606 #define MPI_SAS_IOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 2607 #define MPI_SAS_IOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 2608 2609 /* values for SAS IO Unit Page 1 AdditionalControlFlags */ 2610 #define MPI_SAS_IOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 2611 #define MPI_SAS_IOUNIT1_ACONTROL_HIDE_NONZERO_ATTACHED_PHY_IDENT (0x0020) 2612 #define MPI_SAS_IOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 2613 #define MPI_SAS_IOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 2614 #define MPI_SAS_IOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 2615 #define MPI_SAS_IOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 2616 #define MPI_SAS_IOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 2617 2618 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 2619 #define MPI_SAS_IOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 2620 #define MPI_SAS_IOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 2621 2622 /* values for SAS IO Unit Page 1 PortFlags */ 2623 #define MPI_SAS_IOUNIT1_PORT_FLAGS_0_TARGET_IOC_NUM (0x00) 2624 #define MPI_SAS_IOUNIT1_PORT_FLAGS_1_TARGET_IOC_NUM (0x04) 2625 #define MPI_SAS_IOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2626 2627 /* values for SAS IO Unit Page 0 PhyFlags */ 2628 #define MPI_SAS_IOUNIT1_PHY_FLAGS_PHY_DISABLE (0x04) 2629 #define MPI_SAS_IOUNIT1_PHY_FLAGS_TX_INVERT (0x02) 2630 #define MPI_SAS_IOUNIT1_PHY_FLAGS_RX_INVERT (0x01) 2631 2632 /* values for SAS IO Unit Page 0 MaxMinLinkRate */ 2633 #define MPI_SAS_IOUNIT1_MAX_RATE_MASK (0xF0) 2634 #define MPI_SAS_IOUNIT1_MAX_RATE_1_5 (0x80) 2635 #define MPI_SAS_IOUNIT1_MAX_RATE_3_0 (0x90) 2636 #define MPI_SAS_IOUNIT1_MIN_RATE_MASK (0x0F) 2637 #define MPI_SAS_IOUNIT1_MIN_RATE_1_5 (0x08) 2638 #define MPI_SAS_IOUNIT1_MIN_RATE_3_0 (0x09) 2639 2640 /* see mpi_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 2641 2642 2643 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_2 2644 { 2645 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2646 U8 NumDevsPerEnclosure; /* 08h */ 2647 U8 Reserved1; /* 09h */ 2648 U16 Reserved2; /* 0Ah */ 2649 U16 MaxPersistentIDs; /* 0Ch */ 2650 U16 NumPersistentIDsUsed; /* 0Eh */ 2651 U8 Status; /* 10h */ 2652 U8 Flags; /* 11h */ 2653 U16 MaxNumPhysicalMappedIDs;/* 12h */ 2654 } CONFIG_PAGE_SAS_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_2, 2655 SasIOUnitPage2_t, MPI_POINTER pSasIOUnitPage2_t; 2656 2657 #define MPI_SASIOUNITPAGE2_PAGEVERSION (0x06) 2658 2659 /* values for SAS IO Unit Page 2 Status field */ 2660 #define MPI_SAS_IOUNIT2_STATUS_DEVICE_LIMIT_EXCEEDED (0x08) 2661 #define MPI_SAS_IOUNIT2_STATUS_ENCLOSURE_DEVICES_UNMAPPED (0x04) 2662 #define MPI_SAS_IOUNIT2_STATUS_DISABLED_PERSISTENT_MAPPINGS (0x02) 2663 #define MPI_SAS_IOUNIT2_STATUS_FULL_PERSISTENT_MAPPINGS (0x01) 2664 2665 /* values for SAS IO Unit Page 2 Flags field */ 2666 #define MPI_SAS_IOUNIT2_FLAGS_DISABLE_PERSISTENT_MAPPINGS (0x01) 2667 /* Physical Mapping Modes */ 2668 #define MPI_SAS_IOUNIT2_FLAGS_MASK_PHYS_MAP_MODE (0x0E) 2669 #define MPI_SAS_IOUNIT2_FLAGS_SHIFT_PHYS_MAP_MODE (1) 2670 #define MPI_SAS_IOUNIT2_FLAGS_NO_PHYS_MAP (0x00) 2671 #define MPI_SAS_IOUNIT2_FLAGS_DIRECT_ATTACH_PHYS_MAP (0x01) 2672 #define MPI_SAS_IOUNIT2_FLAGS_ENCLOSURE_SLOT_PHYS_MAP (0x02) 2673 #define MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP (0x07) 2674 2675 #define MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT (0x10) 2676 #define MPI_SAS_IOUNIT2_FLAGS_DA_STARTING_SLOT (0x20) 2677 2678 2679 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_3 2680 { 2681 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2682 U32 Reserved1; /* 08h */ 2683 U32 MaxInvalidDwordCount; /* 0Ch */ 2684 U32 InvalidDwordCountTime; /* 10h */ 2685 U32 MaxRunningDisparityErrorCount; /* 14h */ 2686 U32 RunningDisparityErrorTime; /* 18h */ 2687 U32 MaxLossDwordSynchCount; /* 1Ch */ 2688 U32 LossDwordSynchCountTime; /* 20h */ 2689 U32 MaxPhyResetProblemCount; /* 24h */ 2690 U32 PhyResetProblemTime; /* 28h */ 2691 } CONFIG_PAGE_SAS_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_3, 2692 SasIOUnitPage3_t, MPI_POINTER pSasIOUnitPage3_t; 2693 2694 #define MPI_SASIOUNITPAGE3_PAGEVERSION (0x00) 2695 2696 2697 /**************************************************************************** 2698 * SAS Expander Config Pages 2699 ****************************************************************************/ 2700 2701 typedef struct _CONFIG_PAGE_SAS_EXPANDER_0 2702 { 2703 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2704 U8 PhysicalPort; /* 08h */ 2705 U8 Reserved1; /* 09h */ 2706 U16 EnclosureHandle; /* 0Ah */ 2707 U64 SASAddress; /* 0Ch */ 2708 U32 DiscoveryStatus; /* 14h */ 2709 U16 DevHandle; /* 18h */ 2710 U16 ParentDevHandle; /* 1Ah */ 2711 U16 ExpanderChangeCount; /* 1Ch */ 2712 U16 ExpanderRouteIndexes; /* 1Eh */ 2713 U8 NumPhys; /* 20h */ 2714 U8 SASLevel; /* 21h */ 2715 U8 Flags; /* 22h */ 2716 U8 Reserved3; /* 23h */ 2717 } CONFIG_PAGE_SAS_EXPANDER_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_0, 2718 SasExpanderPage0_t, MPI_POINTER pSasExpanderPage0_t; 2719 2720 #define MPI_SASEXPANDER0_PAGEVERSION (0x03) 2721 2722 /* values for SAS Expander Page 0 DiscoveryStatus field */ 2723 #define MPI_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2724 #define MPI_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2725 #define MPI_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2726 #define MPI_SAS_EXPANDER0_DS_EXPANDER_ERR (0x00000008) 2727 #define MPI_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2728 #define MPI_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2729 #define MPI_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2730 #define MPI_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2731 #define MPI_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2732 #define MPI_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2733 #define MPI_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2734 #define MPI_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2735 2736 /* values for SAS Expander Page 0 Flags field */ 2737 #define MPI_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x02) 2738 #define MPI_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x01) 2739 2740 2741 typedef struct _CONFIG_PAGE_SAS_EXPANDER_1 2742 { 2743 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2744 U8 PhysicalPort; /* 08h */ 2745 U8 Reserved1; /* 09h */ 2746 U16 Reserved2; /* 0Ah */ 2747 U8 NumPhys; /* 0Ch */ 2748 U8 Phy; /* 0Dh */ 2749 U16 NumTableEntriesProgrammed; /* 0Eh */ 2750 U8 ProgrammedLinkRate; /* 10h */ 2751 U8 HwLinkRate; /* 11h */ 2752 U16 AttachedDevHandle; /* 12h */ 2753 U32 PhyInfo; /* 14h */ 2754 U32 AttachedDeviceInfo; /* 18h */ 2755 U16 OwnerDevHandle; /* 1Ch */ 2756 U8 ChangeCount; /* 1Eh */ 2757 U8 NegotiatedLinkRate; /* 1Fh */ 2758 U8 PhyIdentifier; /* 20h */ 2759 U8 AttachedPhyIdentifier; /* 21h */ 2760 U8 Reserved3; /* 22h */ 2761 U8 DiscoveryInfo; /* 23h */ 2762 U32 Reserved4; /* 24h */ 2763 } CONFIG_PAGE_SAS_EXPANDER_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_1, 2764 SasExpanderPage1_t, MPI_POINTER pSasExpanderPage1_t; 2765 2766 #define MPI_SASEXPANDER1_PAGEVERSION (0x01) 2767 2768 /* use MPI_SAS_PHY0_PRATE_ defines for ProgrammedLinkRate */ 2769 2770 /* use MPI_SAS_PHY0_HWRATE_ defines for HwLinkRate */ 2771 2772 /* use MPI_SAS_PHY0_PHYINFO_ defines for PhyInfo */ 2773 2774 /* see mpi_sas.h for values for SAS Expander Page 1 AttachedDeviceInfo values */ 2775 2776 /* values for SAS Expander Page 1 DiscoveryInfo field */ 2777 #define MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY DISABLED (0x04) 2778 #define MPI_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2779 #define MPI_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2780 2781 /* values for SAS Expander Page 1 NegotiatedLinkRate field */ 2782 #define MPI_SAS_EXPANDER1_NEG_RATE_UNKNOWN (0x00) 2783 #define MPI_SAS_EXPANDER1_NEG_RATE_PHY_DISABLED (0x01) 2784 #define MPI_SAS_EXPANDER1_NEG_RATE_FAILED_NEGOTIATION (0x02) 2785 #define MPI_SAS_EXPANDER1_NEG_RATE_SATA_OOB_COMPLETE (0x03) 2786 #define MPI_SAS_EXPANDER1_NEG_RATE_1_5 (0x08) 2787 #define MPI_SAS_EXPANDER1_NEG_RATE_3_0 (0x09) 2788 2789 2790 /**************************************************************************** 2791 * SAS Device Config Pages 2792 ****************************************************************************/ 2793 2794 typedef struct _CONFIG_PAGE_SAS_DEVICE_0 2795 { 2796 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2797 U16 Slot; /* 08h */ 2798 U16 EnclosureHandle; /* 0Ah */ 2799 U64 SASAddress; /* 0Ch */ 2800 U16 ParentDevHandle; /* 14h */ 2801 U8 PhyNum; /* 16h */ 2802 U8 AccessStatus; /* 17h */ 2803 U16 DevHandle; /* 18h */ 2804 U8 TargetID; /* 1Ah */ 2805 U8 Bus; /* 1Bh */ 2806 U32 DeviceInfo; /* 1Ch */ 2807 U16 Flags; /* 20h */ 2808 U8 PhysicalPort; /* 22h */ 2809 U8 Reserved2; /* 23h */ 2810 } CONFIG_PAGE_SAS_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_0, 2811 SasDevicePage0_t, MPI_POINTER pSasDevicePage0_t; 2812 2813 #define MPI_SASDEVICE0_PAGEVERSION (0x05) 2814 2815 /* values for SAS Device Page 0 AccessStatus field */ 2816 #define MPI_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2817 #define MPI_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2818 #define MPI_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2819 #define MPI_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2820 /* specific values for SATA Init failures */ 2821 #define MPI_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2822 #define MPI_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2823 #define MPI_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2824 #define MPI_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2825 #define MPI_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2826 #define MPI_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2827 #define MPI_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2828 #define MPI_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2829 #define MPI_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2830 #define MPI_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2831 #define MPI_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2832 2833 /* values for SAS Device Page 0 Flags field */ 2834 #define MPI_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2835 #define MPI_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2836 #define MPI_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2837 #define MPI_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2838 #define MPI_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2839 #define MPI_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2840 #define MPI_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2841 #define MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2842 #define MPI_SAS_DEVICE0_FLAGS_MAPPING_PERSISTENT (0x0004) 2843 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_MAPPED (0x0002) 2844 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2845 2846 /* see mpi_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2847 2848 2849 typedef struct _CONFIG_PAGE_SAS_DEVICE_1 2850 { 2851 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2852 U32 Reserved1; /* 08h */ 2853 U64 SASAddress; /* 0Ch */ 2854 U32 Reserved2; /* 14h */ 2855 U16 DevHandle; /* 18h */ 2856 U8 TargetID; /* 1Ah */ 2857 U8 Bus; /* 1Bh */ 2858 U8 InitialRegDeviceFIS[20];/* 1Ch */ 2859 } CONFIG_PAGE_SAS_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_1, 2860 SasDevicePage1_t, MPI_POINTER pSasDevicePage1_t; 2861 2862 #define MPI_SASDEVICE1_PAGEVERSION (0x00) 2863 2864 2865 typedef struct _CONFIG_PAGE_SAS_DEVICE_2 2866 { 2867 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2868 U64 PhysicalIdentifier; /* 08h */ 2869 U32 EnclosureMapping; /* 10h */ 2870 } CONFIG_PAGE_SAS_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_2, 2871 SasDevicePage2_t, MPI_POINTER pSasDevicePage2_t; 2872 2873 #define MPI_SASDEVICE2_PAGEVERSION (0x01) 2874 2875 /* defines for SAS Device Page 2 EnclosureMapping field */ 2876 #define MPI_SASDEVICE2_ENC_MAP_MASK_MISSING_COUNT (0x0000000F) 2877 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_MISSING_COUNT (0) 2878 #define MPI_SASDEVICE2_ENC_MAP_MASK_NUM_SLOTS (0x000007F0) 2879 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_NUM_SLOTS (4) 2880 #define MPI_SASDEVICE2_ENC_MAP_MASK_START_INDEX (0x001FF800) 2881 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_START_INDEX (11) 2882 2883 2884 /**************************************************************************** 2885 * SAS PHY Config Pages 2886 ****************************************************************************/ 2887 2888 typedef struct _CONFIG_PAGE_SAS_PHY_0 2889 { 2890 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2891 U16 OwnerDevHandle; /* 08h */ 2892 U16 Reserved1; /* 0Ah */ 2893 U64 SASAddress; /* 0Ch */ 2894 U16 AttachedDevHandle; /* 14h */ 2895 U8 AttachedPhyIdentifier; /* 16h */ 2896 U8 Reserved2; /* 17h */ 2897 U32 AttachedDeviceInfo; /* 18h */ 2898 U8 ProgrammedLinkRate; /* 20h */ 2899 U8 HwLinkRate; /* 21h */ 2900 U8 ChangeCount; /* 22h */ 2901 U8 Flags; /* 23h */ 2902 U32 PhyInfo; /* 24h */ 2903 } CONFIG_PAGE_SAS_PHY_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_0, 2904 SasPhyPage0_t, MPI_POINTER pSasPhyPage0_t; 2905 2906 #define MPI_SASPHY0_PAGEVERSION (0x01) 2907 2908 /* values for SAS PHY Page 0 ProgrammedLinkRate field */ 2909 #define MPI_SAS_PHY0_PRATE_MAX_RATE_MASK (0xF0) 2910 #define MPI_SAS_PHY0_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 2911 #define MPI_SAS_PHY0_PRATE_MAX_RATE_1_5 (0x80) 2912 #define MPI_SAS_PHY0_PRATE_MAX_RATE_3_0 (0x90) 2913 #define MPI_SAS_PHY0_PRATE_MIN_RATE_MASK (0x0F) 2914 #define MPI_SAS_PHY0_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 2915 #define MPI_SAS_PHY0_PRATE_MIN_RATE_1_5 (0x08) 2916 #define MPI_SAS_PHY0_PRATE_MIN_RATE_3_0 (0x09) 2917 2918 /* values for SAS PHY Page 0 HwLinkRate field */ 2919 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_MASK (0xF0) 2920 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_1_5 (0x80) 2921 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_3_0 (0x90) 2922 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_MASK (0x0F) 2923 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_1_5 (0x08) 2924 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_3_0 (0x09) 2925 2926 /* values for SAS PHY Page 0 Flags field */ 2927 #define MPI_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2928 2929 /* values for SAS PHY Page 0 PhyInfo field */ 2930 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 2931 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_SELECTOR (0x00002000) 2932 #define MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY (0x00001000) 2933 2934 #define MPI_SAS_PHY0_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 2935 #define MPI_SAS_PHY0_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 2936 2937 #define MPI_SAS_PHY0_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 2938 #define MPI_SAS_PHY0_PHYINFO_DIRECT_ROUTING (0x00000000) 2939 #define MPI_SAS_PHY0_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 2940 #define MPI_SAS_PHY0_PHYINFO_TABLE_ROUTING (0x00000020) 2941 2942 #define MPI_SAS_PHY0_PHYINFO_MASK_LINK_RATE (0x0000000F) 2943 #define MPI_SAS_PHY0_PHYINFO_UNKNOWN_LINK_RATE (0x00000000) 2944 #define MPI_SAS_PHY0_PHYINFO_PHY_DISABLED (0x00000001) 2945 #define MPI_SAS_PHY0_PHYINFO_NEGOTIATION_FAILED (0x00000002) 2946 #define MPI_SAS_PHY0_PHYINFO_SATA_OOB_COMPLETE (0x00000003) 2947 #define MPI_SAS_PHY0_PHYINFO_RATE_1_5 (0x00000008) 2948 #define MPI_SAS_PHY0_PHYINFO_RATE_3_0 (0x00000009) 2949 2950 2951 typedef struct _CONFIG_PAGE_SAS_PHY_1 2952 { 2953 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2954 U32 Reserved1; /* 08h */ 2955 U32 InvalidDwordCount; /* 0Ch */ 2956 U32 RunningDisparityErrorCount; /* 10h */ 2957 U32 LossDwordSynchCount; /* 14h */ 2958 U32 PhyResetProblemCount; /* 18h */ 2959 } CONFIG_PAGE_SAS_PHY_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_1, 2960 SasPhyPage1_t, MPI_POINTER pSasPhyPage1_t; 2961 2962 #define MPI_SASPHY1_PAGEVERSION (0x00) 2963 2964 2965 /**************************************************************************** 2966 * SAS Enclosure Config Pages 2967 ****************************************************************************/ 2968 2969 typedef struct _CONFIG_PAGE_SAS_ENCLOSURE_0 2970 { 2971 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2972 U32 Reserved1; /* 08h */ 2973 U64 EnclosureLogicalID; /* 0Ch */ 2974 U16 Flags; /* 14h */ 2975 U16 EnclosureHandle; /* 16h */ 2976 U16 NumSlots; /* 18h */ 2977 U16 StartSlot; /* 1Ah */ 2978 U8 StartTargetID; /* 1Ch */ 2979 U8 StartBus; /* 1Dh */ 2980 U8 SEPTargetID; /* 1Eh */ 2981 U8 SEPBus; /* 1Fh */ 2982 U32 Reserved2; /* 20h */ 2983 U32 Reserved3; /* 24h */ 2984 } CONFIG_PAGE_SAS_ENCLOSURE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_ENCLOSURE_0, 2985 SasEnclosurePage0_t, MPI_POINTER pSasEnclosurePage0_t; 2986 2987 #define MPI_SASENCLOSURE0_PAGEVERSION (0x01) 2988 2989 /* values for SAS Enclosure Page 0 Flags field */ 2990 #define MPI_SAS_ENCLS0_FLAGS_SEP_BUS_ID_VALID (0x0020) 2991 #define MPI_SAS_ENCLS0_FLAGS_START_BUS_ID_VALID (0x0010) 2992 2993 #define MPI_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 2994 #define MPI_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 2995 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 2996 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 2997 #define MPI_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 2998 #define MPI_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 2999 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3000 3001 3002 /**************************************************************************** 3003 * Log Config Pages 3004 ****************************************************************************/ 3005 /* 3006 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3007 * one and check NumLogEntries at runtime. 3008 */ 3009 #ifndef MPI_LOG_0_NUM_LOG_ENTRIES 3010 #define MPI_LOG_0_NUM_LOG_ENTRIES (1) 3011 #endif 3012 3013 #define MPI_LOG_0_LOG_DATA_LENGTH (0x1C) 3014 3015 typedef struct _MPI_LOG_0_ENTRY 3016 { 3017 U32 TimeStamp; /* 00h */ 3018 U32 Reserved1; /* 04h */ 3019 U16 LogSequence; /* 08h */ 3020 U16 LogEntryQualifier; /* 0Ah */ 3021 U8 LogData[MPI_LOG_0_LOG_DATA_LENGTH]; /* 0Ch */ 3022 } MPI_LOG_0_ENTRY, MPI_POINTER PTR_MPI_LOG_0_ENTRY, 3023 MpiLog0Entry_t, MPI_POINTER pMpiLog0Entry_t; 3024 3025 /* values for Log Page 0 LogEntry LogEntryQualifier field */ 3026 #define MPI_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 3027 #define MPI_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 3028 3029 typedef struct _CONFIG_PAGE_LOG_0 3030 { 3031 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 3032 U32 Reserved1; /* 08h */ 3033 U32 Reserved2; /* 0Ch */ 3034 U16 NumLogEntries; /* 10h */ 3035 U16 Reserved3; /* 12h */ 3036 MPI_LOG_0_ENTRY LogEntry[MPI_LOG_0_NUM_LOG_ENTRIES]; /* 14h */ 3037 } CONFIG_PAGE_LOG_0, MPI_POINTER PTR_CONFIG_PAGE_LOG_0, 3038 LogPage0_t, MPI_POINTER pLogPage0_t; 3039 3040 #define MPI_LOG_0_PAGEVERSION (0x01) 3041 3042 3043 #endif 3044 3045