1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 21da177e4SLinus Torvalds /* 3cddc0ab7SPrakash, Sathya * Copyright (c) 2000-2008 LSI Corporation. 41da177e4SLinus Torvalds * 51da177e4SLinus Torvalds * 61da177e4SLinus Torvalds * Name: mpi_cnfg.h 71da177e4SLinus Torvalds * Title: MPI Config message, structures, and Pages 81da177e4SLinus Torvalds * Creation Date: July 27, 2000 91da177e4SLinus Torvalds * 10fd7a2533SKashyap, Desai * mpi_cnfg.h Version: 01.05.18 111da177e4SLinus Torvalds * 121da177e4SLinus Torvalds * Version History 131da177e4SLinus Torvalds * --------------- 141da177e4SLinus Torvalds * 151da177e4SLinus Torvalds * Date Version Description 161da177e4SLinus Torvalds * -------- -------- ------------------------------------------------------ 171da177e4SLinus Torvalds * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 181da177e4SLinus Torvalds * 06-06-00 01.00.01 Update version number for 1.0 release. 191da177e4SLinus Torvalds * 06-08-00 01.00.02 Added _PAGEVERSION definitions for all pages. 201da177e4SLinus Torvalds * Added FcPhLowestVersion, FcPhHighestVersion, Reserved2 211da177e4SLinus Torvalds * fields to FC_DEVICE_0 page, updated the page version. 221da177e4SLinus Torvalds * Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in 231da177e4SLinus Torvalds * SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages 241da177e4SLinus Torvalds * and updated the page versions. 251da177e4SLinus Torvalds * Added _RESPONSE_ID_MASK definition to SCSI_PORT_1 261da177e4SLinus Torvalds * page and updated the page version. 271da177e4SLinus Torvalds * Added Information field and _INFO_PARAMS_NEGOTIATED 281da177e4SLinus Torvalds * definitionto SCSI_DEVICE_0 page. 291da177e4SLinus Torvalds * 06-22-00 01.00.03 Removed batch controls from LAN_0 page and updated the 301da177e4SLinus Torvalds * page version. 311da177e4SLinus Torvalds * Added BucketsRemaining to LAN_1 page, redefined the 321da177e4SLinus Torvalds * state values, and updated the page version. 331da177e4SLinus Torvalds * Revised bus width definitions in SCSI_PORT_0, 341da177e4SLinus Torvalds * SCSI_DEVICE_0 and SCSI_DEVICE_1 pages. 351da177e4SLinus Torvalds * 06-30-00 01.00.04 Added MaxReplySize to LAN_1 page and updated the page 361da177e4SLinus Torvalds * version. 371da177e4SLinus Torvalds * Moved FC_DEVICE_0 PageAddress description to spec. 381da177e4SLinus Torvalds * 07-27-00 01.00.05 Corrected the SubsystemVendorID and SubsystemID field 391da177e4SLinus Torvalds * widths in IOC_0 page and updated the page version. 401da177e4SLinus Torvalds * 11-02-00 01.01.01 Original release for post 1.0 work 411da177e4SLinus Torvalds * Added Manufacturing pages, IO Unit Page 2, SCSI SPI 421da177e4SLinus Torvalds * Port Page 2, FC Port Page 4, FC Port Page 5 431da177e4SLinus Torvalds * 11-15-00 01.01.02 Interim changes to match proposals 441da177e4SLinus Torvalds * 12-04-00 01.01.03 Config page changes to match MPI rev 1.00.01. 451da177e4SLinus Torvalds * 12-05-00 01.01.04 Modified config page actions. 461da177e4SLinus Torvalds * 01-09-01 01.01.05 Added defines for page address formats. 471da177e4SLinus Torvalds * Data size for Manufacturing pages 2 and 3 no longer 481da177e4SLinus Torvalds * defined here. 491da177e4SLinus Torvalds * Io Unit Page 2 size is fixed at 4 adapters and some 501da177e4SLinus Torvalds * flags were changed. 511da177e4SLinus Torvalds * SCSI Port Page 2 Device Settings modified. 521da177e4SLinus Torvalds * New fields added to FC Port Page 0 and some flags 531da177e4SLinus Torvalds * cleaned up. 541da177e4SLinus Torvalds * Removed impedance flash from FC Port Page 1. 551da177e4SLinus Torvalds * Added FC Port pages 6 and 7. 561da177e4SLinus Torvalds * 01-25-01 01.01.06 Added MaxInitiators field to FcPortPage0. 571da177e4SLinus Torvalds * 01-29-01 01.01.07 Changed some defines to make them 32 character unique. 581da177e4SLinus Torvalds * Added some LinkType defines for FcPortPage0. 591da177e4SLinus Torvalds * 02-20-01 01.01.08 Started using MPI_POINTER. 601da177e4SLinus Torvalds * 02-27-01 01.01.09 Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with 611da177e4SLinus Torvalds * MPI_CONFIG_PAGETYPE_RAID_VOLUME. 621da177e4SLinus Torvalds * Added definitions and structures for IOC Page 2 and 631da177e4SLinus Torvalds * RAID Volume Page 2. 641da177e4SLinus Torvalds * 03-27-01 01.01.10 Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9. 651da177e4SLinus Torvalds * CONFIG_PAGE_FC_PORT_3 now supports persistent by DID. 661da177e4SLinus Torvalds * Added VendorId and ProductRevLevel fields to 671da177e4SLinus Torvalds * RAIDVOL2_IM_PHYS_ID struct. 681da177e4SLinus Torvalds * Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_ 691da177e4SLinus Torvalds * defines to make them compatible to MPI version 1.0. 701da177e4SLinus Torvalds * Added structure offset comments. 711da177e4SLinus Torvalds * 04-09-01 01.01.11 Added some new defines for the PageAddress field and 721da177e4SLinus Torvalds * removed some obsolete ones. 731da177e4SLinus Torvalds * Added IO Unit Page 3. 741da177e4SLinus Torvalds * Modified defines for Scsi Port Page 2. 751da177e4SLinus Torvalds * Modified RAID Volume Pages. 761da177e4SLinus Torvalds * 08-08-01 01.02.01 Original release for v1.2 work. 771da177e4SLinus Torvalds * Added SepID and SepBus to RVP2 IMPhysicalDisk struct. 781da177e4SLinus Torvalds * Added defines for the SEP bits in RVP2 VolumeSettings. 791da177e4SLinus Torvalds * Modified the DeviceSettings field in RVP2 to use the 801da177e4SLinus Torvalds * proper structure. 811da177e4SLinus Torvalds * Added defines for SES, SAF-TE, and cross channel for 821da177e4SLinus Torvalds * IOCPage2 CapabilitiesFlags. 831da177e4SLinus Torvalds * Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE. 841da177e4SLinus Torvalds * Removed define for 851da177e4SLinus Torvalds * MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE. 861da177e4SLinus Torvalds * Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT. 871da177e4SLinus Torvalds * 08-29-01 01.02.02 Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035. 881da177e4SLinus Torvalds * Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY 891da177e4SLinus Torvalds * and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY. 901da177e4SLinus Torvalds * Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS, 911da177e4SLinus Torvalds * MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and 921da177e4SLinus Torvalds * MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and 931da177e4SLinus Torvalds * MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED. 941da177e4SLinus Torvalds * Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED 951da177e4SLinus Torvalds * and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED. 961da177e4SLinus Torvalds * Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1. 971da177e4SLinus Torvalds * Added rejected bits to SCSI Device Page 0 Information. 981da177e4SLinus Torvalds * Increased size of ALPA array in FC Port Page 2 by one 991da177e4SLinus Torvalds * and removed a one byte reserved field. 1001da177e4SLinus Torvalds * 09-28-01 01.02.03 Swapped NegWireSpeedLow and NegWireSpeedLow in 1011da177e4SLinus Torvalds * CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering. 1021da177e4SLinus Torvalds * Added structures for Manufacturing Page 4, IO Unit 1031da177e4SLinus Torvalds * Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and 1041da177e4SLinus Torvalds * RAID PhysDisk Page 0. 1051da177e4SLinus Torvalds * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK. 1061da177e4SLinus Torvalds * Modified some of the new defines to make them 32 1071da177e4SLinus Torvalds * character unique. 1081da177e4SLinus Torvalds * Modified how variable length pages (arrays) are defined. 1091da177e4SLinus Torvalds * Added generic defines for hot spare pools and RAID 1101da177e4SLinus Torvalds * volume types. 1111da177e4SLinus Torvalds * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR. 1121da177e4SLinus Torvalds * 03-14-02 01.02.06 Added PCISlotNum field to CONFIG_PAGE_IOC_1 along with 1131da177e4SLinus Torvalds * related define, and bumped the page version define. 1141da177e4SLinus Torvalds * 05-31-02 01.02.07 Added a Flags field to CONFIG_PAGE_IOC_2_RAID_VOL in a 1151da177e4SLinus Torvalds * reserved byte and added a define. 1161da177e4SLinus Torvalds * Added define for 1171da177e4SLinus Torvalds * MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE. 1181da177e4SLinus Torvalds * Added new config page: CONFIG_PAGE_IOC_5. 1191da177e4SLinus Torvalds * Added MaxAliases, MaxHardAliases, and NumCurrentAliases 1201da177e4SLinus Torvalds * fields to CONFIG_PAGE_FC_PORT_0. 1211da177e4SLinus Torvalds * Added AltConnector and NumRequestedAliases fields to 1221da177e4SLinus Torvalds * CONFIG_PAGE_FC_PORT_1. 1231da177e4SLinus Torvalds * Added new config page: CONFIG_PAGE_FC_PORT_10. 1241da177e4SLinus Torvalds * 07-12-02 01.02.08 Added more MPI_MANUFACTPAGE_DEVID_ defines. 1251da177e4SLinus Torvalds * Added additional MPI_SCSIDEVPAGE0_NP_ defines. 1261da177e4SLinus Torvalds * Added more MPI_SCSIDEVPAGE1_RP_ defines. 1271da177e4SLinus Torvalds * Added define for 1281da177e4SLinus Torvalds * MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE. 1291da177e4SLinus Torvalds * Added new config page: CONFIG_PAGE_SCSI_DEVICE_3. 1301da177e4SLinus Torvalds * Modified MPI_FCPORTPAGE5_FLAGS_ defines. 1311da177e4SLinus Torvalds * 09-16-02 01.02.09 Added MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG define. 1321da177e4SLinus Torvalds * 11-15-02 01.02.10 Added ConnectedID defines for CONFIG_PAGE_SCSI_PORT_0. 1331da177e4SLinus Torvalds * Added more Flags defines for CONFIG_PAGE_FC_PORT_1. 1341da177e4SLinus Torvalds * Added more Flags defines for CONFIG_PAGE_FC_DEVICE_0. 1351da177e4SLinus Torvalds * 04-01-03 01.02.11 Added RR_TOV field and additional Flags defines for 1361da177e4SLinus Torvalds * CONFIG_PAGE_FC_PORT_1. 1371da177e4SLinus Torvalds * Added define MPI_FCPORTPAGE5_FLAGS_DISABLE to disable 1381da177e4SLinus Torvalds * an alias. 1391da177e4SLinus Torvalds * Added more device id defines. 1401da177e4SLinus Torvalds * 06-26-03 01.02.12 Added MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID define. 1411da177e4SLinus Torvalds * Added TargetConfig and IDConfig fields to 1421da177e4SLinus Torvalds * CONFIG_PAGE_SCSI_PORT_1. 1431da177e4SLinus Torvalds * Added more PortFlags defines for CONFIG_PAGE_SCSI_PORT_2 1441da177e4SLinus Torvalds * to control DV. 1451da177e4SLinus Torvalds * Added more Flags defines for CONFIG_PAGE_FC_PORT_1. 1461da177e4SLinus Torvalds * In CONFIG_PAGE_FC_DEVICE_0, replaced Reserved1 field 1471da177e4SLinus Torvalds * with ADISCHardALPA. 1481da177e4SLinus Torvalds * Added MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY define. 149c1a71d1cSMoore, Eric Dean * 01-16-04 01.02.13 Added InitiatorDeviceTimeout and InitiatorIoPendTimeout 150c1a71d1cSMoore, Eric Dean * fields and related defines to CONFIG_PAGE_FC_PORT_1. 151c1a71d1cSMoore, Eric Dean * Added define for 152c1a71d1cSMoore, Eric Dean * MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK. 153c1a71d1cSMoore, Eric Dean * Added new fields to the substructures of 154c1a71d1cSMoore, Eric Dean * CONFIG_PAGE_FC_PORT_10. 155c1a71d1cSMoore, Eric Dean * 04-29-04 01.02.14 Added define for IDP bit for CONFIG_PAGE_SCSI_PORT_0, 156c1a71d1cSMoore, Eric Dean * CONFIG_PAGE_SCSI_DEVICE_0, and 157c1a71d1cSMoore, Eric Dean * CONFIG_PAGE_SCSI_DEVICE_1. Also bumped Page Version for 158c1a71d1cSMoore, Eric Dean * these pages. 159c1a71d1cSMoore, Eric Dean * 05-11-04 01.03.01 Added structure for CONFIG_PAGE_INBAND_0. 160c1a71d1cSMoore, Eric Dean * 08-19-04 01.05.01 Modified MSG_CONFIG request to support extended config 161c1a71d1cSMoore, Eric Dean * pages. 162c1a71d1cSMoore, Eric Dean * Added a new structure for extended config page header. 163c1a71d1cSMoore, Eric Dean * Added new extended config pages types and structures for 164c1a71d1cSMoore, Eric Dean * SAS IO Unit, SAS Expander, SAS Device, and SAS PHY. 165c1a71d1cSMoore, Eric Dean * Replaced a reserved byte in CONFIG_PAGE_MANUFACTURING_4 166c1a71d1cSMoore, Eric Dean * to add a Flags field. 167c1a71d1cSMoore, Eric Dean * Two new Manufacturing config pages (5 and 6). 168c1a71d1cSMoore, Eric Dean * Two new bits defined for IO Unit Page 1 Flags field. 169c1a71d1cSMoore, Eric Dean * Modified CONFIG_PAGE_IO_UNIT_2 to add three new fields 170c1a71d1cSMoore, Eric Dean * to specify the BIOS boot device. 171c1a71d1cSMoore, Eric Dean * Four new Flags bits defined for IO Unit Page 2. 172c1a71d1cSMoore, Eric Dean * Added IO Unit Page 4. 173c1a71d1cSMoore, Eric Dean * Added EEDP Flags settings to IOC Page 1. 174c1a71d1cSMoore, Eric Dean * Added new BIOS Page 1 config page. 175c1a71d1cSMoore, Eric Dean * 10-05-04 01.05.02 Added define for 176c1a71d1cSMoore, Eric Dean * MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE. 177c1a71d1cSMoore, Eric Dean * Added new Flags field to CONFIG_PAGE_MANUFACTURING_5 and 178c1a71d1cSMoore, Eric Dean * associated defines. 179c1a71d1cSMoore, Eric Dean * Added more defines for SAS IO Unit Page 0 180c1a71d1cSMoore, Eric Dean * DiscoveryStatus field. 181c1a71d1cSMoore, Eric Dean * Added define for MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK 182c1a71d1cSMoore, Eric Dean * and MPI_SAS_IOUNIT0_DS_TABLE_LINK. 183c1a71d1cSMoore, Eric Dean * Added defines for Physical Mapping Modes to SAS IO Unit 184c1a71d1cSMoore, Eric Dean * Page 2. 185c1a71d1cSMoore, Eric Dean * Added define for 186c1a71d1cSMoore, Eric Dean * MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH. 187c1a71d1cSMoore, Eric Dean * 10-27-04 01.05.03 Added defines for new SAS PHY page addressing mode. 188c1a71d1cSMoore, Eric Dean * Added defines for MaxTargetSpinUp to BIOS Page 1. 189c1a71d1cSMoore, Eric Dean * Added 5 new ControlFlags defines for SAS IO Unit 190c1a71d1cSMoore, Eric Dean * Page 1. 191c1a71d1cSMoore, Eric Dean * Added MaxNumPhysicalMappedIDs field to SAS IO Unit 192c1a71d1cSMoore, Eric Dean * Page 2. 193c1a71d1cSMoore, Eric Dean * Added AccessStatus field to SAS Device Page 0 and added 194c1a71d1cSMoore, Eric Dean * new Flags bits for supported SATA features. 195c1a71d1cSMoore, Eric Dean * 12-07-04 01.05.04 Added config page structures for BIOS Page 2, RAID 196c1a71d1cSMoore, Eric Dean * Volume Page 1, and RAID Physical Disk Page 1. 197c1a71d1cSMoore, Eric Dean * Replaced IO Unit Page 1 BootTargetID,BootBus, and 198c1a71d1cSMoore, Eric Dean * BootAdapterNum with reserved field. 199c1a71d1cSMoore, Eric Dean * Added DataScrubRate and ResyncRate to RAID Volume 200c1a71d1cSMoore, Eric Dean * Page 0. 201c1a71d1cSMoore, Eric Dean * Added MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT 202c1a71d1cSMoore, Eric Dean * define. 203c1a71d1cSMoore, Eric Dean * 12-09-04 01.05.05 Added Target Mode Large CDB Enable to FC Port Page 1 204c1a71d1cSMoore, Eric Dean * Flags field. 205c1a71d1cSMoore, Eric Dean * Added Auto Port Config flag define for SAS IOUNIT 206c1a71d1cSMoore, Eric Dean * Page 1 ControlFlags. 207c1a71d1cSMoore, Eric Dean * Added Disabled bad Phy define to Expander Page 1 208c1a71d1cSMoore, Eric Dean * Discovery Info field. 209c1a71d1cSMoore, Eric Dean * Added SAS/SATA device support to SAS IOUnit Page 1 210c1a71d1cSMoore, Eric Dean * ControlFlags. 211c1a71d1cSMoore, Eric Dean * Added Unsupported device to SAS Dev Page 0 Flags field 212c1a71d1cSMoore, Eric Dean * Added disable use SATA Hash Address for SAS IOUNIT 213c1a71d1cSMoore, Eric Dean * page 1 in ControlFields. 214c1a71d1cSMoore, Eric Dean * 01-15-05 01.05.06 Added defaults for data scrub rate and resync rate to 215c1a71d1cSMoore, Eric Dean * Manufacturing Page 4. 216c1a71d1cSMoore, Eric Dean * Added new defines for BIOS Page 1 IOCSettings field. 217c1a71d1cSMoore, Eric Dean * Added ExtDiskIdentifier field to RAID Physical Disk 218c1a71d1cSMoore, Eric Dean * Page 0. 219c1a71d1cSMoore, Eric Dean * Added new defines for SAS IO Unit Page 1 ControlFlags 220c1a71d1cSMoore, Eric Dean * and to SAS Device Page 0 Flags to control SATA devices. 221c1a71d1cSMoore, Eric Dean * Added defines and structures for the new Log Page 0, a 222c1a71d1cSMoore, Eric Dean * new type of configuration page. 223c1a71d1cSMoore, Eric Dean * 02-09-05 01.05.07 Added InactiveStatus field to RAID Volume Page 0. 224c1a71d1cSMoore, Eric Dean * Added WWID field to RAID Volume Page 1. 225c1a71d1cSMoore, Eric Dean * Added PhysicalPort field to SAS Expander pages 0 and 1. 226c1a71d1cSMoore, Eric Dean * 03-11-05 01.05.08 Removed the EEDP flags from IOC Page 1. 227c1a71d1cSMoore, Eric Dean * Added Enclosure/Slot boot device format to BIOS Page 2. 228c1a71d1cSMoore, Eric Dean * New status value for RAID Volume Page 0 VolumeStatus 229c1a71d1cSMoore, Eric Dean * (VolumeState subfield). 230c1a71d1cSMoore, Eric Dean * New value for RAID Physical Page 0 InactiveStatus. 231c1a71d1cSMoore, Eric Dean * Added Inactive Volume Member flag RAID Physical Disk 232c1a71d1cSMoore, Eric Dean * Page 0 PhysDiskStatus field. 233c1a71d1cSMoore, Eric Dean * New physical mapping mode in SAS IO Unit Page 2. 234c1a71d1cSMoore, Eric Dean * Added CONFIG_PAGE_SAS_ENCLOSURE_0. 235c1a71d1cSMoore, Eric Dean * Added Slot and Enclosure fields to SAS Device Page 0. 236ccf3b7bdSChristoph Hellwig * 06-24-05 01.05.09 Added EEDP defines to IOC Page 1. 237ccf3b7bdSChristoph Hellwig * Added more RAID type defines to IOC Page 2. 238ccf3b7bdSChristoph Hellwig * Added Port Enable Delay settings to BIOS Page 1. 239ccf3b7bdSChristoph Hellwig * Added Bad Block Table Full define to RAID Volume Page 0. 240ccf3b7bdSChristoph Hellwig * Added Previous State defines to RAID Physical Disk 241ccf3b7bdSChristoph Hellwig * Page 0. 242ccf3b7bdSChristoph Hellwig * Added Max Sata Targets define for DiscoveryStatus field 243ccf3b7bdSChristoph Hellwig * of SAS IO Unit Page 0. 244ccf3b7bdSChristoph Hellwig * Added Device Self Test to Control Flags of SAS IO Unit 245ccf3b7bdSChristoph Hellwig * Page 1. 246ccf3b7bdSChristoph Hellwig * Added Direct Attach Starting Slot Number define for SAS 247ccf3b7bdSChristoph Hellwig * IO Unit Page 2. 248ccf3b7bdSChristoph Hellwig * Added new fields in SAS Device Page 2 for enclosure 249ccf3b7bdSChristoph Hellwig * mapping. 250ccf3b7bdSChristoph Hellwig * Added OwnerDevHandle and Flags field to SAS PHY Page 0. 251ccf3b7bdSChristoph Hellwig * Added IOC GPIO Flags define to SAS Enclosure Page 0. 252ccf3b7bdSChristoph Hellwig * Fixed the value for MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT. 2534b915a73SMoore, Eric * 08-03-05 01.05.10 Removed ISDataScrubRate and ISResyncRate from 2544b915a73SMoore, Eric * Manufacturing Page 4. 2554b915a73SMoore, Eric * Added MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE bit. 2564b915a73SMoore, Eric * Added NumDevsPerEnclosure field to SAS IO Unit page 2. 2574b915a73SMoore, Eric * Added MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP 2584b915a73SMoore, Eric * define. 2594b915a73SMoore, Eric * Added EnclosureHandle field to SAS Expander page 0. 2604b915a73SMoore, Eric * Removed redundant NumTableEntriesProg field from SAS 2614b915a73SMoore, Eric * Expander Page 1. 2624b915a73SMoore, Eric * 08-30-05 01.05.11 Added DeviceID for FC949E and changed the DeviceID for 2634b915a73SMoore, Eric * SAS1078. 2644b915a73SMoore, Eric * Added more defines for Manufacturing Page 4 Flags field. 2654b915a73SMoore, Eric * Added more defines for IOCSettings and added 2664b915a73SMoore, Eric * ExpanderSpinup field to Bios Page 1. 2674b915a73SMoore, Eric * Added postpone SATA Init bit to SAS IO Unit Page 1 2684b915a73SMoore, Eric * ControlFlags. 2694b915a73SMoore, Eric * Changed LogEntry format for Log Page 0. 2702076eb6aSEric Moore * 03-27-06 01.05.12 Added two new Flags defines for Manufacturing Page 4. 2712076eb6aSEric Moore * Added Manufacturing Page 7. 2722076eb6aSEric Moore * Added MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING. 2732076eb6aSEric Moore * Added IOC Page 6. 2742076eb6aSEric Moore * Added PrevBootDeviceForm field to CONFIG_PAGE_BIOS_2. 2752076eb6aSEric Moore * Added MaxLBAHigh field to RAID Volume Page 0. 2762076eb6aSEric Moore * Added Nvdata version fields to SAS IO Unit Page 0. 2772076eb6aSEric Moore * Added AdditionalControlFlags, MaxTargetPortConnectTime, 2782076eb6aSEric Moore * ReportDeviceMissingDelay, and IODeviceMissingDelay 2792076eb6aSEric Moore * fields to SAS IO Unit Page 1. 280eae225ebSEric Moore * 10-11-06 01.05.13 Added NumForceWWID field and ForceWWID array to 281eae225ebSEric Moore * Manufacturing Page 5. 282eae225ebSEric Moore * Added Manufacturing pages 8 through 10. 283eae225ebSEric Moore * Added defines for supported metadata size bits in 284eae225ebSEric Moore * CapabilitiesFlags field of IOC Page 6. 285eae225ebSEric Moore * Added defines for metadata size bits in VolumeSettings 286eae225ebSEric Moore * field of RAID Volume Page 0. 287eae225ebSEric Moore * Added SATA Link Reset settings, Enable SATA Asynchronous 288eae225ebSEric Moore * Notification bit, and HideNonZeroAttachedPhyIdentifiers 289eae225ebSEric Moore * bit to AdditionalControlFlags field of SAS IO Unit 290eae225ebSEric Moore * Page 1. 291eae225ebSEric Moore * Added defines for Enclosure Devices Unmapped and 292eae225ebSEric Moore * Device Limit Exceeded bits in Status field of SAS IO 293eae225ebSEric Moore * Unit Page 2. 294eae225ebSEric Moore * Added more AccessStatus values for SAS Device Page 0. 295eae225ebSEric Moore * Added bit for SATA Asynchronous Notification Support in 296eae225ebSEric Moore * Flags field of SAS Device Page 0. 297d16291b1SEric Moore * 02-28-07 01.05.14 Added ExtFlags field to Manufacturing Page 4. 298d16291b1SEric Moore * Added Disable SMART Polling for CapabilitiesFlags of 299d16291b1SEric Moore * IOC Page 6. 300d16291b1SEric Moore * Added Disable SMART Polling to DeviceSettings of BIOS 301d16291b1SEric Moore * Page 1. 302d16291b1SEric Moore * Added Multi-Port Domain bit for DiscoveryStatus field 303d16291b1SEric Moore * of SAS IO Unit Page. 304d16291b1SEric Moore * Added Multi-Port Domain Illegal flag for SAS IO Unit 305d16291b1SEric Moore * Page 1 AdditionalControlFlags field. 306d16291b1SEric Moore * 05-24-07 01.05.15 Added Hide Physical Disks with Non-Integrated RAID 307d16291b1SEric Moore * Metadata bit to Manufacturing Page 4 ExtFlags field. 308d16291b1SEric Moore * Added Internal Connector to End Device Present bit to 309d16291b1SEric Moore * Expander Page 0 Flags field. 310d16291b1SEric Moore * Fixed define for 311d16291b1SEric Moore * MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED. 312fd7a2533SKashyap, Desai * 08-07-07 01.05.16 Added MPI_IOCPAGE6_CAP_FLAGS_MULTIPORT_DRIVE_SUPPORT 313fd7a2533SKashyap, Desai * define. 314fd7a2533SKashyap, Desai * Added BIOS Page 4 structure. 315fd7a2533SKashyap, Desai * Added MPI_RAID_PHYS_DISK1_PATH_MAX define for RAID 316a927ec39SBjorn Helgaas * Physical Disk Page 1. 317fd7a2533SKashyap, Desai * 01-15-07 01.05.17 Added additional bit defines for ExtFlags field of 318fd7a2533SKashyap, Desai * Manufacturing Page 4. 319fd7a2533SKashyap, Desai * Added Solid State Drives Supported bit to IOC Page 6 320fd7a2533SKashyap, Desai * Capabilities Flags. 321fd7a2533SKashyap, Desai * Added new value for AccessStatus field of SAS Device 322fd7a2533SKashyap, Desai * Page 0 (_SATA_NEEDS_INITIALIZATION). 323fd7a2533SKashyap, Desai * 03-28-08 01.05.18 Defined new bits in Manufacturing Page 4 ExtFlags field 324fd7a2533SKashyap, Desai * to control coercion size and the mixing of SAS and SATA 325fd7a2533SKashyap, Desai * SSD drives. 3261da177e4SLinus Torvalds * -------------------------------------------------------------------------- 3271da177e4SLinus Torvalds */ 3281da177e4SLinus Torvalds 3291da177e4SLinus Torvalds #ifndef MPI_CNFG_H 3301da177e4SLinus Torvalds #define MPI_CNFG_H 3311da177e4SLinus Torvalds 3321da177e4SLinus Torvalds 3331da177e4SLinus Torvalds /***************************************************************************** 3341da177e4SLinus Torvalds * 3351da177e4SLinus Torvalds * C o n f i g M e s s a g e a n d S t r u c t u r e s 3361da177e4SLinus Torvalds * 3371da177e4SLinus Torvalds *****************************************************************************/ 3381da177e4SLinus Torvalds 3391da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_HEADER 3401da177e4SLinus Torvalds { 3411da177e4SLinus Torvalds U8 PageVersion; /* 00h */ 3421da177e4SLinus Torvalds U8 PageLength; /* 01h */ 3431da177e4SLinus Torvalds U8 PageNumber; /* 02h */ 3441da177e4SLinus Torvalds U8 PageType; /* 03h */ 345c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER, 3461da177e4SLinus Torvalds ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t; 3471da177e4SLinus Torvalds 3481da177e4SLinus Torvalds typedef union _CONFIG_PAGE_HEADER_UNION 3491da177e4SLinus Torvalds { 3501da177e4SLinus Torvalds ConfigPageHeader_t Struct; 3511da177e4SLinus Torvalds U8 Bytes[4]; 3521da177e4SLinus Torvalds U16 Word16[2]; 3531da177e4SLinus Torvalds U32 Word32; 3541da177e4SLinus Torvalds } ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion, 355c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION; 3561da177e4SLinus Torvalds 3571da177e4SLinus Torvalds typedef struct _CONFIG_EXTENDED_PAGE_HEADER 3581da177e4SLinus Torvalds { 3591da177e4SLinus Torvalds U8 PageVersion; /* 00h */ 3601da177e4SLinus Torvalds U8 Reserved1; /* 01h */ 3611da177e4SLinus Torvalds U8 PageNumber; /* 02h */ 3621da177e4SLinus Torvalds U8 PageType; /* 03h */ 3631da177e4SLinus Torvalds U16 ExtPageLength; /* 04h */ 3641da177e4SLinus Torvalds U8 ExtPageType; /* 06h */ 3651da177e4SLinus Torvalds U8 Reserved2; /* 07h */ 366c1a71d1cSMoore, Eric Dean } CONFIG_EXTENDED_PAGE_HEADER, MPI_POINTER PTR_CONFIG_EXTENDED_PAGE_HEADER, 3671da177e4SLinus Torvalds ConfigExtendedPageHeader_t, MPI_POINTER pConfigExtendedPageHeader_t; 3681da177e4SLinus Torvalds 3691da177e4SLinus Torvalds 3701da177e4SLinus Torvalds 3711da177e4SLinus Torvalds /**************************************************************************** 3721da177e4SLinus Torvalds * PageType field values 3731da177e4SLinus Torvalds ****************************************************************************/ 3741da177e4SLinus Torvalds #define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00) 3751da177e4SLinus Torvalds #define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10) 3761da177e4SLinus Torvalds #define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20) 3771da177e4SLinus Torvalds #define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30) 3781da177e4SLinus Torvalds #define MPI_CONFIG_PAGEATTR_MASK (0xF0) 3791da177e4SLinus Torvalds 3801da177e4SLinus Torvalds #define MPI_CONFIG_PAGETYPE_IO_UNIT (0x00) 3811da177e4SLinus Torvalds #define MPI_CONFIG_PAGETYPE_IOC (0x01) 3821da177e4SLinus Torvalds #define MPI_CONFIG_PAGETYPE_BIOS (0x02) 3831da177e4SLinus Torvalds #define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03) 3841da177e4SLinus Torvalds #define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04) 3851da177e4SLinus Torvalds #define MPI_CONFIG_PAGETYPE_FC_PORT (0x05) 3861da177e4SLinus Torvalds #define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06) 3871da177e4SLinus Torvalds #define MPI_CONFIG_PAGETYPE_LAN (0x07) 3881da177e4SLinus Torvalds #define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 3891da177e4SLinus Torvalds #define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09) 3901da177e4SLinus Torvalds #define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 3911da177e4SLinus Torvalds #define MPI_CONFIG_PAGETYPE_INBAND (0x0B) 3921da177e4SLinus Torvalds #define MPI_CONFIG_PAGETYPE_EXTENDED (0x0F) 3931da177e4SLinus Torvalds #define MPI_CONFIG_PAGETYPE_MASK (0x0F) 3941da177e4SLinus Torvalds 3951da177e4SLinus Torvalds #define MPI_CONFIG_TYPENUM_MASK (0x0FFF) 3961da177e4SLinus Torvalds 3971da177e4SLinus Torvalds 3981da177e4SLinus Torvalds /**************************************************************************** 3991da177e4SLinus Torvalds * ExtPageType field values 4001da177e4SLinus Torvalds ****************************************************************************/ 4011da177e4SLinus Torvalds #define MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 4021da177e4SLinus Torvalds #define MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 4031da177e4SLinus Torvalds #define MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 4041da177e4SLinus Torvalds #define MPI_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 405c1a71d1cSMoore, Eric Dean #define MPI_CONFIG_EXTPAGETYPE_LOG (0x14) 406c1a71d1cSMoore, Eric Dean #define MPI_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 4071da177e4SLinus Torvalds 4081da177e4SLinus Torvalds 4091da177e4SLinus Torvalds /**************************************************************************** 4101da177e4SLinus Torvalds * PageAddress field values 4111da177e4SLinus Torvalds ****************************************************************************/ 4121da177e4SLinus Torvalds #define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF) 4131da177e4SLinus Torvalds 414c1a71d1cSMoore, Eric Dean #define MPI_SCSI_DEVICE_FORM_MASK (0xF0000000) 415c1a71d1cSMoore, Eric Dean #define MPI_SCSI_DEVICE_FORM_BUS_TID (0x00000000) 4161da177e4SLinus Torvalds #define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF) 4171da177e4SLinus Torvalds #define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0) 4181da177e4SLinus Torvalds #define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00) 4191da177e4SLinus Torvalds #define MPI_SCSI_DEVICE_BUS_SHIFT (8) 420c1a71d1cSMoore, Eric Dean #define MPI_SCSI_DEVICE_FORM_TARGET_MODE (0x10000000) 421c1a71d1cSMoore, Eric Dean #define MPI_SCSI_DEVICE_TM_RESPOND_ID_MASK (0x000000FF) 422c1a71d1cSMoore, Eric Dean #define MPI_SCSI_DEVICE_TM_RESPOND_ID_SHIFT (0) 423c1a71d1cSMoore, Eric Dean #define MPI_SCSI_DEVICE_TM_BUS_MASK (0x0000FF00) 424c1a71d1cSMoore, Eric Dean #define MPI_SCSI_DEVICE_TM_BUS_SHIFT (8) 425c1a71d1cSMoore, Eric Dean #define MPI_SCSI_DEVICE_TM_INIT_ID_MASK (0x00FF0000) 426c1a71d1cSMoore, Eric Dean #define MPI_SCSI_DEVICE_TM_INIT_ID_SHIFT (16) 4271da177e4SLinus Torvalds 4281da177e4SLinus Torvalds #define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000) 4291da177e4SLinus Torvalds #define MPI_FC_PORT_PGAD_PORT_SHIFT (28) 4301da177e4SLinus Torvalds #define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000) 4311da177e4SLinus Torvalds #define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000) 4321da177e4SLinus Torvalds #define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF) 4331da177e4SLinus Torvalds #define MPI_FC_PORT_PGAD_INDEX_SHIFT (0) 4341da177e4SLinus Torvalds 4351da177e4SLinus Torvalds #define MPI_FC_DEVICE_PGAD_PORT_MASK (0xF0000000) 4361da177e4SLinus Torvalds #define MPI_FC_DEVICE_PGAD_PORT_SHIFT (28) 4371da177e4SLinus Torvalds #define MPI_FC_DEVICE_PGAD_FORM_MASK (0x0F000000) 4381da177e4SLinus Torvalds #define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID (0x00000000) 4391da177e4SLinus Torvalds #define MPI_FC_DEVICE_PGAD_ND_PORT_MASK (0xF0000000) 4401da177e4SLinus Torvalds #define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT (28) 4411da177e4SLinus Torvalds #define MPI_FC_DEVICE_PGAD_ND_DID_MASK (0x00FFFFFF) 4421da177e4SLinus Torvalds #define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT (0) 4431da177e4SLinus Torvalds #define MPI_FC_DEVICE_PGAD_FORM_BUS_TID (0x01000000) 4441da177e4SLinus Torvalds #define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00) 4451da177e4SLinus Torvalds #define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8) 4461da177e4SLinus Torvalds #define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF) 4471da177e4SLinus Torvalds #define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0) 4481da177e4SLinus Torvalds 4491da177e4SLinus Torvalds #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 4501da177e4SLinus Torvalds #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0) 4511da177e4SLinus Torvalds 452c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 453c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPAND_PGAD_FORM_SHIFT (28) 454c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 455c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x00000001) 456c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE (0x00000002) 457c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPAND_PGAD_GNH_MASK_HANDLE (0x0000FFFF) 458c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPAND_PGAD_GNH_SHIFT_HANDLE (0) 459c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPAND_PGAD_HPN_MASK_PHY (0x00FF0000) 460c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_PHY (16) 461c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPAND_PGAD_HPN_MASK_HANDLE (0x0000FFFF) 462c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_HANDLE (0) 463c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPAND_PGAD_H_MASK_HANDLE (0x0000FFFF) 464c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPAND_PGAD_H_SHIFT_HANDLE (0) 465c1a71d1cSMoore, Eric Dean 4661da177e4SLinus Torvalds #define MPI_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 4671da177e4SLinus Torvalds #define MPI_SAS_DEVICE_PGAD_FORM_SHIFT (28) 4681da177e4SLinus Torvalds #define MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 4691da177e4SLinus Torvalds #define MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID (0x00000001) 4701da177e4SLinus Torvalds #define MPI_SAS_DEVICE_PGAD_FORM_HANDLE (0x00000002) 4711da177e4SLinus Torvalds #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_MASK (0x0000FFFF) 4721da177e4SLinus Torvalds #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_SHIFT (0) 4731da177e4SLinus Torvalds #define MPI_SAS_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00) 4741da177e4SLinus Torvalds #define MPI_SAS_DEVICE_PGAD_BT_BUS_SHIFT (8) 4751da177e4SLinus Torvalds #define MPI_SAS_DEVICE_PGAD_BT_TID_MASK (0x000000FF) 4761da177e4SLinus Torvalds #define MPI_SAS_DEVICE_PGAD_BT_TID_SHIFT (0) 4771da177e4SLinus Torvalds #define MPI_SAS_DEVICE_PGAD_H_HANDLE_MASK (0x0000FFFF) 4781da177e4SLinus Torvalds #define MPI_SAS_DEVICE_PGAD_H_HANDLE_SHIFT (0) 4791da177e4SLinus Torvalds 480c1a71d1cSMoore, Eric Dean #define MPI_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 481c1a71d1cSMoore, Eric Dean #define MPI_SAS_PHY_PGAD_FORM_SHIFT (28) 482c1a71d1cSMoore, Eric Dean #define MPI_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x0) 483c1a71d1cSMoore, Eric Dean #define MPI_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x1) 484c1a71d1cSMoore, Eric Dean #define MPI_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 485c1a71d1cSMoore, Eric Dean #define MPI_SAS_PHY_PGAD_PHY_NUMBER_SHIFT (0) 486c1a71d1cSMoore, Eric Dean #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 487c1a71d1cSMoore, Eric Dean #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_SHIFT (0) 488c1a71d1cSMoore, Eric Dean 489c1a71d1cSMoore, Eric Dean #define MPI_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 490c1a71d1cSMoore, Eric Dean #define MPI_SAS_ENCLOS_PGAD_FORM_SHIFT (28) 491c1a71d1cSMoore, Eric Dean #define MPI_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 492c1a71d1cSMoore, Eric Dean #define MPI_SAS_ENCLOS_PGAD_FORM_HANDLE (0x00000001) 493c1a71d1cSMoore, Eric Dean #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_MASK (0x0000FFFF) 494c1a71d1cSMoore, Eric Dean #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_SHIFT (0) 495c1a71d1cSMoore, Eric Dean #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_MASK (0x0000FFFF) 496c1a71d1cSMoore, Eric Dean #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_SHIFT (0) 497c1a71d1cSMoore, Eric Dean 4981da177e4SLinus Torvalds 4991da177e4SLinus Torvalds 5001da177e4SLinus Torvalds /**************************************************************************** 5011da177e4SLinus Torvalds * Config Request Message 5021da177e4SLinus Torvalds ****************************************************************************/ 5031da177e4SLinus Torvalds typedef struct _MSG_CONFIG 5041da177e4SLinus Torvalds { 5051da177e4SLinus Torvalds U8 Action; /* 00h */ 5061da177e4SLinus Torvalds U8 Reserved; /* 01h */ 5071da177e4SLinus Torvalds U8 ChainOffset; /* 02h */ 5081da177e4SLinus Torvalds U8 Function; /* 03h */ 5091da177e4SLinus Torvalds U16 ExtPageLength; /* 04h */ 5101da177e4SLinus Torvalds U8 ExtPageType; /* 06h */ 5111da177e4SLinus Torvalds U8 MsgFlags; /* 07h */ 5121da177e4SLinus Torvalds U32 MsgContext; /* 08h */ 5131da177e4SLinus Torvalds U8 Reserved2[8]; /* 0Ch */ 514c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 14h */ 5151da177e4SLinus Torvalds U32 PageAddress; /* 18h */ 5161da177e4SLinus Torvalds SGE_IO_UNION PageBufferSGE; /* 1Ch */ 5171da177e4SLinus Torvalds } MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG, 5181da177e4SLinus Torvalds Config_t, MPI_POINTER pConfig_t; 5191da177e4SLinus Torvalds 5201da177e4SLinus Torvalds 5211da177e4SLinus Torvalds /**************************************************************************** 5221da177e4SLinus Torvalds * Action field values 5231da177e4SLinus Torvalds ****************************************************************************/ 5241da177e4SLinus Torvalds #define MPI_CONFIG_ACTION_PAGE_HEADER (0x00) 5251da177e4SLinus Torvalds #define MPI_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 5261da177e4SLinus Torvalds #define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 5271da177e4SLinus Torvalds #define MPI_CONFIG_ACTION_PAGE_DEFAULT (0x03) 5281da177e4SLinus Torvalds #define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 5291da177e4SLinus Torvalds #define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 5301da177e4SLinus Torvalds #define MPI_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 5311da177e4SLinus Torvalds 5321da177e4SLinus Torvalds 5331da177e4SLinus Torvalds /* Config Reply Message */ 5341da177e4SLinus Torvalds typedef struct _MSG_CONFIG_REPLY 5351da177e4SLinus Torvalds { 5361da177e4SLinus Torvalds U8 Action; /* 00h */ 5371da177e4SLinus Torvalds U8 Reserved; /* 01h */ 5381da177e4SLinus Torvalds U8 MsgLength; /* 02h */ 5391da177e4SLinus Torvalds U8 Function; /* 03h */ 5401da177e4SLinus Torvalds U16 ExtPageLength; /* 04h */ 5411da177e4SLinus Torvalds U8 ExtPageType; /* 06h */ 5421da177e4SLinus Torvalds U8 MsgFlags; /* 07h */ 5431da177e4SLinus Torvalds U32 MsgContext; /* 08h */ 5441da177e4SLinus Torvalds U8 Reserved2[2]; /* 0Ch */ 5451da177e4SLinus Torvalds U16 IOCStatus; /* 0Eh */ 5461da177e4SLinus Torvalds U32 IOCLogInfo; /* 10h */ 547c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 14h */ 5481da177e4SLinus Torvalds } MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY, 5491da177e4SLinus Torvalds ConfigReply_t, MPI_POINTER pConfigReply_t; 5501da177e4SLinus Torvalds 5511da177e4SLinus Torvalds 5521da177e4SLinus Torvalds 5531da177e4SLinus Torvalds /***************************************************************************** 5541da177e4SLinus Torvalds * 5551da177e4SLinus Torvalds * C o n f i g u r a t i o n P a g e s 5561da177e4SLinus Torvalds * 5571da177e4SLinus Torvalds *****************************************************************************/ 5581da177e4SLinus Torvalds 5591da177e4SLinus Torvalds /**************************************************************************** 5601da177e4SLinus Torvalds * Manufacturing Config pages 5611da177e4SLinus Torvalds ****************************************************************************/ 5621da177e4SLinus Torvalds #define MPI_MANUFACTPAGE_VENDORID_LSILOGIC (0x1000) 5631da177e4SLinus Torvalds /* Fibre Channel */ 5641da177e4SLinus Torvalds #define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621) 5651da177e4SLinus Torvalds #define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624) 5661da177e4SLinus Torvalds #define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622) 5671da177e4SLinus Torvalds #define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628) 5681da177e4SLinus Torvalds #define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626) 569c1a71d1cSMoore, Eric Dean #define MPI_MANUFACTPAGE_DEVICEID_FC939X (0x0642) 570c1a71d1cSMoore, Eric Dean #define MPI_MANUFACTPAGE_DEVICEID_FC949X (0x0640) 5714b915a73SMoore, Eric #define MPI_MANUFACTPAGE_DEVICEID_FC949E (0x0646) 5721da177e4SLinus Torvalds /* SCSI */ 5731da177e4SLinus Torvalds #define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030) 5741da177e4SLinus Torvalds #define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031) 5751da177e4SLinus Torvalds #define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032) 5761da177e4SLinus Torvalds #define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033) 5771da177e4SLinus Torvalds #define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040) 5781da177e4SLinus Torvalds #define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041) 5791da177e4SLinus Torvalds /* SAS */ 5801da177e4SLinus Torvalds #define MPI_MANUFACTPAGE_DEVID_SAS1064 (0x0050) 581c1a71d1cSMoore, Eric Dean #define MPI_MANUFACTPAGE_DEVID_SAS1064A (0x005C) 582c1a71d1cSMoore, Eric Dean #define MPI_MANUFACTPAGE_DEVID_SAS1064E (0x0056) 583c1a71d1cSMoore, Eric Dean #define MPI_MANUFACTPAGE_DEVID_SAS1066 (0x005E) 584c1a71d1cSMoore, Eric Dean #define MPI_MANUFACTPAGE_DEVID_SAS1066E (0x005A) 585c1a71d1cSMoore, Eric Dean #define MPI_MANUFACTPAGE_DEVID_SAS1068 (0x0054) 586c1a71d1cSMoore, Eric Dean #define MPI_MANUFACTPAGE_DEVID_SAS1068E (0x0058) 58785d37226SChandrakala Chavva #define MPI_MANUFACTPAGE_DEVID_SAS1068_820XELP (0x0059) 5884b915a73SMoore, Eric #define MPI_MANUFACTPAGE_DEVID_SAS1078 (0x0062) 5891da177e4SLinus Torvalds 5901da177e4SLinus Torvalds 5911da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_MANUFACTURING_0 5921da177e4SLinus Torvalds { 593c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 5941da177e4SLinus Torvalds U8 ChipName[16]; /* 04h */ 5951da177e4SLinus Torvalds U8 ChipRevision[8]; /* 14h */ 5961da177e4SLinus Torvalds U8 BoardName[16]; /* 1Ch */ 5971da177e4SLinus Torvalds U8 BoardAssembly[16]; /* 2Ch */ 5981da177e4SLinus Torvalds U8 BoardTracerNumber[16]; /* 3Ch */ 5991da177e4SLinus Torvalds 600c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0, 6011da177e4SLinus Torvalds ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t; 6021da177e4SLinus Torvalds 6031da177e4SLinus Torvalds #define MPI_MANUFACTURING0_PAGEVERSION (0x00) 6041da177e4SLinus Torvalds 6051da177e4SLinus Torvalds 6061da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_MANUFACTURING_1 6071da177e4SLinus Torvalds { 608c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 6091da177e4SLinus Torvalds U8 VPD[256]; /* 04h */ 610c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1, 6111da177e4SLinus Torvalds ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t; 6121da177e4SLinus Torvalds 6131da177e4SLinus Torvalds #define MPI_MANUFACTURING1_PAGEVERSION (0x00) 6141da177e4SLinus Torvalds 6151da177e4SLinus Torvalds 6161da177e4SLinus Torvalds typedef struct _MPI_CHIP_REVISION_ID 6171da177e4SLinus Torvalds { 6181da177e4SLinus Torvalds U16 DeviceID; /* 00h */ 6191da177e4SLinus Torvalds U8 PCIRevisionID; /* 02h */ 6201da177e4SLinus Torvalds U8 Reserved; /* 03h */ 6211da177e4SLinus Torvalds } MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID, 6221da177e4SLinus Torvalds MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t; 6231da177e4SLinus Torvalds 6241da177e4SLinus Torvalds 6251da177e4SLinus Torvalds /* 6261da177e4SLinus Torvalds * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 6271da177e4SLinus Torvalds * one and check Header.PageLength at runtime. 6281da177e4SLinus Torvalds */ 6291da177e4SLinus Torvalds #ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS 6301da177e4SLinus Torvalds #define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 6311da177e4SLinus Torvalds #endif 6321da177e4SLinus Torvalds 6331da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_MANUFACTURING_2 6341da177e4SLinus Torvalds { 635c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 6361da177e4SLinus Torvalds MPI_CHIP_REVISION_ID ChipId; /* 04h */ 6371da177e4SLinus Torvalds U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */ 638c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2, 6391da177e4SLinus Torvalds ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t; 6401da177e4SLinus Torvalds 6411da177e4SLinus Torvalds #define MPI_MANUFACTURING2_PAGEVERSION (0x00) 6421da177e4SLinus Torvalds 6431da177e4SLinus Torvalds 6441da177e4SLinus Torvalds /* 6451da177e4SLinus Torvalds * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 6461da177e4SLinus Torvalds * one and check Header.PageLength at runtime. 6471da177e4SLinus Torvalds */ 6481da177e4SLinus Torvalds #ifndef MPI_MAN_PAGE_3_INFO_WORDS 6491da177e4SLinus Torvalds #define MPI_MAN_PAGE_3_INFO_WORDS (1) 6501da177e4SLinus Torvalds #endif 6511da177e4SLinus Torvalds 6521da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_MANUFACTURING_3 6531da177e4SLinus Torvalds { 654c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 6551da177e4SLinus Torvalds MPI_CHIP_REVISION_ID ChipId; /* 04h */ 6561da177e4SLinus Torvalds U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */ 657c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3, 6581da177e4SLinus Torvalds ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t; 6591da177e4SLinus Torvalds 6601da177e4SLinus Torvalds #define MPI_MANUFACTURING3_PAGEVERSION (0x00) 6611da177e4SLinus Torvalds 6621da177e4SLinus Torvalds 6631da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_MANUFACTURING_4 6641da177e4SLinus Torvalds { 665c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 6661da177e4SLinus Torvalds U32 Reserved1; /* 04h */ 6671da177e4SLinus Torvalds U8 InfoOffset0; /* 08h */ 6681da177e4SLinus Torvalds U8 InfoSize0; /* 09h */ 6691da177e4SLinus Torvalds U8 InfoOffset1; /* 0Ah */ 6701da177e4SLinus Torvalds U8 InfoSize1; /* 0Bh */ 6711da177e4SLinus Torvalds U8 InquirySize; /* 0Ch */ 6721da177e4SLinus Torvalds U8 Flags; /* 0Dh */ 673d16291b1SEric Moore U16 ExtFlags; /* 0Eh */ 6741da177e4SLinus Torvalds U8 InquiryData[56]; /* 10h */ 6751da177e4SLinus Torvalds U32 ISVolumeSettings; /* 48h */ 6761da177e4SLinus Torvalds U32 IMEVolumeSettings; /* 4Ch */ 6771da177e4SLinus Torvalds U32 IMVolumeSettings; /* 50h */ 678c1a71d1cSMoore, Eric Dean U32 Reserved3; /* 54h */ 679c1a71d1cSMoore, Eric Dean U32 Reserved4; /* 58h */ 6804b915a73SMoore, Eric U32 Reserved5; /* 5Ch */ 681c1a71d1cSMoore, Eric Dean U8 IMEDataScrubRate; /* 60h */ 682c1a71d1cSMoore, Eric Dean U8 IMEResyncRate; /* 61h */ 683c1a71d1cSMoore, Eric Dean U16 Reserved6; /* 62h */ 684c1a71d1cSMoore, Eric Dean U8 IMDataScrubRate; /* 64h */ 685c1a71d1cSMoore, Eric Dean U8 IMResyncRate; /* 65h */ 686c1a71d1cSMoore, Eric Dean U16 Reserved7; /* 66h */ 687c1a71d1cSMoore, Eric Dean U32 Reserved8; /* 68h */ 688c1a71d1cSMoore, Eric Dean U32 Reserved9; /* 6Ch */ 689c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4, 6901da177e4SLinus Torvalds ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t; 6911da177e4SLinus Torvalds 692d16291b1SEric Moore #define MPI_MANUFACTURING4_PAGEVERSION (0x05) 6931da177e4SLinus Torvalds 6941da177e4SLinus Torvalds /* defines for the Flags field */ 6952076eb6aSEric Moore #define MPI_MANPAGE4_FORCE_BAD_BLOCK_TABLE (0x80) 6962076eb6aSEric Moore #define MPI_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x40) 6974b915a73SMoore, Eric #define MPI_MANPAGE4_IME_DISABLE (0x20) 6984b915a73SMoore, Eric #define MPI_MANPAGE4_IM_DISABLE (0x10) 6994b915a73SMoore, Eric #define MPI_MANPAGE4_IS_DISABLE (0x08) 7004b915a73SMoore, Eric #define MPI_MANPAGE4_IR_MODEPAGE8_DISABLE (0x04) 7014b915a73SMoore, Eric #define MPI_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x02) 7021da177e4SLinus Torvalds #define MPI_MANPAGE4_IR_NO_MIX_SAS_SATA (0x01) 7031da177e4SLinus Torvalds 704d16291b1SEric Moore /* defines for the ExtFlags field */ 705fd7a2533SKashyap, Desai #define MPI_MANPAGE4_EXTFLAGS_MASK_COERCION_SIZE (0x0180) 706fd7a2533SKashyap, Desai #define MPI_MANPAGE4_EXTFLAGS_SHIFT_COERCION_SIZE (7) 707fd7a2533SKashyap, Desai #define MPI_MANPAGE4_EXTFLAGS_1GB_COERCION_SIZE (0) 708fd7a2533SKashyap, Desai #define MPI_MANPAGE4_EXTFLAGS_128MB_COERCION_SIZE (1) 709fd7a2533SKashyap, Desai 710fd7a2533SKashyap, Desai #define MPI_MANPAGE4_EXTFLAGS_NO_MIX_SSD_SAS_SATA (0x0040) 711fd7a2533SKashyap, Desai #define MPI_MANPAGE4_EXTFLAGS_MIX_SSD_AND_NON_SSD (0x0020) 712fd7a2533SKashyap, Desai #define MPI_MANPAGE4_EXTFLAGS_DUAL_PORT_SUPPORT (0x0010) 713d16291b1SEric Moore #define MPI_MANPAGE4_EXTFLAGS_HIDE_NON_IR_METADATA (0x0008) 714d16291b1SEric Moore #define MPI_MANPAGE4_EXTFLAGS_SAS_CACHE_DISABLE (0x0004) 715d16291b1SEric Moore #define MPI_MANPAGE4_EXTFLAGS_SATA_CACHE_DISABLE (0x0002) 716d16291b1SEric Moore #define MPI_MANPAGE4_EXTFLAGS_LEGACY_MODE (0x0001) 717d16291b1SEric Moore 7181da177e4SLinus Torvalds 719eae225ebSEric Moore #ifndef MPI_MANPAGE5_NUM_FORCEWWID 720eae225ebSEric Moore #define MPI_MANPAGE5_NUM_FORCEWWID (1) 721eae225ebSEric Moore #endif 722eae225ebSEric Moore 7231da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_MANUFACTURING_5 7241da177e4SLinus Torvalds { 725c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 7261da177e4SLinus Torvalds U64 BaseWWID; /* 04h */ 727c1a71d1cSMoore, Eric Dean U8 Flags; /* 0Ch */ 728eae225ebSEric Moore U8 NumForceWWID; /* 0Dh */ 729c1a71d1cSMoore, Eric Dean U16 Reserved2; /* 0Eh */ 730eae225ebSEric Moore U32 Reserved3; /* 10h */ 731eae225ebSEric Moore U32 Reserved4; /* 14h */ 732eae225ebSEric Moore U64 ForceWWID[MPI_MANPAGE5_NUM_FORCEWWID]; /* 18h */ 733c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_MANUFACTURING_5, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_5, 7341da177e4SLinus Torvalds ManufacturingPage5_t, MPI_POINTER pManufacturingPage5_t; 7351da177e4SLinus Torvalds 736eae225ebSEric Moore #define MPI_MANUFACTURING5_PAGEVERSION (0x02) 737c1a71d1cSMoore, Eric Dean 738c1a71d1cSMoore, Eric Dean /* defines for the Flags field */ 739c1a71d1cSMoore, Eric Dean #define MPI_MANPAGE5_TWO_WWID_PER_PHY (0x01) 7401da177e4SLinus Torvalds 7411da177e4SLinus Torvalds 7421da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_MANUFACTURING_6 7431da177e4SLinus Torvalds { 744c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 7451da177e4SLinus Torvalds U32 ProductSpecificInfo;/* 04h */ 746c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_MANUFACTURING_6, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_6, 7471da177e4SLinus Torvalds ManufacturingPage6_t, MPI_POINTER pManufacturingPage6_t; 7481da177e4SLinus Torvalds 7491da177e4SLinus Torvalds #define MPI_MANUFACTURING6_PAGEVERSION (0x00) 7501da177e4SLinus Torvalds 7511da177e4SLinus Torvalds 7522076eb6aSEric Moore typedef struct _MPI_MANPAGE7_CONNECTOR_INFO 7532076eb6aSEric Moore { 7542076eb6aSEric Moore U32 Pinout; /* 00h */ 7552076eb6aSEric Moore U8 Connector[16]; /* 04h */ 7562076eb6aSEric Moore U8 Location; /* 14h */ 7572076eb6aSEric Moore U8 Reserved1; /* 15h */ 7582076eb6aSEric Moore U16 Slot; /* 16h */ 7592076eb6aSEric Moore U32 Reserved2; /* 18h */ 7602076eb6aSEric Moore } MPI_MANPAGE7_CONNECTOR_INFO, MPI_POINTER PTR_MPI_MANPAGE7_CONNECTOR_INFO, 7612076eb6aSEric Moore MpiManPage7ConnectorInfo_t, MPI_POINTER pMpiManPage7ConnectorInfo_t; 7622076eb6aSEric Moore 7632076eb6aSEric Moore /* defines for the Pinout field */ 7642076eb6aSEric Moore #define MPI_MANPAGE7_PINOUT_SFF_8484_L4 (0x00080000) 7652076eb6aSEric Moore #define MPI_MANPAGE7_PINOUT_SFF_8484_L3 (0x00040000) 7662076eb6aSEric Moore #define MPI_MANPAGE7_PINOUT_SFF_8484_L2 (0x00020000) 7672076eb6aSEric Moore #define MPI_MANPAGE7_PINOUT_SFF_8484_L1 (0x00010000) 7682076eb6aSEric Moore #define MPI_MANPAGE7_PINOUT_SFF_8470_L4 (0x00000800) 7692076eb6aSEric Moore #define MPI_MANPAGE7_PINOUT_SFF_8470_L3 (0x00000400) 7702076eb6aSEric Moore #define MPI_MANPAGE7_PINOUT_SFF_8470_L2 (0x00000200) 7712076eb6aSEric Moore #define MPI_MANPAGE7_PINOUT_SFF_8470_L1 (0x00000100) 7722076eb6aSEric Moore #define MPI_MANPAGE7_PINOUT_SFF_8482 (0x00000002) 7732076eb6aSEric Moore #define MPI_MANPAGE7_PINOUT_CONNECTION_UNKNOWN (0x00000001) 7742076eb6aSEric Moore 7752076eb6aSEric Moore /* defines for the Location field */ 7762076eb6aSEric Moore #define MPI_MANPAGE7_LOCATION_UNKNOWN (0x01) 7772076eb6aSEric Moore #define MPI_MANPAGE7_LOCATION_INTERNAL (0x02) 7782076eb6aSEric Moore #define MPI_MANPAGE7_LOCATION_EXTERNAL (0x04) 7792076eb6aSEric Moore #define MPI_MANPAGE7_LOCATION_SWITCHABLE (0x08) 7802076eb6aSEric Moore #define MPI_MANPAGE7_LOCATION_AUTO (0x10) 7812076eb6aSEric Moore #define MPI_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 7822076eb6aSEric Moore #define MPI_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 7832076eb6aSEric Moore 7842076eb6aSEric Moore /* 7852076eb6aSEric Moore * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 7862076eb6aSEric Moore * one and check NumPhys at runtime. 7872076eb6aSEric Moore */ 7882076eb6aSEric Moore #ifndef MPI_MANPAGE7_CONNECTOR_INFO_MAX 7892076eb6aSEric Moore #define MPI_MANPAGE7_CONNECTOR_INFO_MAX (1) 7902076eb6aSEric Moore #endif 7912076eb6aSEric Moore 7922076eb6aSEric Moore typedef struct _CONFIG_PAGE_MANUFACTURING_7 7932076eb6aSEric Moore { 7942076eb6aSEric Moore CONFIG_PAGE_HEADER Header; /* 00h */ 7952076eb6aSEric Moore U32 Reserved1; /* 04h */ 7962076eb6aSEric Moore U32 Reserved2; /* 08h */ 7972076eb6aSEric Moore U32 Flags; /* 0Ch */ 7982076eb6aSEric Moore U8 EnclosureName[16]; /* 10h */ 7992076eb6aSEric Moore U8 NumPhys; /* 20h */ 8002076eb6aSEric Moore U8 Reserved3; /* 21h */ 8012076eb6aSEric Moore U16 Reserved4; /* 22h */ 8022076eb6aSEric Moore MPI_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI_MANPAGE7_CONNECTOR_INFO_MAX]; /* 24h */ 8032076eb6aSEric Moore } CONFIG_PAGE_MANUFACTURING_7, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_7, 8042076eb6aSEric Moore ManufacturingPage7_t, MPI_POINTER pManufacturingPage7_t; 8052076eb6aSEric Moore 8062076eb6aSEric Moore #define MPI_MANUFACTURING7_PAGEVERSION (0x00) 8072076eb6aSEric Moore 8082076eb6aSEric Moore /* defines for the Flags field */ 8092076eb6aSEric Moore #define MPI_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 8102076eb6aSEric Moore 8112076eb6aSEric Moore 812eae225ebSEric Moore typedef struct _CONFIG_PAGE_MANUFACTURING_8 813eae225ebSEric Moore { 814eae225ebSEric Moore CONFIG_PAGE_HEADER Header; /* 00h */ 815eae225ebSEric Moore U32 ProductSpecificInfo;/* 04h */ 816eae225ebSEric Moore } CONFIG_PAGE_MANUFACTURING_8, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_8, 817eae225ebSEric Moore ManufacturingPage8_t, MPI_POINTER pManufacturingPage8_t; 818eae225ebSEric Moore 819eae225ebSEric Moore #define MPI_MANUFACTURING8_PAGEVERSION (0x00) 820eae225ebSEric Moore 821eae225ebSEric Moore 822eae225ebSEric Moore typedef struct _CONFIG_PAGE_MANUFACTURING_9 823eae225ebSEric Moore { 824eae225ebSEric Moore CONFIG_PAGE_HEADER Header; /* 00h */ 825eae225ebSEric Moore U32 ProductSpecificInfo;/* 04h */ 826eae225ebSEric Moore } CONFIG_PAGE_MANUFACTURING_9, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_9, 827eae225ebSEric Moore ManufacturingPage9_t, MPI_POINTER pManufacturingPage9_t; 828eae225ebSEric Moore 829d16291b1SEric Moore #define MPI_MANUFACTURING9_PAGEVERSION (0x00) 830eae225ebSEric Moore 831eae225ebSEric Moore 832eae225ebSEric Moore typedef struct _CONFIG_PAGE_MANUFACTURING_10 833eae225ebSEric Moore { 834eae225ebSEric Moore CONFIG_PAGE_HEADER Header; /* 00h */ 835eae225ebSEric Moore U32 ProductSpecificInfo;/* 04h */ 836eae225ebSEric Moore } CONFIG_PAGE_MANUFACTURING_10, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_10, 837eae225ebSEric Moore ManufacturingPage10_t, MPI_POINTER pManufacturingPage10_t; 838eae225ebSEric Moore 839eae225ebSEric Moore #define MPI_MANUFACTURING10_PAGEVERSION (0x00) 840eae225ebSEric Moore 841eae225ebSEric Moore 8421da177e4SLinus Torvalds /**************************************************************************** 8431da177e4SLinus Torvalds * IO Unit Config Pages 8441da177e4SLinus Torvalds ****************************************************************************/ 8451da177e4SLinus Torvalds 8461da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_IO_UNIT_0 8471da177e4SLinus Torvalds { 848c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 8491da177e4SLinus Torvalds U64 UniqueValue; /* 04h */ 850c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0, 8511da177e4SLinus Torvalds IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t; 8521da177e4SLinus Torvalds 8531da177e4SLinus Torvalds #define MPI_IOUNITPAGE0_PAGEVERSION (0x00) 8541da177e4SLinus Torvalds 8551da177e4SLinus Torvalds 8561da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_IO_UNIT_1 8571da177e4SLinus Torvalds { 858c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 8591da177e4SLinus Torvalds U32 Flags; /* 04h */ 860c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1, 8611da177e4SLinus Torvalds IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t; 8621da177e4SLinus Torvalds 8634b915a73SMoore, Eric #define MPI_IOUNITPAGE1_PAGEVERSION (0x02) 8641da177e4SLinus Torvalds 8651da177e4SLinus Torvalds /* IO Unit Page 1 Flags defines */ 8661da177e4SLinus Torvalds #define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000) 8671da177e4SLinus Torvalds #define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001) 8681da177e4SLinus Torvalds #define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002) 8691da177e4SLinus Torvalds #define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000) 8701da177e4SLinus Torvalds #define MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 8711da177e4SLinus Torvalds #define MPI_IOUNITPAGE1_DISABLE_QUEUE_FULL_HANDLING (0x00000020) 8721da177e4SLinus Torvalds #define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040) 8731da177e4SLinus Torvalds #define MPI_IOUNITPAGE1_FORCE_32 (0x00000080) 8741da177e4SLinus Torvalds #define MPI_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 8754b915a73SMoore, Eric #define MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE (0x00000200) 8761da177e4SLinus Torvalds 8771da177e4SLinus Torvalds typedef struct _MPI_ADAPTER_INFO 8781da177e4SLinus Torvalds { 8791da177e4SLinus Torvalds U8 PciBusNumber; /* 00h */ 8801da177e4SLinus Torvalds U8 PciDeviceAndFunctionNumber; /* 01h */ 8811da177e4SLinus Torvalds U16 AdapterFlags; /* 02h */ 8821da177e4SLinus Torvalds } MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO, 8831da177e4SLinus Torvalds MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t; 8841da177e4SLinus Torvalds 8851da177e4SLinus Torvalds #define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 8861da177e4SLinus Torvalds #define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 8871da177e4SLinus Torvalds 8881da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_IO_UNIT_2 8891da177e4SLinus Torvalds { 890c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 8911da177e4SLinus Torvalds U32 Flags; /* 04h */ 8921da177e4SLinus Torvalds U32 BiosVersion; /* 08h */ 8931da177e4SLinus Torvalds MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */ 894c1a71d1cSMoore, Eric Dean U32 Reserved1; /* 1Ch */ 895c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2, 8961da177e4SLinus Torvalds IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t; 8971da177e4SLinus Torvalds 898c1a71d1cSMoore, Eric Dean #define MPI_IOUNITPAGE2_PAGEVERSION (0x02) 8991da177e4SLinus Torvalds 9001da177e4SLinus Torvalds #define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002) 9011da177e4SLinus Torvalds #define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004) 9021da177e4SLinus Torvalds #define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008) 9031da177e4SLinus Torvalds #define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010) 9041da177e4SLinus Torvalds 9051da177e4SLinus Torvalds #define MPI_IOUNITPAGE2_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 9061da177e4SLinus Torvalds #define MPI_IOUNITPAGE2_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 9071da177e4SLinus Torvalds #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DISPLAY (0x00000020) 9081da177e4SLinus Torvalds #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 9091da177e4SLinus Torvalds 9101da177e4SLinus Torvalds 9111da177e4SLinus Torvalds /* 9121da177e4SLinus Torvalds * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 9131da177e4SLinus Torvalds * one and check Header.PageLength at runtime. 9141da177e4SLinus Torvalds */ 9151da177e4SLinus Torvalds #ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX 9161da177e4SLinus Torvalds #define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 9171da177e4SLinus Torvalds #endif 9181da177e4SLinus Torvalds 9191da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_IO_UNIT_3 9201da177e4SLinus Torvalds { 921c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 9221da177e4SLinus Torvalds U8 GPIOCount; /* 04h */ 9231da177e4SLinus Torvalds U8 Reserved1; /* 05h */ 9241da177e4SLinus Torvalds U16 Reserved2; /* 06h */ 9251da177e4SLinus Torvalds U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */ 926c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3, 9271da177e4SLinus Torvalds IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t; 9281da177e4SLinus Torvalds 9291da177e4SLinus Torvalds #define MPI_IOUNITPAGE3_PAGEVERSION (0x01) 9301da177e4SLinus Torvalds 9311da177e4SLinus Torvalds #define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC) 9321da177e4SLinus Torvalds #define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 9331da177e4SLinus Torvalds #define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00) 9341da177e4SLinus Torvalds #define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01) 9351da177e4SLinus Torvalds 9361da177e4SLinus Torvalds 937c1a71d1cSMoore, Eric Dean typedef struct _CONFIG_PAGE_IO_UNIT_4 938c1a71d1cSMoore, Eric Dean { 939c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 940c1a71d1cSMoore, Eric Dean U32 Reserved1; /* 04h */ 941c1a71d1cSMoore, Eric Dean SGE_SIMPLE_UNION FWImageSGE; /* 08h */ 942c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_IO_UNIT_4, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_4, 943c1a71d1cSMoore, Eric Dean IOUnitPage4_t, MPI_POINTER pIOUnitPage4_t; 944c1a71d1cSMoore, Eric Dean 945c1a71d1cSMoore, Eric Dean #define MPI_IOUNITPAGE4_PAGEVERSION (0x00) 946c1a71d1cSMoore, Eric Dean 947c1a71d1cSMoore, Eric Dean 9481da177e4SLinus Torvalds /**************************************************************************** 9491da177e4SLinus Torvalds * IOC Config Pages 9501da177e4SLinus Torvalds ****************************************************************************/ 9511da177e4SLinus Torvalds 9521da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_IOC_0 9531da177e4SLinus Torvalds { 954c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 9551da177e4SLinus Torvalds U32 TotalNVStore; /* 04h */ 9561da177e4SLinus Torvalds U32 FreeNVStore; /* 08h */ 9571da177e4SLinus Torvalds U16 VendorID; /* 0Ch */ 9581da177e4SLinus Torvalds U16 DeviceID; /* 0Eh */ 9591da177e4SLinus Torvalds U8 RevisionID; /* 10h */ 9601da177e4SLinus Torvalds U8 Reserved[3]; /* 11h */ 9611da177e4SLinus Torvalds U32 ClassCode; /* 14h */ 9621da177e4SLinus Torvalds U16 SubsystemVendorID; /* 18h */ 9631da177e4SLinus Torvalds U16 SubsystemID; /* 1Ah */ 964c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0, 9651da177e4SLinus Torvalds IOCPage0_t, MPI_POINTER pIOCPage0_t; 9661da177e4SLinus Torvalds 9671da177e4SLinus Torvalds #define MPI_IOCPAGE0_PAGEVERSION (0x01) 9681da177e4SLinus Torvalds 9691da177e4SLinus Torvalds 9701da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_IOC_1 9711da177e4SLinus Torvalds { 972c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 9731da177e4SLinus Torvalds U32 Flags; /* 04h */ 9741da177e4SLinus Torvalds U32 CoalescingTimeout; /* 08h */ 9751da177e4SLinus Torvalds U8 CoalescingDepth; /* 0Ch */ 9761da177e4SLinus Torvalds U8 PCISlotNum; /* 0Dh */ 9771da177e4SLinus Torvalds U8 Reserved[2]; /* 0Eh */ 978c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1, 9791da177e4SLinus Torvalds IOCPage1_t, MPI_POINTER pIOCPage1_t; 9801da177e4SLinus Torvalds 981ccf3b7bdSChristoph Hellwig #define MPI_IOCPAGE1_PAGEVERSION (0x03) 9821da177e4SLinus Torvalds 9831da177e4SLinus Torvalds /* defines for the Flags field */ 984ccf3b7bdSChristoph Hellwig #define MPI_IOCPAGE1_EEDP_MODE_MASK (0x07000000) 985ccf3b7bdSChristoph Hellwig #define MPI_IOCPAGE1_EEDP_MODE_OFF (0x00000000) 986ccf3b7bdSChristoph Hellwig #define MPI_IOCPAGE1_EEDP_MODE_T10 (0x01000000) 987ccf3b7bdSChristoph Hellwig #define MPI_IOCPAGE1_EEDP_MODE_LSI_1 (0x02000000) 988c1a71d1cSMoore, Eric Dean #define MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE (0x00000010) 9891da177e4SLinus Torvalds #define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001) 9901da177e4SLinus Torvalds 9911da177e4SLinus Torvalds #define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 9921da177e4SLinus Torvalds 9931da177e4SLinus Torvalds 9941da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL 9951da177e4SLinus Torvalds { 9961da177e4SLinus Torvalds U8 VolumeID; /* 00h */ 9971da177e4SLinus Torvalds U8 VolumeBus; /* 01h */ 9981da177e4SLinus Torvalds U8 VolumeIOC; /* 02h */ 9991da177e4SLinus Torvalds U8 VolumePageNumber; /* 03h */ 10001da177e4SLinus Torvalds U8 VolumeType; /* 04h */ 10011da177e4SLinus Torvalds U8 Flags; /* 05h */ 10021da177e4SLinus Torvalds U16 Reserved3; /* 06h */ 1003c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL, 10041da177e4SLinus Torvalds ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t; 10051da177e4SLinus Torvalds 10061da177e4SLinus Torvalds /* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */ 10071da177e4SLinus Torvalds 10081da177e4SLinus Torvalds #define MPI_RAID_VOL_TYPE_IS (0x00) 10091da177e4SLinus Torvalds #define MPI_RAID_VOL_TYPE_IME (0x01) 10101da177e4SLinus Torvalds #define MPI_RAID_VOL_TYPE_IM (0x02) 1011ccf3b7bdSChristoph Hellwig #define MPI_RAID_VOL_TYPE_RAID_5 (0x03) 1012ccf3b7bdSChristoph Hellwig #define MPI_RAID_VOL_TYPE_RAID_6 (0x04) 1013ccf3b7bdSChristoph Hellwig #define MPI_RAID_VOL_TYPE_RAID_10 (0x05) 1014ccf3b7bdSChristoph Hellwig #define MPI_RAID_VOL_TYPE_RAID_50 (0x06) 1015ccf3b7bdSChristoph Hellwig #define MPI_RAID_VOL_TYPE_UNKNOWN (0xFF) 10161da177e4SLinus Torvalds 10171da177e4SLinus Torvalds /* IOC Page 2 Volume Flags values */ 10181da177e4SLinus Torvalds 10191da177e4SLinus Torvalds #define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE (0x08) 10201da177e4SLinus Torvalds 10211da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_IOC_2 10221da177e4SLinus Torvalds { 1023c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 10241da177e4SLinus Torvalds U32 CapabilitiesFlags; /* 04h */ 10251da177e4SLinus Torvalds U8 NumActiveVolumes; /* 08h */ 10261da177e4SLinus Torvalds U8 MaxVolumes; /* 09h */ 10271da177e4SLinus Torvalds U8 NumActivePhysDisks; /* 0Ah */ 10281da177e4SLinus Torvalds U8 MaxPhysDisks; /* 0Bh */ 1029de80fe29SKees Cook CONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[] __counted_by(NumActiveVolumes); /* 0Ch */ 1030c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2, 10311da177e4SLinus Torvalds IOCPage2_t, MPI_POINTER pIOCPage2_t; 10321da177e4SLinus Torvalds 10332076eb6aSEric Moore #define MPI_IOCPAGE2_PAGEVERSION (0x04) 10341da177e4SLinus Torvalds 10351da177e4SLinus Torvalds /* IOC Page 2 Capabilities flags */ 10361da177e4SLinus Torvalds 10371da177e4SLinus Torvalds #define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001) 10381da177e4SLinus Torvalds #define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002) 10391da177e4SLinus Torvalds #define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004) 1040ccf3b7bdSChristoph Hellwig #define MPI_IOCPAGE2_CAP_FLAGS_RAID_5_SUPPORT (0x00000008) 1041ccf3b7bdSChristoph Hellwig #define MPI_IOCPAGE2_CAP_FLAGS_RAID_6_SUPPORT (0x00000010) 1042ccf3b7bdSChristoph Hellwig #define MPI_IOCPAGE2_CAP_FLAGS_RAID_10_SUPPORT (0x00000020) 1043ccf3b7bdSChristoph Hellwig #define MPI_IOCPAGE2_CAP_FLAGS_RAID_50_SUPPORT (0x00000040) 10442076eb6aSEric Moore #define MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING (0x10000000) 10451da177e4SLinus Torvalds #define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000) 10461da177e4SLinus Torvalds #define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000) 10471da177e4SLinus Torvalds #define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000) 10481da177e4SLinus Torvalds 10491da177e4SLinus Torvalds 10501da177e4SLinus Torvalds typedef struct _IOC_3_PHYS_DISK 10511da177e4SLinus Torvalds { 10521da177e4SLinus Torvalds U8 PhysDiskID; /* 00h */ 10531da177e4SLinus Torvalds U8 PhysDiskBus; /* 01h */ 10541da177e4SLinus Torvalds U8 PhysDiskIOC; /* 02h */ 10551da177e4SLinus Torvalds U8 PhysDiskNum; /* 03h */ 10561da177e4SLinus Torvalds } IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK, 10571da177e4SLinus Torvalds Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t; 10581da177e4SLinus Torvalds 10591da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_IOC_3 10601da177e4SLinus Torvalds { 1061c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 10621da177e4SLinus Torvalds U8 NumPhysDisks; /* 04h */ 10631da177e4SLinus Torvalds U8 Reserved1; /* 05h */ 10641da177e4SLinus Torvalds U16 Reserved2; /* 06h */ 106570631322SKees Cook IOC_3_PHYS_DISK PhysDisk[] __counted_by(NumPhysDisks); /* 08h */ 1066c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3, 10671da177e4SLinus Torvalds IOCPage3_t, MPI_POINTER pIOCPage3_t; 10681da177e4SLinus Torvalds 10691da177e4SLinus Torvalds #define MPI_IOCPAGE3_PAGEVERSION (0x00) 10701da177e4SLinus Torvalds 10711da177e4SLinus Torvalds 10721da177e4SLinus Torvalds typedef struct _IOC_4_SEP 10731da177e4SLinus Torvalds { 10741da177e4SLinus Torvalds U8 SEPTargetID; /* 00h */ 10751da177e4SLinus Torvalds U8 SEPBus; /* 01h */ 10761da177e4SLinus Torvalds U16 Reserved; /* 02h */ 10771da177e4SLinus Torvalds } IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP, 10781da177e4SLinus Torvalds Ioc4Sep_t, MPI_POINTER pIoc4Sep_t; 10791da177e4SLinus Torvalds 10801da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_IOC_4 10811da177e4SLinus Torvalds { 1082c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 10831da177e4SLinus Torvalds U8 ActiveSEP; /* 04h */ 10841da177e4SLinus Torvalds U8 MaxSEP; /* 05h */ 10851da177e4SLinus Torvalds U16 Reserved1; /* 06h */ 1086*f296cc1dSKees Cook IOC_4_SEP SEP[] __counted_by(ActiveSEP); /* 08h */ 1087c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4, 10881da177e4SLinus Torvalds IOCPage4_t, MPI_POINTER pIOCPage4_t; 10891da177e4SLinus Torvalds 10901da177e4SLinus Torvalds #define MPI_IOCPAGE4_PAGEVERSION (0x00) 10911da177e4SLinus Torvalds 10921da177e4SLinus Torvalds 10931da177e4SLinus Torvalds typedef struct _IOC_5_HOT_SPARE 10941da177e4SLinus Torvalds { 10951da177e4SLinus Torvalds U8 PhysDiskNum; /* 00h */ 10961da177e4SLinus Torvalds U8 Reserved; /* 01h */ 10971da177e4SLinus Torvalds U8 HotSparePool; /* 02h */ 10981da177e4SLinus Torvalds U8 Flags; /* 03h */ 10991da177e4SLinus Torvalds } IOC_5_HOT_SPARE, MPI_POINTER PTR_IOC_5_HOT_SPARE, 11001da177e4SLinus Torvalds Ioc5HotSpare_t, MPI_POINTER pIoc5HotSpare_t; 11011da177e4SLinus Torvalds 11021da177e4SLinus Torvalds /* IOC Page 5 HotSpare Flags */ 11031da177e4SLinus Torvalds #define MPI_IOC_PAGE_5_HOT_SPARE_ACTIVE (0x01) 11041da177e4SLinus Torvalds 11051da177e4SLinus Torvalds /* 11061da177e4SLinus Torvalds * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 11071da177e4SLinus Torvalds * one and check Header.PageLength at runtime. 11081da177e4SLinus Torvalds */ 11091da177e4SLinus Torvalds #ifndef MPI_IOC_PAGE_5_HOT_SPARE_MAX 11101da177e4SLinus Torvalds #define MPI_IOC_PAGE_5_HOT_SPARE_MAX (1) 11111da177e4SLinus Torvalds #endif 11121da177e4SLinus Torvalds 11131da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_IOC_5 11141da177e4SLinus Torvalds { 1115c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 11161da177e4SLinus Torvalds U32 Reserved1; /* 04h */ 11171da177e4SLinus Torvalds U8 NumHotSpares; /* 08h */ 11181da177e4SLinus Torvalds U8 Reserved2; /* 09h */ 11191da177e4SLinus Torvalds U16 Reserved3; /* 0Ah */ 11201da177e4SLinus Torvalds IOC_5_HOT_SPARE HotSpare[MPI_IOC_PAGE_5_HOT_SPARE_MAX]; /* 0Ch */ 1121c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_IOC_5, MPI_POINTER PTR_CONFIG_PAGE_IOC_5, 11221da177e4SLinus Torvalds IOCPage5_t, MPI_POINTER pIOCPage5_t; 11231da177e4SLinus Torvalds 11241da177e4SLinus Torvalds #define MPI_IOCPAGE5_PAGEVERSION (0x00) 11251da177e4SLinus Torvalds 11262076eb6aSEric Moore typedef struct _CONFIG_PAGE_IOC_6 11272076eb6aSEric Moore { 11282076eb6aSEric Moore CONFIG_PAGE_HEADER Header; /* 00h */ 11292076eb6aSEric Moore U32 CapabilitiesFlags; /* 04h */ 11302076eb6aSEric Moore U8 MaxDrivesIS; /* 08h */ 11312076eb6aSEric Moore U8 MaxDrivesIM; /* 09h */ 11322076eb6aSEric Moore U8 MaxDrivesIME; /* 0Ah */ 11332076eb6aSEric Moore U8 Reserved1; /* 0Bh */ 11342076eb6aSEric Moore U8 MinDrivesIS; /* 0Ch */ 11352076eb6aSEric Moore U8 MinDrivesIM; /* 0Dh */ 11362076eb6aSEric Moore U8 MinDrivesIME; /* 0Eh */ 11372076eb6aSEric Moore U8 Reserved2; /* 0Fh */ 11382076eb6aSEric Moore U8 MaxGlobalHotSpares; /* 10h */ 11392076eb6aSEric Moore U8 Reserved3; /* 11h */ 11402076eb6aSEric Moore U16 Reserved4; /* 12h */ 11412076eb6aSEric Moore U32 Reserved5; /* 14h */ 11422076eb6aSEric Moore U32 SupportedStripeSizeMapIS; /* 18h */ 11432076eb6aSEric Moore U32 SupportedStripeSizeMapIME; /* 1Ch */ 11442076eb6aSEric Moore U32 Reserved6; /* 20h */ 11452076eb6aSEric Moore U8 MetadataSize; /* 24h */ 11462076eb6aSEric Moore U8 Reserved7; /* 25h */ 11472076eb6aSEric Moore U16 Reserved8; /* 26h */ 11482076eb6aSEric Moore U16 MaxBadBlockTableEntries; /* 28h */ 11492076eb6aSEric Moore U16 Reserved9; /* 2Ah */ 11502076eb6aSEric Moore U16 IRNvsramUsage; /* 2Ch */ 11512076eb6aSEric Moore U16 Reserved10; /* 2Eh */ 11522076eb6aSEric Moore U32 IRNvsramVersion; /* 30h */ 11532076eb6aSEric Moore U32 Reserved11; /* 34h */ 11542076eb6aSEric Moore U32 Reserved12; /* 38h */ 11552076eb6aSEric Moore } CONFIG_PAGE_IOC_6, MPI_POINTER PTR_CONFIG_PAGE_IOC_6, 11562076eb6aSEric Moore IOCPage6_t, MPI_POINTER pIOCPage6_t; 11572076eb6aSEric Moore 1158eae225ebSEric Moore #define MPI_IOCPAGE6_PAGEVERSION (0x01) 11592076eb6aSEric Moore 11602076eb6aSEric Moore /* IOC Page 6 Capabilities Flags */ 11612076eb6aSEric Moore 1162fd7a2533SKashyap, Desai #define MPI_IOCPAGE6_CAP_FLAGS_SSD_SUPPORT (0x00000020) 1163fd7a2533SKashyap, Desai #define MPI_IOCPAGE6_CAP_FLAGS_MULTIPORT_DRIVE_SUPPORT (0x00000010) 1164d16291b1SEric Moore #define MPI_IOCPAGE6_CAP_FLAGS_DISABLE_SMART_POLLING (0x00000008) 1165d16291b1SEric Moore 1166eae225ebSEric Moore #define MPI_IOCPAGE6_CAP_FLAGS_MASK_METADATA_SIZE (0x00000006) 1167eae225ebSEric Moore #define MPI_IOCPAGE6_CAP_FLAGS_64MB_METADATA_SIZE (0x00000000) 1168eae225ebSEric Moore #define MPI_IOCPAGE6_CAP_FLAGS_512MB_METADATA_SIZE (0x00000002) 1169eae225ebSEric Moore 11702076eb6aSEric Moore #define MPI_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 11712076eb6aSEric Moore 11721da177e4SLinus Torvalds 11731da177e4SLinus Torvalds /**************************************************************************** 1174c1a71d1cSMoore, Eric Dean * BIOS Config Pages 11751da177e4SLinus Torvalds ****************************************************************************/ 11761da177e4SLinus Torvalds 11771da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_BIOS_1 11781da177e4SLinus Torvalds { 1179c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 11801da177e4SLinus Torvalds U32 BiosOptions; /* 04h */ 11811da177e4SLinus Torvalds U32 IOCSettings; /* 08h */ 11821da177e4SLinus Torvalds U32 Reserved1; /* 0Ch */ 11831da177e4SLinus Torvalds U32 DeviceSettings; /* 10h */ 11841da177e4SLinus Torvalds U16 NumberOfDevices; /* 14h */ 11854b915a73SMoore, Eric U8 ExpanderSpinup; /* 16h */ 11864b915a73SMoore, Eric U8 Reserved2; /* 17h */ 11871da177e4SLinus Torvalds U16 IOTimeoutBlockDevicesNonRM; /* 18h */ 11881da177e4SLinus Torvalds U16 IOTimeoutSequential; /* 1Ah */ 11891da177e4SLinus Torvalds U16 IOTimeoutOther; /* 1Ch */ 11901da177e4SLinus Torvalds U16 IOTimeoutBlockDevicesRM; /* 1Eh */ 1191c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_BIOS_1, MPI_POINTER PTR_CONFIG_PAGE_BIOS_1, 11921da177e4SLinus Torvalds BIOSPage1_t, MPI_POINTER pBIOSPage1_t; 11931da177e4SLinus Torvalds 11944b915a73SMoore, Eric #define MPI_BIOSPAGE1_PAGEVERSION (0x03) 11951da177e4SLinus Torvalds 11961da177e4SLinus Torvalds /* values for the BiosOptions field */ 11971da177e4SLinus Torvalds #define MPI_BIOSPAGE1_OPTIONS_SPI_ENABLE (0x00000400) 11981da177e4SLinus Torvalds #define MPI_BIOSPAGE1_OPTIONS_FC_ENABLE (0x00000200) 11991da177e4SLinus Torvalds #define MPI_BIOSPAGE1_OPTIONS_SAS_ENABLE (0x00000100) 12001da177e4SLinus Torvalds #define MPI_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 12011da177e4SLinus Torvalds 12021da177e4SLinus Torvalds /* values for the IOCSettings field */ 12034b915a73SMoore, Eric #define MPI_BIOSPAGE1_IOCSET_MASK_INITIAL_SPINUP_DELAY (0x0F000000) 12044b915a73SMoore, Eric #define MPI_BIOSPAGE1_IOCSET_SHIFT_INITIAL_SPINUP_DELAY (24) 12054b915a73SMoore, Eric 1206ccf3b7bdSChristoph Hellwig #define MPI_BIOSPAGE1_IOCSET_MASK_PORT_ENABLE_DELAY (0x00F00000) 1207ccf3b7bdSChristoph Hellwig #define MPI_BIOSPAGE1_IOCSET_SHIFT_PORT_ENABLE_DELAY (20) 12084b915a73SMoore, Eric 12094b915a73SMoore, Eric #define MPI_BIOSPAGE1_IOCSET_AUTO_PORT_ENABLE (0x00080000) 12104b915a73SMoore, Eric #define MPI_BIOSPAGE1_IOCSET_DIRECT_ATTACH_SPINUP_MODE (0x00040000) 12114b915a73SMoore, Eric 1212c1a71d1cSMoore, Eric Dean #define MPI_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1213c1a71d1cSMoore, Eric Dean #define MPI_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1214c1a71d1cSMoore, Eric Dean #define MPI_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1215c1a71d1cSMoore, Eric Dean 1216c1a71d1cSMoore, Eric Dean #define MPI_BIOSPAGE1_IOCSET_MASK_MAX_TARGET_SPIN_UP (0x0000F000) 1217c1a71d1cSMoore, Eric Dean #define MPI_BIOSPAGE1_IOCSET_SHIFT_MAX_TARGET_SPIN_UP (12) 1218c1a71d1cSMoore, Eric Dean 12191da177e4SLinus Torvalds #define MPI_BIOSPAGE1_IOCSET_MASK_SPINUP_DELAY (0x00000F00) 12201da177e4SLinus Torvalds #define MPI_BIOSPAGE1_IOCSET_SHIFT_SPINUP_DELAY (8) 12211da177e4SLinus Torvalds 12221da177e4SLinus Torvalds #define MPI_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 12231da177e4SLinus Torvalds #define MPI_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 12241da177e4SLinus Torvalds #define MPI_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 12251da177e4SLinus Torvalds #define MPI_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 12261da177e4SLinus Torvalds 12271da177e4SLinus Torvalds #define MPI_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 12281da177e4SLinus Torvalds #define MPI_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 12291da177e4SLinus Torvalds #define MPI_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 12301da177e4SLinus Torvalds #define MPI_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 12311da177e4SLinus Torvalds #define MPI_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 12321da177e4SLinus Torvalds 12331da177e4SLinus Torvalds #define MPI_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 12341da177e4SLinus Torvalds 12351da177e4SLinus Torvalds /* values for the DeviceSettings field */ 1236d16291b1SEric Moore #define MPI_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 12371da177e4SLinus Torvalds #define MPI_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 12381da177e4SLinus Torvalds #define MPI_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 12391da177e4SLinus Torvalds #define MPI_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 12401da177e4SLinus Torvalds #define MPI_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 12411da177e4SLinus Torvalds 12424b915a73SMoore, Eric /* defines for the ExpanderSpinup field */ 12434b915a73SMoore, Eric #define MPI_BIOSPAGE1_EXPSPINUP_MASK_MAX_TARGET (0xF0) 12444b915a73SMoore, Eric #define MPI_BIOSPAGE1_EXPSPINUP_SHIFT_MAX_TARGET (4) 12454b915a73SMoore, Eric #define MPI_BIOSPAGE1_EXPSPINUP_MASK_DELAY (0x0F) 12464b915a73SMoore, Eric 1247c1a71d1cSMoore, Eric Dean typedef struct _MPI_BOOT_DEVICE_ADAPTER_ORDER 1248c1a71d1cSMoore, Eric Dean { 1249c1a71d1cSMoore, Eric Dean U32 Reserved1; /* 00h */ 1250c1a71d1cSMoore, Eric Dean U32 Reserved2; /* 04h */ 1251c1a71d1cSMoore, Eric Dean U32 Reserved3; /* 08h */ 1252c1a71d1cSMoore, Eric Dean U32 Reserved4; /* 0Ch */ 1253c1a71d1cSMoore, Eric Dean U32 Reserved5; /* 10h */ 1254c1a71d1cSMoore, Eric Dean U32 Reserved6; /* 14h */ 1255c1a71d1cSMoore, Eric Dean U32 Reserved7; /* 18h */ 1256c1a71d1cSMoore, Eric Dean U32 Reserved8; /* 1Ch */ 1257c1a71d1cSMoore, Eric Dean U32 Reserved9; /* 20h */ 1258c1a71d1cSMoore, Eric Dean U32 Reserved10; /* 24h */ 1259c1a71d1cSMoore, Eric Dean U32 Reserved11; /* 28h */ 1260c1a71d1cSMoore, Eric Dean U32 Reserved12; /* 2Ch */ 1261c1a71d1cSMoore, Eric Dean U32 Reserved13; /* 30h */ 1262c1a71d1cSMoore, Eric Dean U32 Reserved14; /* 34h */ 1263c1a71d1cSMoore, Eric Dean U32 Reserved15; /* 38h */ 1264c1a71d1cSMoore, Eric Dean U32 Reserved16; /* 3Ch */ 1265c1a71d1cSMoore, Eric Dean U32 Reserved17; /* 40h */ 1266c1a71d1cSMoore, Eric Dean } MPI_BOOT_DEVICE_ADAPTER_ORDER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_ORDER; 1267c1a71d1cSMoore, Eric Dean 1268c1a71d1cSMoore, Eric Dean typedef struct _MPI_BOOT_DEVICE_ADAPTER_NUMBER 1269c1a71d1cSMoore, Eric Dean { 1270c1a71d1cSMoore, Eric Dean U8 TargetID; /* 00h */ 1271c1a71d1cSMoore, Eric Dean U8 Bus; /* 01h */ 1272c1a71d1cSMoore, Eric Dean U8 AdapterNumber; /* 02h */ 1273c1a71d1cSMoore, Eric Dean U8 Reserved1; /* 03h */ 1274c1a71d1cSMoore, Eric Dean U32 Reserved2; /* 04h */ 1275c1a71d1cSMoore, Eric Dean U32 Reserved3; /* 08h */ 1276c1a71d1cSMoore, Eric Dean U32 Reserved4; /* 0Ch */ 1277c1a71d1cSMoore, Eric Dean U8 LUN[8]; /* 10h */ 1278c1a71d1cSMoore, Eric Dean U32 Reserved5; /* 18h */ 1279c1a71d1cSMoore, Eric Dean U32 Reserved6; /* 1Ch */ 1280c1a71d1cSMoore, Eric Dean U32 Reserved7; /* 20h */ 1281c1a71d1cSMoore, Eric Dean U32 Reserved8; /* 24h */ 1282c1a71d1cSMoore, Eric Dean U32 Reserved9; /* 28h */ 1283c1a71d1cSMoore, Eric Dean U32 Reserved10; /* 2Ch */ 1284c1a71d1cSMoore, Eric Dean U32 Reserved11; /* 30h */ 1285c1a71d1cSMoore, Eric Dean U32 Reserved12; /* 34h */ 1286c1a71d1cSMoore, Eric Dean U32 Reserved13; /* 38h */ 1287c1a71d1cSMoore, Eric Dean U32 Reserved14; /* 3Ch */ 1288c1a71d1cSMoore, Eric Dean U32 Reserved15; /* 40h */ 1289c1a71d1cSMoore, Eric Dean } MPI_BOOT_DEVICE_ADAPTER_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_NUMBER; 1290c1a71d1cSMoore, Eric Dean 1291c1a71d1cSMoore, Eric Dean typedef struct _MPI_BOOT_DEVICE_PCI_ADDRESS 1292c1a71d1cSMoore, Eric Dean { 1293c1a71d1cSMoore, Eric Dean U8 TargetID; /* 00h */ 1294c1a71d1cSMoore, Eric Dean U8 Bus; /* 01h */ 1295c1a71d1cSMoore, Eric Dean U16 PCIAddress; /* 02h */ 1296c1a71d1cSMoore, Eric Dean U32 Reserved1; /* 04h */ 1297c1a71d1cSMoore, Eric Dean U32 Reserved2; /* 08h */ 1298c1a71d1cSMoore, Eric Dean U32 Reserved3; /* 0Ch */ 1299c1a71d1cSMoore, Eric Dean U8 LUN[8]; /* 10h */ 1300c1a71d1cSMoore, Eric Dean U32 Reserved4; /* 18h */ 1301c1a71d1cSMoore, Eric Dean U32 Reserved5; /* 1Ch */ 1302c1a71d1cSMoore, Eric Dean U32 Reserved6; /* 20h */ 1303c1a71d1cSMoore, Eric Dean U32 Reserved7; /* 24h */ 1304c1a71d1cSMoore, Eric Dean U32 Reserved8; /* 28h */ 1305c1a71d1cSMoore, Eric Dean U32 Reserved9; /* 2Ch */ 1306c1a71d1cSMoore, Eric Dean U32 Reserved10; /* 30h */ 1307c1a71d1cSMoore, Eric Dean U32 Reserved11; /* 34h */ 1308c1a71d1cSMoore, Eric Dean U32 Reserved12; /* 38h */ 1309c1a71d1cSMoore, Eric Dean U32 Reserved13; /* 3Ch */ 1310c1a71d1cSMoore, Eric Dean U32 Reserved14; /* 40h */ 1311c1a71d1cSMoore, Eric Dean } MPI_BOOT_DEVICE_PCI_ADDRESS, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_ADDRESS; 1312c1a71d1cSMoore, Eric Dean 1313c1a71d1cSMoore, Eric Dean typedef struct _MPI_BOOT_DEVICE_SLOT_NUMBER 1314c1a71d1cSMoore, Eric Dean { 1315c1a71d1cSMoore, Eric Dean U8 TargetID; /* 00h */ 1316c1a71d1cSMoore, Eric Dean U8 Bus; /* 01h */ 1317c1a71d1cSMoore, Eric Dean U8 PCISlotNumber; /* 02h */ 1318c1a71d1cSMoore, Eric Dean U8 Reserved1; /* 03h */ 1319c1a71d1cSMoore, Eric Dean U32 Reserved2; /* 04h */ 1320c1a71d1cSMoore, Eric Dean U32 Reserved3; /* 08h */ 1321c1a71d1cSMoore, Eric Dean U32 Reserved4; /* 0Ch */ 1322c1a71d1cSMoore, Eric Dean U8 LUN[8]; /* 10h */ 1323c1a71d1cSMoore, Eric Dean U32 Reserved5; /* 18h */ 1324c1a71d1cSMoore, Eric Dean U32 Reserved6; /* 1Ch */ 1325c1a71d1cSMoore, Eric Dean U32 Reserved7; /* 20h */ 1326c1a71d1cSMoore, Eric Dean U32 Reserved8; /* 24h */ 1327c1a71d1cSMoore, Eric Dean U32 Reserved9; /* 28h */ 1328c1a71d1cSMoore, Eric Dean U32 Reserved10; /* 2Ch */ 1329c1a71d1cSMoore, Eric Dean U32 Reserved11; /* 30h */ 1330c1a71d1cSMoore, Eric Dean U32 Reserved12; /* 34h */ 1331c1a71d1cSMoore, Eric Dean U32 Reserved13; /* 38h */ 1332c1a71d1cSMoore, Eric Dean U32 Reserved14; /* 3Ch */ 1333c1a71d1cSMoore, Eric Dean U32 Reserved15; /* 40h */ 1334c1a71d1cSMoore, Eric Dean } MPI_BOOT_DEVICE_PCI_SLOT_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_SLOT_NUMBER; 1335c1a71d1cSMoore, Eric Dean 1336c1a71d1cSMoore, Eric Dean typedef struct _MPI_BOOT_DEVICE_FC_WWN 1337c1a71d1cSMoore, Eric Dean { 1338c1a71d1cSMoore, Eric Dean U64 WWPN; /* 00h */ 1339c1a71d1cSMoore, Eric Dean U32 Reserved1; /* 08h */ 1340c1a71d1cSMoore, Eric Dean U32 Reserved2; /* 0Ch */ 1341c1a71d1cSMoore, Eric Dean U8 LUN[8]; /* 10h */ 1342c1a71d1cSMoore, Eric Dean U32 Reserved3; /* 18h */ 1343c1a71d1cSMoore, Eric Dean U32 Reserved4; /* 1Ch */ 1344c1a71d1cSMoore, Eric Dean U32 Reserved5; /* 20h */ 1345c1a71d1cSMoore, Eric Dean U32 Reserved6; /* 24h */ 1346c1a71d1cSMoore, Eric Dean U32 Reserved7; /* 28h */ 1347c1a71d1cSMoore, Eric Dean U32 Reserved8; /* 2Ch */ 1348c1a71d1cSMoore, Eric Dean U32 Reserved9; /* 30h */ 1349c1a71d1cSMoore, Eric Dean U32 Reserved10; /* 34h */ 1350c1a71d1cSMoore, Eric Dean U32 Reserved11; /* 38h */ 1351c1a71d1cSMoore, Eric Dean U32 Reserved12; /* 3Ch */ 1352c1a71d1cSMoore, Eric Dean U32 Reserved13; /* 40h */ 1353c1a71d1cSMoore, Eric Dean } MPI_BOOT_DEVICE_FC_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_FC_WWN; 1354c1a71d1cSMoore, Eric Dean 1355c1a71d1cSMoore, Eric Dean typedef struct _MPI_BOOT_DEVICE_SAS_WWN 1356c1a71d1cSMoore, Eric Dean { 1357c1a71d1cSMoore, Eric Dean U64 SASAddress; /* 00h */ 1358c1a71d1cSMoore, Eric Dean U32 Reserved1; /* 08h */ 1359c1a71d1cSMoore, Eric Dean U32 Reserved2; /* 0Ch */ 1360c1a71d1cSMoore, Eric Dean U8 LUN[8]; /* 10h */ 1361c1a71d1cSMoore, Eric Dean U32 Reserved3; /* 18h */ 1362c1a71d1cSMoore, Eric Dean U32 Reserved4; /* 1Ch */ 1363c1a71d1cSMoore, Eric Dean U32 Reserved5; /* 20h */ 1364c1a71d1cSMoore, Eric Dean U32 Reserved6; /* 24h */ 1365c1a71d1cSMoore, Eric Dean U32 Reserved7; /* 28h */ 1366c1a71d1cSMoore, Eric Dean U32 Reserved8; /* 2Ch */ 1367c1a71d1cSMoore, Eric Dean U32 Reserved9; /* 30h */ 1368c1a71d1cSMoore, Eric Dean U32 Reserved10; /* 34h */ 1369c1a71d1cSMoore, Eric Dean U32 Reserved11; /* 38h */ 1370c1a71d1cSMoore, Eric Dean U32 Reserved12; /* 3Ch */ 1371c1a71d1cSMoore, Eric Dean U32 Reserved13; /* 40h */ 1372c1a71d1cSMoore, Eric Dean } MPI_BOOT_DEVICE_SAS_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_SAS_WWN; 1373c1a71d1cSMoore, Eric Dean 1374c1a71d1cSMoore, Eric Dean typedef struct _MPI_BOOT_DEVICE_ENCLOSURE_SLOT 1375c1a71d1cSMoore, Eric Dean { 1376c1a71d1cSMoore, Eric Dean U64 EnclosureLogicalID; /* 00h */ 1377c1a71d1cSMoore, Eric Dean U32 Reserved1; /* 08h */ 1378c1a71d1cSMoore, Eric Dean U32 Reserved2; /* 0Ch */ 1379c1a71d1cSMoore, Eric Dean U8 LUN[8]; /* 10h */ 1380c1a71d1cSMoore, Eric Dean U16 SlotNumber; /* 18h */ 1381c1a71d1cSMoore, Eric Dean U16 Reserved3; /* 1Ah */ 1382c1a71d1cSMoore, Eric Dean U32 Reserved4; /* 1Ch */ 1383c1a71d1cSMoore, Eric Dean U32 Reserved5; /* 20h */ 1384c1a71d1cSMoore, Eric Dean U32 Reserved6; /* 24h */ 1385c1a71d1cSMoore, Eric Dean U32 Reserved7; /* 28h */ 1386c1a71d1cSMoore, Eric Dean U32 Reserved8; /* 2Ch */ 1387c1a71d1cSMoore, Eric Dean U32 Reserved9; /* 30h */ 1388c1a71d1cSMoore, Eric Dean U32 Reserved10; /* 34h */ 1389c1a71d1cSMoore, Eric Dean U32 Reserved11; /* 38h */ 1390c1a71d1cSMoore, Eric Dean U32 Reserved12; /* 3Ch */ 1391c1a71d1cSMoore, Eric Dean U32 Reserved13; /* 40h */ 1392c1a71d1cSMoore, Eric Dean } MPI_BOOT_DEVICE_ENCLOSURE_SLOT, 1393c1a71d1cSMoore, Eric Dean MPI_POINTER PTR_MPI_BOOT_DEVICE_ENCLOSURE_SLOT; 1394c1a71d1cSMoore, Eric Dean 1395c1a71d1cSMoore, Eric Dean typedef union _MPI_BIOSPAGE2_BOOT_DEVICE 1396c1a71d1cSMoore, Eric Dean { 1397c1a71d1cSMoore, Eric Dean MPI_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1398c1a71d1cSMoore, Eric Dean MPI_BOOT_DEVICE_ADAPTER_NUMBER AdapterNumber; 1399c1a71d1cSMoore, Eric Dean MPI_BOOT_DEVICE_PCI_ADDRESS PCIAddress; 1400c1a71d1cSMoore, Eric Dean MPI_BOOT_DEVICE_PCI_SLOT_NUMBER PCISlotNumber; 1401c1a71d1cSMoore, Eric Dean MPI_BOOT_DEVICE_FC_WWN FcWwn; 1402c1a71d1cSMoore, Eric Dean MPI_BOOT_DEVICE_SAS_WWN SasWwn; 1403c1a71d1cSMoore, Eric Dean MPI_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1404c1a71d1cSMoore, Eric Dean } MPI_BIOSPAGE2_BOOT_DEVICE, MPI_POINTER PTR_MPI_BIOSPAGE2_BOOT_DEVICE; 1405c1a71d1cSMoore, Eric Dean 1406c1a71d1cSMoore, Eric Dean typedef struct _CONFIG_PAGE_BIOS_2 1407c1a71d1cSMoore, Eric Dean { 1408c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 1409c1a71d1cSMoore, Eric Dean U32 Reserved1; /* 04h */ 1410c1a71d1cSMoore, Eric Dean U32 Reserved2; /* 08h */ 1411c1a71d1cSMoore, Eric Dean U32 Reserved3; /* 0Ch */ 1412c1a71d1cSMoore, Eric Dean U32 Reserved4; /* 10h */ 1413c1a71d1cSMoore, Eric Dean U32 Reserved5; /* 14h */ 1414c1a71d1cSMoore, Eric Dean U32 Reserved6; /* 18h */ 1415c1a71d1cSMoore, Eric Dean U8 BootDeviceForm; /* 1Ch */ 14162076eb6aSEric Moore U8 PrevBootDeviceForm; /* 1Ch */ 1417c1a71d1cSMoore, Eric Dean U16 Reserved8; /* 1Eh */ 1418c1a71d1cSMoore, Eric Dean MPI_BIOSPAGE2_BOOT_DEVICE BootDevice; /* 20h */ 1419c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_BIOS_2, MPI_POINTER PTR_CONFIG_PAGE_BIOS_2, 1420c1a71d1cSMoore, Eric Dean BIOSPage2_t, MPI_POINTER pBIOSPage2_t; 1421c1a71d1cSMoore, Eric Dean 14222076eb6aSEric Moore #define MPI_BIOSPAGE2_PAGEVERSION (0x02) 1423c1a71d1cSMoore, Eric Dean 1424c1a71d1cSMoore, Eric Dean #define MPI_BIOSPAGE2_FORM_MASK (0x0F) 1425c1a71d1cSMoore, Eric Dean #define MPI_BIOSPAGE2_FORM_ADAPTER_ORDER (0x00) 1426c1a71d1cSMoore, Eric Dean #define MPI_BIOSPAGE2_FORM_ADAPTER_NUMBER (0x01) 1427c1a71d1cSMoore, Eric Dean #define MPI_BIOSPAGE2_FORM_PCI_ADDRESS (0x02) 1428c1a71d1cSMoore, Eric Dean #define MPI_BIOSPAGE2_FORM_PCI_SLOT_NUMBER (0x03) 1429c1a71d1cSMoore, Eric Dean #define MPI_BIOSPAGE2_FORM_FC_WWN (0x04) 1430c1a71d1cSMoore, Eric Dean #define MPI_BIOSPAGE2_FORM_SAS_WWN (0x05) 1431ccf3b7bdSChristoph Hellwig #define MPI_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1432c1a71d1cSMoore, Eric Dean 1433fd7a2533SKashyap, Desai typedef struct _CONFIG_PAGE_BIOS_4 1434fd7a2533SKashyap, Desai { 1435fd7a2533SKashyap, Desai CONFIG_PAGE_HEADER Header; /* 00h */ 1436fd7a2533SKashyap, Desai U64 ReassignmentBaseWWID; /* 04h */ 1437fd7a2533SKashyap, Desai } CONFIG_PAGE_BIOS_4, MPI_POINTER PTR_CONFIG_PAGE_BIOS_4, 1438fd7a2533SKashyap, Desai BIOSPage4_t, MPI_POINTER pBIOSPage4_t; 1439fd7a2533SKashyap, Desai 1440fd7a2533SKashyap, Desai #define MPI_BIOSPAGE4_PAGEVERSION (0x00) 1441fd7a2533SKashyap, Desai 14421da177e4SLinus Torvalds 14431da177e4SLinus Torvalds /**************************************************************************** 14441da177e4SLinus Torvalds * SCSI Port Config Pages 14451da177e4SLinus Torvalds ****************************************************************************/ 14461da177e4SLinus Torvalds 14471da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_SCSI_PORT_0 14481da177e4SLinus Torvalds { 1449c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 14501da177e4SLinus Torvalds U32 Capabilities; /* 04h */ 14511da177e4SLinus Torvalds U32 PhysicalInterface; /* 08h */ 1452c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0, 14531da177e4SLinus Torvalds SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t; 14541da177e4SLinus Torvalds 1455c1a71d1cSMoore, Eric Dean #define MPI_SCSIPORTPAGE0_PAGEVERSION (0x02) 14561da177e4SLinus Torvalds 14571da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001) 14581da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002) 14591da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004) 14601da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 14611da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_SYNC_ASYNC (0x00) 14621da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_SYNC_5 (0x32) 14631da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_SYNC_10 (0x19) 14641da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_SYNC_20 (0x0C) 14651da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_SYNC_33_33 (0x0B) 14661da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_SYNC_40 (0x0A) 14671da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_SYNC_80 (0x09) 14681da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_SYNC_160 (0x08) 14691da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_SYNC_UNKNOWN (0xFF) 14701da177e4SLinus Torvalds 14711da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD (8) 14721da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_CAP_GET_MIN_SYNC_PERIOD(Cap) \ 14734b915a73SMoore, Eric ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK) \ 14741da177e4SLinus Torvalds >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD \ 14751da177e4SLinus Torvalds ) 14761da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 14771da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET (16) 14781da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_CAP_GET_MAX_SYNC_OFFSET(Cap) \ 14794b915a73SMoore, Eric ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK) \ 14801da177e4SLinus Torvalds >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET \ 14811da177e4SLinus Torvalds ) 1482c1a71d1cSMoore, Eric Dean #define MPI_SCSIPORTPAGE0_CAP_IDP (0x08000000) 14831da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000) 14841da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000) 14851da177e4SLinus Torvalds 14861da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003) 14871da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01) 14881da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02) 14891da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03) 14901da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID (0xFF000000) 14911da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_PHY_SHIFT_CONNECTED_ID (24) 14921da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_PHY_BUS_FREE_CONNECTED_ID (0xFE) 14931da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE0_PHY_UNKNOWN_CONNECTED_ID (0xFF) 14941da177e4SLinus Torvalds 14951da177e4SLinus Torvalds 14961da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_SCSI_PORT_1 14971da177e4SLinus Torvalds { 1498c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 14991da177e4SLinus Torvalds U32 Configuration; /* 04h */ 15001da177e4SLinus Torvalds U32 OnBusTimerValue; /* 08h */ 15011da177e4SLinus Torvalds U8 TargetConfig; /* 0Ch */ 15021da177e4SLinus Torvalds U8 Reserved1; /* 0Dh */ 15031da177e4SLinus Torvalds U16 IDConfig; /* 0Eh */ 1504c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1, 15051da177e4SLinus Torvalds SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t; 15061da177e4SLinus Torvalds 15071da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE1_PAGEVERSION (0x03) 15081da177e4SLinus Torvalds 15091da177e4SLinus Torvalds /* Configuration values */ 15101da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF) 15111da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000) 15121da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE1_CFG_SHIFT_PORT_RESPONSE_ID (16) 15131da177e4SLinus Torvalds 15141da177e4SLinus Torvalds /* TargetConfig values */ 15151da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE1_TARGCONFIG_TARG_ONLY (0x01) 15161da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE1_TARGCONFIG_INIT_TARG (0x02) 15171da177e4SLinus Torvalds 15181da177e4SLinus Torvalds 15191da177e4SLinus Torvalds typedef struct _MPI_DEVICE_INFO 15201da177e4SLinus Torvalds { 15211da177e4SLinus Torvalds U8 Timeout; /* 00h */ 15221da177e4SLinus Torvalds U8 SyncFactor; /* 01h */ 15231da177e4SLinus Torvalds U16 DeviceFlags; /* 02h */ 15241da177e4SLinus Torvalds } MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO, 15251da177e4SLinus Torvalds MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t; 15261da177e4SLinus Torvalds 15271da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_SCSI_PORT_2 15281da177e4SLinus Torvalds { 1529c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 15301da177e4SLinus Torvalds U32 PortFlags; /* 04h */ 15311da177e4SLinus Torvalds U32 PortSettings; /* 08h */ 15321da177e4SLinus Torvalds MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */ 1533c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2, 15341da177e4SLinus Torvalds SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t; 15351da177e4SLinus Torvalds 15361da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_PAGEVERSION (0x02) 15371da177e4SLinus Torvalds 15381da177e4SLinus Torvalds /* PortFlags values */ 15391da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001) 15401da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004) 15411da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 15421da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010) 15431da177e4SLinus Torvalds 15441da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK (0x00000060) 15451da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_PORT_FLAGS_FULL_DV (0x00000000) 15461da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_PORT_FLAGS_BASIC_DV_ONLY (0x00000020) 15471da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_PORT_FLAGS_OFF_DV (0x00000060) 15481da177e4SLinus Torvalds 15491da177e4SLinus Torvalds 15501da177e4SLinus Torvalds /* PortSettings values */ 15511da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F) 15521da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030) 15531da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000) 15541da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010) 15551da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020) 15561da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030) 15571da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0) 15581da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_PORT_RM_NONE (0x00000000) 15591da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_PORT_RM_BOOT_ONLY (0x00000040) 15601da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_PORT_RM_WITH_MEDIA (0x00000080) 15611da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00) 15621da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_PORT_SHIFT_SPINUP_DELAY (8) 15631da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000) 15641da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000) 15651da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000) 15661da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000) 15671da177e4SLinus Torvalds 15681da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001) 15691da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002) 15701da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004) 15711da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008) 15721da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010) 15731da177e4SLinus Torvalds #define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020) 15741da177e4SLinus Torvalds 15751da177e4SLinus Torvalds 15761da177e4SLinus Torvalds /**************************************************************************** 15771da177e4SLinus Torvalds * SCSI Target Device Config Pages 15781da177e4SLinus Torvalds ****************************************************************************/ 15791da177e4SLinus Torvalds 15801da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_SCSI_DEVICE_0 15811da177e4SLinus Torvalds { 1582c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 15831da177e4SLinus Torvalds U32 NegotiatedParameters; /* 04h */ 15841da177e4SLinus Torvalds U32 Information; /* 08h */ 1585c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0, 15861da177e4SLinus Torvalds SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t; 15871da177e4SLinus Torvalds 1588c1a71d1cSMoore, Eric Dean #define MPI_SCSIDEVPAGE0_PAGEVERSION (0x04) 15891da177e4SLinus Torvalds 15901da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE0_NP_IU (0x00000001) 15911da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE0_NP_DT (0x00000002) 15921da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004) 15931da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE0_NP_HOLD_MCS (0x00000008) 15941da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE0_NP_WR_FLOW (0x00000010) 15951da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE0_NP_RD_STRM (0x00000020) 15961da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE0_NP_RTI (0x00000040) 15971da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE0_NP_PCOMP_EN (0x00000080) 15981da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00) 15991da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_PERIOD (8) 16001da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000) 16011da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_OFFSET (16) 1602c1a71d1cSMoore, Eric Dean #define MPI_SCSIDEVPAGE0_NP_IDP (0x08000000) 16031da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000) 16041da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000) 16051da177e4SLinus Torvalds 16061da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001) 16071da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002) 16081da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004) 16091da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008) 16101da177e4SLinus Torvalds 16111da177e4SLinus Torvalds 16121da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_SCSI_DEVICE_1 16131da177e4SLinus Torvalds { 1614c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 16151da177e4SLinus Torvalds U32 RequestedParameters; /* 04h */ 16161da177e4SLinus Torvalds U32 Reserved; /* 08h */ 16171da177e4SLinus Torvalds U32 Configuration; /* 0Ch */ 1618c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1, 16191da177e4SLinus Torvalds SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t; 16201da177e4SLinus Torvalds 1621c1a71d1cSMoore, Eric Dean #define MPI_SCSIDEVPAGE1_PAGEVERSION (0x05) 16221da177e4SLinus Torvalds 16231da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE1_RP_IU (0x00000001) 16241da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE1_RP_DT (0x00000002) 16251da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004) 16261da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE1_RP_HOLD_MCS (0x00000008) 16271da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE1_RP_WR_FLOW (0x00000010) 16281da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE1_RP_RD_STRM (0x00000020) 16291da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE1_RP_RTI (0x00000040) 16301da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE1_RP_PCOMP_EN (0x00000080) 16311da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 16321da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE1_RP_SHIFT_MIN_SYNC_PERIOD (8) 16331da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 16341da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE1_RP_SHIFT_MAX_SYNC_OFFSET (16) 1635c1a71d1cSMoore, Eric Dean #define MPI_SCSIDEVPAGE1_RP_IDP (0x08000000) 16361da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000) 16371da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000) 16381da177e4SLinus Torvalds 16391da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002) 16401da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004) 16411da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE (0x00000008) 16421da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG (0x00000010) 16431da177e4SLinus Torvalds 16441da177e4SLinus Torvalds 16451da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_SCSI_DEVICE_2 16461da177e4SLinus Torvalds { 1647c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 16481da177e4SLinus Torvalds U32 DomainValidation; /* 04h */ 16491da177e4SLinus Torvalds U32 ParityPipeSelect; /* 08h */ 16501da177e4SLinus Torvalds U32 DataPipeSelect; /* 0Ch */ 1651c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2, 16521da177e4SLinus Torvalds SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t; 16531da177e4SLinus Torvalds 16541da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_PAGEVERSION (0x01) 16551da177e4SLinus Torvalds 16561da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010) 16571da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020) 16581da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380) 16591da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00) 16601da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000) 16611da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000) 16621da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000) 16631da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000) 16641da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000) 16651da177e4SLinus Torvalds 16661da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003) 16671da177e4SLinus Torvalds 16681da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003) 16691da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C) 16701da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030) 16711da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0) 16721da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300) 16731da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00) 16741da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000) 16751da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000) 16761da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000) 16771da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK (0x000C0000) 16781da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000) 16791da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000) 16801da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000) 16811da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000) 16821da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000) 16831da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000) 16841da177e4SLinus Torvalds 16851da177e4SLinus Torvalds 16861da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_SCSI_DEVICE_3 16871da177e4SLinus Torvalds { 1688c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 16891da177e4SLinus Torvalds U16 MsgRejectCount; /* 04h */ 16901da177e4SLinus Torvalds U16 PhaseErrorCount; /* 06h */ 16911da177e4SLinus Torvalds U16 ParityErrorCount; /* 08h */ 16921da177e4SLinus Torvalds U16 Reserved; /* 0Ah */ 1693c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_SCSI_DEVICE_3, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_3, 16941da177e4SLinus Torvalds SCSIDevicePage3_t, MPI_POINTER pSCSIDevicePage3_t; 16951da177e4SLinus Torvalds 16961da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE3_PAGEVERSION (0x00) 16971da177e4SLinus Torvalds 16981da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE3_MAX_COUNTER (0xFFFE) 16991da177e4SLinus Torvalds #define MPI_SCSIDEVPAGE3_UNSUPPORTED_COUNTER (0xFFFF) 17001da177e4SLinus Torvalds 17011da177e4SLinus Torvalds 17021da177e4SLinus Torvalds /**************************************************************************** 17031da177e4SLinus Torvalds * FC Port Config Pages 17041da177e4SLinus Torvalds ****************************************************************************/ 17051da177e4SLinus Torvalds 17061da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_FC_PORT_0 17071da177e4SLinus Torvalds { 1708c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 17091da177e4SLinus Torvalds U32 Flags; /* 04h */ 17101da177e4SLinus Torvalds U8 MPIPortNumber; /* 08h */ 17111da177e4SLinus Torvalds U8 LinkType; /* 09h */ 17121da177e4SLinus Torvalds U8 PortState; /* 0Ah */ 17131da177e4SLinus Torvalds U8 Reserved; /* 0Bh */ 17141da177e4SLinus Torvalds U32 PortIdentifier; /* 0Ch */ 17151da177e4SLinus Torvalds U64 WWNN; /* 10h */ 17161da177e4SLinus Torvalds U64 WWPN; /* 18h */ 17171da177e4SLinus Torvalds U32 SupportedServiceClass; /* 20h */ 17181da177e4SLinus Torvalds U32 SupportedSpeeds; /* 24h */ 17191da177e4SLinus Torvalds U32 CurrentSpeed; /* 28h */ 17201da177e4SLinus Torvalds U32 MaxFrameSize; /* 2Ch */ 17211da177e4SLinus Torvalds U64 FabricWWNN; /* 30h */ 17221da177e4SLinus Torvalds U64 FabricWWPN; /* 38h */ 17231da177e4SLinus Torvalds U32 DiscoveredPortsCount; /* 40h */ 17241da177e4SLinus Torvalds U32 MaxInitiators; /* 44h */ 17251da177e4SLinus Torvalds U8 MaxAliasesSupported; /* 48h */ 17261da177e4SLinus Torvalds U8 MaxHardAliasesSupported; /* 49h */ 17271da177e4SLinus Torvalds U8 NumCurrentAliases; /* 4Ah */ 17281da177e4SLinus Torvalds U8 Reserved1; /* 4Bh */ 1729c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0, 17301da177e4SLinus Torvalds FCPortPage0_t, MPI_POINTER pFCPortPage0_t; 17311da177e4SLinus Torvalds 17321da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_PAGEVERSION (0x02) 17331da177e4SLinus Torvalds 17341da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F) 17351da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR) 17361da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET) 17371da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN) 17381da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR) 17391da177e4SLinus Torvalds 17401da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010) 17411da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020) 17421da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000040) 17431da177e4SLinus Torvalds 17441da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00) 17451da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000) 17461da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100) 17471da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200) 17481da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400) 17491da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800) 17501da177e4SLinus Torvalds 17511da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_LTYPE_RESERVED (0x00) 17521da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_LTYPE_OTHER (0x01) 17531da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_LTYPE_UNKNOWN (0x02) 17541da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_LTYPE_COPPER (0x03) 17551da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 (0x04) 17561da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 (0x05) 17571da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI (0x06) 17581da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI (0x07) 17591da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI (0x08) 17601da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI (0x09) 17611da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE (0x0A) 17621da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE (0x0B) 17631da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE (0x0C) 17641da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE (0x0D) 17651da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE (0x0E) 17661da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE (0x0F) 17671da177e4SLinus Torvalds 17681da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN (0x01) /*(SNIA)HBA_PORTSTATE_UNKNOWN 1 Unknown */ 17691da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_PORTSTATE_ONLINE (0x02) /*(SNIA)HBA_PORTSTATE_ONLINE 2 Operational */ 17701da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE (0x03) /*(SNIA)HBA_PORTSTATE_OFFLINE 3 User Offline */ 17711da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED (0x04) /*(SNIA)HBA_PORTSTATE_BYPASSED 4 Bypassed */ 17721da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST (0x05) /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS 5 In diagnostics mode */ 17731da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */ 17741da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */ 17751da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */ 17761da177e4SLinus Torvalds 17771da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001) 17781da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002) 17791da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004) 17801da177e4SLinus Torvalds 1781bcbba7bbSColin Ian King #define MPI_FCPORTPAGE0_SUPPORT_SPEED_UNKNOWN (0x00000000) /* (SNIA)HBA_PORTSPEED_UNKNOWN 0 Unknown - transceiver incapable of reporting */ 17821da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */ 17831da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */ 17841da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */ 17851da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED (0x00000008) /* (SNIA)HBA_PORTSPEED_4GBIT 8 4 GBit/sec */ 17861da177e4SLinus Torvalds 1787bcbba7bbSColin Ian King #define MPI_FCPORTPAGE0_CURRENT_SPEED_UNKNOWN MPI_FCPORTPAGE0_SUPPORT_SPEED_UNKNOWN 17881da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED 17891da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED 17901da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED 17911da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_CURRENT_SPEED_4GBIT MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED 17921da177e4SLinus Torvalds #define MPI_FCPORTPAGE0_CURRENT_SPEED_NOT_NEGOTIATED (0x00008000) /* (SNIA)HBA_PORTSPEED_NOT_NEGOTIATED (1<<15) Speed not established */ 17931da177e4SLinus Torvalds 17941da177e4SLinus Torvalds 17951da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_FC_PORT_1 17961da177e4SLinus Torvalds { 1797c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 17981da177e4SLinus Torvalds U32 Flags; /* 04h */ 17991da177e4SLinus Torvalds U64 NoSEEPROMWWNN; /* 08h */ 18001da177e4SLinus Torvalds U64 NoSEEPROMWWPN; /* 10h */ 18011da177e4SLinus Torvalds U8 HardALPA; /* 18h */ 18021da177e4SLinus Torvalds U8 LinkConfig; /* 19h */ 18031da177e4SLinus Torvalds U8 TopologyConfig; /* 1Ah */ 18041da177e4SLinus Torvalds U8 AltConnector; /* 1Bh */ 18051da177e4SLinus Torvalds U8 NumRequestedAliases; /* 1Ch */ 18061da177e4SLinus Torvalds U8 RR_TOV; /* 1Dh */ 18071da177e4SLinus Torvalds U8 InitiatorDeviceTimeout; /* 1Eh */ 18081da177e4SLinus Torvalds U8 InitiatorIoPendTimeout; /* 1Fh */ 1809c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1, 18101da177e4SLinus Torvalds FCPortPage1_t, MPI_POINTER pFCPortPage1_t; 18111da177e4SLinus Torvalds 18121da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_PAGEVERSION (0x06) 18131da177e4SLinus Torvalds 18141da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000) 18151da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000) 18161da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_FLAGS_FORCE_USE_NOSEEPROM_WWNS (0x02000000) 18171da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS (0x01000000) 18181da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_FLAGS_TARGET_MODE_OXID (0x00800000) 18191da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_FLAGS_PORT_OFFLINE (0x00400000) 18201da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK (0x00200000) 1821c1a71d1cSMoore, Eric Dean #define MPI_FCPORTPAGE1_FLAGS_TARGET_LARGE_CDB_ENABLE (0x00000080) 18221da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_FLAGS_MASK_RR_TOV_UNITS (0x00000070) 18231da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_FLAGS_SUPPRESS_PROT_REG (0x00000008) 18241da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_FLAGS_PLOGI_ON_LOGO (0x00000004) 18251da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_FLAGS_MAINTAIN_LOGINS (0x00000002) 18261da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001) 18271da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000) 18281da177e4SLinus Torvalds 18291da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000) 18301da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28) 18311da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 18321da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 18331da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 18341da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 18351da177e4SLinus Torvalds 18361da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_FLAGS_NONE_RR_TOV_UNITS (0x00000000) 18371da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_FLAGS_THOUSANDTH_RR_TOV_UNITS (0x00000010) 18381da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_FLAGS_TENTH_RR_TOV_UNITS (0x00000030) 18391da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_FLAGS_TEN_RR_TOV_UNITS (0x00000050) 18401da177e4SLinus Torvalds 18411da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF) 18421da177e4SLinus Torvalds 18431da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F) 18441da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00) 18451da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01) 18461da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02) 18471da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03) 18481da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F) 18491da177e4SLinus Torvalds 18501da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F) 18511da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01) 18521da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02) 18531da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F) 18541da177e4SLinus Torvalds 18551da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_ALT_CONN_UNKNOWN (0x00) 18561da177e4SLinus Torvalds 18571da177e4SLinus Torvalds #define MPI_FCPORTPAGE1_INITIATOR_DEV_TIMEOUT_MASK (0x7F) 1858c1a71d1cSMoore, Eric Dean #define MPI_FCPORTPAGE1_INITIATOR_DEV_UNIT_16 (0x80) 18591da177e4SLinus Torvalds 18601da177e4SLinus Torvalds 18611da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_FC_PORT_2 18621da177e4SLinus Torvalds { 1863c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 18641da177e4SLinus Torvalds U8 NumberActive; /* 04h */ 18651da177e4SLinus Torvalds U8 ALPA[127]; /* 05h */ 1866c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2, 18671da177e4SLinus Torvalds FCPortPage2_t, MPI_POINTER pFCPortPage2_t; 18681da177e4SLinus Torvalds 18691da177e4SLinus Torvalds #define MPI_FCPORTPAGE2_PAGEVERSION (0x01) 18701da177e4SLinus Torvalds 18711da177e4SLinus Torvalds 18721da177e4SLinus Torvalds typedef struct _WWN_FORMAT 18731da177e4SLinus Torvalds { 18741da177e4SLinus Torvalds U64 WWNN; /* 00h */ 18751da177e4SLinus Torvalds U64 WWPN; /* 08h */ 18761da177e4SLinus Torvalds } WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT, 18771da177e4SLinus Torvalds WWNFormat, MPI_POINTER pWWNFormat; 18781da177e4SLinus Torvalds 18791da177e4SLinus Torvalds typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID 18801da177e4SLinus Torvalds { 18811da177e4SLinus Torvalds WWN_FORMAT WWN; 18821da177e4SLinus Torvalds U32 Did; 18831da177e4SLinus Torvalds } FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID, 18841da177e4SLinus Torvalds PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t; 18851da177e4SLinus Torvalds 18861da177e4SLinus Torvalds typedef struct _FC_PORT_PERSISTENT 18871da177e4SLinus Torvalds { 18881da177e4SLinus Torvalds FC_PORT_PERSISTENT_PHYSICAL_ID PhysicalIdentifier; /* 00h */ 18891da177e4SLinus Torvalds U8 TargetID; /* 10h */ 18901da177e4SLinus Torvalds U8 Bus; /* 11h */ 18911da177e4SLinus Torvalds U16 Flags; /* 12h */ 18921da177e4SLinus Torvalds } FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT, 18931da177e4SLinus Torvalds PersistentData_t, MPI_POINTER pPersistentData_t; 18941da177e4SLinus Torvalds 18951da177e4SLinus Torvalds #define MPI_PERSISTENT_FLAGS_SHIFT (16) 18961da177e4SLinus Torvalds #define MPI_PERSISTENT_FLAGS_ENTRY_VALID (0x0001) 18971da177e4SLinus Torvalds #define MPI_PERSISTENT_FLAGS_SCAN_ID (0x0002) 18981da177e4SLinus Torvalds #define MPI_PERSISTENT_FLAGS_SCAN_LUNS (0x0004) 18991da177e4SLinus Torvalds #define MPI_PERSISTENT_FLAGS_BOOT_DEVICE (0x0008) 19001da177e4SLinus Torvalds #define MPI_PERSISTENT_FLAGS_BY_DID (0x0080) 19011da177e4SLinus Torvalds 19021da177e4SLinus Torvalds /* 19031da177e4SLinus Torvalds * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 19041da177e4SLinus Torvalds * one and check Header.PageLength at runtime. 19051da177e4SLinus Torvalds */ 19061da177e4SLinus Torvalds #ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX 19071da177e4SLinus Torvalds #define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1) 19081da177e4SLinus Torvalds #endif 19091da177e4SLinus Torvalds 19101da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_FC_PORT_3 19111da177e4SLinus Torvalds { 1912c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 19131da177e4SLinus Torvalds FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */ 1914c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3, 19151da177e4SLinus Torvalds FCPortPage3_t, MPI_POINTER pFCPortPage3_t; 19161da177e4SLinus Torvalds 19171da177e4SLinus Torvalds #define MPI_FCPORTPAGE3_PAGEVERSION (0x01) 19181da177e4SLinus Torvalds 19191da177e4SLinus Torvalds 19201da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_FC_PORT_4 19211da177e4SLinus Torvalds { 1922c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 19231da177e4SLinus Torvalds U32 PortFlags; /* 04h */ 19241da177e4SLinus Torvalds U32 PortSettings; /* 08h */ 1925c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4, 19261da177e4SLinus Torvalds FCPortPage4_t, MPI_POINTER pFCPortPage4_t; 19271da177e4SLinus Torvalds 19281da177e4SLinus Torvalds #define MPI_FCPORTPAGE4_PAGEVERSION (0x00) 19291da177e4SLinus Torvalds 19301da177e4SLinus Torvalds #define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 19311da177e4SLinus Torvalds 19321da177e4SLinus Torvalds #define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030) 19331da177e4SLinus Torvalds #define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000) 19341da177e4SLinus Torvalds #define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA (0x00000010) 19351da177e4SLinus Torvalds #define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA (0x00000020) 19361da177e4SLinus Torvalds #define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA (0x00000030) 19371da177e4SLinus Torvalds #define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA (0x000000C0) 19381da177e4SLinus Torvalds #define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00) 19391da177e4SLinus Torvalds 19401da177e4SLinus Torvalds 19411da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO 19421da177e4SLinus Torvalds { 19431da177e4SLinus Torvalds U8 Flags; /* 00h */ 19441da177e4SLinus Torvalds U8 AliasAlpa; /* 01h */ 19451da177e4SLinus Torvalds U16 Reserved; /* 02h */ 19461da177e4SLinus Torvalds U64 AliasWWNN; /* 04h */ 19471da177e4SLinus Torvalds U64 AliasWWPN; /* 0Ch */ 1948c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 19491da177e4SLinus Torvalds MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 19501da177e4SLinus Torvalds FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t; 19511da177e4SLinus Torvalds 19521da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_FC_PORT_5 19531da177e4SLinus Torvalds { 1954c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 1955c1a71d1cSMoore, Eric Dean CONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo; /* 04h */ 1956c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5, 19571da177e4SLinus Torvalds FCPortPage5_t, MPI_POINTER pFCPortPage5_t; 19581da177e4SLinus Torvalds 19591da177e4SLinus Torvalds #define MPI_FCPORTPAGE5_PAGEVERSION (0x02) 19601da177e4SLinus Torvalds 19611da177e4SLinus Torvalds #define MPI_FCPORTPAGE5_FLAGS_ALPA_ACQUIRED (0x01) 19621da177e4SLinus Torvalds #define MPI_FCPORTPAGE5_FLAGS_HARD_ALPA (0x02) 19631da177e4SLinus Torvalds #define MPI_FCPORTPAGE5_FLAGS_HARD_WWNN (0x04) 19641da177e4SLinus Torvalds #define MPI_FCPORTPAGE5_FLAGS_HARD_WWPN (0x08) 19651da177e4SLinus Torvalds #define MPI_FCPORTPAGE5_FLAGS_DISABLE (0x10) 19661da177e4SLinus Torvalds 19671da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_FC_PORT_6 19681da177e4SLinus Torvalds { 1969c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 19701da177e4SLinus Torvalds U32 Reserved; /* 04h */ 19711da177e4SLinus Torvalds U64 TimeSinceReset; /* 08h */ 19721da177e4SLinus Torvalds U64 TxFrames; /* 10h */ 19731da177e4SLinus Torvalds U64 RxFrames; /* 18h */ 19741da177e4SLinus Torvalds U64 TxWords; /* 20h */ 19751da177e4SLinus Torvalds U64 RxWords; /* 28h */ 19761da177e4SLinus Torvalds U64 LipCount; /* 30h */ 19771da177e4SLinus Torvalds U64 NosCount; /* 38h */ 19781da177e4SLinus Torvalds U64 ErrorFrames; /* 40h */ 19791da177e4SLinus Torvalds U64 DumpedFrames; /* 48h */ 19801da177e4SLinus Torvalds U64 LinkFailureCount; /* 50h */ 19811da177e4SLinus Torvalds U64 LossOfSyncCount; /* 58h */ 19821da177e4SLinus Torvalds U64 LossOfSignalCount; /* 60h */ 198394e989deSColin Ian King U64 PrimitiveSeqErrCount; /* 68h */ 19841da177e4SLinus Torvalds U64 InvalidTxWordCount; /* 70h */ 19851da177e4SLinus Torvalds U64 InvalidCrcCount; /* 78h */ 19861da177e4SLinus Torvalds U64 FcpInitiatorIoCount; /* 80h */ 1987c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6, 19881da177e4SLinus Torvalds FCPortPage6_t, MPI_POINTER pFCPortPage6_t; 19891da177e4SLinus Torvalds 19901da177e4SLinus Torvalds #define MPI_FCPORTPAGE6_PAGEVERSION (0x00) 19911da177e4SLinus Torvalds 19921da177e4SLinus Torvalds 19931da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_FC_PORT_7 19941da177e4SLinus Torvalds { 1995c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 19961da177e4SLinus Torvalds U32 Reserved; /* 04h */ 19971da177e4SLinus Torvalds U8 PortSymbolicName[256]; /* 08h */ 1998c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7, 19991da177e4SLinus Torvalds FCPortPage7_t, MPI_POINTER pFCPortPage7_t; 20001da177e4SLinus Torvalds 20011da177e4SLinus Torvalds #define MPI_FCPORTPAGE7_PAGEVERSION (0x00) 20021da177e4SLinus Torvalds 20031da177e4SLinus Torvalds 20041da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_FC_PORT_8 20051da177e4SLinus Torvalds { 2006c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 20071da177e4SLinus Torvalds U32 BitVector[8]; /* 04h */ 2008c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8, 20091da177e4SLinus Torvalds FCPortPage8_t, MPI_POINTER pFCPortPage8_t; 20101da177e4SLinus Torvalds 20111da177e4SLinus Torvalds #define MPI_FCPORTPAGE8_PAGEVERSION (0x00) 20121da177e4SLinus Torvalds 20131da177e4SLinus Torvalds 20141da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_FC_PORT_9 20151da177e4SLinus Torvalds { 2016c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 20171da177e4SLinus Torvalds U32 Reserved; /* 04h */ 20181da177e4SLinus Torvalds U64 GlobalWWPN; /* 08h */ 20191da177e4SLinus Torvalds U64 GlobalWWNN; /* 10h */ 20201da177e4SLinus Torvalds U32 UnitType; /* 18h */ 20211da177e4SLinus Torvalds U32 PhysicalPortNumber; /* 1Ch */ 20221da177e4SLinus Torvalds U32 NumAttachedNodes; /* 20h */ 20231da177e4SLinus Torvalds U16 IPVersion; /* 24h */ 20241da177e4SLinus Torvalds U16 UDPPortNumber; /* 26h */ 20251da177e4SLinus Torvalds U8 IPAddress[16]; /* 28h */ 20261da177e4SLinus Torvalds U16 Reserved1; /* 38h */ 20271da177e4SLinus Torvalds U16 TopologyDiscoveryFlags; /* 3Ah */ 2028c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9, 20291da177e4SLinus Torvalds FCPortPage9_t, MPI_POINTER pFCPortPage9_t; 20301da177e4SLinus Torvalds 20311da177e4SLinus Torvalds #define MPI_FCPORTPAGE9_PAGEVERSION (0x00) 20321da177e4SLinus Torvalds 20331da177e4SLinus Torvalds 20341da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA 20351da177e4SLinus Torvalds { 20361da177e4SLinus Torvalds U8 Id; /* 10h */ 20371da177e4SLinus Torvalds U8 ExtId; /* 11h */ 20381da177e4SLinus Torvalds U8 Connector; /* 12h */ 20391da177e4SLinus Torvalds U8 Transceiver[8]; /* 13h */ 20401da177e4SLinus Torvalds U8 Encoding; /* 1Bh */ 20411da177e4SLinus Torvalds U8 BitRate_100mbs; /* 1Ch */ 20421da177e4SLinus Torvalds U8 Reserved1; /* 1Dh */ 20431da177e4SLinus Torvalds U8 Length9u_km; /* 1Eh */ 20441da177e4SLinus Torvalds U8 Length9u_100m; /* 1Fh */ 20451da177e4SLinus Torvalds U8 Length50u_10m; /* 20h */ 20461da177e4SLinus Torvalds U8 Length62p5u_10m; /* 21h */ 20471da177e4SLinus Torvalds U8 LengthCopper_m; /* 22h */ 20481da177e4SLinus Torvalds U8 Reseverved2; /* 22h */ 20491da177e4SLinus Torvalds U8 VendorName[16]; /* 24h */ 20501da177e4SLinus Torvalds U8 Reserved3; /* 34h */ 20511da177e4SLinus Torvalds U8 VendorOUI[3]; /* 35h */ 20521da177e4SLinus Torvalds U8 VendorPN[16]; /* 38h */ 20531da177e4SLinus Torvalds U8 VendorRev[4]; /* 48h */ 2054c1a71d1cSMoore, Eric Dean U16 Wavelength; /* 4Ch */ 2055c1a71d1cSMoore, Eric Dean U8 Reserved4; /* 4Eh */ 20561da177e4SLinus Torvalds U8 CC_BASE; /* 4Fh */ 2057c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA, 20581da177e4SLinus Torvalds MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA, 20591da177e4SLinus Torvalds FCPortPage10BaseSfpData_t, MPI_POINTER pFCPortPage10BaseSfpData_t; 20601da177e4SLinus Torvalds 20611da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_ID_UNKNOWN (0x00) 20621da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_ID_GBIC (0x01) 20631da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_ID_FIXED (0x02) 20641da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_ID_SFP (0x03) 20651da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_ID_SFP_MIN (0x04) 20661da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_ID_SFP_MAX (0x7F) 20671da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_ID_VEND_SPEC_MASK (0x80) 20681da177e4SLinus Torvalds 20691da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_EXTID_UNKNOWN (0x00) 20701da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_EXTID_MODDEF1 (0x01) 20711da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_EXTID_MODDEF2 (0x02) 20721da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_EXTID_MODDEF3 (0x03) 20731da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_EXTID_SEEPROM (0x04) 20741da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_EXTID_MODDEF5 (0x05) 20751da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_EXTID_MODDEF6 (0x06) 20761da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_EXTID_MODDEF7 (0x07) 20771da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_EXTID_VNDSPC_MASK (0x80) 20781da177e4SLinus Torvalds 20791da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_CONN_UNKNOWN (0x00) 20801da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_CONN_SC (0x01) 20811da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_CONN_COPPER1 (0x02) 20821da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_CONN_COPPER2 (0x03) 20831da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_CONN_BNC_TNC (0x04) 20841da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_CONN_COAXIAL (0x05) 20851da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_CONN_FIBERJACK (0x06) 20861da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_CONN_LC (0x07) 20871da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_CONN_MT_RJ (0x08) 20881da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_CONN_MU (0x09) 20891da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_CONN_SG (0x0A) 20901da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_CONN_OPT_PIGT (0x0B) 20911da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_CONN_RSV1_MIN (0x0C) 20921da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_CONN_RSV1_MAX (0x1F) 20931da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_CONN_HSSDC_II (0x20) 20941da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_CONN_CPR_PIGT (0x21) 20951da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_CONN_RSV2_MIN (0x22) 20961da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_CONN_RSV2_MAX (0x7F) 20971da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_CONN_VNDSPC_MASK (0x80) 20981da177e4SLinus Torvalds 20991da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_ENCODE_UNSPEC (0x00) 21001da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_ENCODE_8B10B (0x01) 21011da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_ENCODE_4B5B (0x02) 21021da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_ENCODE_NRZ (0x03) 21031da177e4SLinus Torvalds #define MPI_FCPORT10_BASE_ENCODE_MANCHESTER (0x04) 21041da177e4SLinus Torvalds 21051da177e4SLinus Torvalds 21061da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA 21071da177e4SLinus Torvalds { 21081da177e4SLinus Torvalds U8 Options[2]; /* 50h */ 21091da177e4SLinus Torvalds U8 BitRateMax; /* 52h */ 21101da177e4SLinus Torvalds U8 BitRateMin; /* 53h */ 21111da177e4SLinus Torvalds U8 VendorSN[16]; /* 54h */ 21121da177e4SLinus Torvalds U8 DateCode[8]; /* 64h */ 2113c1a71d1cSMoore, Eric Dean U8 DiagMonitoringType; /* 6Ch */ 2114c1a71d1cSMoore, Eric Dean U8 EnhancedOptions; /* 6Dh */ 2115c1a71d1cSMoore, Eric Dean U8 SFF8472Compliance; /* 6Eh */ 21161da177e4SLinus Torvalds U8 CC_EXT; /* 6Fh */ 2117c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA, 21181da177e4SLinus Torvalds MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA, 21191da177e4SLinus Torvalds FCPortPage10ExtendedSfpData_t, MPI_POINTER pFCPortPage10ExtendedSfpData_t; 21201da177e4SLinus Torvalds 21211da177e4SLinus Torvalds #define MPI_FCPORT10_EXT_OPTION1_RATESEL (0x20) 21221da177e4SLinus Torvalds #define MPI_FCPORT10_EXT_OPTION1_TX_DISABLE (0x10) 21231da177e4SLinus Torvalds #define MPI_FCPORT10_EXT_OPTION1_TX_FAULT (0x08) 21241da177e4SLinus Torvalds #define MPI_FCPORT10_EXT_OPTION1_LOS_INVERT (0x04) 21251da177e4SLinus Torvalds #define MPI_FCPORT10_EXT_OPTION1_LOS (0x02) 21261da177e4SLinus Torvalds 21271da177e4SLinus Torvalds 21281da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_FC_PORT_10 21291da177e4SLinus Torvalds { 2130c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 21311da177e4SLinus Torvalds U8 Flags; /* 04h */ 21321da177e4SLinus Torvalds U8 Reserved1; /* 05h */ 21331da177e4SLinus Torvalds U16 Reserved2; /* 06h */ 21341da177e4SLinus Torvalds U32 HwConfig1; /* 08h */ 21351da177e4SLinus Torvalds U32 HwConfig2; /* 0Ch */ 2136c1a71d1cSMoore, Eric Dean CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA Base; /* 10h */ 2137c1a71d1cSMoore, Eric Dean CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA Extended; /* 50h */ 21381da177e4SLinus Torvalds U8 VendorSpecific[32]; /* 70h */ 2139c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_FC_PORT_10, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10, 21401da177e4SLinus Torvalds FCPortPage10_t, MPI_POINTER pFCPortPage10_t; 21411da177e4SLinus Torvalds 2142c1a71d1cSMoore, Eric Dean #define MPI_FCPORTPAGE10_PAGEVERSION (0x01) 21431da177e4SLinus Torvalds 21441da177e4SLinus Torvalds /* standard MODDEF pin definitions (from GBIC spec.) */ 21451da177e4SLinus Torvalds #define MPI_FCPORTPAGE10_FLAGS_MODDEF_MASK (0x00000007) 21461da177e4SLinus Torvalds #define MPI_FCPORTPAGE10_FLAGS_MODDEF2 (0x00000001) 21471da177e4SLinus Torvalds #define MPI_FCPORTPAGE10_FLAGS_MODDEF1 (0x00000002) 21481da177e4SLinus Torvalds #define MPI_FCPORTPAGE10_FLAGS_MODDEF0 (0x00000004) 21491da177e4SLinus Torvalds #define MPI_FCPORTPAGE10_FLAGS_MODDEF_NOGBIC (0x00000007) 21501da177e4SLinus Torvalds #define MPI_FCPORTPAGE10_FLAGS_MODDEF_CPR_IEEE_CX (0x00000006) 21511da177e4SLinus Torvalds #define MPI_FCPORTPAGE10_FLAGS_MODDEF_COPPER (0x00000005) 21521da177e4SLinus Torvalds #define MPI_FCPORTPAGE10_FLAGS_MODDEF_OPTICAL_LW (0x00000004) 21531da177e4SLinus Torvalds #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SEEPROM (0x00000003) 21541da177e4SLinus Torvalds #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SW_OPTICAL (0x00000002) 21551da177e4SLinus Torvalds #define MPI_FCPORTPAGE10_FLAGS_MODDEF_LX_IEEE_OPT_LW (0x00000001) 21561da177e4SLinus Torvalds #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SX_IEEE_OPT_SW (0x00000000) 21571da177e4SLinus Torvalds 21581da177e4SLinus Torvalds #define MPI_FCPORTPAGE10_FLAGS_CC_BASE_OK (0x00000010) 21591da177e4SLinus Torvalds #define MPI_FCPORTPAGE10_FLAGS_CC_EXT_OK (0x00000020) 21601da177e4SLinus Torvalds 21611da177e4SLinus Torvalds 21621da177e4SLinus Torvalds /**************************************************************************** 21631da177e4SLinus Torvalds * FC Device Config Pages 21641da177e4SLinus Torvalds ****************************************************************************/ 21651da177e4SLinus Torvalds 21661da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_FC_DEVICE_0 21671da177e4SLinus Torvalds { 2168c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 21691da177e4SLinus Torvalds U64 WWNN; /* 04h */ 21701da177e4SLinus Torvalds U64 WWPN; /* 0Ch */ 21711da177e4SLinus Torvalds U32 PortIdentifier; /* 14h */ 21721da177e4SLinus Torvalds U8 Protocol; /* 18h */ 21731da177e4SLinus Torvalds U8 Flags; /* 19h */ 21741da177e4SLinus Torvalds U16 BBCredit; /* 1Ah */ 21751da177e4SLinus Torvalds U16 MaxRxFrameSize; /* 1Ch */ 21761da177e4SLinus Torvalds U8 ADISCHardALPA; /* 1Eh */ 21771da177e4SLinus Torvalds U8 PortNumber; /* 1Fh */ 21781da177e4SLinus Torvalds U8 FcPhLowestVersion; /* 20h */ 21791da177e4SLinus Torvalds U8 FcPhHighestVersion; /* 21h */ 21801da177e4SLinus Torvalds U8 CurrentTargetID; /* 22h */ 21811da177e4SLinus Torvalds U8 CurrentBus; /* 23h */ 2182c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0, 21831da177e4SLinus Torvalds FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t; 21841da177e4SLinus Torvalds 21851da177e4SLinus Torvalds #define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x03) 21861da177e4SLinus Torvalds 21871da177e4SLinus Torvalds #define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01) 21881da177e4SLinus Torvalds #define MPI_FC_DEVICE_PAGE0_FLAGS_PLOGI_INVALID (0x02) 21891da177e4SLinus Torvalds #define MPI_FC_DEVICE_PAGE0_FLAGS_PRLI_INVALID (0x04) 21901da177e4SLinus Torvalds 21911da177e4SLinus Torvalds #define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01) 21921da177e4SLinus Torvalds #define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02) 21931da177e4SLinus Torvalds #define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04) 21941da177e4SLinus Torvalds #define MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY (0x08) 21951da177e4SLinus Torvalds 21961da177e4SLinus Torvalds #define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK) 21971da177e4SLinus Torvalds #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK) 21981da177e4SLinus Torvalds #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID) 21991da177e4SLinus Torvalds #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID) 22001da177e4SLinus Torvalds #define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK) 22011da177e4SLinus Torvalds #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK) 22021da177e4SLinus Torvalds #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT) 22031da177e4SLinus Torvalds #define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK) 22041da177e4SLinus Torvalds 22051da177e4SLinus Torvalds #define MPI_FC_DEVICE_PAGE0_HARD_ALPA_UNKNOWN (0xFF) 22061da177e4SLinus Torvalds 22071da177e4SLinus Torvalds /**************************************************************************** 22081da177e4SLinus Torvalds * RAID Volume Config Pages 22091da177e4SLinus Torvalds ****************************************************************************/ 22101da177e4SLinus Torvalds 22111da177e4SLinus Torvalds typedef struct _RAID_VOL0_PHYS_DISK 22121da177e4SLinus Torvalds { 22131da177e4SLinus Torvalds U16 Reserved; /* 00h */ 22141da177e4SLinus Torvalds U8 PhysDiskMap; /* 02h */ 22151da177e4SLinus Torvalds U8 PhysDiskNum; /* 03h */ 22161da177e4SLinus Torvalds } RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK, 22171da177e4SLinus Torvalds RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t; 22181da177e4SLinus Torvalds 22191da177e4SLinus Torvalds #define MPI_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 22201da177e4SLinus Torvalds #define MPI_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 22211da177e4SLinus Torvalds 22221da177e4SLinus Torvalds typedef struct _RAID_VOL0_STATUS 22231da177e4SLinus Torvalds { 22241da177e4SLinus Torvalds U8 Flags; /* 00h */ 22251da177e4SLinus Torvalds U8 State; /* 01h */ 22261da177e4SLinus Torvalds U16 Reserved; /* 02h */ 22271da177e4SLinus Torvalds } RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS, 22281da177e4SLinus Torvalds RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t; 22291da177e4SLinus Torvalds 22301da177e4SLinus Torvalds /* RAID Volume Page 0 VolumeStatus defines */ 22311da177e4SLinus Torvalds #define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01) 22321da177e4SLinus Torvalds #define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02) 22331da177e4SLinus Torvalds #define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04) 22341da177e4SLinus Torvalds #define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x08) 2235ccf3b7bdSChristoph Hellwig #define MPI_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x10) 22361da177e4SLinus Torvalds 22371da177e4SLinus Torvalds #define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00) 22381da177e4SLinus Torvalds #define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01) 22391da177e4SLinus Torvalds #define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02) 2240c1a71d1cSMoore, Eric Dean #define MPI_RAIDVOL0_STATUS_STATE_MISSING (0x03) 22411da177e4SLinus Torvalds 22421da177e4SLinus Torvalds typedef struct _RAID_VOL0_SETTINGS 22431da177e4SLinus Torvalds { 22441da177e4SLinus Torvalds U16 Settings; /* 00h */ 22451da177e4SLinus Torvalds U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 22461da177e4SLinus Torvalds U8 Reserved; /* 02h */ 22471da177e4SLinus Torvalds } RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS, 22481da177e4SLinus Torvalds RaidVol0Settings, MPI_POINTER pRaidVol0Settings; 22491da177e4SLinus Torvalds 22501da177e4SLinus Torvalds /* RAID Volume Page 0 VolumeSettings defines */ 22511da177e4SLinus Torvalds #define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001) 22521da177e4SLinus Torvalds #define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002) 22531da177e4SLinus Torvalds #define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004) 22541da177e4SLinus Torvalds #define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008) 2255c1a71d1cSMoore, Eric Dean #define MPI_RAIDVOL0_SETTING_FAST_DATA_SCRUBBING_0102 (0x0020) /* obsolete */ 2256eae225ebSEric Moore 2257eae225ebSEric Moore #define MPI_RAIDVOL0_SETTING_MASK_METADATA_SIZE (0x00C0) 2258eae225ebSEric Moore #define MPI_RAIDVOL0_SETTING_64MB_METADATA_SIZE (0x0000) 2259eae225ebSEric Moore #define MPI_RAIDVOL0_SETTING_512MB_METADATA_SIZE (0x0040) 2260eae225ebSEric Moore 22611da177e4SLinus Torvalds #define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010) 22621da177e4SLinus Torvalds #define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000) 22631da177e4SLinus Torvalds 22641da177e4SLinus Torvalds /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 22651da177e4SLinus Torvalds #define MPI_RAID_HOT_SPARE_POOL_0 (0x01) 22661da177e4SLinus Torvalds #define MPI_RAID_HOT_SPARE_POOL_1 (0x02) 22671da177e4SLinus Torvalds #define MPI_RAID_HOT_SPARE_POOL_2 (0x04) 22681da177e4SLinus Torvalds #define MPI_RAID_HOT_SPARE_POOL_3 (0x08) 22691da177e4SLinus Torvalds #define MPI_RAID_HOT_SPARE_POOL_4 (0x10) 22701da177e4SLinus Torvalds #define MPI_RAID_HOT_SPARE_POOL_5 (0x20) 22711da177e4SLinus Torvalds #define MPI_RAID_HOT_SPARE_POOL_6 (0x40) 22721da177e4SLinus Torvalds #define MPI_RAID_HOT_SPARE_POOL_7 (0x80) 22731da177e4SLinus Torvalds 22741da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_RAID_VOL_0 22751da177e4SLinus Torvalds { 2276c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 22771da177e4SLinus Torvalds U8 VolumeID; /* 04h */ 22781da177e4SLinus Torvalds U8 VolumeBus; /* 05h */ 22791da177e4SLinus Torvalds U8 VolumeIOC; /* 06h */ 22801da177e4SLinus Torvalds U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */ 22811da177e4SLinus Torvalds RAID_VOL0_STATUS VolumeStatus; /* 08h */ 22821da177e4SLinus Torvalds RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */ 22831da177e4SLinus Torvalds U32 MaxLBA; /* 10h */ 22842076eb6aSEric Moore U32 MaxLBAHigh; /* 14h */ 22851da177e4SLinus Torvalds U32 StripeSize; /* 18h */ 22861da177e4SLinus Torvalds U32 Reserved2; /* 1Ch */ 22871da177e4SLinus Torvalds U32 Reserved3; /* 20h */ 22881da177e4SLinus Torvalds U8 NumPhysDisks; /* 24h */ 2289c1a71d1cSMoore, Eric Dean U8 DataScrubRate; /* 25h */ 2290c1a71d1cSMoore, Eric Dean U8 ResyncRate; /* 26h */ 2291c1a71d1cSMoore, Eric Dean U8 InactiveStatus; /* 27h */ 22928e76c9c9SKees Cook RAID_VOL0_PHYS_DISK PhysDisk[] __counted_by(NumPhysDisks); /* 28h */ 2293c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0, 22941da177e4SLinus Torvalds RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t; 22951da177e4SLinus Torvalds 2296eae225ebSEric Moore #define MPI_RAIDVOLPAGE0_PAGEVERSION (0x07) 2297c1a71d1cSMoore, Eric Dean 2298c1a71d1cSMoore, Eric Dean /* values for RAID Volume Page 0 InactiveStatus field */ 2299c1a71d1cSMoore, Eric Dean #define MPI_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 2300c1a71d1cSMoore, Eric Dean #define MPI_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 2301c1a71d1cSMoore, Eric Dean #define MPI_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 2302c1a71d1cSMoore, Eric Dean #define MPI_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 2303c1a71d1cSMoore, Eric Dean #define MPI_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 2304c1a71d1cSMoore, Eric Dean #define MPI_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 2305c1a71d1cSMoore, Eric Dean #define MPI_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 2306c1a71d1cSMoore, Eric Dean 2307c1a71d1cSMoore, Eric Dean 2308c1a71d1cSMoore, Eric Dean typedef struct _CONFIG_PAGE_RAID_VOL_1 2309c1a71d1cSMoore, Eric Dean { 2310c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 2311d16291b1SEric Moore U8 VolumeID; /* 04h */ 2312d16291b1SEric Moore U8 VolumeBus; /* 05h */ 2313d16291b1SEric Moore U8 VolumeIOC; /* 06h */ 2314d16291b1SEric Moore U8 Reserved0; /* 07h */ 2315d16291b1SEric Moore U8 GUID[24]; /* 08h */ 2316c1a71d1cSMoore, Eric Dean U8 Name[32]; /* 20h */ 2317c1a71d1cSMoore, Eric Dean U64 WWID; /* 40h */ 2318c1a71d1cSMoore, Eric Dean U32 Reserved1; /* 48h */ 2319c1a71d1cSMoore, Eric Dean U32 Reserved2; /* 4Ch */ 2320c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_RAID_VOL_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_1, 2321c1a71d1cSMoore, Eric Dean RaidVolumePage1_t, MPI_POINTER pRaidVolumePage1_t; 2322c1a71d1cSMoore, Eric Dean 2323c1a71d1cSMoore, Eric Dean #define MPI_RAIDVOLPAGE1_PAGEVERSION (0x01) 23241da177e4SLinus Torvalds 23251da177e4SLinus Torvalds 23261da177e4SLinus Torvalds /**************************************************************************** 23271da177e4SLinus Torvalds * RAID Physical Disk Config Pages 23281da177e4SLinus Torvalds ****************************************************************************/ 23291da177e4SLinus Torvalds 23301da177e4SLinus Torvalds typedef struct _RAID_PHYS_DISK0_ERROR_DATA 23311da177e4SLinus Torvalds { 23321da177e4SLinus Torvalds U8 ErrorCdbByte; /* 00h */ 23331da177e4SLinus Torvalds U8 ErrorSenseKey; /* 01h */ 23341da177e4SLinus Torvalds U16 Reserved; /* 02h */ 23351da177e4SLinus Torvalds U16 ErrorCount; /* 04h */ 23361da177e4SLinus Torvalds U8 ErrorASC; /* 06h */ 23371da177e4SLinus Torvalds U8 ErrorASCQ; /* 07h */ 23381da177e4SLinus Torvalds U16 SmartCount; /* 08h */ 23391da177e4SLinus Torvalds U8 SmartASC; /* 0Ah */ 23401da177e4SLinus Torvalds U8 SmartASCQ; /* 0Bh */ 23411da177e4SLinus Torvalds } RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA, 23421da177e4SLinus Torvalds RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t; 23431da177e4SLinus Torvalds 23441da177e4SLinus Torvalds typedef struct _RAID_PHYS_DISK_INQUIRY_DATA 23451da177e4SLinus Torvalds { 23461da177e4SLinus Torvalds U8 VendorID[8]; /* 00h */ 23471da177e4SLinus Torvalds U8 ProductID[16]; /* 08h */ 23481da177e4SLinus Torvalds U8 ProductRevLevel[4]; /* 18h */ 23491da177e4SLinus Torvalds U8 Info[32]; /* 1Ch */ 23501da177e4SLinus Torvalds } RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA, 23511da177e4SLinus Torvalds RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData; 23521da177e4SLinus Torvalds 23531da177e4SLinus Torvalds typedef struct _RAID_PHYS_DISK0_SETTINGS 23541da177e4SLinus Torvalds { 23551da177e4SLinus Torvalds U8 SepID; /* 00h */ 23561da177e4SLinus Torvalds U8 SepBus; /* 01h */ 23571da177e4SLinus Torvalds U8 HotSparePool; /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 23581da177e4SLinus Torvalds U8 PhysDiskSettings; /* 03h */ 23591da177e4SLinus Torvalds } RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS, 23601da177e4SLinus Torvalds RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t; 23611da177e4SLinus Torvalds 23621da177e4SLinus Torvalds typedef struct _RAID_PHYS_DISK0_STATUS 23631da177e4SLinus Torvalds { 23641da177e4SLinus Torvalds U8 Flags; /* 00h */ 23651da177e4SLinus Torvalds U8 State; /* 01h */ 23661da177e4SLinus Torvalds U16 Reserved; /* 02h */ 23671da177e4SLinus Torvalds } RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS, 23681da177e4SLinus Torvalds RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t; 23691da177e4SLinus Torvalds 2370d16291b1SEric Moore /* RAID Physical Disk PhysDiskStatus flags */ 23711da177e4SLinus Torvalds 23721da177e4SLinus Torvalds #define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01) 23731da177e4SLinus Torvalds #define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02) 2374c1a71d1cSMoore, Eric Dean #define MPI_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x04) 2375ccf3b7bdSChristoph Hellwig #define MPI_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00) 2376ccf3b7bdSChristoph Hellwig #define MPI_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x08) 23771da177e4SLinus Torvalds 23781da177e4SLinus Torvalds #define MPI_PHYSDISK0_STATUS_ONLINE (0x00) 23791da177e4SLinus Torvalds #define MPI_PHYSDISK0_STATUS_MISSING (0x01) 23801da177e4SLinus Torvalds #define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02) 23811da177e4SLinus Torvalds #define MPI_PHYSDISK0_STATUS_FAILED (0x03) 23821da177e4SLinus Torvalds #define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04) 23831da177e4SLinus Torvalds #define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05) 23841da177e4SLinus Torvalds #define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06) 23851da177e4SLinus Torvalds #define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF) 23861da177e4SLinus Torvalds 23871da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0 23881da177e4SLinus Torvalds { 2389c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 23901da177e4SLinus Torvalds U8 PhysDiskID; /* 04h */ 23911da177e4SLinus Torvalds U8 PhysDiskBus; /* 05h */ 23921da177e4SLinus Torvalds U8 PhysDiskIOC; /* 06h */ 23931da177e4SLinus Torvalds U8 PhysDiskNum; /* 07h */ 23941da177e4SLinus Torvalds RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */ 23951da177e4SLinus Torvalds U32 Reserved1; /* 0Ch */ 2396c1a71d1cSMoore, Eric Dean U8 ExtDiskIdentifier[8]; /* 10h */ 23971da177e4SLinus Torvalds U8 DiskIdentifier[16]; /* 18h */ 23981da177e4SLinus Torvalds RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */ 23991da177e4SLinus Torvalds RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */ 24001da177e4SLinus Torvalds U32 MaxLBA; /* 68h */ 24011da177e4SLinus Torvalds RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */ 2402c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0, 24031da177e4SLinus Torvalds RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t; 24041da177e4SLinus Torvalds 2405ccf3b7bdSChristoph Hellwig #define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x02) 2406c1a71d1cSMoore, Eric Dean 2407c1a71d1cSMoore, Eric Dean 2408c1a71d1cSMoore, Eric Dean typedef struct _RAID_PHYS_DISK1_PATH 2409c1a71d1cSMoore, Eric Dean { 2410c1a71d1cSMoore, Eric Dean U8 PhysDiskID; /* 00h */ 2411c1a71d1cSMoore, Eric Dean U8 PhysDiskBus; /* 01h */ 2412c1a71d1cSMoore, Eric Dean U16 Reserved1; /* 02h */ 2413c1a71d1cSMoore, Eric Dean U64 WWID; /* 04h */ 2414c1a71d1cSMoore, Eric Dean U64 OwnerWWID; /* 0Ch */ 2415c1a71d1cSMoore, Eric Dean U8 OwnerIdentifier; /* 14h */ 2416c1a71d1cSMoore, Eric Dean U8 Reserved2; /* 15h */ 2417c1a71d1cSMoore, Eric Dean U16 Flags; /* 16h */ 2418c1a71d1cSMoore, Eric Dean } RAID_PHYS_DISK1_PATH, MPI_POINTER PTR_RAID_PHYS_DISK1_PATH, 2419c1a71d1cSMoore, Eric Dean RaidPhysDisk1Path_t, MPI_POINTER pRaidPhysDisk1Path_t; 2420c1a71d1cSMoore, Eric Dean 2421c1a71d1cSMoore, Eric Dean /* RAID Physical Disk Page 1 Flags field defines */ 2422c1a71d1cSMoore, Eric Dean #define MPI_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 2423c1a71d1cSMoore, Eric Dean #define MPI_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 2424c1a71d1cSMoore, Eric Dean 2425fd7a2533SKashyap, Desai 2426c1a71d1cSMoore, Eric Dean typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_1 2427c1a71d1cSMoore, Eric Dean { 2428c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 2429c1a71d1cSMoore, Eric Dean U8 NumPhysDiskPaths; /* 04h */ 2430c1a71d1cSMoore, Eric Dean U8 PhysDiskNum; /* 05h */ 2431c1a71d1cSMoore, Eric Dean U16 Reserved2; /* 06h */ 2432c1a71d1cSMoore, Eric Dean U32 Reserved1; /* 08h */ 2433dc8932fbSKees Cook RAID_PHYS_DISK1_PATH Path[] __counted_by(NumPhysDiskPaths);/* 0Ch */ 2434c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_RAID_PHYS_DISK_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_1, 2435c1a71d1cSMoore, Eric Dean RaidPhysDiskPage1_t, MPI_POINTER pRaidPhysDiskPage1_t; 2436c1a71d1cSMoore, Eric Dean 2437c1a71d1cSMoore, Eric Dean #define MPI_RAIDPHYSDISKPAGE1_PAGEVERSION (0x00) 24381da177e4SLinus Torvalds 24391da177e4SLinus Torvalds 24401da177e4SLinus Torvalds /**************************************************************************** 24411da177e4SLinus Torvalds * LAN Config Pages 24421da177e4SLinus Torvalds ****************************************************************************/ 24431da177e4SLinus Torvalds 24441da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_LAN_0 24451da177e4SLinus Torvalds { 24461da177e4SLinus Torvalds ConfigPageHeader_t Header; /* 00h */ 24471da177e4SLinus Torvalds U16 TxRxModes; /* 04h */ 24481da177e4SLinus Torvalds U16 Reserved; /* 06h */ 24491da177e4SLinus Torvalds U32 PacketPrePad; /* 08h */ 2450c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0, 24511da177e4SLinus Torvalds LANPage0_t, MPI_POINTER pLANPage0_t; 24521da177e4SLinus Torvalds 24531da177e4SLinus Torvalds #define MPI_LAN_PAGE0_PAGEVERSION (0x01) 24541da177e4SLinus Torvalds 24551da177e4SLinus Torvalds #define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000) 24561da177e4SLinus Torvalds #define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001) 24571da177e4SLinus Torvalds #define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001) 24581da177e4SLinus Torvalds 24591da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_LAN_1 24601da177e4SLinus Torvalds { 24611da177e4SLinus Torvalds ConfigPageHeader_t Header; /* 00h */ 24621da177e4SLinus Torvalds U16 Reserved; /* 04h */ 24631da177e4SLinus Torvalds U8 CurrentDeviceState; /* 06h */ 24641da177e4SLinus Torvalds U8 Reserved1; /* 07h */ 24651da177e4SLinus Torvalds U32 MinPacketSize; /* 08h */ 24661da177e4SLinus Torvalds U32 MaxPacketSize; /* 0Ch */ 24671da177e4SLinus Torvalds U32 HardwareAddressLow; /* 10h */ 24681da177e4SLinus Torvalds U32 HardwareAddressHigh; /* 14h */ 24691da177e4SLinus Torvalds U32 MaxWireSpeedLow; /* 18h */ 24701da177e4SLinus Torvalds U32 MaxWireSpeedHigh; /* 1Ch */ 24711da177e4SLinus Torvalds U32 BucketsRemaining; /* 20h */ 24721da177e4SLinus Torvalds U32 MaxReplySize; /* 24h */ 24731da177e4SLinus Torvalds U32 NegWireSpeedLow; /* 28h */ 24741da177e4SLinus Torvalds U32 NegWireSpeedHigh; /* 2Ch */ 2475c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1, 24761da177e4SLinus Torvalds LANPage1_t, MPI_POINTER pLANPage1_t; 24771da177e4SLinus Torvalds 24781da177e4SLinus Torvalds #define MPI_LAN_PAGE1_PAGEVERSION (0x03) 24791da177e4SLinus Torvalds 24801da177e4SLinus Torvalds #define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00) 24811da177e4SLinus Torvalds #define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01) 24821da177e4SLinus Torvalds 24831da177e4SLinus Torvalds 24841da177e4SLinus Torvalds /**************************************************************************** 24851da177e4SLinus Torvalds * Inband Config Pages 24861da177e4SLinus Torvalds ****************************************************************************/ 24871da177e4SLinus Torvalds 24881da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_INBAND_0 24891da177e4SLinus Torvalds { 2490c1a71d1cSMoore, Eric Dean CONFIG_PAGE_HEADER Header; /* 00h */ 24911da177e4SLinus Torvalds MPI_VERSION_FORMAT InbandVersion; /* 04h */ 24921da177e4SLinus Torvalds U16 MaximumBuffers; /* 08h */ 24931da177e4SLinus Torvalds U16 Reserved1; /* 0Ah */ 2494c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_INBAND_0, MPI_POINTER PTR_CONFIG_PAGE_INBAND_0, 24951da177e4SLinus Torvalds InbandPage0_t, MPI_POINTER pInbandPage0_t; 24961da177e4SLinus Torvalds 24971da177e4SLinus Torvalds #define MPI_INBAND_PAGEVERSION (0x00) 24981da177e4SLinus Torvalds 24991da177e4SLinus Torvalds 25001da177e4SLinus Torvalds 25011da177e4SLinus Torvalds /**************************************************************************** 25021da177e4SLinus Torvalds * SAS IO Unit Config Pages 25031da177e4SLinus Torvalds ****************************************************************************/ 25041da177e4SLinus Torvalds 25051da177e4SLinus Torvalds typedef struct _MPI_SAS_IO_UNIT0_PHY_DATA 25061da177e4SLinus Torvalds { 25071da177e4SLinus Torvalds U8 Port; /* 00h */ 25081da177e4SLinus Torvalds U8 PortFlags; /* 01h */ 25091da177e4SLinus Torvalds U8 PhyFlags; /* 02h */ 25101da177e4SLinus Torvalds U8 NegotiatedLinkRate; /* 03h */ 25111da177e4SLinus Torvalds U32 ControllerPhyDeviceInfo;/* 04h */ 25121da177e4SLinus Torvalds U16 AttachedDeviceHandle; /* 08h */ 25131da177e4SLinus Torvalds U16 ControllerDevHandle; /* 0Ah */ 2514c1a71d1cSMoore, Eric Dean U32 DiscoveryStatus; /* 0Ch */ 25151da177e4SLinus Torvalds } MPI_SAS_IO_UNIT0_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT0_PHY_DATA, 25161da177e4SLinus Torvalds SasIOUnit0PhyData, MPI_POINTER pSasIOUnit0PhyData; 25171da177e4SLinus Torvalds 25181da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_SAS_IO_UNIT_0 25191da177e4SLinus Torvalds { 2520c1a71d1cSMoore, Eric Dean CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 25212076eb6aSEric Moore U16 NvdataVersionDefault; /* 08h */ 25222076eb6aSEric Moore U16 NvdataVersionPersistent; /* 0Ah */ 25231da177e4SLinus Torvalds U8 NumPhys; /* 0Ch */ 25241da177e4SLinus Torvalds U8 Reserved2; /* 0Dh */ 25251da177e4SLinus Torvalds U16 Reserved3; /* 0Eh */ 252614c1f88cSKees Cook MPI_SAS_IO_UNIT0_PHY_DATA PhyData[] __counted_by(NumPhys); /* 10h */ 2527c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_SAS_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_0, 25281da177e4SLinus Torvalds SasIOUnitPage0_t, MPI_POINTER pSasIOUnitPage0_t; 25291da177e4SLinus Torvalds 25302076eb6aSEric Moore #define MPI_SASIOUNITPAGE0_PAGEVERSION (0x04) 25311da177e4SLinus Torvalds 25321da177e4SLinus Torvalds /* values for SAS IO Unit Page 0 PortFlags */ 25331da177e4SLinus Torvalds #define MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS (0x08) 25341da177e4SLinus Torvalds #define MPI_SAS_IOUNIT0_PORT_FLAGS_0_TARGET_IOC_NUM (0x00) 25351da177e4SLinus Torvalds #define MPI_SAS_IOUNIT0_PORT_FLAGS_1_TARGET_IOC_NUM (0x04) 25361da177e4SLinus Torvalds #define MPI_SAS_IOUNIT0_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 25371da177e4SLinus Torvalds 25381da177e4SLinus Torvalds /* values for SAS IO Unit Page 0 PhyFlags */ 25391da177e4SLinus Torvalds #define MPI_SAS_IOUNIT0_PHY_FLAGS_PHY_DISABLED (0x04) 25401da177e4SLinus Torvalds #define MPI_SAS_IOUNIT0_PHY_FLAGS_TX_INVERT (0x02) 25411da177e4SLinus Torvalds #define MPI_SAS_IOUNIT0_PHY_FLAGS_RX_INVERT (0x01) 25421da177e4SLinus Torvalds 25431da177e4SLinus Torvalds /* values for SAS IO Unit Page 0 NegotiatedLinkRate */ 25441da177e4SLinus Torvalds #define MPI_SAS_IOUNIT0_RATE_UNKNOWN (0x00) 25451da177e4SLinus Torvalds #define MPI_SAS_IOUNIT0_RATE_PHY_DISABLED (0x01) 25461da177e4SLinus Torvalds #define MPI_SAS_IOUNIT0_RATE_FAILED_SPEED_NEGOTIATION (0x02) 25471da177e4SLinus Torvalds #define MPI_SAS_IOUNIT0_RATE_SATA_OOB_COMPLETE (0x03) 25481da177e4SLinus Torvalds #define MPI_SAS_IOUNIT0_RATE_1_5 (0x08) 25491da177e4SLinus Torvalds #define MPI_SAS_IOUNIT0_RATE_3_0 (0x09) 2550d75733d5SKashyap, Desai #define MPI_SAS_IOUNIT0_RATE_6_0 (0x0A) 25511da177e4SLinus Torvalds 25521da177e4SLinus Torvalds /* see mpi_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 25531da177e4SLinus Torvalds 2554c1a71d1cSMoore, Eric Dean /* values for SAS IO Unit Page 0 DiscoveryStatus */ 2555c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT0_DS_LOOP_DETECTED (0x00000001) 2556c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2557c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 2558c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT0_DS_EXPANDER_ERR (0x00000008) 2559c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT0_DS_SMP_TIMEOUT (0x00000010) 2560c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2561c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 2562c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 2563c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 2564c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 2565c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT0_DS_TABLE_LINK (0x00000400) 2566c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 2567ccf3b7bdSChristoph Hellwig #define MPI_SAS_IOUNIT0_DS_MAX_SATA_TARGETS (0x00001000) 2568d16291b1SEric Moore #define MPI_SAS_IOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 2569c1a71d1cSMoore, Eric Dean 25701da177e4SLinus Torvalds 25711da177e4SLinus Torvalds typedef struct _MPI_SAS_IO_UNIT1_PHY_DATA 25721da177e4SLinus Torvalds { 25731da177e4SLinus Torvalds U8 Port; /* 00h */ 25741da177e4SLinus Torvalds U8 PortFlags; /* 01h */ 25751da177e4SLinus Torvalds U8 PhyFlags; /* 02h */ 25761da177e4SLinus Torvalds U8 MaxMinLinkRate; /* 03h */ 25771da177e4SLinus Torvalds U32 ControllerPhyDeviceInfo; /* 04h */ 25782076eb6aSEric Moore U16 MaxTargetPortConnectTime; /* 08h */ 25792076eb6aSEric Moore U16 Reserved1; /* 0Ah */ 25801da177e4SLinus Torvalds } MPI_SAS_IO_UNIT1_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT1_PHY_DATA, 25811da177e4SLinus Torvalds SasIOUnit1PhyData, MPI_POINTER pSasIOUnit1PhyData; 25821da177e4SLinus Torvalds 25831da177e4SLinus Torvalds /* 25841da177e4SLinus Torvalds * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 25851da177e4SLinus Torvalds * one and check Header.PageLength at runtime. 25861da177e4SLinus Torvalds */ 25871da177e4SLinus Torvalds #ifndef MPI_SAS_IOUNIT1_PHY_MAX 25881da177e4SLinus Torvalds #define MPI_SAS_IOUNIT1_PHY_MAX (1) 25891da177e4SLinus Torvalds #endif 25901da177e4SLinus Torvalds 25911da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_SAS_IO_UNIT_1 25921da177e4SLinus Torvalds { 2593c1a71d1cSMoore, Eric Dean CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2594c1a71d1cSMoore, Eric Dean U16 ControlFlags; /* 08h */ 2595c1a71d1cSMoore, Eric Dean U16 MaxNumSATATargets; /* 0Ah */ 25962076eb6aSEric Moore U16 AdditionalControlFlags; /* 0Ch */ 25972076eb6aSEric Moore U16 Reserved1; /* 0Eh */ 2598c1a71d1cSMoore, Eric Dean U8 NumPhys; /* 10h */ 2599c1a71d1cSMoore, Eric Dean U8 SATAMaxQDepth; /* 11h */ 26002076eb6aSEric Moore U8 ReportDeviceMissingDelay; /* 12h */ 26012076eb6aSEric Moore U8 IODeviceMissingDelay; /* 13h */ 2602c1a71d1cSMoore, Eric Dean MPI_SAS_IO_UNIT1_PHY_DATA PhyData[MPI_SAS_IOUNIT1_PHY_MAX]; /* 14h */ 2603c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_SAS_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_1, 26041da177e4SLinus Torvalds SasIOUnitPage1_t, MPI_POINTER pSasIOUnitPage1_t; 26051da177e4SLinus Torvalds 2606eae225ebSEric Moore #define MPI_SASIOUNITPAGE1_PAGEVERSION (0x07) 26071da177e4SLinus Torvalds 2608c1a71d1cSMoore, Eric Dean /* values for SAS IO Unit Page 1 ControlFlags */ 2609ccf3b7bdSChristoph Hellwig #define MPI_SAS_IOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 2610c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 2611c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 2612c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 2613c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT1_CONTROL_DISABLE_SAS_HASH (0x0800) 2614c1a71d1cSMoore, Eric Dean 2615c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 2616c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 2617c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x00) 2618c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x01) 2619ccf3b7bdSChristoph Hellwig #define MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x02) 2620c1a71d1cSMoore, Eric Dean 26214b915a73SMoore, Eric #define MPI_SAS_IOUNIT1_CONTROL_POSTPONE_SATA_INIT (0x0100) 2622c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 2623c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 2624c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 2625c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 2626c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT1_CONTROL_PHY_ENABLE_ORDER_HIGH (0x0008) 2627c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 2628c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 2629c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 2630c1a71d1cSMoore, Eric Dean 26312076eb6aSEric Moore /* values for SAS IO Unit Page 1 AdditionalControlFlags */ 2632d16291b1SEric Moore #define MPI_SAS_IOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 2633eae225ebSEric Moore #define MPI_SAS_IOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 2634eae225ebSEric Moore #define MPI_SAS_IOUNIT1_ACONTROL_HIDE_NONZERO_ATTACHED_PHY_IDENT (0x0020) 2635eae225ebSEric Moore #define MPI_SAS_IOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 2636eae225ebSEric Moore #define MPI_SAS_IOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 2637eae225ebSEric Moore #define MPI_SAS_IOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 2638eae225ebSEric Moore #define MPI_SAS_IOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 26392076eb6aSEric Moore #define MPI_SAS_IOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 26402076eb6aSEric Moore 26412076eb6aSEric Moore /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 26422076eb6aSEric Moore #define MPI_SAS_IOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 26432076eb6aSEric Moore #define MPI_SAS_IOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 26442076eb6aSEric Moore 2645c1a71d1cSMoore, Eric Dean /* values for SAS IO Unit Page 1 PortFlags */ 26461da177e4SLinus Torvalds #define MPI_SAS_IOUNIT1_PORT_FLAGS_0_TARGET_IOC_NUM (0x00) 26471da177e4SLinus Torvalds #define MPI_SAS_IOUNIT1_PORT_FLAGS_1_TARGET_IOC_NUM (0x04) 26481da177e4SLinus Torvalds #define MPI_SAS_IOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 26491da177e4SLinus Torvalds 26501da177e4SLinus Torvalds /* values for SAS IO Unit Page 0 PhyFlags */ 26511da177e4SLinus Torvalds #define MPI_SAS_IOUNIT1_PHY_FLAGS_PHY_DISABLE (0x04) 26521da177e4SLinus Torvalds #define MPI_SAS_IOUNIT1_PHY_FLAGS_TX_INVERT (0x02) 26531da177e4SLinus Torvalds #define MPI_SAS_IOUNIT1_PHY_FLAGS_RX_INVERT (0x01) 26541da177e4SLinus Torvalds 26551da177e4SLinus Torvalds /* values for SAS IO Unit Page 0 MaxMinLinkRate */ 26561da177e4SLinus Torvalds #define MPI_SAS_IOUNIT1_MAX_RATE_MASK (0xF0) 26571da177e4SLinus Torvalds #define MPI_SAS_IOUNIT1_MAX_RATE_1_5 (0x80) 26581da177e4SLinus Torvalds #define MPI_SAS_IOUNIT1_MAX_RATE_3_0 (0x90) 26591da177e4SLinus Torvalds #define MPI_SAS_IOUNIT1_MIN_RATE_MASK (0x0F) 26601da177e4SLinus Torvalds #define MPI_SAS_IOUNIT1_MIN_RATE_1_5 (0x08) 26611da177e4SLinus Torvalds #define MPI_SAS_IOUNIT1_MIN_RATE_3_0 (0x09) 26621da177e4SLinus Torvalds 26631da177e4SLinus Torvalds /* see mpi_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 26641da177e4SLinus Torvalds 26651da177e4SLinus Torvalds 26661da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_SAS_IO_UNIT_2 26671da177e4SLinus Torvalds { 2668c1a71d1cSMoore, Eric Dean CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 26694b915a73SMoore, Eric U8 NumDevsPerEnclosure; /* 08h */ 26704b915a73SMoore, Eric U8 Reserved1; /* 09h */ 26714b915a73SMoore, Eric U16 Reserved2; /* 0Ah */ 26721da177e4SLinus Torvalds U16 MaxPersistentIDs; /* 0Ch */ 26731da177e4SLinus Torvalds U16 NumPersistentIDsUsed; /* 0Eh */ 26741da177e4SLinus Torvalds U8 Status; /* 10h */ 26751da177e4SLinus Torvalds U8 Flags; /* 11h */ 26764b915a73SMoore, Eric U16 MaxNumPhysicalMappedIDs;/* 12h */ 2677c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_SAS_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_2, 26781da177e4SLinus Torvalds SasIOUnitPage2_t, MPI_POINTER pSasIOUnitPage2_t; 26791da177e4SLinus Torvalds 2680eae225ebSEric Moore #define MPI_SASIOUNITPAGE2_PAGEVERSION (0x06) 26811da177e4SLinus Torvalds 26821da177e4SLinus Torvalds /* values for SAS IO Unit Page 2 Status field */ 2683eae225ebSEric Moore #define MPI_SAS_IOUNIT2_STATUS_DEVICE_LIMIT_EXCEEDED (0x08) 2684eae225ebSEric Moore #define MPI_SAS_IOUNIT2_STATUS_ENCLOSURE_DEVICES_UNMAPPED (0x04) 26851da177e4SLinus Torvalds #define MPI_SAS_IOUNIT2_STATUS_DISABLED_PERSISTENT_MAPPINGS (0x02) 26861da177e4SLinus Torvalds #define MPI_SAS_IOUNIT2_STATUS_FULL_PERSISTENT_MAPPINGS (0x01) 26871da177e4SLinus Torvalds 26881da177e4SLinus Torvalds /* values for SAS IO Unit Page 2 Flags field */ 26891da177e4SLinus Torvalds #define MPI_SAS_IOUNIT2_FLAGS_DISABLE_PERSISTENT_MAPPINGS (0x01) 2690c1a71d1cSMoore, Eric Dean /* Physical Mapping Modes */ 2691c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT2_FLAGS_MASK_PHYS_MAP_MODE (0x0E) 2692c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT2_FLAGS_SHIFT_PHYS_MAP_MODE (1) 2693c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT2_FLAGS_NO_PHYS_MAP (0x00) 2694c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT2_FLAGS_DIRECT_ATTACH_PHYS_MAP (0x01) 2695c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT2_FLAGS_ENCLOSURE_SLOT_PHYS_MAP (0x02) 26964b915a73SMoore, Eric #define MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP (0x07) 2697c1a71d1cSMoore, Eric Dean 2698c1a71d1cSMoore, Eric Dean #define MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT (0x10) 2699ccf3b7bdSChristoph Hellwig #define MPI_SAS_IOUNIT2_FLAGS_DA_STARTING_SLOT (0x20) 27001da177e4SLinus Torvalds 27011da177e4SLinus Torvalds 27021da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_SAS_IO_UNIT_3 27031da177e4SLinus Torvalds { 2704c1a71d1cSMoore, Eric Dean CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 27051da177e4SLinus Torvalds U32 Reserved1; /* 08h */ 27061da177e4SLinus Torvalds U32 MaxInvalidDwordCount; /* 0Ch */ 27071da177e4SLinus Torvalds U32 InvalidDwordCountTime; /* 10h */ 27081da177e4SLinus Torvalds U32 MaxRunningDisparityErrorCount; /* 14h */ 27091da177e4SLinus Torvalds U32 RunningDisparityErrorTime; /* 18h */ 27101da177e4SLinus Torvalds U32 MaxLossDwordSynchCount; /* 1Ch */ 27111da177e4SLinus Torvalds U32 LossDwordSynchCountTime; /* 20h */ 27121da177e4SLinus Torvalds U32 MaxPhyResetProblemCount; /* 24h */ 27131da177e4SLinus Torvalds U32 PhyResetProblemTime; /* 28h */ 2714c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_SAS_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_3, 27151da177e4SLinus Torvalds SasIOUnitPage3_t, MPI_POINTER pSasIOUnitPage3_t; 27161da177e4SLinus Torvalds 27171da177e4SLinus Torvalds #define MPI_SASIOUNITPAGE3_PAGEVERSION (0x00) 27181da177e4SLinus Torvalds 27191da177e4SLinus Torvalds 2720c1a71d1cSMoore, Eric Dean /**************************************************************************** 2721c1a71d1cSMoore, Eric Dean * SAS Expander Config Pages 2722c1a71d1cSMoore, Eric Dean ****************************************************************************/ 2723c1a71d1cSMoore, Eric Dean 27241da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_SAS_EXPANDER_0 27251da177e4SLinus Torvalds { 2726c1a71d1cSMoore, Eric Dean CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2727c1a71d1cSMoore, Eric Dean U8 PhysicalPort; /* 08h */ 2728c1a71d1cSMoore, Eric Dean U8 Reserved1; /* 09h */ 27294b915a73SMoore, Eric U16 EnclosureHandle; /* 0Ah */ 27301da177e4SLinus Torvalds U64 SASAddress; /* 0Ch */ 2731c1a71d1cSMoore, Eric Dean U32 DiscoveryStatus; /* 14h */ 27321da177e4SLinus Torvalds U16 DevHandle; /* 18h */ 27331da177e4SLinus Torvalds U16 ParentDevHandle; /* 1Ah */ 27341da177e4SLinus Torvalds U16 ExpanderChangeCount; /* 1Ch */ 27351da177e4SLinus Torvalds U16 ExpanderRouteIndexes; /* 1Eh */ 27361da177e4SLinus Torvalds U8 NumPhys; /* 20h */ 27371da177e4SLinus Torvalds U8 SASLevel; /* 21h */ 27381da177e4SLinus Torvalds U8 Flags; /* 22h */ 27391da177e4SLinus Torvalds U8 Reserved3; /* 23h */ 2740c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_SAS_EXPANDER_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_0, 27411da177e4SLinus Torvalds SasExpanderPage0_t, MPI_POINTER pSasExpanderPage0_t; 27421da177e4SLinus Torvalds 27434b915a73SMoore, Eric #define MPI_SASEXPANDER0_PAGEVERSION (0x03) 2744c1a71d1cSMoore, Eric Dean 2745c1a71d1cSMoore, Eric Dean /* values for SAS Expander Page 0 DiscoveryStatus field */ 2746c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2747c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2748c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2749c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPANDER0_DS_EXPANDER_ERR (0x00000008) 2750c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2751c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2752c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2753c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2754c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2755c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2756c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2757c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 27581da177e4SLinus Torvalds 27591da177e4SLinus Torvalds /* values for SAS Expander Page 0 Flags field */ 2760d16291b1SEric Moore #define MPI_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x04) 27611da177e4SLinus Torvalds #define MPI_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x02) 27621da177e4SLinus Torvalds #define MPI_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x01) 27631da177e4SLinus Torvalds 27641da177e4SLinus Torvalds 2765c1a71d1cSMoore, Eric Dean typedef struct _CONFIG_PAGE_SAS_EXPANDER_1 2766c1a71d1cSMoore, Eric Dean { 2767c1a71d1cSMoore, Eric Dean CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2768c1a71d1cSMoore, Eric Dean U8 PhysicalPort; /* 08h */ 2769c1a71d1cSMoore, Eric Dean U8 Reserved1; /* 09h */ 2770c1a71d1cSMoore, Eric Dean U16 Reserved2; /* 0Ah */ 2771c1a71d1cSMoore, Eric Dean U8 NumPhys; /* 0Ch */ 2772c1a71d1cSMoore, Eric Dean U8 Phy; /* 0Dh */ 2773c1a71d1cSMoore, Eric Dean U16 NumTableEntriesProgrammed; /* 0Eh */ 2774c1a71d1cSMoore, Eric Dean U8 ProgrammedLinkRate; /* 10h */ 2775c1a71d1cSMoore, Eric Dean U8 HwLinkRate; /* 11h */ 2776c1a71d1cSMoore, Eric Dean U16 AttachedDevHandle; /* 12h */ 2777c1a71d1cSMoore, Eric Dean U32 PhyInfo; /* 14h */ 2778c1a71d1cSMoore, Eric Dean U32 AttachedDeviceInfo; /* 18h */ 2779c1a71d1cSMoore, Eric Dean U16 OwnerDevHandle; /* 1Ch */ 2780c1a71d1cSMoore, Eric Dean U8 ChangeCount; /* 1Eh */ 2781c1a71d1cSMoore, Eric Dean U8 NegotiatedLinkRate; /* 1Fh */ 2782c1a71d1cSMoore, Eric Dean U8 PhyIdentifier; /* 20h */ 2783c1a71d1cSMoore, Eric Dean U8 AttachedPhyIdentifier; /* 21h */ 27844b915a73SMoore, Eric U8 Reserved3; /* 22h */ 2785c1a71d1cSMoore, Eric Dean U8 DiscoveryInfo; /* 23h */ 27864b915a73SMoore, Eric U32 Reserved4; /* 24h */ 2787c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_SAS_EXPANDER_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_1, 2788c1a71d1cSMoore, Eric Dean SasExpanderPage1_t, MPI_POINTER pSasExpanderPage1_t; 2789c1a71d1cSMoore, Eric Dean 2790c1a71d1cSMoore, Eric Dean #define MPI_SASEXPANDER1_PAGEVERSION (0x01) 2791c1a71d1cSMoore, Eric Dean 2792c1a71d1cSMoore, Eric Dean /* use MPI_SAS_PHY0_PRATE_ defines for ProgrammedLinkRate */ 2793c1a71d1cSMoore, Eric Dean 2794c1a71d1cSMoore, Eric Dean /* use MPI_SAS_PHY0_HWRATE_ defines for HwLinkRate */ 2795c1a71d1cSMoore, Eric Dean 2796c1a71d1cSMoore, Eric Dean /* use MPI_SAS_PHY0_PHYINFO_ defines for PhyInfo */ 2797c1a71d1cSMoore, Eric Dean 2798c1a71d1cSMoore, Eric Dean /* see mpi_sas.h for values for SAS Expander Page 1 AttachedDeviceInfo values */ 2799c1a71d1cSMoore, Eric Dean 2800c1a71d1cSMoore, Eric Dean /* values for SAS Expander Page 1 DiscoveryInfo field */ 2801d16291b1SEric Moore #define MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2802c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2803c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2804c1a71d1cSMoore, Eric Dean 2805c1a71d1cSMoore, Eric Dean /* values for SAS Expander Page 1 NegotiatedLinkRate field */ 2806c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPANDER1_NEG_RATE_UNKNOWN (0x00) 2807c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPANDER1_NEG_RATE_PHY_DISABLED (0x01) 2808c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPANDER1_NEG_RATE_FAILED_NEGOTIATION (0x02) 2809c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPANDER1_NEG_RATE_SATA_OOB_COMPLETE (0x03) 2810c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPANDER1_NEG_RATE_1_5 (0x08) 2811c1a71d1cSMoore, Eric Dean #define MPI_SAS_EXPANDER1_NEG_RATE_3_0 (0x09) 2812c1a71d1cSMoore, Eric Dean 2813c1a71d1cSMoore, Eric Dean 2814c1a71d1cSMoore, Eric Dean /**************************************************************************** 2815c1a71d1cSMoore, Eric Dean * SAS Device Config Pages 2816c1a71d1cSMoore, Eric Dean ****************************************************************************/ 2817c1a71d1cSMoore, Eric Dean 28181da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_SAS_DEVICE_0 28191da177e4SLinus Torvalds { 2820c1a71d1cSMoore, Eric Dean CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2821c1a71d1cSMoore, Eric Dean U16 Slot; /* 08h */ 2822c1a71d1cSMoore, Eric Dean U16 EnclosureHandle; /* 0Ah */ 28231da177e4SLinus Torvalds U64 SASAddress; /* 0Ch */ 2824c1a71d1cSMoore, Eric Dean U16 ParentDevHandle; /* 14h */ 2825c1a71d1cSMoore, Eric Dean U8 PhyNum; /* 16h */ 2826c1a71d1cSMoore, Eric Dean U8 AccessStatus; /* 17h */ 28271da177e4SLinus Torvalds U16 DevHandle; /* 18h */ 28281da177e4SLinus Torvalds U8 TargetID; /* 1Ah */ 28291da177e4SLinus Torvalds U8 Bus; /* 1Bh */ 28301da177e4SLinus Torvalds U32 DeviceInfo; /* 1Ch */ 28311da177e4SLinus Torvalds U16 Flags; /* 20h */ 28321da177e4SLinus Torvalds U8 PhysicalPort; /* 22h */ 2833c1a71d1cSMoore, Eric Dean U8 Reserved2; /* 23h */ 2834c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_SAS_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_0, 28351da177e4SLinus Torvalds SasDevicePage0_t, MPI_POINTER pSasDevicePage0_t; 28361da177e4SLinus Torvalds 2837eae225ebSEric Moore #define MPI_SASDEVICE0_PAGEVERSION (0x05) 2838c1a71d1cSMoore, Eric Dean 2839c1a71d1cSMoore, Eric Dean /* values for SAS Device Page 0 AccessStatus field */ 2840c1a71d1cSMoore, Eric Dean #define MPI_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2841c1a71d1cSMoore, Eric Dean #define MPI_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2842c1a71d1cSMoore, Eric Dean #define MPI_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2843eae225ebSEric Moore #define MPI_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2844fd7a2533SKashyap, Desai #define MPI_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2845eae225ebSEric Moore /* specific values for SATA Init failures */ 2846eae225ebSEric Moore #define MPI_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2847eae225ebSEric Moore #define MPI_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2848eae225ebSEric Moore #define MPI_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2849eae225ebSEric Moore #define MPI_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2850eae225ebSEric Moore #define MPI_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2851eae225ebSEric Moore #define MPI_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2852eae225ebSEric Moore #define MPI_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2853eae225ebSEric Moore #define MPI_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2854eae225ebSEric Moore #define MPI_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2855eae225ebSEric Moore #define MPI_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2856eae225ebSEric Moore #define MPI_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 28571da177e4SLinus Torvalds 28581da177e4SLinus Torvalds /* values for SAS Device Page 0 Flags field */ 2859eae225ebSEric Moore #define MPI_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2860c1a71d1cSMoore, Eric Dean #define MPI_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2861c1a71d1cSMoore, Eric Dean #define MPI_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2862c1a71d1cSMoore, Eric Dean #define MPI_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2863c1a71d1cSMoore, Eric Dean #define MPI_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2864c1a71d1cSMoore, Eric Dean #define MPI_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2865c1a71d1cSMoore, Eric Dean #define MPI_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2866c1a71d1cSMoore, Eric Dean #define MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2867c1a71d1cSMoore, Eric Dean #define MPI_SAS_DEVICE0_FLAGS_MAPPING_PERSISTENT (0x0004) 2868c1a71d1cSMoore, Eric Dean #define MPI_SAS_DEVICE0_FLAGS_DEVICE_MAPPED (0x0002) 2869c1a71d1cSMoore, Eric Dean #define MPI_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 28701da177e4SLinus Torvalds 28711da177e4SLinus Torvalds /* see mpi_sas.h for values for SAS Device Page 0 DeviceInfo values */ 28721da177e4SLinus Torvalds 28731da177e4SLinus Torvalds 28741da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_SAS_DEVICE_1 28751da177e4SLinus Torvalds { 2876c1a71d1cSMoore, Eric Dean CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 28771da177e4SLinus Torvalds U32 Reserved1; /* 08h */ 28781da177e4SLinus Torvalds U64 SASAddress; /* 0Ch */ 28791da177e4SLinus Torvalds U32 Reserved2; /* 14h */ 28801da177e4SLinus Torvalds U16 DevHandle; /* 18h */ 28811da177e4SLinus Torvalds U8 TargetID; /* 1Ah */ 28821da177e4SLinus Torvalds U8 Bus; /* 1Bh */ 28831da177e4SLinus Torvalds U8 InitialRegDeviceFIS[20];/* 1Ch */ 2884c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_SAS_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_1, 28851da177e4SLinus Torvalds SasDevicePage1_t, MPI_POINTER pSasDevicePage1_t; 28861da177e4SLinus Torvalds 28871da177e4SLinus Torvalds #define MPI_SASDEVICE1_PAGEVERSION (0x00) 28881da177e4SLinus Torvalds 28891da177e4SLinus Torvalds 2890c1a71d1cSMoore, Eric Dean typedef struct _CONFIG_PAGE_SAS_DEVICE_2 2891c1a71d1cSMoore, Eric Dean { 2892c1a71d1cSMoore, Eric Dean CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2893c1a71d1cSMoore, Eric Dean U64 PhysicalIdentifier; /* 08h */ 2894ccf3b7bdSChristoph Hellwig U32 EnclosureMapping; /* 10h */ 2895c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_SAS_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_2, 2896c1a71d1cSMoore, Eric Dean SasDevicePage2_t, MPI_POINTER pSasDevicePage2_t; 2897c1a71d1cSMoore, Eric Dean 2898ccf3b7bdSChristoph Hellwig #define MPI_SASDEVICE2_PAGEVERSION (0x01) 2899ccf3b7bdSChristoph Hellwig 2900ccf3b7bdSChristoph Hellwig /* defines for SAS Device Page 2 EnclosureMapping field */ 2901ccf3b7bdSChristoph Hellwig #define MPI_SASDEVICE2_ENC_MAP_MASK_MISSING_COUNT (0x0000000F) 2902ccf3b7bdSChristoph Hellwig #define MPI_SASDEVICE2_ENC_MAP_SHIFT_MISSING_COUNT (0) 2903ccf3b7bdSChristoph Hellwig #define MPI_SASDEVICE2_ENC_MAP_MASK_NUM_SLOTS (0x000007F0) 2904ccf3b7bdSChristoph Hellwig #define MPI_SASDEVICE2_ENC_MAP_SHIFT_NUM_SLOTS (4) 2905ccf3b7bdSChristoph Hellwig #define MPI_SASDEVICE2_ENC_MAP_MASK_START_INDEX (0x001FF800) 2906ccf3b7bdSChristoph Hellwig #define MPI_SASDEVICE2_ENC_MAP_SHIFT_START_INDEX (11) 2907c1a71d1cSMoore, Eric Dean 2908c1a71d1cSMoore, Eric Dean 2909c1a71d1cSMoore, Eric Dean /**************************************************************************** 2910c1a71d1cSMoore, Eric Dean * SAS PHY Config Pages 2911c1a71d1cSMoore, Eric Dean ****************************************************************************/ 2912c1a71d1cSMoore, Eric Dean 29131da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_SAS_PHY_0 29141da177e4SLinus Torvalds { 2915c1a71d1cSMoore, Eric Dean CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2916ccf3b7bdSChristoph Hellwig U16 OwnerDevHandle; /* 08h */ 2917ccf3b7bdSChristoph Hellwig U16 Reserved1; /* 0Ah */ 29181da177e4SLinus Torvalds U64 SASAddress; /* 0Ch */ 29191da177e4SLinus Torvalds U16 AttachedDevHandle; /* 14h */ 29201da177e4SLinus Torvalds U8 AttachedPhyIdentifier; /* 16h */ 29211da177e4SLinus Torvalds U8 Reserved2; /* 17h */ 29221da177e4SLinus Torvalds U32 AttachedDeviceInfo; /* 18h */ 2923d16291b1SEric Moore U8 ProgrammedLinkRate; /* 1Ch */ 2924d16291b1SEric Moore U8 HwLinkRate; /* 1Dh */ 2925d16291b1SEric Moore U8 ChangeCount; /* 1Eh */ 2926d16291b1SEric Moore U8 Flags; /* 1Fh */ 2927d16291b1SEric Moore U32 PhyInfo; /* 20h */ 2928c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_SAS_PHY_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_0, 29291da177e4SLinus Torvalds SasPhyPage0_t, MPI_POINTER pSasPhyPage0_t; 29301da177e4SLinus Torvalds 2931ccf3b7bdSChristoph Hellwig #define MPI_SASPHY0_PAGEVERSION (0x01) 29321da177e4SLinus Torvalds 29331da177e4SLinus Torvalds /* values for SAS PHY Page 0 ProgrammedLinkRate field */ 29341da177e4SLinus Torvalds #define MPI_SAS_PHY0_PRATE_MAX_RATE_MASK (0xF0) 29351da177e4SLinus Torvalds #define MPI_SAS_PHY0_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 29361da177e4SLinus Torvalds #define MPI_SAS_PHY0_PRATE_MAX_RATE_1_5 (0x80) 29371da177e4SLinus Torvalds #define MPI_SAS_PHY0_PRATE_MAX_RATE_3_0 (0x90) 29381da177e4SLinus Torvalds #define MPI_SAS_PHY0_PRATE_MIN_RATE_MASK (0x0F) 29391da177e4SLinus Torvalds #define MPI_SAS_PHY0_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 29401da177e4SLinus Torvalds #define MPI_SAS_PHY0_PRATE_MIN_RATE_1_5 (0x08) 29411da177e4SLinus Torvalds #define MPI_SAS_PHY0_PRATE_MIN_RATE_3_0 (0x09) 29421da177e4SLinus Torvalds 29431da177e4SLinus Torvalds /* values for SAS PHY Page 0 HwLinkRate field */ 29441da177e4SLinus Torvalds #define MPI_SAS_PHY0_HWRATE_MAX_RATE_MASK (0xF0) 29451da177e4SLinus Torvalds #define MPI_SAS_PHY0_HWRATE_MAX_RATE_1_5 (0x80) 29461da177e4SLinus Torvalds #define MPI_SAS_PHY0_HWRATE_MAX_RATE_3_0 (0x90) 29471da177e4SLinus Torvalds #define MPI_SAS_PHY0_HWRATE_MIN_RATE_MASK (0x0F) 29481da177e4SLinus Torvalds #define MPI_SAS_PHY0_HWRATE_MIN_RATE_1_5 (0x08) 29491da177e4SLinus Torvalds #define MPI_SAS_PHY0_HWRATE_MIN_RATE_3_0 (0x09) 29501da177e4SLinus Torvalds 2951ccf3b7bdSChristoph Hellwig /* values for SAS PHY Page 0 Flags field */ 2952ccf3b7bdSChristoph Hellwig #define MPI_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2953ccf3b7bdSChristoph Hellwig 29541da177e4SLinus Torvalds /* values for SAS PHY Page 0 PhyInfo field */ 29551da177e4SLinus Torvalds #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 29561da177e4SLinus Torvalds #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_SELECTOR (0x00002000) 29571da177e4SLinus Torvalds #define MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY (0x00001000) 29581da177e4SLinus Torvalds 29591da177e4SLinus Torvalds #define MPI_SAS_PHY0_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 29601da177e4SLinus Torvalds #define MPI_SAS_PHY0_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 29611da177e4SLinus Torvalds 29621da177e4SLinus Torvalds #define MPI_SAS_PHY0_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 29631da177e4SLinus Torvalds #define MPI_SAS_PHY0_PHYINFO_DIRECT_ROUTING (0x00000000) 29641da177e4SLinus Torvalds #define MPI_SAS_PHY0_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 29651da177e4SLinus Torvalds #define MPI_SAS_PHY0_PHYINFO_TABLE_ROUTING (0x00000020) 29661da177e4SLinus Torvalds 29671da177e4SLinus Torvalds #define MPI_SAS_PHY0_PHYINFO_MASK_LINK_RATE (0x0000000F) 29681da177e4SLinus Torvalds #define MPI_SAS_PHY0_PHYINFO_UNKNOWN_LINK_RATE (0x00000000) 29691da177e4SLinus Torvalds #define MPI_SAS_PHY0_PHYINFO_PHY_DISABLED (0x00000001) 29701da177e4SLinus Torvalds #define MPI_SAS_PHY0_PHYINFO_NEGOTIATION_FAILED (0x00000002) 29711da177e4SLinus Torvalds #define MPI_SAS_PHY0_PHYINFO_SATA_OOB_COMPLETE (0x00000003) 29721da177e4SLinus Torvalds #define MPI_SAS_PHY0_PHYINFO_RATE_1_5 (0x00000008) 29731da177e4SLinus Torvalds #define MPI_SAS_PHY0_PHYINFO_RATE_3_0 (0x00000009) 29741da177e4SLinus Torvalds 29751da177e4SLinus Torvalds 29761da177e4SLinus Torvalds typedef struct _CONFIG_PAGE_SAS_PHY_1 29771da177e4SLinus Torvalds { 2978c1a71d1cSMoore, Eric Dean CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 29791da177e4SLinus Torvalds U32 Reserved1; /* 08h */ 29801da177e4SLinus Torvalds U32 InvalidDwordCount; /* 0Ch */ 29811da177e4SLinus Torvalds U32 RunningDisparityErrorCount; /* 10h */ 29821da177e4SLinus Torvalds U32 LossDwordSynchCount; /* 14h */ 29831da177e4SLinus Torvalds U32 PhyResetProblemCount; /* 18h */ 2984c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_SAS_PHY_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_1, 29851da177e4SLinus Torvalds SasPhyPage1_t, MPI_POINTER pSasPhyPage1_t; 29861da177e4SLinus Torvalds 29871da177e4SLinus Torvalds #define MPI_SASPHY1_PAGEVERSION (0x00) 29881da177e4SLinus Torvalds 29891da177e4SLinus Torvalds 2990c1a71d1cSMoore, Eric Dean /**************************************************************************** 2991c1a71d1cSMoore, Eric Dean * SAS Enclosure Config Pages 2992c1a71d1cSMoore, Eric Dean ****************************************************************************/ 2993c1a71d1cSMoore, Eric Dean 2994c1a71d1cSMoore, Eric Dean typedef struct _CONFIG_PAGE_SAS_ENCLOSURE_0 2995c1a71d1cSMoore, Eric Dean { 2996c1a71d1cSMoore, Eric Dean CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2997c1a71d1cSMoore, Eric Dean U32 Reserved1; /* 08h */ 2998c1a71d1cSMoore, Eric Dean U64 EnclosureLogicalID; /* 0Ch */ 2999c1a71d1cSMoore, Eric Dean U16 Flags; /* 14h */ 3000c1a71d1cSMoore, Eric Dean U16 EnclosureHandle; /* 16h */ 3001c1a71d1cSMoore, Eric Dean U16 NumSlots; /* 18h */ 3002c1a71d1cSMoore, Eric Dean U16 StartSlot; /* 1Ah */ 3003c1a71d1cSMoore, Eric Dean U8 StartTargetID; /* 1Ch */ 3004c1a71d1cSMoore, Eric Dean U8 StartBus; /* 1Dh */ 3005c1a71d1cSMoore, Eric Dean U8 SEPTargetID; /* 1Eh */ 3006c1a71d1cSMoore, Eric Dean U8 SEPBus; /* 1Fh */ 3007c1a71d1cSMoore, Eric Dean U32 Reserved2; /* 20h */ 3008c1a71d1cSMoore, Eric Dean U32 Reserved3; /* 24h */ 3009c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_SAS_ENCLOSURE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_ENCLOSURE_0, 3010c1a71d1cSMoore, Eric Dean SasEnclosurePage0_t, MPI_POINTER pSasEnclosurePage0_t; 3011c1a71d1cSMoore, Eric Dean 3012ccf3b7bdSChristoph Hellwig #define MPI_SASENCLOSURE0_PAGEVERSION (0x01) 3013c1a71d1cSMoore, Eric Dean 3014c1a71d1cSMoore, Eric Dean /* values for SAS Enclosure Page 0 Flags field */ 3015c1a71d1cSMoore, Eric Dean #define MPI_SAS_ENCLS0_FLAGS_SEP_BUS_ID_VALID (0x0020) 3016c1a71d1cSMoore, Eric Dean #define MPI_SAS_ENCLS0_FLAGS_START_BUS_ID_VALID (0x0010) 3017c1a71d1cSMoore, Eric Dean 3018c1a71d1cSMoore, Eric Dean #define MPI_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 3019c1a71d1cSMoore, Eric Dean #define MPI_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3020c1a71d1cSMoore, Eric Dean #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3021c1a71d1cSMoore, Eric Dean #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3022c1a71d1cSMoore, Eric Dean #define MPI_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3023c1a71d1cSMoore, Eric Dean #define MPI_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3024ccf3b7bdSChristoph Hellwig #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3025c1a71d1cSMoore, Eric Dean 3026c1a71d1cSMoore, Eric Dean 3027c1a71d1cSMoore, Eric Dean /**************************************************************************** 3028c1a71d1cSMoore, Eric Dean * Log Config Pages 3029c1a71d1cSMoore, Eric Dean ****************************************************************************/ 3030c1a71d1cSMoore, Eric Dean /* 3031c1a71d1cSMoore, Eric Dean * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3032c1a71d1cSMoore, Eric Dean * one and check NumLogEntries at runtime. 3033c1a71d1cSMoore, Eric Dean */ 3034c1a71d1cSMoore, Eric Dean #ifndef MPI_LOG_0_NUM_LOG_ENTRIES 3035c1a71d1cSMoore, Eric Dean #define MPI_LOG_0_NUM_LOG_ENTRIES (1) 3036c1a71d1cSMoore, Eric Dean #endif 3037c1a71d1cSMoore, Eric Dean 30384b915a73SMoore, Eric #define MPI_LOG_0_LOG_DATA_LENGTH (0x1C) 3039c1a71d1cSMoore, Eric Dean 3040c1a71d1cSMoore, Eric Dean typedef struct _MPI_LOG_0_ENTRY 3041c1a71d1cSMoore, Eric Dean { 30424b915a73SMoore, Eric U32 TimeStamp; /* 00h */ 30434b915a73SMoore, Eric U32 Reserved1; /* 04h */ 30444b915a73SMoore, Eric U16 LogSequence; /* 08h */ 30454b915a73SMoore, Eric U16 LogEntryQualifier; /* 0Ah */ 30464b915a73SMoore, Eric U8 LogData[MPI_LOG_0_LOG_DATA_LENGTH]; /* 0Ch */ 3047c1a71d1cSMoore, Eric Dean } MPI_LOG_0_ENTRY, MPI_POINTER PTR_MPI_LOG_0_ENTRY, 3048c1a71d1cSMoore, Eric Dean MpiLog0Entry_t, MPI_POINTER pMpiLog0Entry_t; 3049c1a71d1cSMoore, Eric Dean 3050c1a71d1cSMoore, Eric Dean /* values for Log Page 0 LogEntry LogEntryQualifier field */ 3051c1a71d1cSMoore, Eric Dean #define MPI_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 3052c1a71d1cSMoore, Eric Dean #define MPI_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 3053c1a71d1cSMoore, Eric Dean 3054c1a71d1cSMoore, Eric Dean typedef struct _CONFIG_PAGE_LOG_0 3055c1a71d1cSMoore, Eric Dean { 3056c1a71d1cSMoore, Eric Dean CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 3057c1a71d1cSMoore, Eric Dean U32 Reserved1; /* 08h */ 3058c1a71d1cSMoore, Eric Dean U32 Reserved2; /* 0Ch */ 3059c1a71d1cSMoore, Eric Dean U16 NumLogEntries; /* 10h */ 3060c1a71d1cSMoore, Eric Dean U16 Reserved3; /* 12h */ 3061c1a71d1cSMoore, Eric Dean MPI_LOG_0_ENTRY LogEntry[MPI_LOG_0_NUM_LOG_ENTRIES]; /* 14h */ 3062c1a71d1cSMoore, Eric Dean } CONFIG_PAGE_LOG_0, MPI_POINTER PTR_CONFIG_PAGE_LOG_0, 3063c1a71d1cSMoore, Eric Dean LogPage0_t, MPI_POINTER pLogPage0_t; 3064c1a71d1cSMoore, Eric Dean 30654b915a73SMoore, Eric #define MPI_LOG_0_PAGEVERSION (0x01) 3066c1a71d1cSMoore, Eric Dean 3067c1a71d1cSMoore, Eric Dean 30681da177e4SLinus Torvalds #endif 30691da177e4SLinus Torvalds 3070