1 /* 2 * Copyright (C) 2010 - Maxim Levitsky 3 * driver for Ricoh memstick readers 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/freezer.h> 13 #include <linux/jiffies.h> 14 #include <linux/interrupt.h> 15 #include <linux/pci.h> 16 #include <linux/pci_ids.h> 17 #include <linux/delay.h> 18 #include <linux/slab.h> 19 #include <linux/kthread.h> 20 #include <linux/sched.h> 21 #include <linux/highmem.h> 22 #include <asm/byteorder.h> 23 #include <linux/swab.h> 24 #include "r592.h" 25 26 static bool r592_enable_dma = 1; 27 static int debug; 28 29 static const char *tpc_names[] = { 30 "MS_TPC_READ_MG_STATUS", 31 "MS_TPC_READ_LONG_DATA", 32 "MS_TPC_READ_SHORT_DATA", 33 "MS_TPC_READ_REG", 34 "MS_TPC_READ_QUAD_DATA", 35 "INVALID", 36 "MS_TPC_GET_INT", 37 "MS_TPC_SET_RW_REG_ADRS", 38 "MS_TPC_EX_SET_CMD", 39 "MS_TPC_WRITE_QUAD_DATA", 40 "MS_TPC_WRITE_REG", 41 "MS_TPC_WRITE_SHORT_DATA", 42 "MS_TPC_WRITE_LONG_DATA", 43 "MS_TPC_SET_CMD", 44 }; 45 46 /** 47 * memstick_debug_get_tpc_name - debug helper that returns string for 48 * a TPC number 49 */ 50 const char *memstick_debug_get_tpc_name(int tpc) 51 { 52 return tpc_names[tpc-1]; 53 } 54 EXPORT_SYMBOL(memstick_debug_get_tpc_name); 55 56 57 /* Read a register*/ 58 static inline u32 r592_read_reg(struct r592_device *dev, int address) 59 { 60 u32 value = readl(dev->mmio + address); 61 dbg_reg("reg #%02d == 0x%08x", address, value); 62 return value; 63 } 64 65 /* Write a register */ 66 static inline void r592_write_reg(struct r592_device *dev, 67 int address, u32 value) 68 { 69 dbg_reg("reg #%02d <- 0x%08x", address, value); 70 writel(value, dev->mmio + address); 71 } 72 73 /* Reads a big endian DWORD register */ 74 static inline u32 r592_read_reg_raw_be(struct r592_device *dev, int address) 75 { 76 u32 value = __raw_readl(dev->mmio + address); 77 dbg_reg("reg #%02d == 0x%08x", address, value); 78 return be32_to_cpu(value); 79 } 80 81 /* Writes a big endian DWORD register */ 82 static inline void r592_write_reg_raw_be(struct r592_device *dev, 83 int address, u32 value) 84 { 85 dbg_reg("reg #%02d <- 0x%08x", address, value); 86 __raw_writel(cpu_to_be32(value), dev->mmio + address); 87 } 88 89 /* Set specific bits in a register (little endian) */ 90 static inline void r592_set_reg_mask(struct r592_device *dev, 91 int address, u32 mask) 92 { 93 u32 reg = readl(dev->mmio + address); 94 dbg_reg("reg #%02d |= 0x%08x (old =0x%08x)", address, mask, reg); 95 writel(reg | mask , dev->mmio + address); 96 } 97 98 /* Clear specific bits in a register (little endian) */ 99 static inline void r592_clear_reg_mask(struct r592_device *dev, 100 int address, u32 mask) 101 { 102 u32 reg = readl(dev->mmio + address); 103 dbg_reg("reg #%02d &= 0x%08x (old = 0x%08x, mask = 0x%08x)", 104 address, ~mask, reg, mask); 105 writel(reg & ~mask, dev->mmio + address); 106 } 107 108 109 /* Wait for status bits while checking for errors */ 110 static int r592_wait_status(struct r592_device *dev, u32 mask, u32 wanted_mask) 111 { 112 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 113 u32 reg = r592_read_reg(dev, R592_STATUS); 114 115 if ((reg & mask) == wanted_mask) 116 return 0; 117 118 while (time_before(jiffies, timeout)) { 119 120 reg = r592_read_reg(dev, R592_STATUS); 121 122 if ((reg & mask) == wanted_mask) 123 return 0; 124 125 if (reg & (R592_STATUS_SEND_ERR | R592_STATUS_RECV_ERR)) 126 return -EIO; 127 128 cpu_relax(); 129 } 130 return -ETIME; 131 } 132 133 134 /* Enable/disable device */ 135 static int r592_enable_device(struct r592_device *dev, bool enable) 136 { 137 dbg("%sabling the device", enable ? "en" : "dis"); 138 139 if (enable) { 140 141 /* Power up the card */ 142 r592_write_reg(dev, R592_POWER, R592_POWER_0 | R592_POWER_1); 143 144 /* Perform a reset */ 145 r592_set_reg_mask(dev, R592_IO, R592_IO_RESET); 146 147 msleep(100); 148 } else 149 /* Power down the card */ 150 r592_write_reg(dev, R592_POWER, 0); 151 152 return 0; 153 } 154 155 /* Set serial/parallel mode */ 156 static int r592_set_mode(struct r592_device *dev, bool parallel_mode) 157 { 158 if (!parallel_mode) { 159 dbg("switching to serial mode"); 160 161 /* Set serial mode */ 162 r592_write_reg(dev, R592_IO_MODE, R592_IO_MODE_SERIAL); 163 164 r592_clear_reg_mask(dev, R592_POWER, R592_POWER_20); 165 166 } else { 167 dbg("switching to parallel mode"); 168 169 /* This setting should be set _before_ switch TPC */ 170 r592_set_reg_mask(dev, R592_POWER, R592_POWER_20); 171 172 r592_clear_reg_mask(dev, R592_IO, 173 R592_IO_SERIAL1 | R592_IO_SERIAL2); 174 175 /* Set the parallel mode now */ 176 r592_write_reg(dev, R592_IO_MODE, R592_IO_MODE_PARALLEL); 177 } 178 179 dev->parallel_mode = parallel_mode; 180 return 0; 181 } 182 183 /* Perform a controller reset without powering down the card */ 184 static void r592_host_reset(struct r592_device *dev) 185 { 186 r592_set_reg_mask(dev, R592_IO, R592_IO_RESET); 187 msleep(100); 188 r592_set_mode(dev, dev->parallel_mode); 189 } 190 191 #ifdef CONFIG_PM_SLEEP 192 /* Disable all hardware interrupts */ 193 static void r592_clear_interrupts(struct r592_device *dev) 194 { 195 /* Disable & ACK all interrupts */ 196 r592_clear_reg_mask(dev, R592_REG_MSC, IRQ_ALL_ACK_MASK); 197 r592_clear_reg_mask(dev, R592_REG_MSC, IRQ_ALL_EN_MASK); 198 } 199 #endif 200 201 /* Tests if there is an CRC error */ 202 static int r592_test_io_error(struct r592_device *dev) 203 { 204 if (!(r592_read_reg(dev, R592_STATUS) & 205 (R592_STATUS_SEND_ERR | R592_STATUS_RECV_ERR))) 206 return 0; 207 208 return -EIO; 209 } 210 211 /* Ensure that FIFO is ready for use */ 212 static int r592_test_fifo_empty(struct r592_device *dev) 213 { 214 if (r592_read_reg(dev, R592_REG_MSC) & R592_REG_MSC_FIFO_EMPTY) 215 return 0; 216 217 dbg("FIFO not ready, trying to reset the device"); 218 r592_host_reset(dev); 219 220 if (r592_read_reg(dev, R592_REG_MSC) & R592_REG_MSC_FIFO_EMPTY) 221 return 0; 222 223 message("FIFO still not ready, giving up"); 224 return -EIO; 225 } 226 227 /* Activates the DMA transfer from to FIFO */ 228 static void r592_start_dma(struct r592_device *dev, bool is_write) 229 { 230 unsigned long flags; 231 u32 reg; 232 spin_lock_irqsave(&dev->irq_lock, flags); 233 234 /* Ack interrupts (just in case) + enable them */ 235 r592_clear_reg_mask(dev, R592_REG_MSC, DMA_IRQ_ACK_MASK); 236 r592_set_reg_mask(dev, R592_REG_MSC, DMA_IRQ_EN_MASK); 237 238 /* Set DMA address */ 239 r592_write_reg(dev, R592_FIFO_DMA, sg_dma_address(&dev->req->sg)); 240 241 /* Enable the DMA */ 242 reg = r592_read_reg(dev, R592_FIFO_DMA_SETTINGS); 243 reg |= R592_FIFO_DMA_SETTINGS_EN; 244 245 if (!is_write) 246 reg |= R592_FIFO_DMA_SETTINGS_DIR; 247 else 248 reg &= ~R592_FIFO_DMA_SETTINGS_DIR; 249 r592_write_reg(dev, R592_FIFO_DMA_SETTINGS, reg); 250 251 spin_unlock_irqrestore(&dev->irq_lock, flags); 252 } 253 254 /* Cleanups DMA related settings */ 255 static void r592_stop_dma(struct r592_device *dev, int error) 256 { 257 r592_clear_reg_mask(dev, R592_FIFO_DMA_SETTINGS, 258 R592_FIFO_DMA_SETTINGS_EN); 259 260 /* This is only a precation */ 261 r592_write_reg(dev, R592_FIFO_DMA, 262 dev->dummy_dma_page_physical_address); 263 264 r592_clear_reg_mask(dev, R592_REG_MSC, DMA_IRQ_EN_MASK); 265 r592_clear_reg_mask(dev, R592_REG_MSC, DMA_IRQ_ACK_MASK); 266 dev->dma_error = error; 267 } 268 269 /* Test if hardware supports DMA */ 270 static void r592_check_dma(struct r592_device *dev) 271 { 272 dev->dma_capable = r592_enable_dma && 273 (r592_read_reg(dev, R592_FIFO_DMA_SETTINGS) & 274 R592_FIFO_DMA_SETTINGS_CAP); 275 } 276 277 /* Transfers fifo contents in/out using DMA */ 278 static int r592_transfer_fifo_dma(struct r592_device *dev) 279 { 280 int len, sg_count; 281 bool is_write; 282 283 if (!dev->dma_capable || !dev->req->long_data) 284 return -EINVAL; 285 286 len = dev->req->sg.length; 287 is_write = dev->req->data_dir == WRITE; 288 289 if (len != R592_LFIFO_SIZE) 290 return -EINVAL; 291 292 dbg_verbose("doing dma transfer"); 293 294 dev->dma_error = 0; 295 reinit_completion(&dev->dma_done); 296 297 /* TODO: hidden assumption about nenth beeing always 1 */ 298 sg_count = dma_map_sg(&dev->pci_dev->dev, &dev->req->sg, 1, is_write ? 299 PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE); 300 301 if (sg_count != 1 || 302 (sg_dma_len(&dev->req->sg) < dev->req->sg.length)) { 303 message("problem in dma_map_sg"); 304 return -EIO; 305 } 306 307 r592_start_dma(dev, is_write); 308 309 /* Wait for DMA completion */ 310 if (!wait_for_completion_timeout( 311 &dev->dma_done, msecs_to_jiffies(1000))) { 312 message("DMA timeout"); 313 r592_stop_dma(dev, -ETIMEDOUT); 314 } 315 316 dma_unmap_sg(&dev->pci_dev->dev, &dev->req->sg, 1, is_write ? 317 PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE); 318 319 320 return dev->dma_error; 321 } 322 323 /* 324 * Writes the FIFO in 4 byte chunks. 325 * If length isn't 4 byte aligned, rest of the data if put to a fifo 326 * to be written later 327 * Use r592_flush_fifo_write to flush that fifo when writing for the 328 * last time 329 */ 330 static void r592_write_fifo_pio(struct r592_device *dev, 331 unsigned char *buffer, int len) 332 { 333 /* flush spill from former write */ 334 if (!kfifo_is_empty(&dev->pio_fifo)) { 335 336 u8 tmp[4] = {0}; 337 int copy_len = kfifo_in(&dev->pio_fifo, buffer, len); 338 339 if (!kfifo_is_full(&dev->pio_fifo)) 340 return; 341 len -= copy_len; 342 buffer += copy_len; 343 344 copy_len = kfifo_out(&dev->pio_fifo, tmp, 4); 345 WARN_ON(copy_len != 4); 346 r592_write_reg_raw_be(dev, R592_FIFO_PIO, *(u32 *)tmp); 347 } 348 349 WARN_ON(!kfifo_is_empty(&dev->pio_fifo)); 350 351 /* write full dwords */ 352 while (len >= 4) { 353 r592_write_reg_raw_be(dev, R592_FIFO_PIO, *(u32 *)buffer); 354 buffer += 4; 355 len -= 4; 356 } 357 358 /* put remaining bytes to the spill */ 359 if (len) 360 kfifo_in(&dev->pio_fifo, buffer, len); 361 } 362 363 /* Flushes the temporary FIFO used to make aligned DWORD writes */ 364 static void r592_flush_fifo_write(struct r592_device *dev) 365 { 366 u8 buffer[4] = { 0 }; 367 int len; 368 369 if (kfifo_is_empty(&dev->pio_fifo)) 370 return; 371 372 len = kfifo_out(&dev->pio_fifo, buffer, 4); 373 r592_write_reg_raw_be(dev, R592_FIFO_PIO, *(u32 *)buffer); 374 } 375 376 /* 377 * Read a fifo in 4 bytes chunks. 378 * If input doesn't fit the buffer, it places bytes of last dword in spill 379 * buffer, so that they don't get lost on last read, just throw these away. 380 */ 381 static void r592_read_fifo_pio(struct r592_device *dev, 382 unsigned char *buffer, int len) 383 { 384 u8 tmp[4]; 385 386 /* Read from last spill */ 387 if (!kfifo_is_empty(&dev->pio_fifo)) { 388 int bytes_copied = 389 kfifo_out(&dev->pio_fifo, buffer, min(4, len)); 390 buffer += bytes_copied; 391 len -= bytes_copied; 392 393 if (!kfifo_is_empty(&dev->pio_fifo)) 394 return; 395 } 396 397 /* Reads dwords from FIFO */ 398 while (len >= 4) { 399 *(u32 *)buffer = r592_read_reg_raw_be(dev, R592_FIFO_PIO); 400 buffer += 4; 401 len -= 4; 402 } 403 404 if (len) { 405 *(u32 *)tmp = r592_read_reg_raw_be(dev, R592_FIFO_PIO); 406 kfifo_in(&dev->pio_fifo, tmp, 4); 407 len -= kfifo_out(&dev->pio_fifo, buffer, len); 408 } 409 410 WARN_ON(len); 411 return; 412 } 413 414 /* Transfers actual data using PIO. */ 415 static int r592_transfer_fifo_pio(struct r592_device *dev) 416 { 417 unsigned long flags; 418 419 bool is_write = dev->req->tpc >= MS_TPC_SET_RW_REG_ADRS; 420 struct sg_mapping_iter miter; 421 422 kfifo_reset(&dev->pio_fifo); 423 424 if (!dev->req->long_data) { 425 if (is_write) { 426 r592_write_fifo_pio(dev, dev->req->data, 427 dev->req->data_len); 428 r592_flush_fifo_write(dev); 429 } else 430 r592_read_fifo_pio(dev, dev->req->data, 431 dev->req->data_len); 432 return 0; 433 } 434 435 local_irq_save(flags); 436 sg_miter_start(&miter, &dev->req->sg, 1, SG_MITER_ATOMIC | 437 (is_write ? SG_MITER_FROM_SG : SG_MITER_TO_SG)); 438 439 /* Do the transfer fifo<->memory*/ 440 while (sg_miter_next(&miter)) 441 if (is_write) 442 r592_write_fifo_pio(dev, miter.addr, miter.length); 443 else 444 r592_read_fifo_pio(dev, miter.addr, miter.length); 445 446 447 /* Write last few non aligned bytes*/ 448 if (is_write) 449 r592_flush_fifo_write(dev); 450 451 sg_miter_stop(&miter); 452 local_irq_restore(flags); 453 return 0; 454 } 455 456 /* Executes one TPC (data is read/written from small or large fifo) */ 457 static void r592_execute_tpc(struct r592_device *dev) 458 { 459 bool is_write; 460 int len, error; 461 u32 status, reg; 462 463 if (!dev->req) { 464 message("BUG: tpc execution without request!"); 465 return; 466 } 467 468 is_write = dev->req->tpc >= MS_TPC_SET_RW_REG_ADRS; 469 len = dev->req->long_data ? 470 dev->req->sg.length : dev->req->data_len; 471 472 /* Ensure that FIFO can hold the input data */ 473 if (len > R592_LFIFO_SIZE) { 474 message("IO: hardware doesn't support TPCs longer that 512"); 475 error = -ENOSYS; 476 goto out; 477 } 478 479 if (!(r592_read_reg(dev, R592_REG_MSC) & R592_REG_MSC_PRSNT)) { 480 dbg("IO: refusing to send TPC because card is absent"); 481 error = -ENODEV; 482 goto out; 483 } 484 485 dbg("IO: executing %s LEN=%d", 486 memstick_debug_get_tpc_name(dev->req->tpc), len); 487 488 /* Set IO direction */ 489 if (is_write) 490 r592_set_reg_mask(dev, R592_IO, R592_IO_DIRECTION); 491 else 492 r592_clear_reg_mask(dev, R592_IO, R592_IO_DIRECTION); 493 494 495 error = r592_test_fifo_empty(dev); 496 if (error) 497 goto out; 498 499 /* Transfer write data */ 500 if (is_write) { 501 error = r592_transfer_fifo_dma(dev); 502 if (error == -EINVAL) 503 error = r592_transfer_fifo_pio(dev); 504 } 505 506 if (error) 507 goto out; 508 509 /* Trigger the TPC */ 510 reg = (len << R592_TPC_EXEC_LEN_SHIFT) | 511 (dev->req->tpc << R592_TPC_EXEC_TPC_SHIFT) | 512 R592_TPC_EXEC_BIG_FIFO; 513 514 r592_write_reg(dev, R592_TPC_EXEC, reg); 515 516 /* Wait for TPC completion */ 517 status = R592_STATUS_RDY; 518 if (dev->req->need_card_int) 519 status |= R592_STATUS_CED; 520 521 error = r592_wait_status(dev, status, status); 522 if (error) { 523 message("card didn't respond"); 524 goto out; 525 } 526 527 /* Test IO errors */ 528 error = r592_test_io_error(dev); 529 if (error) { 530 dbg("IO error"); 531 goto out; 532 } 533 534 /* Read data from FIFO */ 535 if (!is_write) { 536 error = r592_transfer_fifo_dma(dev); 537 if (error == -EINVAL) 538 error = r592_transfer_fifo_pio(dev); 539 } 540 541 /* read INT reg. This can be shortened with shifts, but that way 542 its more readable */ 543 if (dev->parallel_mode && dev->req->need_card_int) { 544 545 dev->req->int_reg = 0; 546 status = r592_read_reg(dev, R592_STATUS); 547 548 if (status & R592_STATUS_P_CMDNACK) 549 dev->req->int_reg |= MEMSTICK_INT_CMDNAK; 550 if (status & R592_STATUS_P_BREQ) 551 dev->req->int_reg |= MEMSTICK_INT_BREQ; 552 if (status & R592_STATUS_P_INTERR) 553 dev->req->int_reg |= MEMSTICK_INT_ERR; 554 if (status & R592_STATUS_P_CED) 555 dev->req->int_reg |= MEMSTICK_INT_CED; 556 } 557 558 if (error) 559 dbg("FIFO read error"); 560 out: 561 dev->req->error = error; 562 r592_clear_reg_mask(dev, R592_REG_MSC, R592_REG_MSC_LED); 563 return; 564 } 565 566 /* Main request processing thread */ 567 static int r592_process_thread(void *data) 568 { 569 int error; 570 struct r592_device *dev = (struct r592_device *)data; 571 unsigned long flags; 572 573 while (!kthread_should_stop()) { 574 spin_lock_irqsave(&dev->io_thread_lock, flags); 575 set_current_state(TASK_INTERRUPTIBLE); 576 error = memstick_next_req(dev->host, &dev->req); 577 spin_unlock_irqrestore(&dev->io_thread_lock, flags); 578 579 if (error) { 580 if (error == -ENXIO || error == -EAGAIN) { 581 dbg_verbose("IO: done IO, sleeping"); 582 } else { 583 dbg("IO: unknown error from " 584 "memstick_next_req %d", error); 585 } 586 587 if (kthread_should_stop()) 588 set_current_state(TASK_RUNNING); 589 590 schedule(); 591 } else { 592 set_current_state(TASK_RUNNING); 593 r592_execute_tpc(dev); 594 } 595 } 596 return 0; 597 } 598 599 /* Reprogram chip to detect change in card state */ 600 /* eg, if card is detected, arm it to detect removal, and vice versa */ 601 static void r592_update_card_detect(struct r592_device *dev) 602 { 603 u32 reg = r592_read_reg(dev, R592_REG_MSC); 604 bool card_detected = reg & R592_REG_MSC_PRSNT; 605 606 dbg("update card detect. card state: %s", card_detected ? 607 "present" : "absent"); 608 609 reg &= ~((R592_REG_MSC_IRQ_REMOVE | R592_REG_MSC_IRQ_INSERT) << 16); 610 611 if (card_detected) 612 reg |= (R592_REG_MSC_IRQ_REMOVE << 16); 613 else 614 reg |= (R592_REG_MSC_IRQ_INSERT << 16); 615 616 r592_write_reg(dev, R592_REG_MSC, reg); 617 } 618 619 /* Timer routine that fires 1 second after last card detection event, */ 620 static void r592_detect_timer(long unsigned int data) 621 { 622 struct r592_device *dev = (struct r592_device *)data; 623 r592_update_card_detect(dev); 624 memstick_detect_change(dev->host); 625 } 626 627 /* Interrupt handler */ 628 static irqreturn_t r592_irq(int irq, void *data) 629 { 630 struct r592_device *dev = (struct r592_device *)data; 631 irqreturn_t ret = IRQ_NONE; 632 u32 reg; 633 u16 irq_enable, irq_status; 634 unsigned long flags; 635 int error; 636 637 spin_lock_irqsave(&dev->irq_lock, flags); 638 639 reg = r592_read_reg(dev, R592_REG_MSC); 640 irq_enable = reg >> 16; 641 irq_status = reg & 0xFFFF; 642 643 /* Ack the interrupts */ 644 reg &= ~irq_status; 645 r592_write_reg(dev, R592_REG_MSC, reg); 646 647 /* Get the IRQ status minus bits that aren't enabled */ 648 irq_status &= (irq_enable); 649 650 /* Due to limitation of memstick core, we don't look at bits that 651 indicate that card was removed/inserted and/or present */ 652 if (irq_status & (R592_REG_MSC_IRQ_INSERT | R592_REG_MSC_IRQ_REMOVE)) { 653 654 bool card_was_added = irq_status & R592_REG_MSC_IRQ_INSERT; 655 ret = IRQ_HANDLED; 656 657 message("IRQ: card %s", card_was_added ? "added" : "removed"); 658 659 mod_timer(&dev->detect_timer, 660 jiffies + msecs_to_jiffies(card_was_added ? 500 : 50)); 661 } 662 663 if (irq_status & 664 (R592_REG_MSC_FIFO_DMA_DONE | R592_REG_MSC_FIFO_DMA_ERR)) { 665 ret = IRQ_HANDLED; 666 667 if (irq_status & R592_REG_MSC_FIFO_DMA_ERR) { 668 message("IRQ: DMA error"); 669 error = -EIO; 670 } else { 671 dbg_verbose("IRQ: dma done"); 672 error = 0; 673 } 674 675 r592_stop_dma(dev, error); 676 complete(&dev->dma_done); 677 } 678 679 spin_unlock_irqrestore(&dev->irq_lock, flags); 680 return ret; 681 } 682 683 /* External inteface: set settings */ 684 static int r592_set_param(struct memstick_host *host, 685 enum memstick_param param, int value) 686 { 687 struct r592_device *dev = memstick_priv(host); 688 689 switch (param) { 690 case MEMSTICK_POWER: 691 switch (value) { 692 case MEMSTICK_POWER_ON: 693 return r592_enable_device(dev, true); 694 case MEMSTICK_POWER_OFF: 695 return r592_enable_device(dev, false); 696 default: 697 return -EINVAL; 698 } 699 case MEMSTICK_INTERFACE: 700 switch (value) { 701 case MEMSTICK_SERIAL: 702 return r592_set_mode(dev, 0); 703 case MEMSTICK_PAR4: 704 return r592_set_mode(dev, 1); 705 default: 706 return -EINVAL; 707 } 708 default: 709 return -EINVAL; 710 } 711 } 712 713 /* External interface: submit requests */ 714 static void r592_submit_req(struct memstick_host *host) 715 { 716 struct r592_device *dev = memstick_priv(host); 717 unsigned long flags; 718 719 if (dev->req) 720 return; 721 722 spin_lock_irqsave(&dev->io_thread_lock, flags); 723 if (wake_up_process(dev->io_thread)) 724 dbg_verbose("IO thread woken to process requests"); 725 spin_unlock_irqrestore(&dev->io_thread_lock, flags); 726 } 727 728 static const struct pci_device_id r592_pci_id_tbl[] = { 729 730 { PCI_VDEVICE(RICOH, 0x0592), }, 731 { }, 732 }; 733 734 /* Main entry */ 735 static int r592_probe(struct pci_dev *pdev, const struct pci_device_id *id) 736 { 737 int error = -ENOMEM; 738 struct memstick_host *host; 739 struct r592_device *dev; 740 741 /* Allocate memory */ 742 host = memstick_alloc_host(sizeof(struct r592_device), &pdev->dev); 743 if (!host) 744 goto error1; 745 746 dev = memstick_priv(host); 747 dev->host = host; 748 dev->pci_dev = pdev; 749 pci_set_drvdata(pdev, dev); 750 751 /* pci initialization */ 752 error = pci_enable_device(pdev); 753 if (error) 754 goto error2; 755 756 pci_set_master(pdev); 757 error = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 758 if (error) 759 goto error3; 760 761 error = pci_request_regions(pdev, DRV_NAME); 762 if (error) 763 goto error3; 764 765 dev->mmio = pci_ioremap_bar(pdev, 0); 766 if (!dev->mmio) 767 goto error4; 768 769 dev->irq = pdev->irq; 770 spin_lock_init(&dev->irq_lock); 771 spin_lock_init(&dev->io_thread_lock); 772 init_completion(&dev->dma_done); 773 INIT_KFIFO(dev->pio_fifo); 774 setup_timer(&dev->detect_timer, 775 r592_detect_timer, (long unsigned int)dev); 776 777 /* Host initialization */ 778 host->caps = MEMSTICK_CAP_PAR4; 779 host->request = r592_submit_req; 780 host->set_param = r592_set_param; 781 r592_check_dma(dev); 782 783 dev->io_thread = kthread_run(r592_process_thread, dev, "r592_io"); 784 if (IS_ERR(dev->io_thread)) { 785 error = PTR_ERR(dev->io_thread); 786 goto error5; 787 } 788 789 /* This is just a precation, so don't fail */ 790 dev->dummy_dma_page = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 791 &dev->dummy_dma_page_physical_address, GFP_KERNEL); 792 r592_stop_dma(dev , 0); 793 794 if (request_irq(dev->irq, &r592_irq, IRQF_SHARED, 795 DRV_NAME, dev)) 796 goto error6; 797 798 r592_update_card_detect(dev); 799 if (memstick_add_host(host)) 800 goto error7; 801 802 message("driver successfully loaded"); 803 return 0; 804 error7: 805 free_irq(dev->irq, dev); 806 error6: 807 if (dev->dummy_dma_page) 808 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->dummy_dma_page, 809 dev->dummy_dma_page_physical_address); 810 811 kthread_stop(dev->io_thread); 812 error5: 813 iounmap(dev->mmio); 814 error4: 815 pci_release_regions(pdev); 816 error3: 817 pci_disable_device(pdev); 818 error2: 819 memstick_free_host(host); 820 error1: 821 return error; 822 } 823 824 static void r592_remove(struct pci_dev *pdev) 825 { 826 int error = 0; 827 struct r592_device *dev = pci_get_drvdata(pdev); 828 829 /* Stop the processing thread. 830 That ensures that we won't take any more requests */ 831 kthread_stop(dev->io_thread); 832 833 r592_enable_device(dev, false); 834 835 while (!error && dev->req) { 836 dev->req->error = -ETIME; 837 error = memstick_next_req(dev->host, &dev->req); 838 } 839 memstick_remove_host(dev->host); 840 841 free_irq(dev->irq, dev); 842 iounmap(dev->mmio); 843 pci_release_regions(pdev); 844 pci_disable_device(pdev); 845 memstick_free_host(dev->host); 846 847 if (dev->dummy_dma_page) 848 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->dummy_dma_page, 849 dev->dummy_dma_page_physical_address); 850 } 851 852 #ifdef CONFIG_PM_SLEEP 853 static int r592_suspend(struct device *core_dev) 854 { 855 struct pci_dev *pdev = to_pci_dev(core_dev); 856 struct r592_device *dev = pci_get_drvdata(pdev); 857 858 r592_clear_interrupts(dev); 859 memstick_suspend_host(dev->host); 860 del_timer_sync(&dev->detect_timer); 861 return 0; 862 } 863 864 static int r592_resume(struct device *core_dev) 865 { 866 struct pci_dev *pdev = to_pci_dev(core_dev); 867 struct r592_device *dev = pci_get_drvdata(pdev); 868 869 r592_clear_interrupts(dev); 870 r592_enable_device(dev, false); 871 memstick_resume_host(dev->host); 872 r592_update_card_detect(dev); 873 return 0; 874 } 875 #endif 876 877 static SIMPLE_DEV_PM_OPS(r592_pm_ops, r592_suspend, r592_resume); 878 879 MODULE_DEVICE_TABLE(pci, r592_pci_id_tbl); 880 881 static struct pci_driver r852_pci_driver = { 882 .name = DRV_NAME, 883 .id_table = r592_pci_id_tbl, 884 .probe = r592_probe, 885 .remove = r592_remove, 886 .driver.pm = &r592_pm_ops, 887 }; 888 889 module_pci_driver(r852_pci_driver); 890 891 module_param_named(enable_dma, r592_enable_dma, bool, S_IRUGO); 892 MODULE_PARM_DESC(enable_dma, "Enable usage of the DMA (default)"); 893 module_param(debug, int, S_IRUGO | S_IWUSR); 894 MODULE_PARM_DESC(debug, "Debug level (0-3)"); 895 896 MODULE_LICENSE("GPL"); 897 MODULE_AUTHOR("Maxim Levitsky <maximlevitsky@gmail.com>"); 898 MODULE_DESCRIPTION("Ricoh R5C592 Memstick/Memstick PRO card reader driver"); 899