1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
260fdd931SAlex Dubov /*
360fdd931SAlex Dubov * jmb38x_ms.c - JMicron jmb38x MemoryStick card reader
460fdd931SAlex Dubov *
560fdd931SAlex Dubov * Copyright (C) 2008 Alex Dubov <oakad@yahoo.com>
660fdd931SAlex Dubov */
760fdd931SAlex Dubov
860fdd931SAlex Dubov #include <linux/spinlock.h>
960fdd931SAlex Dubov #include <linux/interrupt.h>
1060fdd931SAlex Dubov #include <linux/pci.h>
11d3597ea2SAndrew Morton #include <linux/dma-mapping.h>
1260fdd931SAlex Dubov #include <linux/delay.h>
1360fdd931SAlex Dubov #include <linux/highmem.h>
1460fdd931SAlex Dubov #include <linux/memstick.h>
155a0e3ad6STejun Heo #include <linux/slab.h>
16c47e7893SPaul Gortmaker #include <linux/module.h>
1760fdd931SAlex Dubov
1860fdd931SAlex Dubov #define DRIVER_NAME "jmb38x_ms"
1960fdd931SAlex Dubov
2090ab5ee9SRusty Russell static bool no_dma;
2160fdd931SAlex Dubov module_param(no_dma, bool, 0644);
2260fdd931SAlex Dubov
2360fdd931SAlex Dubov enum {
2460fdd931SAlex Dubov DMA_ADDRESS = 0x00,
2560fdd931SAlex Dubov BLOCK = 0x04,
2660fdd931SAlex Dubov DMA_CONTROL = 0x08,
2760fdd931SAlex Dubov TPC_P0 = 0x0c,
2860fdd931SAlex Dubov TPC_P1 = 0x10,
2960fdd931SAlex Dubov TPC = 0x14,
3060fdd931SAlex Dubov HOST_CONTROL = 0x18,
3160fdd931SAlex Dubov DATA = 0x1c,
3260fdd931SAlex Dubov STATUS = 0x20,
3360fdd931SAlex Dubov INT_STATUS = 0x24,
3460fdd931SAlex Dubov INT_STATUS_ENABLE = 0x28,
3560fdd931SAlex Dubov INT_SIGNAL_ENABLE = 0x2c,
3660fdd931SAlex Dubov TIMER = 0x30,
3760fdd931SAlex Dubov TIMER_CONTROL = 0x34,
3860fdd931SAlex Dubov PAD_OUTPUT_ENABLE = 0x38,
3960fdd931SAlex Dubov PAD_PU_PD = 0x3c,
4060fdd931SAlex Dubov CLOCK_DELAY = 0x40,
4160fdd931SAlex Dubov ADMA_ADDRESS = 0x44,
4260fdd931SAlex Dubov CLOCK_CONTROL = 0x48,
4360fdd931SAlex Dubov LED_CONTROL = 0x4c,
4460fdd931SAlex Dubov VERSION = 0x50
4560fdd931SAlex Dubov };
4660fdd931SAlex Dubov
4760fdd931SAlex Dubov struct jmb38x_ms_host {
4860fdd931SAlex Dubov struct jmb38x_ms *chip;
4960fdd931SAlex Dubov void __iomem *addr;
5060fdd931SAlex Dubov spinlock_t lock;
51f1d82698SAlex Dubov struct tasklet_struct notify;
5260fdd931SAlex Dubov int id;
53b98cb4b7SGreg Kroah-Hartman char host_id[32];
5460fdd931SAlex Dubov int irq;
5560fdd931SAlex Dubov unsigned int block_pos;
5660fdd931SAlex Dubov unsigned long timeout_jiffies;
5760fdd931SAlex Dubov struct timer_list timer;
586243d38fSKees Cook struct memstick_host *msh;
5960fdd931SAlex Dubov struct memstick_request *req;
6060fdd931SAlex Dubov unsigned char cmd_flags;
6160fdd931SAlex Dubov unsigned char io_pos;
6223c5947aSTakashi Iwai unsigned char ifmode;
6360fdd931SAlex Dubov unsigned int io_word[2];
6460fdd931SAlex Dubov };
6560fdd931SAlex Dubov
6660fdd931SAlex Dubov struct jmb38x_ms {
6760fdd931SAlex Dubov struct pci_dev *pdev;
6860fdd931SAlex Dubov int host_cnt;
69*45492b13SKees Cook struct memstick_host *hosts[] __counted_by(host_cnt);
7060fdd931SAlex Dubov };
7160fdd931SAlex Dubov
7260fdd931SAlex Dubov #define BLOCK_COUNT_MASK 0xffff0000
7360fdd931SAlex Dubov #define BLOCK_SIZE_MASK 0x00000fff
7460fdd931SAlex Dubov
7560fdd931SAlex Dubov #define DMA_CONTROL_ENABLE 0x00000001
7660fdd931SAlex Dubov
7760fdd931SAlex Dubov #define TPC_DATA_SEL 0x00008000
7860fdd931SAlex Dubov #define TPC_DIR 0x00004000
7960fdd931SAlex Dubov #define TPC_WAIT_INT 0x00002000
8060fdd931SAlex Dubov #define TPC_GET_INT 0x00000800
8160fdd931SAlex Dubov #define TPC_CODE_SZ_MASK 0x00000700
8260fdd931SAlex Dubov #define TPC_DATA_SZ_MASK 0x00000007
8360fdd931SAlex Dubov
848e82f8c3SAlex Dubov #define HOST_CONTROL_TDELAY_EN 0x00040000
858e82f8c3SAlex Dubov #define HOST_CONTROL_HW_OC_P 0x00010000
8660fdd931SAlex Dubov #define HOST_CONTROL_RESET_REQ 0x00008000
8760fdd931SAlex Dubov #define HOST_CONTROL_REI 0x00004000
8860fdd931SAlex Dubov #define HOST_CONTROL_LED 0x00000400
8960fdd931SAlex Dubov #define HOST_CONTROL_FAST_CLK 0x00000200
9060fdd931SAlex Dubov #define HOST_CONTROL_RESET 0x00000100
9160fdd931SAlex Dubov #define HOST_CONTROL_POWER_EN 0x00000080
9260fdd931SAlex Dubov #define HOST_CONTROL_CLOCK_EN 0x00000040
938e82f8c3SAlex Dubov #define HOST_CONTROL_REO 0x00000008
9460fdd931SAlex Dubov #define HOST_CONTROL_IF_SHIFT 4
9560fdd931SAlex Dubov
9660fdd931SAlex Dubov #define HOST_CONTROL_IF_SERIAL 0x0
9760fdd931SAlex Dubov #define HOST_CONTROL_IF_PAR4 0x1
9860fdd931SAlex Dubov #define HOST_CONTROL_IF_PAR8 0x3
9960fdd931SAlex Dubov
100ead70773SAlex Dubov #define STATUS_BUSY 0x00080000
101ead70773SAlex Dubov #define STATUS_MS_DAT7 0x00040000
102ead70773SAlex Dubov #define STATUS_MS_DAT6 0x00020000
103ead70773SAlex Dubov #define STATUS_MS_DAT5 0x00010000
104ead70773SAlex Dubov #define STATUS_MS_DAT4 0x00008000
105ead70773SAlex Dubov #define STATUS_MS_DAT3 0x00004000
106ead70773SAlex Dubov #define STATUS_MS_DAT2 0x00002000
107ead70773SAlex Dubov #define STATUS_MS_DAT1 0x00001000
108ead70773SAlex Dubov #define STATUS_MS_DAT0 0x00000800
10960fdd931SAlex Dubov #define STATUS_HAS_MEDIA 0x00000400
11060fdd931SAlex Dubov #define STATUS_FIFO_EMPTY 0x00000200
11160fdd931SAlex Dubov #define STATUS_FIFO_FULL 0x00000100
112ead70773SAlex Dubov #define STATUS_MS_CED 0x00000080
113ead70773SAlex Dubov #define STATUS_MS_ERR 0x00000040
114ead70773SAlex Dubov #define STATUS_MS_BRQ 0x00000020
115ead70773SAlex Dubov #define STATUS_MS_CNK 0x00000001
11660fdd931SAlex Dubov
11760fdd931SAlex Dubov #define INT_STATUS_TPC_ERR 0x00080000
11860fdd931SAlex Dubov #define INT_STATUS_CRC_ERR 0x00040000
11960fdd931SAlex Dubov #define INT_STATUS_TIMER_TO 0x00020000
12060fdd931SAlex Dubov #define INT_STATUS_HSK_TO 0x00010000
12160fdd931SAlex Dubov #define INT_STATUS_ANY_ERR 0x00008000
12260fdd931SAlex Dubov #define INT_STATUS_FIFO_WRDY 0x00000080
12360fdd931SAlex Dubov #define INT_STATUS_FIFO_RRDY 0x00000040
12460fdd931SAlex Dubov #define INT_STATUS_MEDIA_OUT 0x00000010
12560fdd931SAlex Dubov #define INT_STATUS_MEDIA_IN 0x00000008
12660fdd931SAlex Dubov #define INT_STATUS_DMA_BOUNDARY 0x00000004
12760fdd931SAlex Dubov #define INT_STATUS_EOTRAN 0x00000002
12860fdd931SAlex Dubov #define INT_STATUS_EOTPC 0x00000001
12960fdd931SAlex Dubov
13060fdd931SAlex Dubov #define INT_STATUS_ALL 0x000f801f
13160fdd931SAlex Dubov
13260fdd931SAlex Dubov #define PAD_OUTPUT_ENABLE_MS 0x0F3F
13360fdd931SAlex Dubov
13460fdd931SAlex Dubov #define PAD_PU_PD_OFF 0x7FFF0000
13560fdd931SAlex Dubov #define PAD_PU_PD_ON_MS_SOCK0 0x5f8f0000
13660fdd931SAlex Dubov #define PAD_PU_PD_ON_MS_SOCK1 0x0f0f0000
13760fdd931SAlex Dubov
13823c5947aSTakashi Iwai #define CLOCK_CONTROL_BY_MMIO 0x00000008
139cf821e8fSAlex Dubov #define CLOCK_CONTROL_40MHZ 0x00000001
14023c5947aSTakashi Iwai #define CLOCK_CONTROL_50MHZ 0x00000002
14123c5947aSTakashi Iwai #define CLOCK_CONTROL_60MHZ 0x00000010
14223c5947aSTakashi Iwai #define CLOCK_CONTROL_62_5MHZ 0x00000004
143cf821e8fSAlex Dubov #define CLOCK_CONTROL_OFF 0x00000000
144cf821e8fSAlex Dubov
1458e82f8c3SAlex Dubov #define PCI_CTL_CLOCK_DLY_ADDR 0x000000b0
1468e82f8c3SAlex Dubov
14760fdd931SAlex Dubov enum {
14860fdd931SAlex Dubov CMD_READY = 0x01,
14960fdd931SAlex Dubov FIFO_READY = 0x02,
15060fdd931SAlex Dubov REG_DATA = 0x04,
151ead70773SAlex Dubov DMA_DATA = 0x08
15260fdd931SAlex Dubov };
15360fdd931SAlex Dubov
jmb38x_ms_read_data(struct jmb38x_ms_host * host,unsigned char * buf,unsigned int length)15460fdd931SAlex Dubov static unsigned int jmb38x_ms_read_data(struct jmb38x_ms_host *host,
15560fdd931SAlex Dubov unsigned char *buf, unsigned int length)
15660fdd931SAlex Dubov {
15760fdd931SAlex Dubov unsigned int off = 0;
15860fdd931SAlex Dubov
15960fdd931SAlex Dubov while (host->io_pos && length) {
16060fdd931SAlex Dubov buf[off++] = host->io_word[0] & 0xff;
16160fdd931SAlex Dubov host->io_word[0] >>= 8;
16260fdd931SAlex Dubov length--;
16360fdd931SAlex Dubov host->io_pos--;
16460fdd931SAlex Dubov }
16560fdd931SAlex Dubov
16660fdd931SAlex Dubov if (!length)
16760fdd931SAlex Dubov return off;
16860fdd931SAlex Dubov
16960fdd931SAlex Dubov while (!(STATUS_FIFO_EMPTY & readl(host->addr + STATUS))) {
17060fdd931SAlex Dubov if (length < 4)
17160fdd931SAlex Dubov break;
17260fdd931SAlex Dubov *(unsigned int *)(buf + off) = __raw_readl(host->addr + DATA);
17360fdd931SAlex Dubov length -= 4;
17460fdd931SAlex Dubov off += 4;
17560fdd931SAlex Dubov }
17660fdd931SAlex Dubov
17760fdd931SAlex Dubov if (length
17860fdd931SAlex Dubov && !(STATUS_FIFO_EMPTY & readl(host->addr + STATUS))) {
17960fdd931SAlex Dubov host->io_word[0] = readl(host->addr + DATA);
18060fdd931SAlex Dubov for (host->io_pos = 4; host->io_pos; --host->io_pos) {
18160fdd931SAlex Dubov buf[off++] = host->io_word[0] & 0xff;
18260fdd931SAlex Dubov host->io_word[0] >>= 8;
18360fdd931SAlex Dubov length--;
18460fdd931SAlex Dubov if (!length)
18560fdd931SAlex Dubov break;
18660fdd931SAlex Dubov }
18760fdd931SAlex Dubov }
18860fdd931SAlex Dubov
18960fdd931SAlex Dubov return off;
19060fdd931SAlex Dubov }
19160fdd931SAlex Dubov
jmb38x_ms_read_reg_data(struct jmb38x_ms_host * host,unsigned char * buf,unsigned int length)19260fdd931SAlex Dubov static unsigned int jmb38x_ms_read_reg_data(struct jmb38x_ms_host *host,
19360fdd931SAlex Dubov unsigned char *buf,
19460fdd931SAlex Dubov unsigned int length)
19560fdd931SAlex Dubov {
19660fdd931SAlex Dubov unsigned int off = 0;
19760fdd931SAlex Dubov
19860fdd931SAlex Dubov while (host->io_pos > 4 && length) {
19960fdd931SAlex Dubov buf[off++] = host->io_word[0] & 0xff;
20060fdd931SAlex Dubov host->io_word[0] >>= 8;
20160fdd931SAlex Dubov length--;
20260fdd931SAlex Dubov host->io_pos--;
20360fdd931SAlex Dubov }
20460fdd931SAlex Dubov
20560fdd931SAlex Dubov if (!length)
20660fdd931SAlex Dubov return off;
20760fdd931SAlex Dubov
20860fdd931SAlex Dubov while (host->io_pos && length) {
20960fdd931SAlex Dubov buf[off++] = host->io_word[1] & 0xff;
21060fdd931SAlex Dubov host->io_word[1] >>= 8;
21160fdd931SAlex Dubov length--;
21260fdd931SAlex Dubov host->io_pos--;
21360fdd931SAlex Dubov }
21460fdd931SAlex Dubov
21560fdd931SAlex Dubov return off;
21660fdd931SAlex Dubov }
21760fdd931SAlex Dubov
jmb38x_ms_write_data(struct jmb38x_ms_host * host,unsigned char * buf,unsigned int length)21860fdd931SAlex Dubov static unsigned int jmb38x_ms_write_data(struct jmb38x_ms_host *host,
21960fdd931SAlex Dubov unsigned char *buf,
22060fdd931SAlex Dubov unsigned int length)
22160fdd931SAlex Dubov {
22260fdd931SAlex Dubov unsigned int off = 0;
22360fdd931SAlex Dubov
22460fdd931SAlex Dubov if (host->io_pos) {
22560fdd931SAlex Dubov while (host->io_pos < 4 && length) {
22660fdd931SAlex Dubov host->io_word[0] |= buf[off++] << (host->io_pos * 8);
22760fdd931SAlex Dubov host->io_pos++;
22860fdd931SAlex Dubov length--;
22960fdd931SAlex Dubov }
23060fdd931SAlex Dubov }
23160fdd931SAlex Dubov
23260fdd931SAlex Dubov if (host->io_pos == 4
23360fdd931SAlex Dubov && !(STATUS_FIFO_FULL & readl(host->addr + STATUS))) {
23460fdd931SAlex Dubov writel(host->io_word[0], host->addr + DATA);
23560fdd931SAlex Dubov host->io_pos = 0;
23660fdd931SAlex Dubov host->io_word[0] = 0;
23760fdd931SAlex Dubov } else if (host->io_pos) {
23860fdd931SAlex Dubov return off;
23960fdd931SAlex Dubov }
24060fdd931SAlex Dubov
24160fdd931SAlex Dubov if (!length)
24260fdd931SAlex Dubov return off;
24360fdd931SAlex Dubov
24460fdd931SAlex Dubov while (!(STATUS_FIFO_FULL & readl(host->addr + STATUS))) {
24560fdd931SAlex Dubov if (length < 4)
24660fdd931SAlex Dubov break;
24760fdd931SAlex Dubov
24860fdd931SAlex Dubov __raw_writel(*(unsigned int *)(buf + off),
24960fdd931SAlex Dubov host->addr + DATA);
25060fdd931SAlex Dubov length -= 4;
25160fdd931SAlex Dubov off += 4;
25260fdd931SAlex Dubov }
25360fdd931SAlex Dubov
25460fdd931SAlex Dubov switch (length) {
25560fdd931SAlex Dubov case 3:
25660fdd931SAlex Dubov host->io_word[0] |= buf[off + 2] << 16;
25760fdd931SAlex Dubov host->io_pos++;
258df561f66SGustavo A. R. Silva fallthrough;
25960fdd931SAlex Dubov case 2:
26060fdd931SAlex Dubov host->io_word[0] |= buf[off + 1] << 8;
26160fdd931SAlex Dubov host->io_pos++;
262df561f66SGustavo A. R. Silva fallthrough;
26360fdd931SAlex Dubov case 1:
26460fdd931SAlex Dubov host->io_word[0] |= buf[off];
26560fdd931SAlex Dubov host->io_pos++;
26660fdd931SAlex Dubov }
26760fdd931SAlex Dubov
26860fdd931SAlex Dubov off += host->io_pos;
26960fdd931SAlex Dubov
27060fdd931SAlex Dubov return off;
27160fdd931SAlex Dubov }
27260fdd931SAlex Dubov
jmb38x_ms_write_reg_data(struct jmb38x_ms_host * host,unsigned char * buf,unsigned int length)27360fdd931SAlex Dubov static unsigned int jmb38x_ms_write_reg_data(struct jmb38x_ms_host *host,
27460fdd931SAlex Dubov unsigned char *buf,
27560fdd931SAlex Dubov unsigned int length)
27660fdd931SAlex Dubov {
27760fdd931SAlex Dubov unsigned int off = 0;
27860fdd931SAlex Dubov
27960fdd931SAlex Dubov while (host->io_pos < 4 && length) {
28060fdd931SAlex Dubov host->io_word[0] &= ~(0xff << (host->io_pos * 8));
28160fdd931SAlex Dubov host->io_word[0] |= buf[off++] << (host->io_pos * 8);
28260fdd931SAlex Dubov host->io_pos++;
28360fdd931SAlex Dubov length--;
28460fdd931SAlex Dubov }
28560fdd931SAlex Dubov
28660fdd931SAlex Dubov if (!length)
28760fdd931SAlex Dubov return off;
28860fdd931SAlex Dubov
28960fdd931SAlex Dubov while (host->io_pos < 8 && length) {
29060fdd931SAlex Dubov host->io_word[1] &= ~(0xff << (host->io_pos * 8));
29160fdd931SAlex Dubov host->io_word[1] |= buf[off++] << (host->io_pos * 8);
29260fdd931SAlex Dubov host->io_pos++;
29360fdd931SAlex Dubov length--;
29460fdd931SAlex Dubov }
29560fdd931SAlex Dubov
29660fdd931SAlex Dubov return off;
29760fdd931SAlex Dubov }
29860fdd931SAlex Dubov
jmb38x_ms_transfer_data(struct jmb38x_ms_host * host)29960fdd931SAlex Dubov static int jmb38x_ms_transfer_data(struct jmb38x_ms_host *host)
30060fdd931SAlex Dubov {
30160fdd931SAlex Dubov unsigned int length;
30260fdd931SAlex Dubov unsigned int off;
3038195096bSAndrew Morton unsigned int t_size, p_cnt;
30460fdd931SAlex Dubov unsigned char *buf;
30560fdd931SAlex Dubov struct page *pg;
30660fdd931SAlex Dubov unsigned long flags = 0;
30760fdd931SAlex Dubov
30860fdd931SAlex Dubov if (host->req->long_data) {
30960fdd931SAlex Dubov length = host->req->sg.length - host->block_pos;
31060fdd931SAlex Dubov off = host->req->sg.offset + host->block_pos;
31160fdd931SAlex Dubov } else {
31260fdd931SAlex Dubov length = host->req->data_len - host->block_pos;
31360fdd931SAlex Dubov off = 0;
31460fdd931SAlex Dubov }
31560fdd931SAlex Dubov
31660fdd931SAlex Dubov while (length) {
3173f649ab7SKees Cook unsigned int p_off;
3188195096bSAndrew Morton
31960fdd931SAlex Dubov if (host->req->long_data) {
32060fdd931SAlex Dubov pg = nth_page(sg_page(&host->req->sg),
32160fdd931SAlex Dubov off >> PAGE_SHIFT);
32260fdd931SAlex Dubov p_off = offset_in_page(off);
32360fdd931SAlex Dubov p_cnt = PAGE_SIZE - p_off;
32460fdd931SAlex Dubov p_cnt = min(p_cnt, length);
32560fdd931SAlex Dubov
32660fdd931SAlex Dubov local_irq_save(flags);
327eb3f0620SCong Wang buf = kmap_atomic(pg) + p_off;
32860fdd931SAlex Dubov } else {
32960fdd931SAlex Dubov buf = host->req->data + host->block_pos;
33060fdd931SAlex Dubov p_cnt = host->req->data_len - host->block_pos;
33160fdd931SAlex Dubov }
33260fdd931SAlex Dubov
33360fdd931SAlex Dubov if (host->req->data_dir == WRITE)
33460fdd931SAlex Dubov t_size = !(host->cmd_flags & REG_DATA)
33560fdd931SAlex Dubov ? jmb38x_ms_write_data(host, buf, p_cnt)
33660fdd931SAlex Dubov : jmb38x_ms_write_reg_data(host, buf, p_cnt);
33760fdd931SAlex Dubov else
33860fdd931SAlex Dubov t_size = !(host->cmd_flags & REG_DATA)
33960fdd931SAlex Dubov ? jmb38x_ms_read_data(host, buf, p_cnt)
34060fdd931SAlex Dubov : jmb38x_ms_read_reg_data(host, buf, p_cnt);
34160fdd931SAlex Dubov
34260fdd931SAlex Dubov if (host->req->long_data) {
343eb3f0620SCong Wang kunmap_atomic(buf - p_off);
34460fdd931SAlex Dubov local_irq_restore(flags);
34560fdd931SAlex Dubov }
34660fdd931SAlex Dubov
34760fdd931SAlex Dubov if (!t_size)
34860fdd931SAlex Dubov break;
34960fdd931SAlex Dubov host->block_pos += t_size;
35060fdd931SAlex Dubov length -= t_size;
35160fdd931SAlex Dubov off += t_size;
35260fdd931SAlex Dubov }
35360fdd931SAlex Dubov
35460fdd931SAlex Dubov if (!length && host->req->data_dir == WRITE) {
35560fdd931SAlex Dubov if (host->cmd_flags & REG_DATA) {
35660fdd931SAlex Dubov writel(host->io_word[0], host->addr + TPC_P0);
35760fdd931SAlex Dubov writel(host->io_word[1], host->addr + TPC_P1);
35860fdd931SAlex Dubov } else if (host->io_pos) {
35960fdd931SAlex Dubov writel(host->io_word[0], host->addr + DATA);
36060fdd931SAlex Dubov }
36160fdd931SAlex Dubov }
36260fdd931SAlex Dubov
36360fdd931SAlex Dubov return length;
36460fdd931SAlex Dubov }
36560fdd931SAlex Dubov
jmb38x_ms_issue_cmd(struct memstick_host * msh)36660fdd931SAlex Dubov static int jmb38x_ms_issue_cmd(struct memstick_host *msh)
36760fdd931SAlex Dubov {
36860fdd931SAlex Dubov struct jmb38x_ms_host *host = memstick_priv(msh);
36960fdd931SAlex Dubov unsigned int data_len, cmd, t_val;
37060fdd931SAlex Dubov
37160fdd931SAlex Dubov if (!(STATUS_HAS_MEDIA & readl(host->addr + STATUS))) {
372c4c66cf1SGreg Kroah-Hartman dev_dbg(&msh->dev, "no media status\n");
37360fdd931SAlex Dubov host->req->error = -ETIME;
37460fdd931SAlex Dubov return host->req->error;
37560fdd931SAlex Dubov }
37660fdd931SAlex Dubov
3778e82f8c3SAlex Dubov dev_dbg(&msh->dev, "control %08x\n", readl(host->addr + HOST_CONTROL));
378c4c66cf1SGreg Kroah-Hartman dev_dbg(&msh->dev, "status %08x\n", readl(host->addr + INT_STATUS));
379c4c66cf1SGreg Kroah-Hartman dev_dbg(&msh->dev, "hstatus %08x\n", readl(host->addr + STATUS));
38060fdd931SAlex Dubov
38160fdd931SAlex Dubov host->cmd_flags = 0;
38260fdd931SAlex Dubov host->block_pos = 0;
38360fdd931SAlex Dubov host->io_pos = 0;
38460fdd931SAlex Dubov host->io_word[0] = 0;
38560fdd931SAlex Dubov host->io_word[1] = 0;
38660fdd931SAlex Dubov
38760fdd931SAlex Dubov cmd = host->req->tpc << 16;
38860fdd931SAlex Dubov cmd |= TPC_DATA_SEL;
38960fdd931SAlex Dubov
39060fdd931SAlex Dubov if (host->req->data_dir == READ)
39160fdd931SAlex Dubov cmd |= TPC_DIR;
39223c5947aSTakashi Iwai
39323c5947aSTakashi Iwai if (host->req->need_card_int) {
39423c5947aSTakashi Iwai if (host->ifmode == MEMSTICK_SERIAL)
39523c5947aSTakashi Iwai cmd |= TPC_GET_INT;
39623c5947aSTakashi Iwai else
39760fdd931SAlex Dubov cmd |= TPC_WAIT_INT;
39823c5947aSTakashi Iwai }
39960fdd931SAlex Dubov
400ead70773SAlex Dubov if (!no_dma)
401ead70773SAlex Dubov host->cmd_flags |= DMA_DATA;
40260fdd931SAlex Dubov
40360fdd931SAlex Dubov if (host->req->long_data) {
40460fdd931SAlex Dubov data_len = host->req->sg.length;
40560fdd931SAlex Dubov } else {
40660fdd931SAlex Dubov data_len = host->req->data_len;
407ead70773SAlex Dubov host->cmd_flags &= ~DMA_DATA;
40860fdd931SAlex Dubov }
40960fdd931SAlex Dubov
41060fdd931SAlex Dubov if (data_len <= 8) {
41160fdd931SAlex Dubov cmd &= ~(TPC_DATA_SEL | 0xf);
41260fdd931SAlex Dubov host->cmd_flags |= REG_DATA;
41360fdd931SAlex Dubov cmd |= data_len & 0xf;
414ead70773SAlex Dubov host->cmd_flags &= ~DMA_DATA;
41560fdd931SAlex Dubov }
41660fdd931SAlex Dubov
417ead70773SAlex Dubov if (host->cmd_flags & DMA_DATA) {
41843abdbceSQuentin Lambert if (1 != dma_map_sg(&host->chip->pdev->dev, &host->req->sg, 1,
41960fdd931SAlex Dubov host->req->data_dir == READ
42043abdbceSQuentin Lambert ? DMA_FROM_DEVICE
42143abdbceSQuentin Lambert : DMA_TO_DEVICE)) {
42260fdd931SAlex Dubov host->req->error = -ENOMEM;
42360fdd931SAlex Dubov return host->req->error;
42460fdd931SAlex Dubov }
42560fdd931SAlex Dubov data_len = sg_dma_len(&host->req->sg);
42660fdd931SAlex Dubov writel(sg_dma_address(&host->req->sg),
42760fdd931SAlex Dubov host->addr + DMA_ADDRESS);
42860fdd931SAlex Dubov writel(((1 << 16) & BLOCK_COUNT_MASK)
42960fdd931SAlex Dubov | (data_len & BLOCK_SIZE_MASK),
43060fdd931SAlex Dubov host->addr + BLOCK);
43160fdd931SAlex Dubov writel(DMA_CONTROL_ENABLE, host->addr + DMA_CONTROL);
43260fdd931SAlex Dubov } else if (!(host->cmd_flags & REG_DATA)) {
43360fdd931SAlex Dubov writel(((1 << 16) & BLOCK_COUNT_MASK)
43460fdd931SAlex Dubov | (data_len & BLOCK_SIZE_MASK),
43560fdd931SAlex Dubov host->addr + BLOCK);
43660fdd931SAlex Dubov t_val = readl(host->addr + INT_STATUS_ENABLE);
43760fdd931SAlex Dubov t_val |= host->req->data_dir == READ
43860fdd931SAlex Dubov ? INT_STATUS_FIFO_RRDY
43960fdd931SAlex Dubov : INT_STATUS_FIFO_WRDY;
44060fdd931SAlex Dubov
44160fdd931SAlex Dubov writel(t_val, host->addr + INT_STATUS_ENABLE);
44260fdd931SAlex Dubov writel(t_val, host->addr + INT_SIGNAL_ENABLE);
44360fdd931SAlex Dubov } else {
44460fdd931SAlex Dubov cmd &= ~(TPC_DATA_SEL | 0xf);
44560fdd931SAlex Dubov host->cmd_flags |= REG_DATA;
44660fdd931SAlex Dubov cmd |= data_len & 0xf;
44760fdd931SAlex Dubov
44860fdd931SAlex Dubov if (host->req->data_dir == WRITE) {
44960fdd931SAlex Dubov jmb38x_ms_transfer_data(host);
45060fdd931SAlex Dubov writel(host->io_word[0], host->addr + TPC_P0);
45160fdd931SAlex Dubov writel(host->io_word[1], host->addr + TPC_P1);
45260fdd931SAlex Dubov }
45360fdd931SAlex Dubov }
45460fdd931SAlex Dubov
45560fdd931SAlex Dubov mod_timer(&host->timer, jiffies + host->timeout_jiffies);
45660fdd931SAlex Dubov writel(HOST_CONTROL_LED | readl(host->addr + HOST_CONTROL),
45760fdd931SAlex Dubov host->addr + HOST_CONTROL);
45860fdd931SAlex Dubov host->req->error = 0;
45960fdd931SAlex Dubov
46060fdd931SAlex Dubov writel(cmd, host->addr + TPC);
461c4c66cf1SGreg Kroah-Hartman dev_dbg(&msh->dev, "executing TPC %08x, len %x\n", cmd, data_len);
46260fdd931SAlex Dubov
46360fdd931SAlex Dubov return 0;
46460fdd931SAlex Dubov }
46560fdd931SAlex Dubov
jmb38x_ms_complete_cmd(struct memstick_host * msh,int last)46660fdd931SAlex Dubov static void jmb38x_ms_complete_cmd(struct memstick_host *msh, int last)
46760fdd931SAlex Dubov {
46860fdd931SAlex Dubov struct jmb38x_ms_host *host = memstick_priv(msh);
46960fdd931SAlex Dubov unsigned int t_val = 0;
47060fdd931SAlex Dubov int rc;
47160fdd931SAlex Dubov
47260fdd931SAlex Dubov del_timer(&host->timer);
47360fdd931SAlex Dubov
474c4c66cf1SGreg Kroah-Hartman dev_dbg(&msh->dev, "c control %08x\n",
47560fdd931SAlex Dubov readl(host->addr + HOST_CONTROL));
476c4c66cf1SGreg Kroah-Hartman dev_dbg(&msh->dev, "c status %08x\n",
47760fdd931SAlex Dubov readl(host->addr + INT_STATUS));
478c4c66cf1SGreg Kroah-Hartman dev_dbg(&msh->dev, "c hstatus %08x\n", readl(host->addr + STATUS));
47960fdd931SAlex Dubov
480ead70773SAlex Dubov host->req->int_reg = readl(host->addr + STATUS) & 0xff;
48160fdd931SAlex Dubov
482ead70773SAlex Dubov writel(0, host->addr + BLOCK);
48360fdd931SAlex Dubov writel(0, host->addr + DMA_CONTROL);
484ead70773SAlex Dubov
485ead70773SAlex Dubov if (host->cmd_flags & DMA_DATA) {
48643abdbceSQuentin Lambert dma_unmap_sg(&host->chip->pdev->dev, &host->req->sg, 1,
48760fdd931SAlex Dubov host->req->data_dir == READ
48843abdbceSQuentin Lambert ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
48960fdd931SAlex Dubov } else {
49060fdd931SAlex Dubov t_val = readl(host->addr + INT_STATUS_ENABLE);
49160fdd931SAlex Dubov if (host->req->data_dir == READ)
49260fdd931SAlex Dubov t_val &= ~INT_STATUS_FIFO_RRDY;
49360fdd931SAlex Dubov else
49460fdd931SAlex Dubov t_val &= ~INT_STATUS_FIFO_WRDY;
49560fdd931SAlex Dubov
49660fdd931SAlex Dubov writel(t_val, host->addr + INT_STATUS_ENABLE);
49760fdd931SAlex Dubov writel(t_val, host->addr + INT_SIGNAL_ENABLE);
49860fdd931SAlex Dubov }
49960fdd931SAlex Dubov
50060fdd931SAlex Dubov writel((~HOST_CONTROL_LED) & readl(host->addr + HOST_CONTROL),
50160fdd931SAlex Dubov host->addr + HOST_CONTROL);
50260fdd931SAlex Dubov
50360fdd931SAlex Dubov if (!last) {
50460fdd931SAlex Dubov do {
50560fdd931SAlex Dubov rc = memstick_next_req(msh, &host->req);
50660fdd931SAlex Dubov } while (!rc && jmb38x_ms_issue_cmd(msh));
50760fdd931SAlex Dubov } else {
50860fdd931SAlex Dubov do {
50960fdd931SAlex Dubov rc = memstick_next_req(msh, &host->req);
51060fdd931SAlex Dubov if (!rc)
51160fdd931SAlex Dubov host->req->error = -ETIME;
51260fdd931SAlex Dubov } while (!rc);
51360fdd931SAlex Dubov }
51460fdd931SAlex Dubov }
51560fdd931SAlex Dubov
jmb38x_ms_isr(int irq,void * dev_id)51660fdd931SAlex Dubov static irqreturn_t jmb38x_ms_isr(int irq, void *dev_id)
51760fdd931SAlex Dubov {
51860fdd931SAlex Dubov struct memstick_host *msh = dev_id;
51960fdd931SAlex Dubov struct jmb38x_ms_host *host = memstick_priv(msh);
52060fdd931SAlex Dubov unsigned int irq_status;
52160fdd931SAlex Dubov
52260fdd931SAlex Dubov spin_lock(&host->lock);
52360fdd931SAlex Dubov irq_status = readl(host->addr + INT_STATUS);
52460fdd931SAlex Dubov dev_dbg(&host->chip->pdev->dev, "irq_status = %08x\n", irq_status);
52560fdd931SAlex Dubov if (irq_status == 0 || irq_status == (~0)) {
52660fdd931SAlex Dubov spin_unlock(&host->lock);
52760fdd931SAlex Dubov return IRQ_NONE;
52860fdd931SAlex Dubov }
52960fdd931SAlex Dubov
53060fdd931SAlex Dubov if (host->req) {
53160fdd931SAlex Dubov if (irq_status & INT_STATUS_ANY_ERR) {
53260fdd931SAlex Dubov if (irq_status & INT_STATUS_CRC_ERR)
53360fdd931SAlex Dubov host->req->error = -EILSEQ;
53423c5947aSTakashi Iwai else if (irq_status & INT_STATUS_TPC_ERR) {
53523c5947aSTakashi Iwai dev_dbg(&host->chip->pdev->dev, "TPC_ERR\n");
53623c5947aSTakashi Iwai jmb38x_ms_complete_cmd(msh, 0);
53723c5947aSTakashi Iwai } else
53860fdd931SAlex Dubov host->req->error = -ETIME;
53960fdd931SAlex Dubov } else {
540ead70773SAlex Dubov if (host->cmd_flags & DMA_DATA) {
54160fdd931SAlex Dubov if (irq_status & INT_STATUS_EOTRAN)
54260fdd931SAlex Dubov host->cmd_flags |= FIFO_READY;
54360fdd931SAlex Dubov } else {
54460fdd931SAlex Dubov if (irq_status & (INT_STATUS_FIFO_RRDY
54560fdd931SAlex Dubov | INT_STATUS_FIFO_WRDY))
54660fdd931SAlex Dubov jmb38x_ms_transfer_data(host);
54760fdd931SAlex Dubov
54860fdd931SAlex Dubov if (irq_status & INT_STATUS_EOTRAN) {
54960fdd931SAlex Dubov jmb38x_ms_transfer_data(host);
55060fdd931SAlex Dubov host->cmd_flags |= FIFO_READY;
55160fdd931SAlex Dubov }
55260fdd931SAlex Dubov }
55360fdd931SAlex Dubov
55460fdd931SAlex Dubov if (irq_status & INT_STATUS_EOTPC) {
55560fdd931SAlex Dubov host->cmd_flags |= CMD_READY;
55660fdd931SAlex Dubov if (host->cmd_flags & REG_DATA) {
55760fdd931SAlex Dubov if (host->req->data_dir == READ) {
55860fdd931SAlex Dubov host->io_word[0]
55960fdd931SAlex Dubov = readl(host->addr
56060fdd931SAlex Dubov + TPC_P0);
56160fdd931SAlex Dubov host->io_word[1]
56260fdd931SAlex Dubov = readl(host->addr
56360fdd931SAlex Dubov + TPC_P1);
56460fdd931SAlex Dubov host->io_pos = 8;
56560fdd931SAlex Dubov
56660fdd931SAlex Dubov jmb38x_ms_transfer_data(host);
56760fdd931SAlex Dubov }
56860fdd931SAlex Dubov host->cmd_flags |= FIFO_READY;
56960fdd931SAlex Dubov }
57060fdd931SAlex Dubov }
57160fdd931SAlex Dubov }
57260fdd931SAlex Dubov }
57360fdd931SAlex Dubov
57460fdd931SAlex Dubov if (irq_status & (INT_STATUS_MEDIA_IN | INT_STATUS_MEDIA_OUT)) {
57560fdd931SAlex Dubov dev_dbg(&host->chip->pdev->dev, "media changed\n");
57660fdd931SAlex Dubov memstick_detect_change(msh);
57760fdd931SAlex Dubov }
57860fdd931SAlex Dubov
57960fdd931SAlex Dubov writel(irq_status, host->addr + INT_STATUS);
58060fdd931SAlex Dubov
58160fdd931SAlex Dubov if (host->req
58260fdd931SAlex Dubov && (((host->cmd_flags & CMD_READY)
58360fdd931SAlex Dubov && (host->cmd_flags & FIFO_READY))
58460fdd931SAlex Dubov || host->req->error))
58560fdd931SAlex Dubov jmb38x_ms_complete_cmd(msh, 0);
58660fdd931SAlex Dubov
58760fdd931SAlex Dubov spin_unlock(&host->lock);
58860fdd931SAlex Dubov return IRQ_HANDLED;
58960fdd931SAlex Dubov }
59060fdd931SAlex Dubov
jmb38x_ms_abort(struct timer_list * t)5916243d38fSKees Cook static void jmb38x_ms_abort(struct timer_list *t)
59260fdd931SAlex Dubov {
5936243d38fSKees Cook struct jmb38x_ms_host *host = from_timer(host, t, timer);
5946243d38fSKees Cook struct memstick_host *msh = host->msh;
59560fdd931SAlex Dubov unsigned long flags;
59660fdd931SAlex Dubov
59760fdd931SAlex Dubov dev_dbg(&host->chip->pdev->dev, "abort\n");
59860fdd931SAlex Dubov spin_lock_irqsave(&host->lock, flags);
59960fdd931SAlex Dubov if (host->req) {
60060fdd931SAlex Dubov host->req->error = -ETIME;
60160fdd931SAlex Dubov jmb38x_ms_complete_cmd(msh, 0);
60260fdd931SAlex Dubov }
60360fdd931SAlex Dubov spin_unlock_irqrestore(&host->lock, flags);
60460fdd931SAlex Dubov }
60560fdd931SAlex Dubov
jmb38x_ms_req_tasklet(unsigned long data)606f1d82698SAlex Dubov static void jmb38x_ms_req_tasklet(unsigned long data)
60760fdd931SAlex Dubov {
608f1d82698SAlex Dubov struct memstick_host *msh = (struct memstick_host *)data;
60960fdd931SAlex Dubov struct jmb38x_ms_host *host = memstick_priv(msh);
61060fdd931SAlex Dubov unsigned long flags;
61160fdd931SAlex Dubov int rc;
61260fdd931SAlex Dubov
61360fdd931SAlex Dubov spin_lock_irqsave(&host->lock, flags);
614f1d82698SAlex Dubov if (!host->req) {
615f1d82698SAlex Dubov do {
616f1d82698SAlex Dubov rc = memstick_next_req(msh, &host->req);
617f1d82698SAlex Dubov dev_dbg(&host->chip->pdev->dev, "tasklet req %d\n", rc);
618f1d82698SAlex Dubov } while (!rc && jmb38x_ms_issue_cmd(msh));
619f1d82698SAlex Dubov }
62060fdd931SAlex Dubov spin_unlock_irqrestore(&host->lock, flags);
621f1d82698SAlex Dubov }
622f1d82698SAlex Dubov
jmb38x_ms_dummy_submit(struct memstick_host * msh)623f1d82698SAlex Dubov static void jmb38x_ms_dummy_submit(struct memstick_host *msh)
624f1d82698SAlex Dubov {
62560fdd931SAlex Dubov return;
62660fdd931SAlex Dubov }
62760fdd931SAlex Dubov
jmb38x_ms_submit_req(struct memstick_host * msh)628f1d82698SAlex Dubov static void jmb38x_ms_submit_req(struct memstick_host *msh)
629f1d82698SAlex Dubov {
630f1d82698SAlex Dubov struct jmb38x_ms_host *host = memstick_priv(msh);
631f1d82698SAlex Dubov
632f1d82698SAlex Dubov tasklet_schedule(&host->notify);
63360fdd931SAlex Dubov }
63460fdd931SAlex Dubov
jmb38x_ms_reset(struct jmb38x_ms_host * host)635b7789998SAlex Dubov static int jmb38x_ms_reset(struct jmb38x_ms_host *host)
63660fdd931SAlex Dubov {
637b7789998SAlex Dubov int cnt;
63860fdd931SAlex Dubov
639b7789998SAlex Dubov writel(HOST_CONTROL_RESET_REQ | HOST_CONTROL_CLOCK_EN
640b7789998SAlex Dubov | readl(host->addr + HOST_CONTROL),
641b7789998SAlex Dubov host->addr + HOST_CONTROL);
64260fdd931SAlex Dubov
643b7789998SAlex Dubov for (cnt = 0; cnt < 20; ++cnt) {
644b7789998SAlex Dubov if (!(HOST_CONTROL_RESET_REQ
645b7789998SAlex Dubov & readl(host->addr + HOST_CONTROL)))
646b7789998SAlex Dubov goto reset_next;
647b7789998SAlex Dubov
648cf821e8fSAlex Dubov ndelay(20);
64960fdd931SAlex Dubov }
650b7789998SAlex Dubov dev_dbg(&host->chip->pdev->dev, "reset_req timeout\n");
65160fdd931SAlex Dubov
652b7789998SAlex Dubov reset_next:
653b7789998SAlex Dubov writel(HOST_CONTROL_RESET | HOST_CONTROL_CLOCK_EN
654b7789998SAlex Dubov | readl(host->addr + HOST_CONTROL),
655b7789998SAlex Dubov host->addr + HOST_CONTROL);
656b7789998SAlex Dubov
657b7789998SAlex Dubov for (cnt = 0; cnt < 20; ++cnt) {
658b7789998SAlex Dubov if (!(HOST_CONTROL_RESET
659b7789998SAlex Dubov & readl(host->addr + HOST_CONTROL)))
660b7789998SAlex Dubov goto reset_ok;
661b7789998SAlex Dubov
662b7789998SAlex Dubov ndelay(20);
663b7789998SAlex Dubov }
664b7789998SAlex Dubov dev_dbg(&host->chip->pdev->dev, "reset timeout\n");
665b7789998SAlex Dubov return -EIO;
666b7789998SAlex Dubov
667b7789998SAlex Dubov reset_ok:
66860fdd931SAlex Dubov writel(INT_STATUS_ALL, host->addr + INT_SIGNAL_ENABLE);
669cf821e8fSAlex Dubov writel(INT_STATUS_ALL, host->addr + INT_STATUS_ENABLE);
670b7789998SAlex Dubov return 0;
67160fdd931SAlex Dubov }
67260fdd931SAlex Dubov
jmb38x_ms_set_param(struct memstick_host * msh,enum memstick_param param,int value)673b7789998SAlex Dubov static int jmb38x_ms_set_param(struct memstick_host *msh,
67460fdd931SAlex Dubov enum memstick_param param,
67560fdd931SAlex Dubov int value)
67660fdd931SAlex Dubov {
67760fdd931SAlex Dubov struct jmb38x_ms_host *host = memstick_priv(msh);
678cf821e8fSAlex Dubov unsigned int host_ctl = readl(host->addr + HOST_CONTROL);
67923c5947aSTakashi Iwai unsigned int clock_ctl = CLOCK_CONTROL_BY_MMIO, clock_delay = 0;
680b7789998SAlex Dubov int rc = 0;
68160fdd931SAlex Dubov
68260fdd931SAlex Dubov switch (param) {
68360fdd931SAlex Dubov case MEMSTICK_POWER:
68460fdd931SAlex Dubov if (value == MEMSTICK_POWER_ON) {
685b7789998SAlex Dubov rc = jmb38x_ms_reset(host);
686b7789998SAlex Dubov if (rc)
687b7789998SAlex Dubov return rc;
688b7789998SAlex Dubov
689b7789998SAlex Dubov host_ctl = 7;
690b7789998SAlex Dubov host_ctl |= HOST_CONTROL_POWER_EN
69123c5947aSTakashi Iwai | HOST_CONTROL_CLOCK_EN;
692b7789998SAlex Dubov writel(host_ctl, host->addr + HOST_CONTROL);
69360fdd931SAlex Dubov
69460fdd931SAlex Dubov writel(host->id ? PAD_PU_PD_ON_MS_SOCK1
69560fdd931SAlex Dubov : PAD_PU_PD_ON_MS_SOCK0,
69660fdd931SAlex Dubov host->addr + PAD_PU_PD);
69760fdd931SAlex Dubov
69860fdd931SAlex Dubov writel(PAD_OUTPUT_ENABLE_MS,
69960fdd931SAlex Dubov host->addr + PAD_OUTPUT_ENABLE);
70060fdd931SAlex Dubov
701b7789998SAlex Dubov msleep(10);
70260fdd931SAlex Dubov dev_dbg(&host->chip->pdev->dev, "power on\n");
70360fdd931SAlex Dubov } else if (value == MEMSTICK_POWER_OFF) {
704cf821e8fSAlex Dubov host_ctl &= ~(HOST_CONTROL_POWER_EN
705cf821e8fSAlex Dubov | HOST_CONTROL_CLOCK_EN);
706cf821e8fSAlex Dubov writel(host_ctl, host->addr + HOST_CONTROL);
70760fdd931SAlex Dubov writel(0, host->addr + PAD_OUTPUT_ENABLE);
70860fdd931SAlex Dubov writel(PAD_PU_PD_OFF, host->addr + PAD_PU_PD);
70960fdd931SAlex Dubov dev_dbg(&host->chip->pdev->dev, "power off\n");
710b7789998SAlex Dubov } else
711b7789998SAlex Dubov return -EINVAL;
71260fdd931SAlex Dubov break;
71360fdd931SAlex Dubov case MEMSTICK_INTERFACE:
71423c5947aSTakashi Iwai dev_dbg(&host->chip->pdev->dev,
71523c5947aSTakashi Iwai "Set Host Interface Mode to %d\n", value);
71623c5947aSTakashi Iwai host_ctl &= ~(HOST_CONTROL_FAST_CLK | HOST_CONTROL_REI |
71723c5947aSTakashi Iwai HOST_CONTROL_REO);
71823c5947aSTakashi Iwai host_ctl |= HOST_CONTROL_TDELAY_EN | HOST_CONTROL_HW_OC_P;
71960fdd931SAlex Dubov host_ctl &= ~(3 << HOST_CONTROL_IF_SHIFT);
72060fdd931SAlex Dubov
72160fdd931SAlex Dubov if (value == MEMSTICK_SERIAL) {
72260fdd931SAlex Dubov host_ctl |= HOST_CONTROL_IF_SERIAL
72360fdd931SAlex Dubov << HOST_CONTROL_IF_SHIFT;
72460fdd931SAlex Dubov host_ctl |= HOST_CONTROL_REI;
72523c5947aSTakashi Iwai clock_ctl |= CLOCK_CONTROL_40MHZ;
72623c5947aSTakashi Iwai clock_delay = 0;
72760fdd931SAlex Dubov } else if (value == MEMSTICK_PAR4) {
72823c5947aSTakashi Iwai host_ctl |= HOST_CONTROL_FAST_CLK;
72960fdd931SAlex Dubov host_ctl |= HOST_CONTROL_IF_PAR4
73060fdd931SAlex Dubov << HOST_CONTROL_IF_SHIFT;
73123c5947aSTakashi Iwai host_ctl |= HOST_CONTROL_REO;
73223c5947aSTakashi Iwai clock_ctl |= CLOCK_CONTROL_40MHZ;
73323c5947aSTakashi Iwai clock_delay = 4;
73460fdd931SAlex Dubov } else if (value == MEMSTICK_PAR8) {
73560fdd931SAlex Dubov host_ctl |= HOST_CONTROL_FAST_CLK;
73660fdd931SAlex Dubov host_ctl |= HOST_CONTROL_IF_PAR8
73760fdd931SAlex Dubov << HOST_CONTROL_IF_SHIFT;
73823c5947aSTakashi Iwai clock_ctl |= CLOCK_CONTROL_50MHZ;
73923c5947aSTakashi Iwai clock_delay = 0;
740b7789998SAlex Dubov } else
741b7789998SAlex Dubov return -EINVAL;
7428e82f8c3SAlex Dubov
74360fdd931SAlex Dubov writel(host_ctl, host->addr + HOST_CONTROL);
74423c5947aSTakashi Iwai writel(CLOCK_CONTROL_OFF, host->addr + CLOCK_CONTROL);
745cf821e8fSAlex Dubov writel(clock_ctl, host->addr + CLOCK_CONTROL);
74623c5947aSTakashi Iwai pci_write_config_byte(host->chip->pdev,
74723c5947aSTakashi Iwai PCI_CTL_CLOCK_DLY_ADDR + 1,
7488e82f8c3SAlex Dubov clock_delay);
74923c5947aSTakashi Iwai host->ifmode = value;
75060fdd931SAlex Dubov break;
751fb829863STom Rix }
752b7789998SAlex Dubov return 0;
75360fdd931SAlex Dubov }
75460fdd931SAlex Dubov
75568860b96STakashi Iwai #define PCI_PMOS0_CONTROL 0xae
75668860b96STakashi Iwai #define PMOS0_ENABLE 0x01
75768860b96STakashi Iwai #define PMOS0_OVERCURRENT_LEVEL_2_4V 0x06
75868860b96STakashi Iwai #define PMOS0_EN_OVERCURRENT_DEBOUNCE 0x40
75968860b96STakashi Iwai #define PMOS0_SW_LED_POLARITY_ENABLE 0x80
76068860b96STakashi Iwai #define PMOS0_ACTIVE_BITS (PMOS0_ENABLE | PMOS0_EN_OVERCURRENT_DEBOUNCE | \
76168860b96STakashi Iwai PMOS0_OVERCURRENT_LEVEL_2_4V)
7628930c8aaSTakashi Iwai #define PCI_PMOS1_CONTROL 0xbd
7638930c8aaSTakashi Iwai #define PMOS1_ACTIVE_BITS 0x4a
76468860b96STakashi Iwai #define PCI_CLOCK_CTL 0xb9
76568860b96STakashi Iwai
jmb38x_ms_pmos(struct pci_dev * pdev,int flag)76668860b96STakashi Iwai static int jmb38x_ms_pmos(struct pci_dev *pdev, int flag)
76768860b96STakashi Iwai {
76868860b96STakashi Iwai unsigned char val;
76968860b96STakashi Iwai
77068860b96STakashi Iwai pci_read_config_byte(pdev, PCI_PMOS0_CONTROL, &val);
77168860b96STakashi Iwai if (flag)
77268860b96STakashi Iwai val |= PMOS0_ACTIVE_BITS;
77368860b96STakashi Iwai else
77468860b96STakashi Iwai val &= ~PMOS0_ACTIVE_BITS;
77568860b96STakashi Iwai pci_write_config_byte(pdev, PCI_PMOS0_CONTROL, val);
77668860b96STakashi Iwai dev_dbg(&pdev->dev, "JMB38x: set PMOS0 val 0x%x\n", val);
77768860b96STakashi Iwai
7788930c8aaSTakashi Iwai if (pci_resource_flags(pdev, 1)) {
7798930c8aaSTakashi Iwai pci_read_config_byte(pdev, PCI_PMOS1_CONTROL, &val);
7808930c8aaSTakashi Iwai if (flag)
7818930c8aaSTakashi Iwai val |= PMOS1_ACTIVE_BITS;
7828930c8aaSTakashi Iwai else
7838930c8aaSTakashi Iwai val &= ~PMOS1_ACTIVE_BITS;
7848930c8aaSTakashi Iwai pci_write_config_byte(pdev, PCI_PMOS1_CONTROL, val);
7858930c8aaSTakashi Iwai dev_dbg(&pdev->dev, "JMB38x: set PMOS1 val 0x%x\n", val);
7868930c8aaSTakashi Iwai }
7878930c8aaSTakashi Iwai
78868860b96STakashi Iwai pci_read_config_byte(pdev, PCI_CLOCK_CTL, &val);
78968860b96STakashi Iwai pci_write_config_byte(pdev, PCI_CLOCK_CTL, val & ~0x0f);
79068860b96STakashi Iwai pci_write_config_byte(pdev, PCI_CLOCK_CTL, val | 0x01);
79168860b96STakashi Iwai dev_dbg(&pdev->dev, "Clock Control by PCI config is disabled!\n");
79268860b96STakashi Iwai
79368860b96STakashi Iwai return 0;
79468860b96STakashi Iwai }
79568860b96STakashi Iwai
jmb38x_ms_suspend(struct device * dev)796c4e5e22bSVaibhav Gupta static int __maybe_unused jmb38x_ms_suspend(struct device *dev)
79760fdd931SAlex Dubov {
798c4e5e22bSVaibhav Gupta struct jmb38x_ms *jm = dev_get_drvdata(dev);
799c4e5e22bSVaibhav Gupta
80060fdd931SAlex Dubov int cnt;
80160fdd931SAlex Dubov
80260fdd931SAlex Dubov for (cnt = 0; cnt < jm->host_cnt; ++cnt) {
80360fdd931SAlex Dubov if (!jm->hosts[cnt])
80460fdd931SAlex Dubov break;
80560fdd931SAlex Dubov memstick_suspend_host(jm->hosts[cnt]);
80660fdd931SAlex Dubov }
80760fdd931SAlex Dubov
808c4e5e22bSVaibhav Gupta device_wakeup_disable(dev);
809c4e5e22bSVaibhav Gupta
81060fdd931SAlex Dubov return 0;
81160fdd931SAlex Dubov }
81260fdd931SAlex Dubov
jmb38x_ms_resume(struct device * dev)813c4e5e22bSVaibhav Gupta static int __maybe_unused jmb38x_ms_resume(struct device *dev)
81460fdd931SAlex Dubov {
815c4e5e22bSVaibhav Gupta struct jmb38x_ms *jm = dev_get_drvdata(dev);
81660fdd931SAlex Dubov int rc;
81760fdd931SAlex Dubov
818c4e5e22bSVaibhav Gupta jmb38x_ms_pmos(to_pci_dev(dev), 1);
81960fdd931SAlex Dubov
82060fdd931SAlex Dubov for (rc = 0; rc < jm->host_cnt; ++rc) {
82160fdd931SAlex Dubov if (!jm->hosts[rc])
82260fdd931SAlex Dubov break;
82360fdd931SAlex Dubov memstick_resume_host(jm->hosts[rc]);
82460fdd931SAlex Dubov memstick_detect_change(jm->hosts[rc]);
82560fdd931SAlex Dubov }
82660fdd931SAlex Dubov
82760fdd931SAlex Dubov return 0;
82860fdd931SAlex Dubov }
82960fdd931SAlex Dubov
jmb38x_ms_count_slots(struct pci_dev * pdev)83060fdd931SAlex Dubov static int jmb38x_ms_count_slots(struct pci_dev *pdev)
83160fdd931SAlex Dubov {
83260fdd931SAlex Dubov int cnt, rc = 0;
83360fdd931SAlex Dubov
834c9c13ba4SDenis Efremov for (cnt = 0; cnt < PCI_STD_NUM_BARS; ++cnt) {
83560fdd931SAlex Dubov if (!(IORESOURCE_MEM & pci_resource_flags(pdev, cnt)))
83660fdd931SAlex Dubov break;
83760fdd931SAlex Dubov
83860fdd931SAlex Dubov if (256 != pci_resource_len(pdev, cnt))
83960fdd931SAlex Dubov break;
84060fdd931SAlex Dubov
84160fdd931SAlex Dubov ++rc;
84260fdd931SAlex Dubov }
84360fdd931SAlex Dubov return rc;
84460fdd931SAlex Dubov }
84560fdd931SAlex Dubov
jmb38x_ms_alloc_host(struct jmb38x_ms * jm,int cnt)84660fdd931SAlex Dubov static struct memstick_host *jmb38x_ms_alloc_host(struct jmb38x_ms *jm, int cnt)
84760fdd931SAlex Dubov {
84860fdd931SAlex Dubov struct memstick_host *msh;
84960fdd931SAlex Dubov struct jmb38x_ms_host *host;
85060fdd931SAlex Dubov
85160fdd931SAlex Dubov msh = memstick_alloc_host(sizeof(struct jmb38x_ms_host),
85260fdd931SAlex Dubov &jm->pdev->dev);
85360fdd931SAlex Dubov if (!msh)
85460fdd931SAlex Dubov return NULL;
85560fdd931SAlex Dubov
85660fdd931SAlex Dubov host = memstick_priv(msh);
8576243d38fSKees Cook host->msh = msh;
85860fdd931SAlex Dubov host->chip = jm;
85960fdd931SAlex Dubov host->addr = ioremap(pci_resource_start(jm->pdev, cnt),
86060fdd931SAlex Dubov pci_resource_len(jm->pdev, cnt));
86160fdd931SAlex Dubov if (!host->addr)
86260fdd931SAlex Dubov goto err_out_free;
86360fdd931SAlex Dubov
86460fdd931SAlex Dubov spin_lock_init(&host->lock);
86560fdd931SAlex Dubov host->id = cnt;
866b98cb4b7SGreg Kroah-Hartman snprintf(host->host_id, sizeof(host->host_id), DRIVER_NAME ":slot%d",
86760fdd931SAlex Dubov host->id);
86860fdd931SAlex Dubov host->irq = jm->pdev->irq;
869ead70773SAlex Dubov host->timeout_jiffies = msecs_to_jiffies(1000);
870f1d82698SAlex Dubov
871f1d82698SAlex Dubov tasklet_init(&host->notify, jmb38x_ms_req_tasklet, (unsigned long)msh);
872f1d82698SAlex Dubov msh->request = jmb38x_ms_submit_req;
87360fdd931SAlex Dubov msh->set_param = jmb38x_ms_set_param;
874ead70773SAlex Dubov
87560fdd931SAlex Dubov msh->caps = MEMSTICK_CAP_PAR4 | MEMSTICK_CAP_PAR8;
87660fdd931SAlex Dubov
8776243d38fSKees Cook timer_setup(&host->timer, jmb38x_ms_abort, 0);
87860fdd931SAlex Dubov
87960fdd931SAlex Dubov if (!request_irq(host->irq, jmb38x_ms_isr, IRQF_SHARED, host->host_id,
88060fdd931SAlex Dubov msh))
88160fdd931SAlex Dubov return msh;
88260fdd931SAlex Dubov
88360fdd931SAlex Dubov iounmap(host->addr);
88460fdd931SAlex Dubov err_out_free:
885beae4a62SDan Carpenter memstick_free_host(msh);
88660fdd931SAlex Dubov return NULL;
88760fdd931SAlex Dubov }
88860fdd931SAlex Dubov
jmb38x_ms_free_host(struct memstick_host * msh)88960fdd931SAlex Dubov static void jmb38x_ms_free_host(struct memstick_host *msh)
89060fdd931SAlex Dubov {
89160fdd931SAlex Dubov struct jmb38x_ms_host *host = memstick_priv(msh);
89260fdd931SAlex Dubov
89360fdd931SAlex Dubov free_irq(host->irq, msh);
89460fdd931SAlex Dubov iounmap(host->addr);
89560fdd931SAlex Dubov memstick_free_host(msh);
89660fdd931SAlex Dubov }
89760fdd931SAlex Dubov
jmb38x_ms_probe(struct pci_dev * pdev,const struct pci_device_id * dev_id)89860fdd931SAlex Dubov static int jmb38x_ms_probe(struct pci_dev *pdev,
89960fdd931SAlex Dubov const struct pci_device_id *dev_id)
90060fdd931SAlex Dubov {
90160fdd931SAlex Dubov struct jmb38x_ms *jm;
90260fdd931SAlex Dubov int pci_dev_busy = 0;
90360fdd931SAlex Dubov int rc, cnt;
90460fdd931SAlex Dubov
90543abdbceSQuentin Lambert rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
90660fdd931SAlex Dubov if (rc)
90760fdd931SAlex Dubov return rc;
90860fdd931SAlex Dubov
90960fdd931SAlex Dubov rc = pci_enable_device(pdev);
91060fdd931SAlex Dubov if (rc)
91160fdd931SAlex Dubov return rc;
91260fdd931SAlex Dubov
91360fdd931SAlex Dubov pci_set_master(pdev);
91460fdd931SAlex Dubov
91560fdd931SAlex Dubov rc = pci_request_regions(pdev, DRIVER_NAME);
91660fdd931SAlex Dubov if (rc) {
91760fdd931SAlex Dubov pci_dev_busy = 1;
91860fdd931SAlex Dubov goto err_out;
91960fdd931SAlex Dubov }
92060fdd931SAlex Dubov
92168860b96STakashi Iwai jmb38x_ms_pmos(pdev, 1);
92260fdd931SAlex Dubov
92360fdd931SAlex Dubov cnt = jmb38x_ms_count_slots(pdev);
92460fdd931SAlex Dubov if (!cnt) {
92560fdd931SAlex Dubov rc = -ENODEV;
92660fdd931SAlex Dubov pci_dev_busy = 1;
92728c9fac0SChristophe JAILLET goto err_out_int;
92860fdd931SAlex Dubov }
92960fdd931SAlex Dubov
93016e9bde2SLen Baker jm = kzalloc(struct_size(jm, hosts, cnt), GFP_KERNEL);
93160fdd931SAlex Dubov if (!jm) {
93260fdd931SAlex Dubov rc = -ENOMEM;
93360fdd931SAlex Dubov goto err_out_int;
93460fdd931SAlex Dubov }
93560fdd931SAlex Dubov
93660fdd931SAlex Dubov jm->pdev = pdev;
93760fdd931SAlex Dubov jm->host_cnt = cnt;
93860fdd931SAlex Dubov pci_set_drvdata(pdev, jm);
93960fdd931SAlex Dubov
94060fdd931SAlex Dubov for (cnt = 0; cnt < jm->host_cnt; ++cnt) {
94160fdd931SAlex Dubov jm->hosts[cnt] = jmb38x_ms_alloc_host(jm, cnt);
94260fdd931SAlex Dubov if (!jm->hosts[cnt])
94360fdd931SAlex Dubov break;
94460fdd931SAlex Dubov
94560fdd931SAlex Dubov rc = memstick_add_host(jm->hosts[cnt]);
94660fdd931SAlex Dubov
94760fdd931SAlex Dubov if (rc) {
94860fdd931SAlex Dubov jmb38x_ms_free_host(jm->hosts[cnt]);
94960fdd931SAlex Dubov jm->hosts[cnt] = NULL;
95060fdd931SAlex Dubov break;
95160fdd931SAlex Dubov }
95260fdd931SAlex Dubov }
95360fdd931SAlex Dubov
95460fdd931SAlex Dubov if (cnt)
95560fdd931SAlex Dubov return 0;
95660fdd931SAlex Dubov
95760fdd931SAlex Dubov rc = -ENODEV;
95860fdd931SAlex Dubov
95960fdd931SAlex Dubov pci_set_drvdata(pdev, NULL);
96060fdd931SAlex Dubov kfree(jm);
96160fdd931SAlex Dubov err_out_int:
96260fdd931SAlex Dubov pci_release_regions(pdev);
96360fdd931SAlex Dubov err_out:
96460fdd931SAlex Dubov if (!pci_dev_busy)
96560fdd931SAlex Dubov pci_disable_device(pdev);
96660fdd931SAlex Dubov return rc;
96760fdd931SAlex Dubov }
96860fdd931SAlex Dubov
jmb38x_ms_remove(struct pci_dev * dev)96960fdd931SAlex Dubov static void jmb38x_ms_remove(struct pci_dev *dev)
97060fdd931SAlex Dubov {
97160fdd931SAlex Dubov struct jmb38x_ms *jm = pci_get_drvdata(dev);
97260fdd931SAlex Dubov struct jmb38x_ms_host *host;
97360fdd931SAlex Dubov int cnt;
97460fdd931SAlex Dubov unsigned long flags;
97560fdd931SAlex Dubov
97660fdd931SAlex Dubov for (cnt = 0; cnt < jm->host_cnt; ++cnt) {
97760fdd931SAlex Dubov if (!jm->hosts[cnt])
97860fdd931SAlex Dubov break;
97960fdd931SAlex Dubov
98060fdd931SAlex Dubov host = memstick_priv(jm->hosts[cnt]);
98160fdd931SAlex Dubov
982f1d82698SAlex Dubov jm->hosts[cnt]->request = jmb38x_ms_dummy_submit;
983f1d82698SAlex Dubov tasklet_kill(&host->notify);
98460fdd931SAlex Dubov writel(0, host->addr + INT_SIGNAL_ENABLE);
98560fdd931SAlex Dubov writel(0, host->addr + INT_STATUS_ENABLE);
98660fdd931SAlex Dubov dev_dbg(&jm->pdev->dev, "interrupts off\n");
98760fdd931SAlex Dubov spin_lock_irqsave(&host->lock, flags);
98860fdd931SAlex Dubov if (host->req) {
98960fdd931SAlex Dubov host->req->error = -ETIME;
99060fdd931SAlex Dubov jmb38x_ms_complete_cmd(jm->hosts[cnt], 1);
99160fdd931SAlex Dubov }
99260fdd931SAlex Dubov spin_unlock_irqrestore(&host->lock, flags);
99360fdd931SAlex Dubov
99460fdd931SAlex Dubov memstick_remove_host(jm->hosts[cnt]);
99560fdd931SAlex Dubov dev_dbg(&jm->pdev->dev, "host removed\n");
99660fdd931SAlex Dubov
99760fdd931SAlex Dubov jmb38x_ms_free_host(jm->hosts[cnt]);
99860fdd931SAlex Dubov }
99960fdd931SAlex Dubov
100068860b96STakashi Iwai jmb38x_ms_pmos(dev, 0);
100168860b96STakashi Iwai
100260fdd931SAlex Dubov pci_set_drvdata(dev, NULL);
100360fdd931SAlex Dubov pci_release_regions(dev);
100460fdd931SAlex Dubov pci_disable_device(dev);
100560fdd931SAlex Dubov kfree(jm);
100660fdd931SAlex Dubov }
100760fdd931SAlex Dubov
100860fdd931SAlex Dubov static struct pci_device_id jmb38x_ms_id_tbl [] = {
10098930c8aaSTakashi Iwai { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_MS) },
10108930c8aaSTakashi Iwai { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB385_MS) },
10118930c8aaSTakashi Iwai { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMB390_MS) },
101260fdd931SAlex Dubov { }
101360fdd931SAlex Dubov };
101460fdd931SAlex Dubov
1015c4e5e22bSVaibhav Gupta static SIMPLE_DEV_PM_OPS(jmb38x_ms_pm_ops, jmb38x_ms_suspend, jmb38x_ms_resume);
1016c4e5e22bSVaibhav Gupta
101760fdd931SAlex Dubov static struct pci_driver jmb38x_ms_driver = {
101860fdd931SAlex Dubov .name = DRIVER_NAME,
101960fdd931SAlex Dubov .id_table = jmb38x_ms_id_tbl,
102060fdd931SAlex Dubov .probe = jmb38x_ms_probe,
102160fdd931SAlex Dubov .remove = jmb38x_ms_remove,
1022c4e5e22bSVaibhav Gupta .driver.pm = &jmb38x_ms_pm_ops,
102360fdd931SAlex Dubov };
102460fdd931SAlex Dubov
102510560490SLibo Chen module_pci_driver(jmb38x_ms_driver);
102660fdd931SAlex Dubov
102760fdd931SAlex Dubov MODULE_AUTHOR("Alex Dubov");
102860fdd931SAlex Dubov MODULE_DESCRIPTION("JMicron jmb38x MemoryStick driver");
102960fdd931SAlex Dubov MODULE_LICENSE("GPL");
103060fdd931SAlex Dubov MODULE_DEVICE_TABLE(pci, jmb38x_ms_id_tbl);
1031