1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * TI AEMIF driver 4 * 5 * Copyright (C) 2010 - 2013 Texas Instruments Incorporated. http://www.ti.com/ 6 * 7 * Authors: 8 * Murali Karicheri <m-karicheri2@ti.com> 9 * Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/err.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/memory/ti-aemif.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/of.h> 20 #include <linux/of_platform.h> 21 #include <linux/platform_device.h> 22 23 #define TA_SHIFT 2 24 #define RHOLD_SHIFT 4 25 #define RSTROBE_SHIFT 7 26 #define RSETUP_SHIFT 13 27 #define WHOLD_SHIFT 17 28 #define WSTROBE_SHIFT 20 29 #define WSETUP_SHIFT 26 30 #define EW_SHIFT 30 31 #define SSTROBE_SHIFT 31 32 33 #define TA(x) ((x) << TA_SHIFT) 34 #define RHOLD(x) ((x) << RHOLD_SHIFT) 35 #define RSTROBE(x) ((x) << RSTROBE_SHIFT) 36 #define RSETUP(x) ((x) << RSETUP_SHIFT) 37 #define WHOLD(x) ((x) << WHOLD_SHIFT) 38 #define WSTROBE(x) ((x) << WSTROBE_SHIFT) 39 #define WSETUP(x) ((x) << WSETUP_SHIFT) 40 #define EW(x) ((x) << EW_SHIFT) 41 #define SSTROBE(x) ((x) << SSTROBE_SHIFT) 42 43 #define ASIZE_MAX 0x1 44 #define TA_MAX 0x3 45 #define RHOLD_MAX 0x7 46 #define RSTROBE_MAX 0x3f 47 #define RSETUP_MAX 0xf 48 #define WHOLD_MAX 0x7 49 #define WSTROBE_MAX 0x3f 50 #define WSETUP_MAX 0xf 51 #define EW_MAX 0x1 52 #define SSTROBE_MAX 0x1 53 #define NUM_CS 4 54 55 #define TA_VAL(x) (((x) & TA(TA_MAX)) >> TA_SHIFT) 56 #define RHOLD_VAL(x) (((x) & RHOLD(RHOLD_MAX)) >> RHOLD_SHIFT) 57 #define RSTROBE_VAL(x) (((x) & RSTROBE(RSTROBE_MAX)) >> RSTROBE_SHIFT) 58 #define RSETUP_VAL(x) (((x) & RSETUP(RSETUP_MAX)) >> RSETUP_SHIFT) 59 #define WHOLD_VAL(x) (((x) & WHOLD(WHOLD_MAX)) >> WHOLD_SHIFT) 60 #define WSTROBE_VAL(x) (((x) & WSTROBE(WSTROBE_MAX)) >> WSTROBE_SHIFT) 61 #define WSETUP_VAL(x) (((x) & WSETUP(WSETUP_MAX)) >> WSETUP_SHIFT) 62 #define EW_VAL(x) (((x) & EW(EW_MAX)) >> EW_SHIFT) 63 #define SSTROBE_VAL(x) (((x) & SSTROBE(SSTROBE_MAX)) >> SSTROBE_SHIFT) 64 65 #define NRCSR_OFFSET 0x00 66 #define AWCCR_OFFSET 0x04 67 #define A1CR_OFFSET 0x10 68 69 #define ACR_ASIZE_MASK 0x3 70 #define ACR_EW_MASK BIT(30) 71 #define ACR_SSTROBE_MASK BIT(31) 72 #define ASIZE_16BIT 1 73 74 #define TIMINGS_MASK (TA(TA_MAX) | \ 75 RHOLD(RHOLD_MAX) | \ 76 RSTROBE(RSTROBE_MAX) | \ 77 RSETUP(RSETUP_MAX) | \ 78 WHOLD(WHOLD_MAX) | \ 79 WSTROBE(WSTROBE_MAX) | \ 80 WSETUP(WSETUP_MAX)) 81 82 #define CONFIG_MASK (EW(EW_MAX) | SSTROBE(SSTROBE_MAX) | ASIZE_MAX) 83 84 /** 85 * struct aemif_cs_data: structure to hold CS parameters 86 * @timings: timings configuration 87 * @cs: chip-select number 88 * @enable_ss: enable/disable select strobe mode 89 * @enable_ew: enable/disable extended wait mode 90 * @asize: width of the asynchronous device's data bus 91 */ 92 struct aemif_cs_data { 93 struct aemif_cs_timings timings; 94 u8 cs; 95 u8 enable_ss; 96 u8 enable_ew; 97 u8 asize; 98 }; 99 100 /** 101 * struct aemif_device: structure to hold device data 102 * @base: base address of AEMIF registers 103 * @clk: source clock 104 * @clk_rate: clock's rate in kHz 105 * @num_cs: number of assigned chip-selects 106 * @cs_offset: start number of cs nodes 107 * @cs_data: array of chip-select settings 108 * @config_cs_lock: lock used to access CS configuration 109 */ 110 struct aemif_device { 111 void __iomem *base; 112 struct clk *clk; 113 unsigned long clk_rate; 114 u8 num_cs; 115 int cs_offset; 116 struct aemif_cs_data cs_data[NUM_CS]; 117 struct mutex config_cs_lock; 118 }; 119 120 /** 121 * aemif_check_cs_timings() - Check the validity of a CS timing configuration. 122 * @timings: timings configuration 123 * 124 * @return: 0 if the timing configuration is valid, negative error number otherwise. 125 */ 126 int aemif_check_cs_timings(struct aemif_cs_timings *timings) 127 { 128 if (timings->ta > TA_MAX) 129 return -EINVAL; 130 131 if (timings->rhold > RHOLD_MAX) 132 return -EINVAL; 133 134 if (timings->rstrobe > RSTROBE_MAX) 135 return -EINVAL; 136 137 if (timings->rsetup > RSETUP_MAX) 138 return -EINVAL; 139 140 if (timings->whold > WHOLD_MAX) 141 return -EINVAL; 142 143 if (timings->wstrobe > WSTROBE_MAX) 144 return -EINVAL; 145 146 if (timings->wsetup > WSETUP_MAX) 147 return -EINVAL; 148 149 return 0; 150 } 151 EXPORT_SYMBOL_GPL(aemif_check_cs_timings); 152 153 /** 154 * aemif_set_cs_timings() - Set the timing configuration of a given chip select. 155 * @aemif: aemif device to configure 156 * @cs: index of the chip select to configure 157 * @timings: timings configuration to set 158 * 159 * @return: 0 on success, else negative errno. 160 */ 161 int aemif_set_cs_timings(struct aemif_device *aemif, u8 cs, 162 struct aemif_cs_timings *timings) 163 { 164 unsigned int offset; 165 u32 val, set; 166 int ret; 167 168 if (!timings || !aemif) 169 return -EINVAL; 170 171 if (cs > aemif->num_cs) 172 return -EINVAL; 173 174 ret = aemif_check_cs_timings(timings); 175 if (ret) 176 return ret; 177 178 set = TA(timings->ta) | RHOLD(timings->rhold) | RSTROBE(timings->rstrobe) | 179 RSETUP(timings->rsetup) | WHOLD(timings->whold) | 180 WSTROBE(timings->wstrobe) | WSETUP(timings->wsetup); 181 182 offset = A1CR_OFFSET + cs * 4; 183 184 mutex_lock(&aemif->config_cs_lock); 185 val = readl(aemif->base + offset); 186 val &= ~TIMINGS_MASK; 187 val |= set; 188 writel(val, aemif->base + offset); 189 mutex_unlock(&aemif->config_cs_lock); 190 191 return 0; 192 } 193 EXPORT_SYMBOL_GPL(aemif_set_cs_timings); 194 195 /** 196 * aemif_calc_rate - calculate timing data. 197 * @pdev: platform device to calculate for 198 * @wanted: The cycle time needed in nanoseconds. 199 * @clk: The input clock rate in kHz. 200 * 201 * @return: the calculated timing value minus 1 for easy 202 * programming into AEMIF timing registers. 203 */ 204 static u32 aemif_calc_rate(struct platform_device *pdev, int wanted, unsigned long clk) 205 { 206 int result; 207 208 result = DIV_ROUND_UP((wanted * clk), NSEC_PER_MSEC) - 1; 209 210 dev_dbg(&pdev->dev, "%s: result %d from %ld, %d\n", __func__, result, 211 clk, wanted); 212 213 /* It is generally OK to have a more relaxed timing than requested... */ 214 if (result < 0) 215 result = 0; 216 217 return result; 218 } 219 220 /** 221 * aemif_config_abus - configure async bus parameters 222 * @pdev: platform device to configure for 223 * @csnum: aemif chip select number 224 * 225 * This function programs the given timing values (in real clock) into the 226 * AEMIF registers taking the AEMIF clock into account. 227 * 228 * This function does not use any locking while programming the AEMIF 229 * because it is expected that there is only one user of a given 230 * chip-select. 231 * 232 * Returns 0 on success, else negative errno. 233 */ 234 static int aemif_config_abus(struct platform_device *pdev, int csnum) 235 { 236 struct aemif_device *aemif = platform_get_drvdata(pdev); 237 struct aemif_cs_data *data = &aemif->cs_data[csnum]; 238 unsigned offset; 239 u32 set, val; 240 241 offset = A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4; 242 243 set = (data->asize & ACR_ASIZE_MASK); 244 if (data->enable_ew) 245 set |= ACR_EW_MASK; 246 if (data->enable_ss) 247 set |= ACR_SSTROBE_MASK; 248 249 mutex_lock(&aemif->config_cs_lock); 250 val = readl(aemif->base + offset); 251 val &= ~CONFIG_MASK; 252 val |= set; 253 writel(val, aemif->base + offset); 254 mutex_unlock(&aemif->config_cs_lock); 255 256 return aemif_set_cs_timings(aemif, data->cs - aemif->cs_offset, &data->timings); 257 } 258 259 /** 260 * aemif_get_hw_params - function to read hw register values 261 * @pdev: platform device to read for 262 * @csnum: aemif chip select number 263 * 264 * This function reads the defaults from the registers and update 265 * the timing values. Required for get/set commands and also for 266 * the case when driver needs to use defaults in hardware. 267 */ 268 static void aemif_get_hw_params(struct platform_device *pdev, int csnum) 269 { 270 struct aemif_device *aemif = platform_get_drvdata(pdev); 271 struct aemif_cs_data *data = &aemif->cs_data[csnum]; 272 u32 val, offset; 273 274 offset = A1CR_OFFSET + (data->cs - aemif->cs_offset) * 4; 275 val = readl(aemif->base + offset); 276 277 data->timings.ta = TA_VAL(val); 278 data->timings.rhold = RHOLD_VAL(val); 279 data->timings.rstrobe = RSTROBE_VAL(val); 280 data->timings.rsetup = RSETUP_VAL(val); 281 data->timings.whold = WHOLD_VAL(val); 282 data->timings.wstrobe = WSTROBE_VAL(val); 283 data->timings.wsetup = WSETUP_VAL(val); 284 data->enable_ew = EW_VAL(val); 285 data->enable_ss = SSTROBE_VAL(val); 286 data->asize = val & ASIZE_MAX; 287 } 288 289 /** 290 * of_aemif_parse_abus_config - parse CS configuration from DT 291 * @pdev: platform device to parse for 292 * @np: device node ptr 293 * 294 * This function update the emif async bus configuration based on the values 295 * configured in a cs device binding node. 296 */ 297 static int of_aemif_parse_abus_config(struct platform_device *pdev, 298 struct device_node *np) 299 { 300 struct aemif_device *aemif = platform_get_drvdata(pdev); 301 unsigned long clk_rate = aemif->clk_rate; 302 struct aemif_cs_data *data; 303 u32 cs; 304 u32 val; 305 306 if (of_property_read_u32(np, "ti,cs-chipselect", &cs)) { 307 dev_dbg(&pdev->dev, "cs property is required"); 308 return -EINVAL; 309 } 310 311 if (cs - aemif->cs_offset >= NUM_CS || cs < aemif->cs_offset) { 312 dev_dbg(&pdev->dev, "cs number is incorrect %d", cs); 313 return -EINVAL; 314 } 315 316 if (aemif->num_cs >= NUM_CS) { 317 dev_dbg(&pdev->dev, "cs count is more than %d", NUM_CS); 318 return -EINVAL; 319 } 320 321 data = &aemif->cs_data[aemif->num_cs]; 322 data->cs = cs; 323 324 /* read the current value in the hw register */ 325 aemif_get_hw_params(pdev, aemif->num_cs++); 326 327 /* override the values from device node */ 328 if (!of_property_read_u32(np, "ti,cs-min-turnaround-ns", &val)) 329 data->timings.ta = aemif_calc_rate(pdev, val, clk_rate); 330 331 if (!of_property_read_u32(np, "ti,cs-read-hold-ns", &val)) 332 data->timings.rhold = aemif_calc_rate(pdev, val, clk_rate); 333 334 if (!of_property_read_u32(np, "ti,cs-read-strobe-ns", &val)) 335 data->timings.rstrobe = aemif_calc_rate(pdev, val, clk_rate); 336 337 if (!of_property_read_u32(np, "ti,cs-read-setup-ns", &val)) 338 data->timings.rsetup = aemif_calc_rate(pdev, val, clk_rate); 339 340 if (!of_property_read_u32(np, "ti,cs-write-hold-ns", &val)) 341 data->timings.whold = aemif_calc_rate(pdev, val, clk_rate); 342 343 if (!of_property_read_u32(np, "ti,cs-write-strobe-ns", &val)) 344 data->timings.wstrobe = aemif_calc_rate(pdev, val, clk_rate); 345 346 if (!of_property_read_u32(np, "ti,cs-write-setup-ns", &val)) 347 data->timings.wsetup = aemif_calc_rate(pdev, val, clk_rate); 348 349 if (!of_property_read_u32(np, "ti,cs-bus-width", &val)) 350 if (val == 16) 351 data->asize = 1; 352 data->enable_ew = of_property_read_bool(np, "ti,cs-extended-wait-mode"); 353 data->enable_ss = of_property_read_bool(np, "ti,cs-select-strobe-mode"); 354 355 return aemif_check_cs_timings(&data->timings); 356 } 357 358 static const struct of_device_id aemif_of_match[] = { 359 { .compatible = "ti,davinci-aemif", }, 360 { .compatible = "ti,da850-aemif", }, 361 {}, 362 }; 363 MODULE_DEVICE_TABLE(of, aemif_of_match); 364 365 static int aemif_probe(struct platform_device *pdev) 366 { 367 int i; 368 int ret = -ENODEV; 369 struct device *dev = &pdev->dev; 370 struct device_node *np = dev->of_node; 371 struct aemif_device *aemif; 372 373 aemif = devm_kzalloc(dev, sizeof(*aemif), GFP_KERNEL); 374 if (!aemif) 375 return -ENOMEM; 376 377 platform_set_drvdata(pdev, aemif); 378 379 aemif->clk = devm_clk_get_enabled(dev, NULL); 380 if (IS_ERR(aemif->clk)) 381 return dev_err_probe(dev, PTR_ERR(aemif->clk), 382 "cannot get clock 'aemif'\n"); 383 384 aemif->clk_rate = clk_get_rate(aemif->clk) / MSEC_PER_SEC; 385 386 if (np && of_device_is_compatible(np, "ti,da850-aemif")) 387 aemif->cs_offset = 2; 388 389 aemif->base = devm_platform_ioremap_resource(pdev, 0); 390 if (IS_ERR(aemif->base)) 391 return PTR_ERR(aemif->base); 392 393 mutex_init(&aemif->config_cs_lock); 394 if (np) { 395 /* 396 * For every controller device node, there is a cs device node 397 * that describe the bus configuration parameters. This 398 * functions iterate over these nodes and update the cs data 399 * array. 400 */ 401 for_each_available_child_of_node_scoped(np, child_np) { 402 ret = of_aemif_parse_abus_config(pdev, child_np); 403 if (ret < 0) 404 return ret; 405 } 406 } 407 408 for (i = 0; i < aemif->num_cs; i++) { 409 ret = aemif_config_abus(pdev, i); 410 if (ret < 0) { 411 dev_err(dev, "Error configuring chip select %d\n", 412 aemif->cs_data[i].cs); 413 return ret; 414 } 415 } 416 417 /* 418 * Create a child devices explicitly from here to guarantee that the 419 * child will be probed after the AEMIF timing parameters are set. 420 */ 421 if (np) { 422 for_each_available_child_of_node_scoped(np, child_np) { 423 ret = of_platform_populate(child_np, NULL, NULL, dev); 424 if (ret < 0) 425 return ret; 426 } 427 } 428 429 return 0; 430 } 431 432 static struct platform_driver aemif_driver = { 433 .probe = aemif_probe, 434 .driver = { 435 .name = "ti-aemif", 436 .of_match_table = of_match_ptr(aemif_of_match), 437 }, 438 }; 439 440 module_platform_driver(aemif_driver); 441 442 MODULE_AUTHOR("Murali Karicheri <m-karicheri2@ti.com>"); 443 MODULE_AUTHOR("Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>"); 444 MODULE_DESCRIPTION("Texas Instruments AEMIF driver"); 445 MODULE_LICENSE("GPL v2"); 446 MODULE_ALIAS("platform:" KBUILD_MODNAME); 447