1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Tegra30 External Memory Controller driver 4 * 5 * Based on downstream driver from NVIDIA and tegra124-emc.c 6 * Copyright (C) 2011-2014 NVIDIA Corporation 7 * 8 * Author: Dmitry Osipenko <digetx@gmail.com> 9 * Copyright (C) 2019 GRATE-DRIVER project 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/clk.h> 14 #include <linux/clk/tegra.h> 15 #include <linux/debugfs.h> 16 #include <linux/delay.h> 17 #include <linux/err.h> 18 #include <linux/interconnect-provider.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/iopoll.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/mutex.h> 25 #include <linux/of.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_opp.h> 28 #include <linux/slab.h> 29 #include <linux/sort.h> 30 #include <linux/types.h> 31 32 #include <soc/tegra/common.h> 33 #include <soc/tegra/fuse.h> 34 35 #include "../jedec_ddr.h" 36 #include "../of_memory.h" 37 38 #include "mc.h" 39 #include "tegra-emc-common.h" 40 41 #define EMC_INTSTATUS 0x000 42 #define EMC_INTMASK 0x004 43 #define EMC_DBG 0x008 44 #define EMC_ADR_CFG 0x010 45 #define EMC_CFG 0x00c 46 #define EMC_REFCTRL 0x020 47 #define EMC_TIMING_CONTROL 0x028 48 #define EMC_RC 0x02c 49 #define EMC_RFC 0x030 50 #define EMC_RAS 0x034 51 #define EMC_RP 0x038 52 #define EMC_R2W 0x03c 53 #define EMC_W2R 0x040 54 #define EMC_R2P 0x044 55 #define EMC_W2P 0x048 56 #define EMC_RD_RCD 0x04c 57 #define EMC_WR_RCD 0x050 58 #define EMC_RRD 0x054 59 #define EMC_REXT 0x058 60 #define EMC_WDV 0x05c 61 #define EMC_QUSE 0x060 62 #define EMC_QRST 0x064 63 #define EMC_QSAFE 0x068 64 #define EMC_RDV 0x06c 65 #define EMC_REFRESH 0x070 66 #define EMC_BURST_REFRESH_NUM 0x074 67 #define EMC_PDEX2WR 0x078 68 #define EMC_PDEX2RD 0x07c 69 #define EMC_PCHG2PDEN 0x080 70 #define EMC_ACT2PDEN 0x084 71 #define EMC_AR2PDEN 0x088 72 #define EMC_RW2PDEN 0x08c 73 #define EMC_TXSR 0x090 74 #define EMC_TCKE 0x094 75 #define EMC_TFAW 0x098 76 #define EMC_TRPAB 0x09c 77 #define EMC_TCLKSTABLE 0x0a0 78 #define EMC_TCLKSTOP 0x0a4 79 #define EMC_TREFBW 0x0a8 80 #define EMC_QUSE_EXTRA 0x0ac 81 #define EMC_ODT_WRITE 0x0b0 82 #define EMC_ODT_READ 0x0b4 83 #define EMC_WEXT 0x0b8 84 #define EMC_CTT 0x0bc 85 #define EMC_MRS_WAIT_CNT 0x0c8 86 #define EMC_MRS 0x0cc 87 #define EMC_EMRS 0x0d0 88 #define EMC_SELF_REF 0x0e0 89 #define EMC_MRW 0x0e8 90 #define EMC_MRR 0x0ec 91 #define EMC_XM2DQSPADCTRL3 0x0f8 92 #define EMC_FBIO_SPARE 0x100 93 #define EMC_FBIO_CFG5 0x104 94 #define EMC_FBIO_CFG6 0x114 95 #define EMC_CFG_RSV 0x120 96 #define EMC_AUTO_CAL_CONFIG 0x2a4 97 #define EMC_AUTO_CAL_INTERVAL 0x2a8 98 #define EMC_AUTO_CAL_STATUS 0x2ac 99 #define EMC_STATUS 0x2b4 100 #define EMC_CFG_2 0x2b8 101 #define EMC_CFG_DIG_DLL 0x2bc 102 #define EMC_CFG_DIG_DLL_PERIOD 0x2c0 103 #define EMC_CTT_DURATION 0x2d8 104 #define EMC_CTT_TERM_CTRL 0x2dc 105 #define EMC_ZCAL_INTERVAL 0x2e0 106 #define EMC_ZCAL_WAIT_CNT 0x2e4 107 #define EMC_ZQ_CAL 0x2ec 108 #define EMC_XM2CMDPADCTRL 0x2f0 109 #define EMC_XM2DQSPADCTRL2 0x2fc 110 #define EMC_XM2DQPADCTRL2 0x304 111 #define EMC_XM2CLKPADCTRL 0x308 112 #define EMC_XM2COMPPADCTRL 0x30c 113 #define EMC_XM2VTTGENPADCTRL 0x310 114 #define EMC_XM2VTTGENPADCTRL2 0x314 115 #define EMC_XM2QUSEPADCTRL 0x318 116 #define EMC_DLL_XFORM_DQS0 0x328 117 #define EMC_DLL_XFORM_DQS1 0x32c 118 #define EMC_DLL_XFORM_DQS2 0x330 119 #define EMC_DLL_XFORM_DQS3 0x334 120 #define EMC_DLL_XFORM_DQS4 0x338 121 #define EMC_DLL_XFORM_DQS5 0x33c 122 #define EMC_DLL_XFORM_DQS6 0x340 123 #define EMC_DLL_XFORM_DQS7 0x344 124 #define EMC_DLL_XFORM_QUSE0 0x348 125 #define EMC_DLL_XFORM_QUSE1 0x34c 126 #define EMC_DLL_XFORM_QUSE2 0x350 127 #define EMC_DLL_XFORM_QUSE3 0x354 128 #define EMC_DLL_XFORM_QUSE4 0x358 129 #define EMC_DLL_XFORM_QUSE5 0x35c 130 #define EMC_DLL_XFORM_QUSE6 0x360 131 #define EMC_DLL_XFORM_QUSE7 0x364 132 #define EMC_DLL_XFORM_DQ0 0x368 133 #define EMC_DLL_XFORM_DQ1 0x36c 134 #define EMC_DLL_XFORM_DQ2 0x370 135 #define EMC_DLL_XFORM_DQ3 0x374 136 #define EMC_DLI_TRIM_TXDQS0 0x3a8 137 #define EMC_DLI_TRIM_TXDQS1 0x3ac 138 #define EMC_DLI_TRIM_TXDQS2 0x3b0 139 #define EMC_DLI_TRIM_TXDQS3 0x3b4 140 #define EMC_DLI_TRIM_TXDQS4 0x3b8 141 #define EMC_DLI_TRIM_TXDQS5 0x3bc 142 #define EMC_DLI_TRIM_TXDQS6 0x3c0 143 #define EMC_DLI_TRIM_TXDQS7 0x3c4 144 #define EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE 0x3c8 145 #define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc 146 #define EMC_UNSTALL_RW_AFTER_CLKCHANGE 0x3d0 147 #define EMC_SEL_DPD_CTRL 0x3d8 148 #define EMC_PRE_REFRESH_REQ_CNT 0x3dc 149 #define EMC_DYN_SELF_REF_CONTROL 0x3e0 150 #define EMC_TXSRDLL 0x3e4 151 152 #define EMC_STATUS_TIMING_UPDATE_STALLED BIT(23) 153 154 #define EMC_MODE_SET_DLL_RESET BIT(8) 155 #define EMC_MODE_SET_LONG_CNT BIT(26) 156 157 #define EMC_SELF_REF_CMD_ENABLED BIT(0) 158 159 #define DRAM_DEV_SEL_ALL (0 << 30) 160 #define DRAM_DEV_SEL_0 BIT(31) 161 #define DRAM_DEV_SEL_1 BIT(30) 162 #define DRAM_BROADCAST(num) \ 163 ((num) > 1 ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0) 164 165 #define EMC_ZQ_CAL_CMD BIT(0) 166 #define EMC_ZQ_CAL_LONG BIT(4) 167 #define EMC_ZQ_CAL_LONG_CMD_DEV0 \ 168 (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD) 169 #define EMC_ZQ_CAL_LONG_CMD_DEV1 \ 170 (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD) 171 172 #define EMC_DBG_READ_MUX_ASSEMBLY BIT(0) 173 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1) 174 #define EMC_DBG_FORCE_UPDATE BIT(2) 175 #define EMC_DBG_CFG_PRIORITY BIT(24) 176 177 #define EMC_CFG5_QUSE_MODE_SHIFT 13 178 #define EMC_CFG5_QUSE_MODE_MASK (7 << EMC_CFG5_QUSE_MODE_SHIFT) 179 180 #define EMC_CFG5_QUSE_MODE_INTERNAL_LPBK 2 181 #define EMC_CFG5_QUSE_MODE_PULSE_INTERN 3 182 183 #define EMC_SEL_DPD_CTRL_QUSE_DPD_ENABLE BIT(9) 184 185 #define EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE BIT(10) 186 187 #define EMC_XM2QUSEPADCTRL_IVREF_ENABLE BIT(4) 188 189 #define EMC_XM2DQSPADCTRL2_VREF_ENABLE BIT(5) 190 #define EMC_XM2DQSPADCTRL3_VREF_ENABLE BIT(5) 191 192 #define EMC_AUTO_CAL_STATUS_ACTIVE BIT(31) 193 194 #define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3 195 196 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK 0x3ff 197 #define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT 16 198 #define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK \ 199 (0x3ff << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) 200 201 #define EMC_REFCTRL_DEV_SEL_MASK 0x3 202 #define EMC_REFCTRL_ENABLE BIT(31) 203 #define EMC_REFCTRL_ENABLE_ALL(num) \ 204 (((num) > 1 ? 0 : 2) | EMC_REFCTRL_ENABLE) 205 #define EMC_REFCTRL_DISABLE_ALL(num) ((num) > 1 ? 0 : 2) 206 207 #define EMC_CFG_PERIODIC_QRST BIT(21) 208 #define EMC_CFG_DYN_SREF_ENABLE BIT(28) 209 210 #define EMC_CLKCHANGE_REQ_ENABLE BIT(0) 211 #define EMC_CLKCHANGE_PD_ENABLE BIT(1) 212 #define EMC_CLKCHANGE_SR_ENABLE BIT(2) 213 214 #define EMC_TIMING_UPDATE BIT(0) 215 216 #define EMC_REFRESH_OVERFLOW_INT BIT(3) 217 #define EMC_CLKCHANGE_COMPLETE_INT BIT(4) 218 #define EMC_MRR_DIVLD_INT BIT(5) 219 220 #define EMC_MRR_DEV_SELECTN GENMASK(31, 30) 221 #define EMC_MRR_MRR_MA GENMASK(23, 16) 222 #define EMC_MRR_MRR_DATA GENMASK(15, 0) 223 224 #define EMC_ADR_CFG_EMEM_NUMDEV BIT(0) 225 226 enum emc_dram_type { 227 DRAM_TYPE_DDR3, 228 DRAM_TYPE_DDR1, 229 DRAM_TYPE_LPDDR2, 230 DRAM_TYPE_DDR2, 231 }; 232 233 enum emc_dll_change { 234 DLL_CHANGE_NONE, 235 DLL_CHANGE_ON, 236 DLL_CHANGE_OFF 237 }; 238 239 static const u16 emc_timing_registers[] = { 240 [0] = EMC_RC, 241 [1] = EMC_RFC, 242 [2] = EMC_RAS, 243 [3] = EMC_RP, 244 [4] = EMC_R2W, 245 [5] = EMC_W2R, 246 [6] = EMC_R2P, 247 [7] = EMC_W2P, 248 [8] = EMC_RD_RCD, 249 [9] = EMC_WR_RCD, 250 [10] = EMC_RRD, 251 [11] = EMC_REXT, 252 [12] = EMC_WEXT, 253 [13] = EMC_WDV, 254 [14] = EMC_QUSE, 255 [15] = EMC_QRST, 256 [16] = EMC_QSAFE, 257 [17] = EMC_RDV, 258 [18] = EMC_REFRESH, 259 [19] = EMC_BURST_REFRESH_NUM, 260 [20] = EMC_PRE_REFRESH_REQ_CNT, 261 [21] = EMC_PDEX2WR, 262 [22] = EMC_PDEX2RD, 263 [23] = EMC_PCHG2PDEN, 264 [24] = EMC_ACT2PDEN, 265 [25] = EMC_AR2PDEN, 266 [26] = EMC_RW2PDEN, 267 [27] = EMC_TXSR, 268 [28] = EMC_TXSRDLL, 269 [29] = EMC_TCKE, 270 [30] = EMC_TFAW, 271 [31] = EMC_TRPAB, 272 [32] = EMC_TCLKSTABLE, 273 [33] = EMC_TCLKSTOP, 274 [34] = EMC_TREFBW, 275 [35] = EMC_QUSE_EXTRA, 276 [36] = EMC_FBIO_CFG6, 277 [37] = EMC_ODT_WRITE, 278 [38] = EMC_ODT_READ, 279 [39] = EMC_FBIO_CFG5, 280 [40] = EMC_CFG_DIG_DLL, 281 [41] = EMC_CFG_DIG_DLL_PERIOD, 282 [42] = EMC_DLL_XFORM_DQS0, 283 [43] = EMC_DLL_XFORM_DQS1, 284 [44] = EMC_DLL_XFORM_DQS2, 285 [45] = EMC_DLL_XFORM_DQS3, 286 [46] = EMC_DLL_XFORM_DQS4, 287 [47] = EMC_DLL_XFORM_DQS5, 288 [48] = EMC_DLL_XFORM_DQS6, 289 [49] = EMC_DLL_XFORM_DQS7, 290 [50] = EMC_DLL_XFORM_QUSE0, 291 [51] = EMC_DLL_XFORM_QUSE1, 292 [52] = EMC_DLL_XFORM_QUSE2, 293 [53] = EMC_DLL_XFORM_QUSE3, 294 [54] = EMC_DLL_XFORM_QUSE4, 295 [55] = EMC_DLL_XFORM_QUSE5, 296 [56] = EMC_DLL_XFORM_QUSE6, 297 [57] = EMC_DLL_XFORM_QUSE7, 298 [58] = EMC_DLI_TRIM_TXDQS0, 299 [59] = EMC_DLI_TRIM_TXDQS1, 300 [60] = EMC_DLI_TRIM_TXDQS2, 301 [61] = EMC_DLI_TRIM_TXDQS3, 302 [62] = EMC_DLI_TRIM_TXDQS4, 303 [63] = EMC_DLI_TRIM_TXDQS5, 304 [64] = EMC_DLI_TRIM_TXDQS6, 305 [65] = EMC_DLI_TRIM_TXDQS7, 306 [66] = EMC_DLL_XFORM_DQ0, 307 [67] = EMC_DLL_XFORM_DQ1, 308 [68] = EMC_DLL_XFORM_DQ2, 309 [69] = EMC_DLL_XFORM_DQ3, 310 [70] = EMC_XM2CMDPADCTRL, 311 [71] = EMC_XM2DQSPADCTRL2, 312 [72] = EMC_XM2DQPADCTRL2, 313 [73] = EMC_XM2CLKPADCTRL, 314 [74] = EMC_XM2COMPPADCTRL, 315 [75] = EMC_XM2VTTGENPADCTRL, 316 [76] = EMC_XM2VTTGENPADCTRL2, 317 [77] = EMC_XM2QUSEPADCTRL, 318 [78] = EMC_XM2DQSPADCTRL3, 319 [79] = EMC_CTT_TERM_CTRL, 320 [80] = EMC_ZCAL_INTERVAL, 321 [81] = EMC_ZCAL_WAIT_CNT, 322 [82] = EMC_MRS_WAIT_CNT, 323 [83] = EMC_AUTO_CAL_CONFIG, 324 [84] = EMC_CTT, 325 [85] = EMC_CTT_DURATION, 326 [86] = EMC_DYN_SELF_REF_CONTROL, 327 [87] = EMC_FBIO_SPARE, 328 [88] = EMC_CFG_RSV, 329 }; 330 331 struct emc_timing { 332 unsigned long rate; 333 334 u32 data[ARRAY_SIZE(emc_timing_registers)]; 335 336 u32 emc_auto_cal_interval; 337 u32 emc_mode_1; 338 u32 emc_mode_2; 339 u32 emc_mode_reset; 340 u32 emc_zcal_cnt_long; 341 bool emc_cfg_periodic_qrst; 342 bool emc_cfg_dyn_self_ref; 343 }; 344 345 struct tegra_emc { 346 struct device *dev; 347 struct tegra_mc *mc; 348 struct icc_provider provider; 349 struct notifier_block clk_nb; 350 struct clk *clk; 351 void __iomem *regs; 352 unsigned int irq; 353 bool bad_state; 354 355 struct emc_timing *new_timing; 356 struct emc_timing *timings; 357 unsigned int num_timings; 358 359 u32 mc_override; 360 u32 emc_cfg; 361 362 u32 emc_mode_1; 363 u32 emc_mode_2; 364 u32 emc_mode_reset; 365 366 bool vref_cal_toggle : 1; 367 bool zcal_long : 1; 368 bool dll_on : 1; 369 370 struct { 371 struct dentry *root; 372 unsigned long min_rate; 373 unsigned long max_rate; 374 } debugfs; 375 376 struct tegra_emc_rate_requests reqs; 377 378 bool mrr_error; 379 }; 380 381 static int emc_seq_update_timing(struct tegra_emc *emc) 382 { 383 u32 val; 384 int err; 385 386 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); 387 388 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, 389 !(val & EMC_STATUS_TIMING_UPDATE_STALLED), 390 1, 200); 391 if (err) { 392 dev_err(emc->dev, "failed to update timing: %d\n", err); 393 return err; 394 } 395 396 return 0; 397 } 398 399 static irqreturn_t tegra30_emc_isr(int irq, void *data) 400 { 401 struct tegra_emc *emc = data; 402 u32 intmask = EMC_REFRESH_OVERFLOW_INT; 403 u32 status; 404 405 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; 406 if (!status) 407 return IRQ_NONE; 408 409 /* notify about HW problem */ 410 if (status & EMC_REFRESH_OVERFLOW_INT) 411 dev_err_ratelimited(emc->dev, 412 "refresh request overflow timeout\n"); 413 414 /* clear interrupts */ 415 writel_relaxed(status, emc->regs + EMC_INTSTATUS); 416 417 return IRQ_HANDLED; 418 } 419 420 static struct emc_timing *emc_find_timing(struct tegra_emc *emc, 421 unsigned long rate) 422 { 423 struct emc_timing *timing = NULL; 424 unsigned int i; 425 426 for (i = 0; i < emc->num_timings; i++) { 427 if (emc->timings[i].rate >= rate) { 428 timing = &emc->timings[i]; 429 break; 430 } 431 } 432 433 if (!timing) { 434 dev_err(emc->dev, "no timing for rate %lu\n", rate); 435 return NULL; 436 } 437 438 return timing; 439 } 440 441 static bool emc_dqs_preset(struct tegra_emc *emc, struct emc_timing *timing, 442 bool *schmitt_to_vref) 443 { 444 bool preset = false; 445 u32 val; 446 447 if (timing->data[71] & EMC_XM2DQSPADCTRL2_VREF_ENABLE) { 448 val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL2); 449 450 if (!(val & EMC_XM2DQSPADCTRL2_VREF_ENABLE)) { 451 val |= EMC_XM2DQSPADCTRL2_VREF_ENABLE; 452 writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL2); 453 454 preset = true; 455 } 456 } 457 458 if (timing->data[78] & EMC_XM2DQSPADCTRL3_VREF_ENABLE) { 459 val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL3); 460 461 if (!(val & EMC_XM2DQSPADCTRL3_VREF_ENABLE)) { 462 val |= EMC_XM2DQSPADCTRL3_VREF_ENABLE; 463 writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL3); 464 465 preset = true; 466 } 467 } 468 469 if (timing->data[77] & EMC_XM2QUSEPADCTRL_IVREF_ENABLE) { 470 val = readl_relaxed(emc->regs + EMC_XM2QUSEPADCTRL); 471 472 if (!(val & EMC_XM2QUSEPADCTRL_IVREF_ENABLE)) { 473 val |= EMC_XM2QUSEPADCTRL_IVREF_ENABLE; 474 writel_relaxed(val, emc->regs + EMC_XM2QUSEPADCTRL); 475 476 *schmitt_to_vref = true; 477 preset = true; 478 } 479 } 480 481 return preset; 482 } 483 484 static int emc_prepare_mc_clk_cfg(struct tegra_emc *emc, unsigned long rate) 485 { 486 struct tegra_mc *mc = emc->mc; 487 unsigned int misc0_index = 16; 488 unsigned int i; 489 bool same; 490 491 for (i = 0; i < mc->num_timings; i++) { 492 if (mc->timings[i].rate != rate) 493 continue; 494 495 if (mc->timings[i].emem_data[misc0_index] & BIT(27)) 496 same = true; 497 else 498 same = false; 499 500 return tegra20_clk_prepare_emc_mc_same_freq(emc->clk, same); 501 } 502 503 return -EINVAL; 504 } 505 506 static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate) 507 { 508 struct emc_timing *timing = emc_find_timing(emc, rate); 509 enum emc_dll_change dll_change; 510 enum emc_dram_type dram_type; 511 bool schmitt_to_vref = false; 512 unsigned int pre_wait = 0; 513 bool qrst_used = false; 514 unsigned int dram_num; 515 unsigned int i; 516 u32 fbio_cfg5; 517 u32 emc_dbg; 518 u32 val; 519 int err; 520 521 if (!timing || emc->bad_state) 522 return -EINVAL; 523 524 dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n", 525 __func__, timing->rate, rate); 526 527 emc->bad_state = true; 528 529 err = emc_prepare_mc_clk_cfg(emc, rate); 530 if (err) { 531 dev_err(emc->dev, "mc clock preparation failed: %d\n", err); 532 return err; 533 } 534 535 emc->vref_cal_toggle = false; 536 emc->mc_override = mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE); 537 emc->emc_cfg = readl_relaxed(emc->regs + EMC_CFG); 538 emc_dbg = readl_relaxed(emc->regs + EMC_DBG); 539 540 if (emc->dll_on == !(timing->emc_mode_1 & 0x1)) 541 dll_change = DLL_CHANGE_NONE; 542 else if (!(timing->emc_mode_1 & 0x1)) 543 dll_change = DLL_CHANGE_ON; 544 else 545 dll_change = DLL_CHANGE_OFF; 546 547 emc->dll_on = !(timing->emc_mode_1 & 0x1); 548 549 if (timing->data[80] && !readl_relaxed(emc->regs + EMC_ZCAL_INTERVAL)) 550 emc->zcal_long = true; 551 else 552 emc->zcal_long = false; 553 554 fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5); 555 dram_type = fbio_cfg5 & EMC_FBIO_CFG5_DRAM_TYPE_MASK; 556 557 dram_num = tegra_mc_get_emem_device_count(emc->mc); 558 559 /* disable dynamic self-refresh */ 560 if (emc->emc_cfg & EMC_CFG_DYN_SREF_ENABLE) { 561 emc->emc_cfg &= ~EMC_CFG_DYN_SREF_ENABLE; 562 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); 563 564 pre_wait = 5; 565 } 566 567 /* update MC arbiter settings */ 568 val = mc_readl(emc->mc, MC_EMEM_ARB_OUTSTANDING_REQ); 569 if (!(val & MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE) || 570 ((val & MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK) > 0x50)) { 571 572 val = MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE | 573 MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE | 0x50; 574 mc_writel(emc->mc, val, MC_EMEM_ARB_OUTSTANDING_REQ); 575 mc_writel(emc->mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL); 576 } 577 578 if (emc->mc_override & MC_EMEM_ARB_OVERRIDE_EACK_MASK) 579 mc_writel(emc->mc, 580 emc->mc_override & ~MC_EMEM_ARB_OVERRIDE_EACK_MASK, 581 MC_EMEM_ARB_OVERRIDE); 582 583 /* check DQ/DQS VREF delay */ 584 if (emc_dqs_preset(emc, timing, &schmitt_to_vref)) { 585 if (pre_wait < 3) 586 pre_wait = 3; 587 } 588 589 if (pre_wait) { 590 err = emc_seq_update_timing(emc); 591 if (err) 592 return err; 593 594 udelay(pre_wait); 595 } 596 597 /* disable auto-calibration if VREF mode is switching */ 598 if (timing->emc_auto_cal_interval) { 599 val = readl_relaxed(emc->regs + EMC_XM2COMPPADCTRL); 600 val ^= timing->data[74]; 601 602 if (val & EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE) { 603 writel_relaxed(0, emc->regs + EMC_AUTO_CAL_INTERVAL); 604 605 err = readl_relaxed_poll_timeout_atomic( 606 emc->regs + EMC_AUTO_CAL_STATUS, val, 607 !(val & EMC_AUTO_CAL_STATUS_ACTIVE), 1, 300); 608 if (err) { 609 dev_err(emc->dev, 610 "auto-cal finish timeout: %d\n", err); 611 return err; 612 } 613 614 emc->vref_cal_toggle = true; 615 } 616 } 617 618 /* program shadow registers */ 619 for (i = 0; i < ARRAY_SIZE(timing->data); i++) { 620 /* EMC_XM2CLKPADCTRL should be programmed separately */ 621 if (i != 73) 622 writel_relaxed(timing->data[i], 623 emc->regs + emc_timing_registers[i]); 624 } 625 626 err = tegra_mc_write_emem_configuration(emc->mc, timing->rate); 627 if (err) 628 return err; 629 630 /* DDR3: predict MRS long wait count */ 631 if (dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_ON) { 632 u32 cnt = 512; 633 634 if (emc->zcal_long) 635 cnt -= dram_num * 256; 636 637 val = timing->data[82] & EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK; 638 if (cnt < val) 639 cnt = val; 640 641 val = timing->data[82] & ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK; 642 val |= (cnt << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) & 643 EMC_MRS_WAIT_CNT_LONG_WAIT_MASK; 644 645 writel_relaxed(val, emc->regs + EMC_MRS_WAIT_CNT); 646 } 647 648 /* this read also completes the writes */ 649 val = readl_relaxed(emc->regs + EMC_SEL_DPD_CTRL); 650 651 if (!(val & EMC_SEL_DPD_CTRL_QUSE_DPD_ENABLE) && schmitt_to_vref) { 652 u32 cur_mode, new_mode; 653 654 cur_mode = fbio_cfg5 & EMC_CFG5_QUSE_MODE_MASK; 655 cur_mode >>= EMC_CFG5_QUSE_MODE_SHIFT; 656 657 new_mode = timing->data[39] & EMC_CFG5_QUSE_MODE_MASK; 658 new_mode >>= EMC_CFG5_QUSE_MODE_SHIFT; 659 660 if ((cur_mode != EMC_CFG5_QUSE_MODE_PULSE_INTERN && 661 cur_mode != EMC_CFG5_QUSE_MODE_INTERNAL_LPBK) || 662 (new_mode != EMC_CFG5_QUSE_MODE_PULSE_INTERN && 663 new_mode != EMC_CFG5_QUSE_MODE_INTERNAL_LPBK)) 664 qrst_used = true; 665 } 666 667 /* flow control marker 1 */ 668 writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE); 669 670 /* enable periodic reset */ 671 if (qrst_used) { 672 writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, 673 emc->regs + EMC_DBG); 674 writel_relaxed(emc->emc_cfg | EMC_CFG_PERIODIC_QRST, 675 emc->regs + EMC_CFG); 676 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); 677 } 678 679 /* disable auto-refresh to save time after clock change */ 680 writel_relaxed(EMC_REFCTRL_DISABLE_ALL(dram_num), 681 emc->regs + EMC_REFCTRL); 682 683 /* turn off DLL and enter self-refresh on DDR3 */ 684 if (dram_type == DRAM_TYPE_DDR3) { 685 if (dll_change == DLL_CHANGE_OFF) 686 writel_relaxed(timing->emc_mode_1, 687 emc->regs + EMC_EMRS); 688 689 writel_relaxed(DRAM_BROADCAST(dram_num) | 690 EMC_SELF_REF_CMD_ENABLED, 691 emc->regs + EMC_SELF_REF); 692 } 693 694 /* flow control marker 2 */ 695 writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_AFTER_CLKCHANGE); 696 697 /* enable write-active MUX, update unshadowed pad control */ 698 writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, emc->regs + EMC_DBG); 699 writel_relaxed(timing->data[73], emc->regs + EMC_XM2CLKPADCTRL); 700 701 /* restore periodic QRST and disable write-active MUX */ 702 val = !!(emc->emc_cfg & EMC_CFG_PERIODIC_QRST); 703 if (qrst_used || timing->emc_cfg_periodic_qrst != val) { 704 if (timing->emc_cfg_periodic_qrst) 705 emc->emc_cfg |= EMC_CFG_PERIODIC_QRST; 706 else 707 emc->emc_cfg &= ~EMC_CFG_PERIODIC_QRST; 708 709 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); 710 } 711 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); 712 713 /* exit self-refresh on DDR3 */ 714 if (dram_type == DRAM_TYPE_DDR3) 715 writel_relaxed(DRAM_BROADCAST(dram_num), 716 emc->regs + EMC_SELF_REF); 717 718 /* set DRAM-mode registers */ 719 if (dram_type == DRAM_TYPE_DDR3) { 720 if (timing->emc_mode_1 != emc->emc_mode_1) 721 writel_relaxed(timing->emc_mode_1, 722 emc->regs + EMC_EMRS); 723 724 if (timing->emc_mode_2 != emc->emc_mode_2) 725 writel_relaxed(timing->emc_mode_2, 726 emc->regs + EMC_EMRS); 727 728 if (timing->emc_mode_reset != emc->emc_mode_reset || 729 dll_change == DLL_CHANGE_ON) { 730 val = timing->emc_mode_reset; 731 if (dll_change == DLL_CHANGE_ON) { 732 val |= EMC_MODE_SET_DLL_RESET; 733 val |= EMC_MODE_SET_LONG_CNT; 734 } else { 735 val &= ~EMC_MODE_SET_DLL_RESET; 736 } 737 writel_relaxed(val, emc->regs + EMC_MRS); 738 } 739 } else { 740 if (timing->emc_mode_2 != emc->emc_mode_2) 741 writel_relaxed(timing->emc_mode_2, 742 emc->regs + EMC_MRW); 743 744 if (timing->emc_mode_1 != emc->emc_mode_1) 745 writel_relaxed(timing->emc_mode_1, 746 emc->regs + EMC_MRW); 747 } 748 749 emc->emc_mode_1 = timing->emc_mode_1; 750 emc->emc_mode_2 = timing->emc_mode_2; 751 emc->emc_mode_reset = timing->emc_mode_reset; 752 753 /* issue ZCAL command if turning ZCAL on */ 754 if (emc->zcal_long) { 755 writel_relaxed(EMC_ZQ_CAL_LONG_CMD_DEV0, 756 emc->regs + EMC_ZQ_CAL); 757 758 if (dram_num > 1) 759 writel_relaxed(EMC_ZQ_CAL_LONG_CMD_DEV1, 760 emc->regs + EMC_ZQ_CAL); 761 } 762 763 /* flow control marker 3 */ 764 writel_relaxed(0x1, emc->regs + EMC_UNSTALL_RW_AFTER_CLKCHANGE); 765 766 /* 767 * Read and discard an arbitrary MC register (Note: EMC registers 768 * can't be used) to ensure the register writes are completed. 769 */ 770 mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE); 771 772 return 0; 773 } 774 775 static int emc_complete_timing_change(struct tegra_emc *emc, 776 unsigned long rate) 777 { 778 struct emc_timing *timing = emc_find_timing(emc, rate); 779 unsigned int dram_num; 780 int err; 781 u32 v; 782 783 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v, 784 v & EMC_CLKCHANGE_COMPLETE_INT, 785 1, 100); 786 if (err) { 787 dev_err(emc->dev, "emc-car handshake timeout: %d\n", err); 788 return err; 789 } 790 791 /* re-enable auto-refresh */ 792 dram_num = tegra_mc_get_emem_device_count(emc->mc); 793 writel_relaxed(EMC_REFCTRL_ENABLE_ALL(dram_num), 794 emc->regs + EMC_REFCTRL); 795 796 /* restore auto-calibration */ 797 if (emc->vref_cal_toggle) 798 writel_relaxed(timing->emc_auto_cal_interval, 799 emc->regs + EMC_AUTO_CAL_INTERVAL); 800 801 /* restore dynamic self-refresh */ 802 if (timing->emc_cfg_dyn_self_ref) { 803 emc->emc_cfg |= EMC_CFG_DYN_SREF_ENABLE; 804 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); 805 } 806 807 /* set number of clocks to wait after each ZQ command */ 808 if (emc->zcal_long) 809 writel_relaxed(timing->emc_zcal_cnt_long, 810 emc->regs + EMC_ZCAL_WAIT_CNT); 811 812 /* wait for writes to settle */ 813 udelay(2); 814 815 /* update restored timing */ 816 err = emc_seq_update_timing(emc); 817 if (!err) 818 emc->bad_state = false; 819 820 /* restore early ACK */ 821 mc_writel(emc->mc, emc->mc_override, MC_EMEM_ARB_OVERRIDE); 822 823 return err; 824 } 825 826 static int emc_unprepare_timing_change(struct tegra_emc *emc, 827 unsigned long rate) 828 { 829 if (!emc->bad_state) { 830 /* shouldn't ever happen in practice */ 831 dev_err(emc->dev, "timing configuration can't be reverted\n"); 832 emc->bad_state = true; 833 } 834 835 return 0; 836 } 837 838 static int emc_clk_change_notify(struct notifier_block *nb, 839 unsigned long msg, void *data) 840 { 841 struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb); 842 struct clk_notifier_data *cnd = data; 843 int err; 844 845 switch (msg) { 846 case PRE_RATE_CHANGE: 847 /* 848 * Disable interrupt since read accesses are prohibited after 849 * stalling. 850 */ 851 disable_irq(emc->irq); 852 err = emc_prepare_timing_change(emc, cnd->new_rate); 853 enable_irq(emc->irq); 854 break; 855 856 case ABORT_RATE_CHANGE: 857 err = emc_unprepare_timing_change(emc, cnd->old_rate); 858 break; 859 860 case POST_RATE_CHANGE: 861 err = emc_complete_timing_change(emc, cnd->new_rate); 862 break; 863 864 default: 865 return NOTIFY_DONE; 866 } 867 868 return notifier_from_errno(err); 869 } 870 871 static int load_one_timing_from_dt(struct tegra_emc *emc, 872 struct emc_timing *timing, 873 struct device_node *node) 874 { 875 u32 value; 876 int err; 877 878 err = of_property_read_u32(node, "clock-frequency", &value); 879 if (err) { 880 dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n", 881 node, err); 882 return err; 883 } 884 885 timing->rate = value; 886 887 err = of_property_read_u32_array(node, "nvidia,emc-configuration", 888 timing->data, 889 ARRAY_SIZE(emc_timing_registers)); 890 if (err) { 891 dev_err(emc->dev, 892 "timing %pOF: failed to read emc timing data: %d\n", 893 node, err); 894 return err; 895 } 896 897 #define EMC_READ_BOOL(prop, dtprop) \ 898 timing->prop = of_property_read_bool(node, dtprop); 899 900 #define EMC_READ_U32(prop, dtprop) \ 901 err = of_property_read_u32(node, dtprop, &timing->prop); \ 902 if (err) { \ 903 dev_err(emc->dev, \ 904 "timing %pOFn: failed to read " #prop ": %d\n", \ 905 node, err); \ 906 return err; \ 907 } 908 909 EMC_READ_U32(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval") 910 EMC_READ_U32(emc_mode_1, "nvidia,emc-mode-1") 911 EMC_READ_U32(emc_mode_2, "nvidia,emc-mode-2") 912 EMC_READ_U32(emc_mode_reset, "nvidia,emc-mode-reset") 913 EMC_READ_U32(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long") 914 EMC_READ_BOOL(emc_cfg_dyn_self_ref, "nvidia,emc-cfg-dyn-self-ref") 915 EMC_READ_BOOL(emc_cfg_periodic_qrst, "nvidia,emc-cfg-periodic-qrst") 916 917 #undef EMC_READ_U32 918 #undef EMC_READ_BOOL 919 920 dev_dbg(emc->dev, "%s: %pOF: rate %lu\n", __func__, node, timing->rate); 921 922 return 0; 923 } 924 925 static int cmp_timings(const void *_a, const void *_b) 926 { 927 const struct emc_timing *a = _a; 928 const struct emc_timing *b = _b; 929 930 if (a->rate < b->rate) 931 return -1; 932 933 if (a->rate > b->rate) 934 return 1; 935 936 return 0; 937 } 938 939 static int emc_check_mc_timings(struct tegra_emc *emc) 940 { 941 struct tegra_mc *mc = emc->mc; 942 unsigned int i; 943 944 if (emc->num_timings != mc->num_timings) { 945 dev_err(emc->dev, "emc/mc timings number mismatch: %u %u\n", 946 emc->num_timings, mc->num_timings); 947 return -EINVAL; 948 } 949 950 for (i = 0; i < mc->num_timings; i++) { 951 if (emc->timings[i].rate != mc->timings[i].rate) { 952 dev_err(emc->dev, 953 "emc/mc timing rate mismatch: %lu %lu\n", 954 emc->timings[i].rate, mc->timings[i].rate); 955 return -EINVAL; 956 } 957 } 958 959 return 0; 960 } 961 962 static int emc_load_timings_from_dt(struct tegra_emc *emc, 963 struct device_node *node) 964 { 965 struct emc_timing *timing; 966 int child_count; 967 int err; 968 969 child_count = of_get_child_count(node); 970 if (!child_count) { 971 dev_err(emc->dev, "no memory timings in: %pOF\n", node); 972 return -EINVAL; 973 } 974 975 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), 976 GFP_KERNEL); 977 if (!emc->timings) 978 return -ENOMEM; 979 980 emc->num_timings = child_count; 981 timing = emc->timings; 982 983 for_each_child_of_node_scoped(node, child) { 984 err = load_one_timing_from_dt(emc, timing++, child); 985 if (err) 986 return err; 987 } 988 989 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, 990 NULL); 991 992 err = emc_check_mc_timings(emc); 993 if (err) 994 return err; 995 996 dev_info_once(emc->dev, 997 "got %u timings for RAM code %u (min %luMHz max %luMHz)\n", 998 emc->num_timings, 999 tegra_read_ram_code(), 1000 emc->timings[0].rate / 1000000, 1001 emc->timings[emc->num_timings - 1].rate / 1000000); 1002 1003 return 0; 1004 } 1005 1006 static struct device_node *emc_find_node_by_ram_code(struct tegra_emc *emc) 1007 { 1008 struct device *dev = emc->dev; 1009 struct device_node *np; 1010 u32 value, ram_code; 1011 int err; 1012 1013 if (emc->mrr_error) { 1014 dev_warn(dev, "memory timings skipped due to MRR error\n"); 1015 return NULL; 1016 } 1017 1018 if (of_get_child_count(dev->of_node) == 0) { 1019 dev_info_once(dev, "device-tree doesn't have memory timings\n"); 1020 return NULL; 1021 } 1022 1023 ram_code = tegra_read_ram_code(); 1024 1025 for_each_child_of_node(dev->of_node, np) { 1026 err = of_property_read_u32(np, "nvidia,ram-code", &value); 1027 if (err || value != ram_code) 1028 continue; 1029 1030 return np; 1031 } 1032 1033 dev_err(dev, "no memory timings for RAM code %u found in device-tree\n", 1034 ram_code); 1035 1036 return NULL; 1037 } 1038 1039 static int emc_read_lpddr_mode_register(struct tegra_emc *emc, 1040 unsigned int emem_dev, 1041 unsigned int register_addr, 1042 unsigned int *register_data) 1043 { 1044 u32 memory_dev = emem_dev ? 1 : 2; 1045 u32 val, mr_mask = 0xff; 1046 int err; 1047 1048 /* clear data-valid interrupt status */ 1049 writel_relaxed(EMC_MRR_DIVLD_INT, emc->regs + EMC_INTSTATUS); 1050 1051 /* issue mode register read request */ 1052 val = FIELD_PREP(EMC_MRR_DEV_SELECTN, memory_dev); 1053 val |= FIELD_PREP(EMC_MRR_MRR_MA, register_addr); 1054 1055 writel_relaxed(val, emc->regs + EMC_MRR); 1056 1057 /* wait for the LPDDR2 data-valid interrupt */ 1058 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, val, 1059 val & EMC_MRR_DIVLD_INT, 1060 1, 100); 1061 if (err) { 1062 dev_err(emc->dev, "mode register %u read failed: %d\n", 1063 register_addr, err); 1064 emc->mrr_error = true; 1065 return err; 1066 } 1067 1068 /* read out mode register data */ 1069 val = readl_relaxed(emc->regs + EMC_MRR); 1070 *register_data = FIELD_GET(EMC_MRR_MRR_DATA, val) & mr_mask; 1071 1072 return 0; 1073 } 1074 1075 static void emc_read_lpddr_sdram_info(struct tegra_emc *emc, 1076 unsigned int emem_dev) 1077 { 1078 union lpddr2_basic_config4 basic_conf4; 1079 unsigned int manufacturer_id; 1080 unsigned int revision_id1; 1081 unsigned int revision_id2; 1082 1083 /* these registers are standard for all LPDDR JEDEC memory chips */ 1084 emc_read_lpddr_mode_register(emc, emem_dev, 5, &manufacturer_id); 1085 emc_read_lpddr_mode_register(emc, emem_dev, 6, &revision_id1); 1086 emc_read_lpddr_mode_register(emc, emem_dev, 7, &revision_id2); 1087 emc_read_lpddr_mode_register(emc, emem_dev, 8, &basic_conf4.value); 1088 1089 dev_info(emc->dev, "SDRAM[dev%u]: manufacturer: 0x%x (%s) rev1: 0x%x rev2: 0x%x prefetch: S%u density: %uMbit iowidth: %ubit\n", 1090 emem_dev, manufacturer_id, 1091 lpddr2_jedec_manufacturer(manufacturer_id), 1092 revision_id1, revision_id2, 1093 4 >> basic_conf4.arch_type, 1094 64 << basic_conf4.density, 1095 32 >> basic_conf4.io_width); 1096 } 1097 1098 static int emc_setup_hw(struct tegra_emc *emc) 1099 { 1100 u32 fbio_cfg5, emc_cfg, emc_dbg, emc_adr_cfg; 1101 u32 intmask = EMC_REFRESH_OVERFLOW_INT; 1102 static bool print_sdram_info_once; 1103 enum emc_dram_type dram_type; 1104 const char *dram_type_str; 1105 unsigned int emem_numdev; 1106 1107 fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5); 1108 dram_type = fbio_cfg5 & EMC_FBIO_CFG5_DRAM_TYPE_MASK; 1109 1110 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); 1111 1112 /* enable EMC and CAR to handshake on PLL divider/source changes */ 1113 emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE; 1114 1115 /* configure clock change mode accordingly to DRAM type */ 1116 switch (dram_type) { 1117 case DRAM_TYPE_LPDDR2: 1118 emc_cfg |= EMC_CLKCHANGE_PD_ENABLE; 1119 emc_cfg &= ~EMC_CLKCHANGE_SR_ENABLE; 1120 break; 1121 1122 default: 1123 emc_cfg &= ~EMC_CLKCHANGE_SR_ENABLE; 1124 emc_cfg &= ~EMC_CLKCHANGE_PD_ENABLE; 1125 break; 1126 } 1127 1128 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); 1129 1130 /* initialize interrupt */ 1131 writel_relaxed(intmask, emc->regs + EMC_INTMASK); 1132 writel_relaxed(0xffffffff, emc->regs + EMC_INTSTATUS); 1133 1134 /* ensure that unwanted debug features are disabled */ 1135 emc_dbg = readl_relaxed(emc->regs + EMC_DBG); 1136 emc_dbg |= EMC_DBG_CFG_PRIORITY; 1137 emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY; 1138 emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE; 1139 emc_dbg &= ~EMC_DBG_FORCE_UPDATE; 1140 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); 1141 1142 switch (dram_type) { 1143 case DRAM_TYPE_DDR1: 1144 dram_type_str = "DDR1"; 1145 break; 1146 case DRAM_TYPE_LPDDR2: 1147 dram_type_str = "LPDDR2"; 1148 break; 1149 case DRAM_TYPE_DDR2: 1150 dram_type_str = "DDR2"; 1151 break; 1152 case DRAM_TYPE_DDR3: 1153 dram_type_str = "DDR3"; 1154 break; 1155 } 1156 1157 emc_adr_cfg = readl_relaxed(emc->regs + EMC_ADR_CFG); 1158 emem_numdev = FIELD_GET(EMC_ADR_CFG_EMEM_NUMDEV, emc_adr_cfg) + 1; 1159 1160 dev_info_once(emc->dev, "%u %s %s attached\n", emem_numdev, 1161 dram_type_str, emem_numdev == 2 ? "devices" : "device"); 1162 1163 if (dram_type == DRAM_TYPE_LPDDR2 && !print_sdram_info_once) { 1164 while (emem_numdev--) 1165 emc_read_lpddr_sdram_info(emc, emem_numdev); 1166 1167 print_sdram_info_once = true; 1168 } 1169 1170 return 0; 1171 } 1172 1173 static long emc_round_rate(unsigned long rate, 1174 unsigned long min_rate, 1175 unsigned long max_rate, 1176 void *arg) 1177 { 1178 struct emc_timing *timing = NULL; 1179 struct tegra_emc *emc = arg; 1180 unsigned int i; 1181 1182 if (!emc->num_timings) 1183 return clk_get_rate(emc->clk); 1184 1185 min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate); 1186 1187 for (i = 0; i < emc->num_timings; i++) { 1188 if (emc->timings[i].rate < rate && i != emc->num_timings - 1) 1189 continue; 1190 1191 if (emc->timings[i].rate > max_rate) { 1192 i = max(i, 1u) - 1; 1193 1194 if (emc->timings[i].rate < min_rate) 1195 break; 1196 } 1197 1198 if (emc->timings[i].rate < min_rate) 1199 continue; 1200 1201 timing = &emc->timings[i]; 1202 break; 1203 } 1204 1205 if (!timing) { 1206 dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n", 1207 rate, min_rate, max_rate); 1208 return -EINVAL; 1209 } 1210 1211 return timing->rate; 1212 } 1213 1214 /* 1215 * debugfs interface 1216 * 1217 * The memory controller driver exposes some files in debugfs that can be used 1218 * to control the EMC frequency. The top-level directory can be found here: 1219 * 1220 * /sys/kernel/debug/emc 1221 * 1222 * It contains the following files: 1223 * 1224 * - available_rates: This file contains a list of valid, space-separated 1225 * EMC frequencies. 1226 * 1227 * - min_rate: Writing a value to this file sets the given frequency as the 1228 * floor of the permitted range. If this is higher than the currently 1229 * configured EMC frequency, this will cause the frequency to be 1230 * increased so that it stays within the valid range. 1231 * 1232 * - max_rate: Similarily to the min_rate file, writing a value to this file 1233 * sets the given frequency as the ceiling of the permitted range. If 1234 * the value is lower than the currently configured EMC frequency, this 1235 * will cause the frequency to be decreased so that it stays within the 1236 * valid range. 1237 */ 1238 1239 static bool tegra30_emc_validate_rate(struct tegra_emc *emc, unsigned long rate) 1240 { 1241 unsigned int i; 1242 1243 for (i = 0; i < emc->num_timings; i++) 1244 if (rate == emc->timings[i].rate) 1245 return true; 1246 1247 return false; 1248 } 1249 1250 static int tegra30_emc_debug_available_rates_show(struct seq_file *s, void *data) 1251 { 1252 struct tegra_emc *emc = s->private; 1253 const char *prefix = ""; 1254 unsigned int i; 1255 1256 for (i = 0; i < emc->num_timings; i++) { 1257 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate); 1258 prefix = " "; 1259 } 1260 1261 seq_puts(s, "\n"); 1262 1263 return 0; 1264 } 1265 DEFINE_SHOW_ATTRIBUTE(tegra30_emc_debug_available_rates); 1266 1267 static int tegra30_emc_debug_min_rate_get(void *data, u64 *rate) 1268 { 1269 struct tegra_emc *emc = data; 1270 1271 *rate = emc->debugfs.min_rate; 1272 1273 return 0; 1274 } 1275 1276 static int tegra30_emc_debug_min_rate_set(void *data, u64 rate) 1277 { 1278 struct tegra_emc *emc = data; 1279 int err; 1280 1281 if (!tegra30_emc_validate_rate(emc, rate)) 1282 return -EINVAL; 1283 1284 err = tegra_emc_set_min_rate(&emc->reqs, rate, TEGRA_EMC_RATE_DEBUG); 1285 if (err < 0) 1286 return err; 1287 1288 emc->debugfs.min_rate = rate; 1289 1290 return 0; 1291 } 1292 1293 DEFINE_DEBUGFS_ATTRIBUTE(tegra30_emc_debug_min_rate_fops, 1294 tegra30_emc_debug_min_rate_get, 1295 tegra30_emc_debug_min_rate_set, "%llu\n"); 1296 1297 static int tegra30_emc_debug_max_rate_get(void *data, u64 *rate) 1298 { 1299 struct tegra_emc *emc = data; 1300 1301 *rate = emc->debugfs.max_rate; 1302 1303 return 0; 1304 } 1305 1306 static int tegra30_emc_debug_max_rate_set(void *data, u64 rate) 1307 { 1308 struct tegra_emc *emc = data; 1309 int err; 1310 1311 if (!tegra30_emc_validate_rate(emc, rate)) 1312 return -EINVAL; 1313 1314 err = tegra_emc_set_max_rate(&emc->reqs, rate, TEGRA_EMC_RATE_DEBUG); 1315 if (err < 0) 1316 return err; 1317 1318 emc->debugfs.max_rate = rate; 1319 1320 return 0; 1321 } 1322 1323 DEFINE_DEBUGFS_ATTRIBUTE(tegra30_emc_debug_max_rate_fops, 1324 tegra30_emc_debug_max_rate_get, 1325 tegra30_emc_debug_max_rate_set, "%llu\n"); 1326 1327 static void tegra30_emc_debugfs_init(struct tegra_emc *emc) 1328 { 1329 struct device *dev = emc->dev; 1330 unsigned int i; 1331 int err; 1332 1333 emc->debugfs.min_rate = ULONG_MAX; 1334 emc->debugfs.max_rate = 0; 1335 1336 for (i = 0; i < emc->num_timings; i++) { 1337 if (emc->timings[i].rate < emc->debugfs.min_rate) 1338 emc->debugfs.min_rate = emc->timings[i].rate; 1339 1340 if (emc->timings[i].rate > emc->debugfs.max_rate) 1341 emc->debugfs.max_rate = emc->timings[i].rate; 1342 } 1343 1344 if (!emc->num_timings) { 1345 emc->debugfs.min_rate = clk_get_rate(emc->clk); 1346 emc->debugfs.max_rate = emc->debugfs.min_rate; 1347 } 1348 1349 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, 1350 emc->debugfs.max_rate); 1351 if (err < 0) { 1352 dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n", 1353 emc->debugfs.min_rate, emc->debugfs.max_rate, 1354 emc->clk); 1355 } 1356 1357 emc->debugfs.root = debugfs_create_dir("emc", NULL); 1358 1359 debugfs_create_file("available_rates", 0444, emc->debugfs.root, 1360 emc, &tegra30_emc_debug_available_rates_fops); 1361 debugfs_create_file("min_rate", 0644, emc->debugfs.root, 1362 emc, &tegra30_emc_debug_min_rate_fops); 1363 debugfs_create_file("max_rate", 0644, emc->debugfs.root, 1364 emc, &tegra30_emc_debug_max_rate_fops); 1365 } 1366 1367 static inline struct tegra_emc * 1368 to_tegra_emc_provider(struct icc_provider *provider) 1369 { 1370 return container_of(provider, struct tegra_emc, provider); 1371 } 1372 1373 static struct icc_node_data * 1374 emc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data) 1375 { 1376 struct icc_provider *provider = data; 1377 struct icc_node_data *ndata; 1378 struct icc_node *node; 1379 1380 /* External Memory is the only possible ICC route */ 1381 list_for_each_entry(node, &provider->nodes, node_list) { 1382 if (node->id != TEGRA_ICC_EMEM) 1383 continue; 1384 1385 ndata = kzalloc_obj(*ndata); 1386 if (!ndata) 1387 return ERR_PTR(-ENOMEM); 1388 1389 /* 1390 * SRC and DST nodes should have matching TAG in order to have 1391 * it set by default for a requested path. 1392 */ 1393 ndata->tag = TEGRA_MC_ICC_TAG_ISO; 1394 ndata->node = node; 1395 1396 return ndata; 1397 } 1398 1399 return ERR_PTR(-EPROBE_DEFER); 1400 } 1401 1402 static int emc_icc_set(struct icc_node *src, struct icc_node *dst) 1403 { 1404 struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); 1405 unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw); 1406 unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw); 1407 unsigned long long rate = max(avg_bw, peak_bw); 1408 const unsigned int dram_data_bus_width_bytes = 4; 1409 const unsigned int ddr = 2; 1410 int err; 1411 1412 /* 1413 * Tegra30 EMC runs on a clock rate of SDRAM bus. This means that 1414 * EMC clock rate is twice smaller than the peak data rate because 1415 * data is sampled on both EMC clock edges. 1416 */ 1417 do_div(rate, ddr * dram_data_bus_width_bytes); 1418 rate = min_t(u64, rate, U32_MAX); 1419 1420 err = tegra_emc_set_min_rate(&emc->reqs, rate, TEGRA_EMC_RATE_ICC); 1421 if (err) 1422 return err; 1423 1424 return 0; 1425 } 1426 1427 static int tegra30_emc_interconnect_init(struct tegra_emc *emc) 1428 { 1429 const struct tegra_mc_soc *soc = emc->mc->soc; 1430 struct icc_node *node; 1431 int err; 1432 1433 emc->provider.dev = emc->dev; 1434 emc->provider.set = emc_icc_set; 1435 emc->provider.data = &emc->provider; 1436 emc->provider.aggregate = soc->icc_ops->aggregate; 1437 emc->provider.xlate_extended = emc_of_icc_xlate_extended; 1438 1439 icc_provider_init(&emc->provider); 1440 1441 /* create External Memory Controller node */ 1442 node = icc_node_create(TEGRA_ICC_EMC); 1443 if (IS_ERR(node)) 1444 return PTR_ERR(node); 1445 1446 node->name = "External Memory Controller"; 1447 icc_node_add(node, &emc->provider); 1448 1449 /* link External Memory Controller to External Memory (DRAM) */ 1450 err = icc_link_create(node, TEGRA_ICC_EMEM); 1451 if (err) 1452 goto remove_nodes; 1453 1454 /* create External Memory node */ 1455 node = icc_node_create(TEGRA_ICC_EMEM); 1456 if (IS_ERR(node)) { 1457 err = PTR_ERR(node); 1458 goto remove_nodes; 1459 } 1460 1461 node->name = "External Memory (DRAM)"; 1462 icc_node_add(node, &emc->provider); 1463 1464 err = icc_provider_register(&emc->provider); 1465 if (err) 1466 goto remove_nodes; 1467 1468 return 0; 1469 1470 remove_nodes: 1471 icc_nodes_remove(&emc->provider); 1472 1473 return dev_err_probe(emc->dev, err, "failed to initialize ICC\n"); 1474 } 1475 1476 static void devm_tegra30_emc_unset_callback(void *data) 1477 { 1478 tegra20_clk_set_emc_round_callback(NULL, NULL); 1479 } 1480 1481 static void devm_tegra30_emc_unreg_clk_notifier(void *data) 1482 { 1483 struct tegra_emc *emc = data; 1484 1485 clk_notifier_unregister(emc->clk, &emc->clk_nb); 1486 } 1487 1488 static int tegra30_emc_init_clk(struct tegra_emc *emc) 1489 { 1490 int err; 1491 1492 tegra20_clk_set_emc_round_callback(emc_round_rate, emc); 1493 1494 err = devm_add_action_or_reset(emc->dev, devm_tegra30_emc_unset_callback, 1495 NULL); 1496 if (err) 1497 return err; 1498 1499 emc->clk = devm_clk_get(emc->dev, NULL); 1500 if (IS_ERR(emc->clk)) 1501 return dev_err_probe(emc->dev, PTR_ERR(emc->clk), 1502 "failed to get EMC clock\n"); 1503 1504 err = clk_notifier_register(emc->clk, &emc->clk_nb); 1505 if (err) 1506 return dev_err_probe(emc->dev, err, "failed to register clk notifier\n"); 1507 1508 err = devm_add_action_or_reset(emc->dev, 1509 devm_tegra30_emc_unreg_clk_notifier, emc); 1510 if (err) 1511 return err; 1512 1513 return 0; 1514 } 1515 1516 static int tegra30_emc_probe(struct platform_device *pdev) 1517 { 1518 struct tegra_core_opp_params opp_params = {}; 1519 struct device_node *np; 1520 struct tegra_emc *emc; 1521 int err; 1522 1523 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); 1524 if (!emc) 1525 return -ENOMEM; 1526 1527 emc->mc = devm_tegra_memory_controller_get(&pdev->dev); 1528 if (IS_ERR(emc->mc)) 1529 return PTR_ERR(emc->mc); 1530 1531 emc->clk_nb.notifier_call = emc_clk_change_notify; 1532 emc->dev = &pdev->dev; 1533 1534 emc->regs = devm_platform_ioremap_resource(pdev, 0); 1535 if (IS_ERR(emc->regs)) 1536 return PTR_ERR(emc->regs); 1537 1538 err = emc_setup_hw(emc); 1539 if (err) 1540 return err; 1541 1542 np = emc_find_node_by_ram_code(emc); 1543 if (np) { 1544 err = emc_load_timings_from_dt(emc, np); 1545 of_node_put(np); 1546 if (err) 1547 return err; 1548 } 1549 1550 err = platform_get_irq(pdev, 0); 1551 if (err < 0) 1552 return err; 1553 1554 emc->irq = err; 1555 1556 err = devm_request_irq(&pdev->dev, emc->irq, tegra30_emc_isr, 0, 1557 dev_name(&pdev->dev), emc); 1558 if (err) 1559 return dev_err_probe(&pdev->dev, err, "failed to request irq\n"); 1560 1561 err = tegra30_emc_init_clk(emc); 1562 if (err) 1563 return err; 1564 1565 opp_params.init_state = true; 1566 1567 err = devm_tegra_core_dev_init_opp_table(&pdev->dev, &opp_params); 1568 if (err) 1569 return err; 1570 1571 platform_set_drvdata(pdev, emc); 1572 tegra_emc_rate_requests_init(&emc->reqs, &pdev->dev); 1573 tegra30_emc_debugfs_init(emc); 1574 tegra30_emc_interconnect_init(emc); 1575 1576 /* 1577 * Don't allow the kernel module to be unloaded. Unloading adds some 1578 * extra complexity which doesn't really worth the effort in a case of 1579 * this driver. 1580 */ 1581 try_module_get(THIS_MODULE); 1582 1583 return 0; 1584 } 1585 1586 static int tegra30_emc_suspend(struct device *dev) 1587 { 1588 struct tegra_emc *emc = dev_get_drvdata(dev); 1589 int err; 1590 1591 /* take exclusive control over the clock's rate */ 1592 err = clk_rate_exclusive_get(emc->clk); 1593 if (err) { 1594 dev_err(emc->dev, "failed to acquire clk: %d\n", err); 1595 return err; 1596 } 1597 1598 /* suspending in a bad state will hang machine */ 1599 if (WARN(emc->bad_state, "hardware in a bad state\n")) 1600 return -EINVAL; 1601 1602 emc->bad_state = true; 1603 1604 return 0; 1605 } 1606 1607 static int tegra30_emc_resume(struct device *dev) 1608 { 1609 struct tegra_emc *emc = dev_get_drvdata(dev); 1610 1611 emc_setup_hw(emc); 1612 emc->bad_state = false; 1613 1614 clk_rate_exclusive_put(emc->clk); 1615 1616 return 0; 1617 } 1618 1619 static const struct dev_pm_ops tegra30_emc_pm_ops = { 1620 .suspend = tegra30_emc_suspend, 1621 .resume = tegra30_emc_resume, 1622 }; 1623 1624 static const struct of_device_id tegra30_emc_of_match[] = { 1625 { .compatible = "nvidia,tegra30-emc", }, 1626 {}, 1627 }; 1628 MODULE_DEVICE_TABLE(of, tegra30_emc_of_match); 1629 1630 static struct platform_driver tegra30_emc_driver = { 1631 .probe = tegra30_emc_probe, 1632 .driver = { 1633 .name = "tegra30-emc", 1634 .of_match_table = tegra30_emc_of_match, 1635 .pm = &tegra30_emc_pm_ops, 1636 .suppress_bind_attrs = true, 1637 .sync_state = icc_sync_state, 1638 }, 1639 }; 1640 module_platform_driver(tegra30_emc_driver); 1641 1642 MODULE_AUTHOR("Dmitry Osipenko <digetx@gmail.com>"); 1643 MODULE_DESCRIPTION("NVIDIA Tegra30 EMC driver"); 1644 MODULE_LICENSE("GPL v2"); 1645