1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2025-2026, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <dt-bindings/memory/nvidia,tegra264.h> 7 8 #include <linux/interconnect.h> 9 #include <linux/of_device.h> 10 #include <linux/tegra-icc.h> 11 12 #include <soc/tegra/bpmp.h> 13 #include <soc/tegra/mc.h> 14 15 #include "mc.h" 16 #include "tegra264-bwmgr.h" 17 18 /* 19 * MC Client entries are sorted in the increasing order of the 20 * override and security register offsets. 21 */ 22 static const struct tegra_mc_client tegra264_mc_clients[] = { 23 { 24 .id = TEGRA264_MEMORY_CLIENT_HDAR, 25 .name = "hdar", 26 .bpmp_id = TEGRA264_BWMGR_HDA, 27 .type = TEGRA_ICC_ISO_AUDIO, 28 }, { 29 .id = TEGRA264_MEMORY_CLIENT_HDAW, 30 .name = "hdaw", 31 .bpmp_id = TEGRA264_BWMGR_HDA, 32 .type = TEGRA_ICC_ISO_AUDIO, 33 }, { 34 .id = TEGRA264_MEMORY_CLIENT_MGBE0R, 35 .name = "mgbe0r", 36 .bpmp_id = TEGRA264_BWMGR_EQOS, 37 .type = TEGRA_ICC_NISO, 38 }, { 39 .id = TEGRA264_MEMORY_CLIENT_MGBE0W, 40 .name = "mgbe0w", 41 .bpmp_id = TEGRA264_BWMGR_EQOS, 42 .type = TEGRA_ICC_NISO, 43 }, { 44 .id = TEGRA264_MEMORY_CLIENT_MGBE1R, 45 .name = "mgbe1r", 46 .bpmp_id = TEGRA264_BWMGR_EQOS, 47 .type = TEGRA_ICC_NISO, 48 }, { 49 .id = TEGRA264_MEMORY_CLIENT_MGBE1W, 50 .name = "mgbe1w", 51 .bpmp_id = TEGRA264_BWMGR_EQOS, 52 .type = TEGRA_ICC_NISO, 53 }, { 54 .id = TEGRA264_MEMORY_CLIENT_SDMMC0R, 55 .name = "sdmmc0r", 56 .bpmp_id = TEGRA264_BWMGR_SDMMC_1, 57 .type = TEGRA_ICC_NISO, 58 }, { 59 .id = TEGRA264_MEMORY_CLIENT_SDMMC0W, 60 .name = "sdmmc0w", 61 .bpmp_id = TEGRA264_BWMGR_SDMMC_1, 62 .type = TEGRA_ICC_NISO, 63 }, { 64 .id = TEGRA264_MEMORY_CLIENT_VICR, 65 .name = "vicr", 66 .bpmp_id = TEGRA264_BWMGR_VIC, 67 .type = TEGRA_ICC_NISO, 68 }, { 69 .id = TEGRA264_MEMORY_CLIENT_VICW, 70 .name = "vicw", 71 .bpmp_id = TEGRA264_BWMGR_VIC, 72 .type = TEGRA_ICC_NISO, 73 }, { 74 .id = TEGRA264_MEMORY_CLIENT_APER, 75 .name = "aper", 76 .bpmp_id = TEGRA264_BWMGR_APE, 77 .type = TEGRA_ICC_ISO_AUDIO, 78 }, { 79 .id = TEGRA264_MEMORY_CLIENT_APEW, 80 .name = "apew", 81 .bpmp_id = TEGRA264_BWMGR_APE, 82 .type = TEGRA_ICC_ISO_AUDIO, 83 }, { 84 .id = TEGRA264_MEMORY_CLIENT_APEDMAR, 85 .name = "apedmar", 86 .bpmp_id = TEGRA264_BWMGR_APEDMA, 87 .type = TEGRA_ICC_ISO_AUDIO, 88 }, { 89 .id = TEGRA264_MEMORY_CLIENT_APEDMAW, 90 .name = "apedmaw", 91 .bpmp_id = TEGRA264_BWMGR_APEDMA, 92 .type = TEGRA_ICC_ISO_AUDIO, 93 }, { 94 .id = TEGRA264_MEMORY_CLIENT_VIFALCONR, 95 .name = "vifalconr", 96 .bpmp_id = TEGRA264_BWMGR_VIFAL, 97 .type = TEGRA_ICC_ISO_VIFAL, 98 }, { 99 .id = TEGRA264_MEMORY_CLIENT_VIFALCONW, 100 .name = "vifalconw", 101 .bpmp_id = TEGRA264_BWMGR_VIFAL, 102 .type = TEGRA_ICC_ISO_VIFAL, 103 }, { 104 .id = TEGRA264_MEMORY_CLIENT_RCER, 105 .name = "rcer", 106 .bpmp_id = TEGRA264_BWMGR_RCE, 107 .type = TEGRA_ICC_NISO, 108 }, { 109 .id = TEGRA264_MEMORY_CLIENT_RCEW, 110 .name = "rcew", 111 .bpmp_id = TEGRA264_BWMGR_RCE, 112 .type = TEGRA_ICC_NISO, 113 }, { 114 .id = TEGRA264_MEMORY_CLIENT_PCIE0W, 115 .name = "pcie0w", 116 .bpmp_id = TEGRA264_BWMGR_PCIE_0, 117 .type = TEGRA_ICC_NISO, 118 }, { 119 .id = TEGRA264_MEMORY_CLIENT_PCIE1R, 120 .name = "pcie1r", 121 .bpmp_id = TEGRA264_BWMGR_PCIE_1, 122 .type = TEGRA_ICC_NISO, 123 }, { 124 .id = TEGRA264_MEMORY_CLIENT_PCIE1W, 125 .name = "pcie1w", 126 .bpmp_id = TEGRA264_BWMGR_PCIE_1, 127 .type = TEGRA_ICC_NISO, 128 }, { 129 .id = TEGRA264_MEMORY_CLIENT_PCIE2AR, 130 .name = "pcie2ar", 131 .bpmp_id = TEGRA264_BWMGR_PCIE_2, 132 .type = TEGRA_ICC_NISO, 133 }, { 134 .id = TEGRA264_MEMORY_CLIENT_PCIE2AW, 135 .name = "pcie2aw", 136 .bpmp_id = TEGRA264_BWMGR_PCIE_2, 137 .type = TEGRA_ICC_NISO, 138 }, { 139 .id = TEGRA264_MEMORY_CLIENT_PCIE3R, 140 .name = "pcie3r", 141 .bpmp_id = TEGRA264_BWMGR_PCIE_3, 142 .type = TEGRA_ICC_NISO, 143 }, { 144 .id = TEGRA264_MEMORY_CLIENT_PCIE3W, 145 .name = "pcie3w", 146 .bpmp_id = TEGRA264_BWMGR_PCIE_3, 147 .type = TEGRA_ICC_NISO, 148 }, { 149 .id = TEGRA264_MEMORY_CLIENT_PCIE4R, 150 .name = "pcie4r", 151 .bpmp_id = TEGRA264_BWMGR_PCIE_4, 152 .type = TEGRA_ICC_NISO, 153 }, { 154 .id = TEGRA264_MEMORY_CLIENT_PCIE4W, 155 .name = "pcie4w", 156 .bpmp_id = TEGRA264_BWMGR_PCIE_4, 157 .type = TEGRA_ICC_NISO, 158 }, { 159 .id = TEGRA264_MEMORY_CLIENT_PCIE5R, 160 .name = "pcie5r", 161 .bpmp_id = TEGRA264_BWMGR_PCIE_5, 162 .type = TEGRA_ICC_NISO, 163 }, { 164 .id = TEGRA264_MEMORY_CLIENT_PCIE5W, 165 .name = "pcie5w", 166 .bpmp_id = TEGRA264_BWMGR_PCIE_5, 167 .type = TEGRA_ICC_NISO, 168 }, { 169 .id = TEGRA264_MEMORY_CLIENT_GPUR02MC, 170 .name = "gpur02mc", 171 .bpmp_id = TEGRA264_BWMGR_GPU, 172 .type = TEGRA_ICC_NISO, 173 }, { 174 .id = TEGRA264_MEMORY_CLIENT_GPUW02MC, 175 .name = "gpuw02mc", 176 .bpmp_id = TEGRA264_BWMGR_GPU, 177 .type = TEGRA_ICC_NISO, 178 }, { 179 .id = TEGRA264_MEMORY_CLIENT_NVDECSRD2MC, 180 .name = "nvdecsrd2mc", 181 .bpmp_id = TEGRA264_BWMGR_NVDEC, 182 .type = TEGRA_ICC_NISO, 183 }, { 184 .id = TEGRA264_MEMORY_CLIENT_NVDECSWR2MC, 185 .name = "nvdecswr2mc", 186 .bpmp_id = TEGRA264_BWMGR_NVDEC, 187 .type = TEGRA_ICC_NISO, 188 }, 189 }; 190 191 static const char *const tegra264_hub_error_names[32] = { 192 [0] = "coalescer error", 193 [1] = "SMMU BYPASS ALLOW error", 194 [2] = "Illegal tbugrp_id error", 195 [3] = "Malformed MSI request error", 196 [4] = "Read response with poison bit error", 197 [5] = "Restricted access violation error", 198 [6] = "Reserved PA error", 199 }; 200 201 static const char *const tegra264_mc_error_names[4] = { 202 [1] = "EMEM decode error", 203 [2] = "TrustZone violation", 204 [3] = "Carveout violation", 205 }; 206 207 static const char *const tegra264_rt_error_names[16] = { 208 [1] = "DECERR_PARTIAL_POPULATED", 209 [2] = "DECERR_SMMU_BYPASS", 210 [3] = "DECERR_INVALID_MMIO", 211 [4] = "DECERR_INVALID_GIC_MSI", 212 [5] = "DECERR_ATOMIC_SYSRAM", 213 [9] = "DECERR_REMOTE_REQ_PRE_BOOT", 214 [10] = "DECERR_ISO_OVER_C2C", 215 [11] = "DECERR_UNSUPPORTED_SBS_OPCODE", 216 [12] = "DECERR_SBS_REQ_OVER_SISO_LL", 217 }; 218 219 /* 220 * MC instance aperture mapping for hubc registers 221 */ 222 static const int mc_hubc_aperture_number[5] = { 223 7, 8, 9, 10, 11 224 }; 225 226 /* 227 * tegra264_mc_icc_set() - Pass MC client info to the BPMP-FW 228 * @src: ICC node for Memory Controller's (MC) Client 229 * @dst: ICC node for Memory Controller (MC) 230 * 231 * Passing the current request info from the MC to the BPMP-FW where 232 * LA and PTSA registers are accessed and the final EMC freq is set 233 * based on client_id, type, latency and bandwidth. 234 * icc_set_bw() makes set_bw calls for both MC and EMC providers in 235 * sequence. Both the calls are protected by 'mutex_lock(&icc_lock)'. 236 * So, the data passed won't be updated by concurrent set calls from 237 * other clients. 238 */ 239 static int tegra264_mc_icc_set(struct icc_node *src, struct icc_node *dst) 240 { 241 struct tegra_mc *mc = icc_provider_to_tegra_mc(dst->provider); 242 struct mrq_bwmgr_int_request bwmgr_req = { 0 }; 243 struct mrq_bwmgr_int_response bwmgr_resp = { 0 }; 244 const struct tegra_mc_client *pclient = src->data; 245 struct tegra_bpmp_message msg; 246 int ret; 247 248 /* 249 * Same Src and Dst node will happen during boot from icc_node_add(). 250 * This can be used to pre-initialize and set bandwidth for all clients 251 * before their drivers are loaded. We are skipping this case as for us, 252 * the pre-initialization already happened in Bootloader(MB2) and BPMP-FW. 253 */ 254 if (src->id == dst->id) 255 return 0; 256 257 if (!mc->bwmgr_mrq_supported) 258 return 0; 259 260 if (!mc->bpmp) { 261 dev_err(mc->dev, "BPMP reference NULL\n"); 262 return -ENOENT; 263 } 264 265 if (pclient->type == TEGRA_ICC_NISO) 266 bwmgr_req.bwmgr_calc_set_req.niso_bw = src->avg_bw; 267 else 268 bwmgr_req.bwmgr_calc_set_req.iso_bw = src->avg_bw; 269 270 bwmgr_req.bwmgr_calc_set_req.client_id = pclient->bpmp_id; 271 272 bwmgr_req.cmd = CMD_BWMGR_INT_CALC_AND_SET; 273 bwmgr_req.bwmgr_calc_set_req.mc_floor = src->peak_bw; 274 bwmgr_req.bwmgr_calc_set_req.floor_unit = BWMGR_INT_UNIT_KBPS; 275 276 memset(&msg, 0, sizeof(msg)); 277 msg.mrq = MRQ_BWMGR_INT; 278 msg.tx.data = &bwmgr_req; 279 msg.tx.size = sizeof(bwmgr_req); 280 msg.rx.data = &bwmgr_resp; 281 msg.rx.size = sizeof(bwmgr_resp); 282 283 ret = tegra_bpmp_transfer(mc->bpmp, &msg); 284 if (ret < 0) { 285 dev_err(mc->dev, "BPMP transfer failed: %d\n", ret); 286 goto error; 287 } 288 if (msg.rx.ret < 0) { 289 pr_err("failed to set bandwidth for %u: %d\n", 290 bwmgr_req.bwmgr_calc_set_req.client_id, msg.rx.ret); 291 ret = -EINVAL; 292 } 293 294 error: 295 return ret; 296 } 297 298 static int tegra264_mc_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, 299 u32 peak_bw, u32 *agg_avg, u32 *agg_peak) 300 { 301 struct icc_provider *p = node->provider; 302 struct tegra_mc *mc = icc_provider_to_tegra_mc(p); 303 304 if (!mc->bwmgr_mrq_supported) 305 return 0; 306 307 *agg_avg += avg_bw; 308 *agg_peak = max(*agg_peak, peak_bw); 309 310 return 0; 311 } 312 313 static int tegra264_mc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *peak) 314 { 315 *avg = 0; 316 *peak = 0; 317 318 return 0; 319 } 320 321 static void mcf_log_fault(struct tegra_mc *mc, u32 channel, unsigned long mcf_ch_intstatus) 322 { 323 unsigned int bit; 324 325 for_each_set_bit(bit, &mcf_ch_intstatus, 32) { 326 const char *client = "unknown", *desc = "NA"; 327 u32 status_reg, status1_reg = 0, addr_reg, addr_hi_reg = 0, err_type_mask = 0; 328 u32 value, client_id, i, addr_hi_shift = 0, addr_hi_mask = 0, status1; 329 u32 mc_rw_bit = MC_ERR_STATUS_RW, mc_sec_bit = MC_ERR_STATUS_SECURITY; 330 phys_addr_t addr = 0; 331 u8 type; 332 333 switch (BIT(bit)) { 334 case MC_INT_DECERR_EMEM: 335 case MC_INT_SECURITY_VIOLATION: 336 status_reg = mc->soc->regs->err_status; 337 addr_reg = mc->soc->regs->err_add; 338 addr_hi_reg = mc->soc->regs->err_add_hi; 339 err_type_mask = mc->soc->mc_err_status_type_mask; 340 break; 341 342 case MC_INT_DECERR_VPR: 343 status_reg = mc->soc->regs->err_vpr_status; 344 addr_reg = mc->soc->regs->err_vpr_add; 345 addr_hi_shift = MC_ERR_STATUS_ADR_HI_SHIFT; 346 addr_hi_mask = mc->soc->mc_addr_hi_mask; 347 break; 348 349 case MC_INT_SECERR_SEC: 350 status_reg = mc->soc->regs->err_sec_status; 351 addr_reg = mc->soc->regs->err_sec_add; 352 addr_hi_shift = MC_ERR_STATUS_ADR_HI_SHIFT; 353 addr_hi_mask = mc->soc->mc_addr_hi_mask; 354 break; 355 356 case MC_INT_DECERR_MTS: 357 status_reg = mc->soc->regs->err_mts_status; 358 addr_reg = mc->soc->regs->err_mts_add; 359 addr_hi_shift = MC_ERR_STATUS_ADR_HI_SHIFT; 360 addr_hi_mask = mc->soc->mc_addr_hi_mask; 361 break; 362 363 case MC_INT_DECERR_GENERALIZED_CARVEOUT: 364 status_reg = mc->soc->regs->err_gen_co_status; 365 status1_reg = MC_ERR_GENERALIZED_CARVEOUT_STATUS_1_0; 366 addr_reg = mc->soc->regs->err_gen_co_add; 367 addr_hi_shift = MC_ERR_STATUS_GSC_ADR_HI_SHIFT; 368 addr_hi_mask = MC_ERR_STATUS_GSC_ADR_HI_MASK; 369 break; 370 371 case MC_INT_DECERR_ROUTE_SANITY: 372 case MC_INT_DECERR_ROUTE_SANITY_GIC_MSI: 373 status_reg = mc->soc->regs->err_route_status; 374 addr_reg = mc->soc->regs->err_route_add; 375 addr_hi_shift = MC_ERR_STATUS_RT_ADR_HI_SHIFT; 376 addr_hi_mask = mc->soc->mc_addr_hi_mask; 377 mc_sec_bit = MC_ERR_ROUTE_SANITY_SEC; 378 mc_rw_bit = MC_ERR_ROUTE_SANITY_RW; 379 err_type_mask = MC_ERR_STATUS_RT_TYPE_MASK; 380 break; 381 382 default: 383 dev_err_ratelimited(mc->dev, "Incorrect MC interrupt mask\n"); 384 return; 385 } 386 387 value = mc_ch_readl(mc, channel, status_reg); 388 if (addr_hi_reg) { 389 addr = mc_ch_readl(mc, channel, addr_hi_reg); 390 } else { 391 if (!status1_reg) { 392 addr = ((value >> addr_hi_shift) & addr_hi_mask); 393 } else { 394 status1 = mc_ch_readl(mc, channel, status1_reg); 395 addr = ((status1 >> addr_hi_shift) & addr_hi_mask); 396 } 397 } 398 399 addr <<= 32; 400 addr |= mc_ch_readl(mc, channel, addr_reg); 401 402 client_id = value & mc->soc->client_id_mask; 403 for (i = 0; i < mc->soc->num_clients; i++) { 404 if (mc->soc->clients[i].id == client_id) { 405 client = mc->soc->clients[i].name; 406 break; 407 } 408 } 409 410 if (err_type_mask == MC_ERR_STATUS_RT_TYPE_MASK) { 411 type = (value & err_type_mask) >> 412 MC_ERR_STATUS_RT_TYPE_SHIFT; 413 desc = tegra264_rt_error_names[type]; 414 } else if (err_type_mask) { 415 type = (value & err_type_mask) >> 416 MC_ERR_STATUS_TYPE_SHIFT; 417 desc = tegra264_mc_error_names[type]; 418 } 419 420 dev_err_ratelimited(mc->dev, "%s: %s %s @%pa: %s (%s)\n", 421 client, value & mc_sec_bit ? "secure" : "non-secure", 422 value & mc_rw_bit ? "write" : "read", &addr, 423 tegra_mc_status_names[bit] ?: "unknown", desc); 424 if (status1_reg) 425 dev_err_ratelimited(mc->dev, "gsc_apr_id=%u gsc_co_apr_id=%u\n", 426 ((status1 >> ERR_GENERALIZED_APERTURE_ID_SHIFT) 427 & ERR_GENERALIZED_APERTURE_ID_MASK), 428 ((status1 >> ERR_GENERALIZED_CARVEOUT_APERTURE_ID_SHIFT) 429 & ERR_GENERALIZED_CARVEOUT_APERTURE_ID_MASK)); 430 } 431 432 /* clear interrupts */ 433 mc_ch_writel(mc, channel, mcf_ch_intstatus, MCF_INTSTATUS_0); 434 } 435 436 static irqreturn_t handle_mcf_irq(int irq, void *data) 437 { 438 struct tegra_mc *mc = data; 439 unsigned long common_intstat, intstatus; 440 u32 slice; 441 442 /* Read MCF_COMMON_INTSTATUS0_0_0 from MCB block */ 443 common_intstat = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, MCF_COMMON_INTSTATUS0_0_0); 444 if (common_intstat == 0) { 445 dev_warn(mc->dev, "No interrupt in MCF\n"); 446 return IRQ_NONE; 447 } 448 449 for_each_set_bit(slice, &common_intstat, 32) { 450 /* Find out the slice number on which interrupt occurred */ 451 if (slice > 4) { 452 dev_err(mc->dev, "Slice index out of bounds: %u\n", slice); 453 return IRQ_NONE; 454 } 455 456 intstatus = mc_ch_readl(mc, slice, MCF_INTSTATUS_0); 457 if (intstatus != 0) 458 mcf_log_fault(mc, slice, intstatus); 459 } 460 461 return IRQ_HANDLED; 462 } 463 464 static void hub_log_fault(struct tegra_mc *mc, u32 hub, unsigned long hub_intstat) 465 { 466 unsigned int bit; 467 468 for_each_set_bit(bit, &hub_intstat, 32) { 469 const char *client = "unknown"; 470 u32 client_id, status_reg, value, i; 471 phys_addr_t addr = 0; 472 473 switch (BIT(bit)) { 474 case MSS_HUB_COALESCER_ERR_INTMASK: 475 status_reg = MSS_HUB_COALESCE_ERR_STATUS_0; 476 addr = mc_ch_readl(mc, hub, MSS_HUB_COALESCE_ERR_ADR_HI_0); 477 addr <<= 32; 478 addr |= mc_ch_readl(mc, hub, MSS_HUB_COALESCE_ERR_ADR_0); 479 break; 480 481 case MSS_HUB_SMMU_BYPASS_ALLOW_ERR_INTMASK: 482 status_reg = MSS_HUB_SMMU_BYPASS_ALLOW_ERR_STATUS_0; 483 break; 484 485 case MSS_HUB_ILLEGAL_TBUGRP_ID_INTMASK: 486 status_reg = MSS_HUB_ILLEGAL_TBUGRP_ID_ERR_STATUS_0; 487 break; 488 489 case MSS_HUB_MSI_ERR_INTMASK: 490 status_reg = MSS_HUB_MSI_ERR_STATUS_0; 491 break; 492 493 case MSS_HUB_POISON_RSP_INTMASK: 494 status_reg = MSS_HUB_POISON_RSP_STATUS_0; 495 break; 496 497 case MSS_HUB_RESTRICTED_ACCESS_ERR_INTMASK: 498 status_reg = MSS_HUB_RESTRICTED_ACCESS_ERR_STATUS_0; 499 break; 500 501 case MSS_HUB_RESERVED_PA_ERR_INTMASK: 502 status_reg = MSS_HUB_RESERVED_PA_ERR_STATUS_0; 503 break; 504 505 default: 506 dev_err_ratelimited(mc->dev, "Incorrect HUB interrupt mask\n"); 507 return; 508 } 509 510 value = mc_ch_readl(mc, hub, status_reg); 511 512 client_id = value & mc->soc->client_id_mask; 513 for (i = 0; i < mc->soc->num_clients; i++) { 514 if (mc->soc->clients[i].id == client_id) { 515 client = mc->soc->clients[i].name; 516 break; 517 } 518 } 519 520 dev_err_ratelimited(mc->dev, "%s: @%pa: %s status: 0x%x\n", 521 client, &addr, tegra264_hub_error_names[bit] ?: "unknown", 522 value); 523 } 524 525 /* clear interrupts */ 526 mc_ch_writel(mc, hub, hub_intstat, MSS_HUB_INTRSTATUS_0); 527 } 528 529 static irqreturn_t handle_hub_irq(int irq, void *data, int mc_hubc_aperture_number) 530 { 531 struct tegra_mc *mc = data; 532 u32 global_intstat; 533 unsigned long hub_interrupt, intstat, hub; 534 535 /* Read MSS_HUB_GLOBAL_INTSTATUS_0 from mc_hubc_aperture_number block */ 536 global_intstat = mc_ch_readl(mc, mc_hubc_aperture_number, MSS_HUB_GLOBAL_INTSTATUS_0); 537 if (global_intstat == 0) { 538 dev_warn(mc->dev, "No interrupt in HUB/HUBC\n"); 539 return IRQ_NONE; 540 } 541 542 /* Handle interrupt from hubc */ 543 if (global_intstat & MSS_HUBC_INTR) { 544 /* Read MSS_HUB_HUBC_INTSTATUS_0 from block mc_hubc_aperture_number */ 545 intstat = mc_ch_readl(mc, mc_hubc_aperture_number, MSS_HUB_HUBC_INTSTATUS_0); 546 if (intstat != 0) { 547 dev_err_ratelimited(mc->dev, "Scrubber operation status: 0x%lx\n", 548 intstat); 549 /* Clear hubc interrupt */ 550 mc_ch_writel(mc, mc_hubc_aperture_number, intstat, 551 MSS_HUB_HUBC_INTSTATUS_0); 552 } 553 } 554 555 hub_interrupt = (global_intstat & MSS_HUB_GLOBAL_MASK) >> MSS_HUB_GLOBAL_SHIFT; 556 /* Handle interrupt from hub */ 557 for_each_set_bit(hub, &hub_interrupt, 32) { 558 /* Read MSS_HUB_INTRSTATUS_0 from block MCi */ 559 intstat = mc_ch_readl(mc, hub, MSS_HUB_INTRSTATUS_0); 560 if (intstat != 0) 561 hub_log_fault(mc, hub, intstat); 562 } 563 564 /* Clear global interrupt status register */ 565 mc_ch_writel(mc, mc_hubc_aperture_number, global_intstat, MSS_HUB_GLOBAL_INTSTATUS_0); 566 return IRQ_HANDLED; 567 } 568 569 static irqreturn_t handle_disp_hub_irq(int irq, void *data) 570 { 571 return handle_hub_irq(irq, data, mc_hubc_aperture_number[0]); 572 } 573 574 static irqreturn_t handle_system_hub_irq(int irq, void *data) 575 { 576 return handle_hub_irq(irq, data, mc_hubc_aperture_number[1]); 577 } 578 579 static irqreturn_t handle_vision_hub_irq(int irq, void *data) 580 { 581 return handle_hub_irq(irq, data, mc_hubc_aperture_number[2]); 582 } 583 584 static irqreturn_t handle_uphy_hub_irq(int irq, void *data) 585 { 586 return handle_hub_irq(irq, data, mc_hubc_aperture_number[3]); 587 } 588 589 static irqreturn_t handle_top_hub_irq(int irq, void *data) 590 { 591 return handle_hub_irq(irq, data, mc_hubc_aperture_number[4]); 592 } 593 594 static irqreturn_t handle_generic_irq(struct tegra_mc *mc, unsigned long intstat_reg) 595 { 596 u32 intstat, i; 597 598 /* Iterate over all MC blocks to read INTSTATUS */ 599 for (i = 0; i < mc->num_channels; i++) { 600 intstat = mc_ch_readl(mc, i, intstat_reg); 601 if (intstat) { 602 dev_err_ratelimited(mc->dev, "channel: %i status: 0x%x\n", i, intstat); 603 /* Clear interrupt */ 604 mc_ch_writel(mc, i, intstat, intstat_reg); 605 } 606 } 607 608 return IRQ_HANDLED; 609 } 610 611 static irqreturn_t handle_sbs_irq(int irq, void *data) 612 { 613 return handle_generic_irq((struct tegra_mc *)data, MSS_SBS_INTSTATUS_0); 614 } 615 616 static irqreturn_t handle_channel_irq(int irq, void *data) 617 { 618 return handle_generic_irq((struct tegra_mc *)data, MC_CH_INTSTATUS_0); 619 } 620 621 static const irq_handler_t tegra264_mc_irq_handlers[8] = { 622 handle_mcf_irq, handle_disp_hub_irq, handle_vision_hub_irq, 623 handle_system_hub_irq, handle_uphy_hub_irq, handle_top_hub_irq, 624 handle_sbs_irq, handle_channel_irq 625 }; 626 627 static const struct tegra_mc_icc_ops tegra264_mc_icc_ops = { 628 .xlate = tegra_mc_icc_xlate, 629 .aggregate = tegra264_mc_icc_aggregate, 630 .get_bw = tegra264_mc_icc_get_init_bw, 631 .set = tegra264_mc_icc_set, 632 }; 633 634 static const struct tegra_mc_regs tegra264_mc_regs = { 635 .cfg_channel_enable = 0x8870, 636 .err_status = 0xbc00, 637 .err_add = 0xbc04, 638 .err_add_hi = 0xbc08, 639 .err_vpr_status = 0xbc20, 640 .err_vpr_add = 0xbc24, 641 .err_sec_status = 0xbc3c, 642 .err_sec_add = 0xbc40, 643 .err_mts_status = 0xbc5c, 644 .err_mts_add = 0xbc60, 645 .err_gen_co_status = 0xbc78, 646 .err_gen_co_add = 0xbc7c, 647 .err_route_status = 0xbc64, 648 .err_route_add = 0xbc68, 649 }; 650 651 static const struct tegra_mc_intmask tegra264_mc_intmasks[] = { 652 { 653 .reg = MCF_INTMASK_0, 654 .mask = MC_INT_DECERR_ROUTE_SANITY_GIC_MSI | MC_INT_DECERR_ROUTE_SANITY | 655 MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | 656 MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | MC_INT_SECURITY_VIOLATION | 657 MC_INT_DECERR_EMEM, 658 }, 659 { 660 .reg = MCF_INTPRIORITY_0, 661 .mask = MC_INT_DECERR_ROUTE_SANITY_GIC_MSI | MC_INT_DECERR_ROUTE_SANITY | 662 MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | 663 MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | MC_INT_SECURITY_VIOLATION | 664 MC_INT_DECERR_EMEM, 665 }, 666 { 667 .reg = MSS_HUB_INTRMASK_0, 668 .mask = MSS_HUB_COALESCER_ERR_INTMASK | MSS_HUB_SMMU_BYPASS_ALLOW_ERR_INTMASK | 669 MSS_HUB_ILLEGAL_TBUGRP_ID_INTMASK | MSS_HUB_MSI_ERR_INTMASK | 670 MSS_HUB_POISON_RSP_INTMASK | MSS_HUB_RESTRICTED_ACCESS_ERR_INTMASK | 671 MSS_HUB_RESERVED_PA_ERR_INTMASK, 672 }, 673 { 674 .reg = MSS_HUB_INTRPRIORITY_0, 675 .mask = MSS_HUB_COALESCER_ERR_INTMASK | MSS_HUB_SMMU_BYPASS_ALLOW_ERR_INTMASK | 676 MSS_HUB_ILLEGAL_TBUGRP_ID_INTMASK | MSS_HUB_MSI_ERR_INTMASK | 677 MSS_HUB_POISON_RSP_INTMASK | MSS_HUB_RESTRICTED_ACCESS_ERR_INTMASK | 678 MSS_HUB_RESERVED_PA_ERR_INTMASK, 679 }, 680 { 681 .reg = MSS_HUB_HUBC_INTMASK_0, 682 .mask = MSS_HUB_HUBC_SCRUB_DONE_INTMASK, 683 }, 684 { 685 .reg = MSS_HUB_HUBC_INTPRIORITY_0, 686 .mask = MSS_HUB_HUBC_SCRUB_DONE_INTMASK, 687 }, 688 { 689 .reg = MSS_SBS_INTMASK_0, 690 .mask = MSS_SBS_FILL_FIFO_ISO_OVERFLOW_INTMASK | 691 MSS_SBS_FILL_FIFO_SISO_OVERFLOW_INTMASK | 692 MSS_SBS_FILL_FIFO_NISO_OVERFLOW_INTMASK, 693 }, 694 { 695 .reg = MC_CH_INTMASK_0, 696 .mask = WCAM_ERR_INTMASK, 697 } 698 }; 699 700 const struct tegra_mc_soc tegra264_mc_soc = { 701 .num_clients = ARRAY_SIZE(tegra264_mc_clients), 702 .clients = tegra264_mc_clients, 703 .num_address_bits = 40, 704 .num_channels = 16, 705 .client_id_mask = 0x1ff, 706 .intmasks = tegra264_mc_intmasks, 707 .num_intmasks = ARRAY_SIZE(tegra264_mc_intmasks), 708 .has_addr_hi_reg = true, 709 .ops = &tegra186_mc_ops, 710 .icc_ops = &tegra264_mc_icc_ops, 711 .ch_intmask = 0x0000ff00, 712 .global_intstatus_channel_shift = 8, 713 /* 714 * Additionally, there are lite carveouts but those are not currently 715 * supported. 716 */ 717 .num_carveouts = 32, 718 .mc_addr_hi_mask = 0xff, 719 .mc_err_status_type_mask = (0x3 << 28), 720 .regs = &tegra264_mc_regs, 721 .handle_irq = tegra264_mc_irq_handlers, 722 .num_interrupts = ARRAY_SIZE(tegra264_mc_irq_handlers), 723 }; 724