xref: /linux/drivers/memory/tegra/tegra264.c (revision 6505114e82e7541414b176b5da4a3c015a1214ea) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2025-2026, NVIDIA CORPORATION.  All rights reserved.
4  */
5 
6 #include <dt-bindings/memory/nvidia,tegra264.h>
7 
8 #include <linux/interconnect.h>
9 #include <linux/of_device.h>
10 #include <linux/tegra-icc.h>
11 
12 #include <soc/tegra/bpmp.h>
13 #include <soc/tegra/mc.h>
14 
15 #include "mc.h"
16 #include "tegra264-bwmgr.h"
17 
18 /*
19  * MC Client entries are sorted in the increasing order of the
20  * override and security register offsets.
21  */
22 static const struct tegra_mc_client tegra264_mc_clients[] = {
23 	{
24 		.id = TEGRA264_MEMORY_CLIENT_PTCR,
25 		.name = "ptcr",
26 	}, {
27 		.id = TEGRA264_MEMORY_CLIENT_HOST1XR,
28 		.name = "host1xr",
29 	}, {
30 		.id = TEGRA264_MEMORY_CLIENT_MPCORER,
31 		.name = "mpcorer",
32 	}, {
33 		.id = TEGRA264_MEMORY_CLIENT_PSCR,
34 		.name = "pscr",
35 	}, {
36 		.id = TEGRA264_MEMORY_CLIENT_PSCW,
37 		.name = "pscw",
38 	}, {
39 		.id = TEGRA264_MEMORY_CLIENT_ISP0R,
40 		.name = "isp0r",
41 	}, {
42 		.id = TEGRA264_MEMORY_CLIENT_MPCOREW,
43 		.name = "mpcorew",
44 	}, {
45 		.id = TEGRA264_MEMORY_CLIENT_ISP0W,
46 		.name = "isp0w",
47 	}, {
48 		.id = TEGRA264_MEMORY_CLIENT_ISP1W,
49 		.name = "isp1w",
50 	}, {
51 		.id = TEGRA264_MEMORY_CLIENT_ISPFALCONR,
52 		.name = "ispfalconr",
53 	}, {
54 		.id = TEGRA264_MEMORY_CLIENT_ISPFALCONW,
55 		.name = "ispfalconw",
56 	}, {
57 		.id = TEGRA264_MEMORY_CLIENT_MGBE2R,
58 		.name = "mgbe2r",
59 	}, {
60 		.id = TEGRA264_MEMORY_CLIENT_OFAR2MC,
61 		.name = "ofar2mc",
62 	}, {
63 		.id = TEGRA264_MEMORY_CLIENT_OFAW2MC,
64 		.name = "ofaw2mc",
65 	}, {
66 		.id = TEGRA264_MEMORY_CLIENT_MGBE2W,
67 		.name = "mgbe2w",
68 	}, {
69 		.id = TEGRA264_MEMORY_CLIENT_MGBE3R,
70 		.name = "mgbe3r",
71 	}, {
72 		.id = TEGRA264_MEMORY_CLIENT_MGBE3W,
73 		.name = "mgbe3w",
74 	}, {
75 		.id = TEGRA264_MEMORY_CLIENT_SEU1RD,
76 		.name = "seu1rd",
77 	}, {
78 		.id = TEGRA264_MEMORY_CLIENT_SEU1WR,
79 		.name = "seu1wr",
80 	}, {
81 		.id = TEGRA264_MEMORY_CLIENT_VICR,
82 		.name = "vicr",
83 		.bpmp_id = TEGRA264_BWMGR_VIC,
84 		.type = TEGRA_ICC_NISO,
85 	}, {
86 		.id = TEGRA264_MEMORY_CLIENT_VICW,
87 		.name = "vicw",
88 		.bpmp_id = TEGRA264_BWMGR_VIC,
89 		.type = TEGRA_ICC_NISO,
90 	}, {
91 		.id = TEGRA264_MEMORY_CLIENT_VIW,
92 		.name = "viw",
93 	}, {
94 		.id = TEGRA264_MEMORY_CLIENT_XSPI0R,
95 		.name = "xspi0r",
96 	}, {
97 		.id = TEGRA264_MEMORY_CLIENT_XSPI0W,
98 		.name = "xspi0w",
99 	}, {
100 		.id = TEGRA264_MEMORY_CLIENT_APER,
101 		.name = "aper",
102 		.bpmp_id = TEGRA264_BWMGR_APE,
103 		.type = TEGRA_ICC_ISO_AUDIO,
104 	}, {
105 		.id = TEGRA264_MEMORY_CLIENT_APEW,
106 		.name = "apew",
107 		.bpmp_id = TEGRA264_BWMGR_APE,
108 		.type = TEGRA_ICC_ISO_AUDIO,
109 	}, {
110 		.id = TEGRA264_MEMORY_CLIENT_SER,
111 		.name = "ser",
112 	}, {
113 		.id = TEGRA264_MEMORY_CLIENT_SEW,
114 		.name = "sew",
115 	}, {
116 		.id = TEGRA264_MEMORY_CLIENT_AXIAPR,
117 		.name = "axiapr",
118 	}, {
119 		.id = TEGRA264_MEMORY_CLIENT_AXIAPW,
120 		.name = "axiapw",
121 	}, {
122 		.id = TEGRA264_MEMORY_CLIENT_ETRR,
123 		.name = "etrr",
124 	}, {
125 		.id = TEGRA264_MEMORY_CLIENT_ETRW,
126 		.name = "etrw",
127 	}, {
128 		.id = TEGRA264_MEMORY_CLIENT_TSECR,
129 		.name = "tsecr",
130 	}, {
131 		.id = TEGRA264_MEMORY_CLIENT_TSECW,
132 		.name = "tsecw",
133 	}, {
134 		.id = TEGRA264_MEMORY_CLIENT_BPMPR,
135 		.name = "bpmpr",
136 	}, {
137 		.id = TEGRA264_MEMORY_CLIENT_BPMPW,
138 		.name = "bpmpw",
139 	}, {
140 		.id = TEGRA264_MEMORY_CLIENT_AONR,
141 		.name = "aonr",
142 	}, {
143 		.id = TEGRA264_MEMORY_CLIENT_AONW,
144 		.name = "aonw",
145 	}, {
146 		.id = TEGRA264_MEMORY_CLIENT_GPCDMAR,
147 		.name = "gpcdmar",
148 	}, {
149 		.id = TEGRA264_MEMORY_CLIENT_GPCDMAW,
150 		.name = "gpcdmaw",
151 	}, {
152 		.id = TEGRA264_MEMORY_CLIENT_APEDMAR,
153 		.name = "apedmar",
154 		.bpmp_id = TEGRA264_BWMGR_APEDMA,
155 		.type = TEGRA_ICC_ISO_AUDIO,
156 	}, {
157 		.id = TEGRA264_MEMORY_CLIENT_APEDMAW,
158 		.name = "apedmaw",
159 		.bpmp_id = TEGRA264_BWMGR_APEDMA,
160 		.type = TEGRA_ICC_ISO_AUDIO,
161 	}, {
162 		.id = TEGRA264_MEMORY_CLIENT_MIU0R,
163 		.name = "miu0r",
164 	}, {
165 		.id = TEGRA264_MEMORY_CLIENT_MIU0W,
166 		.name = "miu0w",
167 	}, {
168 		.id = TEGRA264_MEMORY_CLIENT_MIU1R,
169 		.name = "miu1r",
170 	}, {
171 		.id = TEGRA264_MEMORY_CLIENT_MIU1W,
172 		.name = "miu1w",
173 	}, {
174 		.id = TEGRA264_MEMORY_CLIENT_MIU2R,
175 		.name = "miu2r",
176 	}, {
177 		.id = TEGRA264_MEMORY_CLIENT_MIU2W,
178 		.name = "miu2w",
179 	}, {
180 		.id = TEGRA264_MEMORY_CLIENT_MIU3R,
181 		.name = "miu3r",
182 	}, {
183 		.id = TEGRA264_MEMORY_CLIENT_MIU3W,
184 		.name = "miu3w",
185 	}, {
186 		.id = TEGRA264_MEMORY_CLIENT_MIU4R,
187 		.name = "miu4r",
188 	}, {
189 		.id = TEGRA264_MEMORY_CLIENT_MIU4W,
190 		.name = "miu4w",
191 	}, {
192 		.id = TEGRA264_MEMORY_CLIENT_VIFALCONR,
193 		.name = "vifalconr",
194 		.bpmp_id = TEGRA264_BWMGR_VIFAL,
195 		.type = TEGRA_ICC_ISO_VIFAL,
196 	}, {
197 		.id = TEGRA264_MEMORY_CLIENT_VIFALCONW,
198 		.name = "vifalconw",
199 		.bpmp_id = TEGRA264_BWMGR_VIFAL,
200 		.type = TEGRA_ICC_ISO_VIFAL,
201 	}, {
202 		.id = TEGRA264_MEMORY_CLIENT_RCER,
203 		.name = "rcer",
204 		.bpmp_id = TEGRA264_BWMGR_RCE,
205 		.type = TEGRA_ICC_NISO,
206 	}, {
207 		.id = TEGRA264_MEMORY_CLIENT_RCEW,
208 		.name = "rcew",
209 		.bpmp_id = TEGRA264_BWMGR_RCE,
210 		.type = TEGRA_ICC_NISO,
211 	}, {
212 		.id = TEGRA264_MEMORY_CLIENT_NVENC1SRD2MC,
213 		.name = "nvenc1srd2mc",
214 	}, {
215 		.id = TEGRA264_MEMORY_CLIENT_NVENC1SWR2MC,
216 		.name = "nvenc1swr2mc",
217 	}, {
218 		.id = TEGRA264_MEMORY_CLIENT_PCIE0W,
219 		.name = "pcie0w",
220 		.bpmp_id = TEGRA264_BWMGR_PCIE_0,
221 		.type = TEGRA_ICC_NISO,
222 	}, {
223 		.id = TEGRA264_MEMORY_CLIENT_PCIE1R,
224 		.name = "pcie1r",
225 		.bpmp_id = TEGRA264_BWMGR_PCIE_1,
226 		.type = TEGRA_ICC_NISO,
227 	}, {
228 		.id = TEGRA264_MEMORY_CLIENT_PCIE1W,
229 		.name = "pcie1w",
230 		.bpmp_id = TEGRA264_BWMGR_PCIE_1,
231 		.type = TEGRA_ICC_NISO,
232 	}, {
233 		.id = TEGRA264_MEMORY_CLIENT_PCIE2AR,
234 		.name = "pcie2ar",
235 		.bpmp_id = TEGRA264_BWMGR_PCIE_2,
236 		.type = TEGRA_ICC_NISO,
237 	}, {
238 		.id = TEGRA264_MEMORY_CLIENT_PCIE2AW,
239 		.name = "pcie2aw",
240 		.bpmp_id = TEGRA264_BWMGR_PCIE_2,
241 		.type = TEGRA_ICC_NISO,
242 	}, {
243 		.id = TEGRA264_MEMORY_CLIENT_PCIE3R,
244 		.name = "pcie3r",
245 		.bpmp_id = TEGRA264_BWMGR_PCIE_3,
246 		.type = TEGRA_ICC_NISO,
247 	}, {
248 		.id = TEGRA264_MEMORY_CLIENT_PCIE3W,
249 		.name = "pcie3w",
250 		.bpmp_id = TEGRA264_BWMGR_PCIE_3,
251 		.type = TEGRA_ICC_NISO,
252 	}, {
253 		.id = TEGRA264_MEMORY_CLIENT_PCIE4R,
254 		.name = "pcie4r",
255 		.bpmp_id = TEGRA264_BWMGR_PCIE_4,
256 		.type = TEGRA_ICC_NISO,
257 	}, {
258 		.id = TEGRA264_MEMORY_CLIENT_PCIE4W,
259 		.name = "pcie4w",
260 		.bpmp_id = TEGRA264_BWMGR_PCIE_4,
261 		.type = TEGRA_ICC_NISO,
262 	}, {
263 		.id = TEGRA264_MEMORY_CLIENT_PCIE5R,
264 		.name = "pcie5r",
265 		.bpmp_id = TEGRA264_BWMGR_PCIE_5,
266 		.type = TEGRA_ICC_NISO,
267 	}, {
268 		.id = TEGRA264_MEMORY_CLIENT_PCIE5W,
269 		.name = "pcie5w",
270 		.bpmp_id = TEGRA264_BWMGR_PCIE_5,
271 		.type = TEGRA_ICC_NISO,
272 	}, {
273 		.id = TEGRA264_MEMORY_CLIENT_GPUR02MC,
274 		.name = "gpur02mc",
275 		.bpmp_id = TEGRA264_BWMGR_GPU,
276 		.type = TEGRA_ICC_NISO,
277 	}, {
278 		.id = TEGRA264_MEMORY_CLIENT_GPUW02MC,
279 		.name = "gpuw02mc",
280 		.bpmp_id = TEGRA264_BWMGR_GPU,
281 		.type = TEGRA_ICC_NISO,
282 	}, {
283 		.id = TEGRA264_MEMORY_CLIENT_NVDECSRD2MC,
284 		.name = "nvdecsrd2mc",
285 		.bpmp_id = TEGRA264_BWMGR_NVDEC,
286 		.type = TEGRA_ICC_NISO,
287 	}, {
288 		.id = TEGRA264_MEMORY_CLIENT_NVDECSWR2MC,
289 		.name = "nvdecswr2mc",
290 		.bpmp_id = TEGRA264_BWMGR_NVDEC,
291 		.type = TEGRA_ICC_NISO,
292 	}, {
293 		.id = TEGRA264_MEMORY_CLIENT_MIU5R,
294 		.name = "miu5r",
295 	}, {
296 		.id = TEGRA264_MEMORY_CLIENT_MIU5W,
297 		.name = "miu5w",
298 	}, {
299 		.id = TEGRA264_MEMORY_CLIENT_MIU6W,
300 		.name = "miu6w",
301 	}, {
302 		.id = TEGRA264_MEMORY_CLIENT_RISTR,
303 		.name = "ristr",
304 	}, {
305 		.id = TEGRA264_MEMORY_CLIENT_RISTW,
306 		.name = "ristw",
307 	}, {
308 		.id = TEGRA264_MEMORY_CLIENT_OESPR,
309 		.name = "oespr",
310 	}, {
311 		.id = TEGRA264_MEMORY_CLIENT_OESPW,
312 		.name = "oespw",
313 	}, {
314 		.id = TEGRA264_MEMORY_CLIENT_MIU7W,
315 		.name = "miu7w",
316 	}, {
317 		.id = TEGRA264_MEMORY_CLIENT_MIU8R,
318 		.name = "miu8r",
319 	}, {
320 		.id = TEGRA264_MEMORY_CLIENT_MIU8W,
321 		.name = "miu8w",
322 	}, {
323 		.id = TEGRA264_MEMORY_CLIENT_MIU9R,
324 		.name = "miu9r",
325 	}, {
326 		.id = TEGRA264_MEMORY_CLIENT_MIU9W,
327 		.name = "miu9w",
328 	}, {
329 		.id = TEGRA264_MEMORY_CLIENT_PMA0AWR,
330 		.name = "pma0awr",
331 	}, {
332 		.id = TEGRA264_MEMORY_CLIENT_NVJPG1SRD2MC,
333 		.name = "nvjpg1srd2mc",
334 	}, {
335 		.id = TEGRA264_MEMORY_CLIENT_NVJPG1SWR2MC,
336 		.name = "nvjpg1swr2mc",
337 	}, {
338 		.id = TEGRA264_MEMORY_CLIENT_SMMU0CTWR,
339 		.name = "smmu0ctwr",
340 	}, {
341 		.id = TEGRA264_MEMORY_CLIENT_SMMU0CMDQVR,
342 		.name = "smmu0cmdqvr",
343 	}, {
344 		.id = TEGRA264_MEMORY_CLIENT_SMMU0CMDQVW,
345 		.name = "smmu0cmdqvw",
346 	}, {
347 		.id = TEGRA264_MEMORY_CLIENT_SMMU0EVNTQW,
348 		.name = "smmu0evntqw",
349 	}, {
350 		.id = TEGRA264_MEMORY_CLIENT_SMMU1PTWR,
351 		.name = "smmu1ptwr",
352 	}, {
353 		.id = TEGRA264_MEMORY_CLIENT_SMMU1CTWR,
354 		.name = "smmu1ctwr",
355 	}, {
356 		.id = TEGRA264_MEMORY_CLIENT_SMMU1CMDQVR,
357 		.name = "smmu1cmdqvr",
358 	}, {
359 		.id = TEGRA264_MEMORY_CLIENT_SMMU1CMDQVW,
360 		.name = "smmu1cmdqvw",
361 	}, {
362 		.id = TEGRA264_MEMORY_CLIENT_SMMU1EVNTQW,
363 		.name = "smmu1evntqw",
364 	}, {
365 		.id = TEGRA264_MEMORY_CLIENT_SMMU2PTWR,
366 		.name = "smmu2ptwr",
367 	}, {
368 		.id = TEGRA264_MEMORY_CLIENT_SMMU2CTWR,
369 		.name = "smmu2ctwr",
370 	}, {
371 		.id = TEGRA264_MEMORY_CLIENT_SMMU2CMDQVR,
372 		.name = "smmu2cmdqvr",
373 	}, {
374 		.id = TEGRA264_MEMORY_CLIENT_SMMU2CMDQVW,
375 		.name = "smmu2cmdqvw",
376 	}, {
377 		.id = TEGRA264_MEMORY_CLIENT_SMMU2EVNTQW,
378 		.name = "smmu2evntqw",
379 	}, {
380 		.id = TEGRA264_MEMORY_CLIENT_SMMU0CMDQR,
381 		.name = "smmu0cmdqr",
382 	}, {
383 		.id = TEGRA264_MEMORY_CLIENT_SMMU1CMDQR,
384 		.name = "smmu1cmdqr",
385 	}, {
386 		.id = TEGRA264_MEMORY_CLIENT_SMMU2CMDQR,
387 		.name = "smmu2cmdqr",
388 	}, {
389 		.id = TEGRA264_MEMORY_CLIENT_APE1R,
390 		.name = "ape1r",
391 	}, {
392 		.id = TEGRA264_MEMORY_CLIENT_APE1W,
393 		.name = "ape1w",
394 	}, {
395 		.id = TEGRA264_MEMORY_CLIENT_UFSR,
396 		.name = "ufsr",
397 	}, {
398 		.id = TEGRA264_MEMORY_CLIENT_UFSW,
399 		.name = "ufsw",
400 	}, {
401 		.id = TEGRA264_MEMORY_CLIENT_XUSB_DEVR,
402 		.name = "xusb_devr",
403 	}, {
404 		.id = TEGRA264_MEMORY_CLIENT_XUSB_DEVW,
405 		.name = "xusb_devw",
406 	}, {
407 		.id = TEGRA264_MEMORY_CLIENT_XUSB_DEV1R,
408 		.name = "xusb_dev1r",
409 	}, {
410 		.id = TEGRA264_MEMORY_CLIENT_XUSB_DEV2W,
411 		.name = "xusb_dev2w",
412 	}, {
413 		.id = TEGRA264_MEMORY_CLIENT_XUSB_DEV3R,
414 		.name = "xusb_dev3r",
415 	}, {
416 		.id = TEGRA264_MEMORY_CLIENT_XUSB_DEV3W,
417 		.name = "xusb_dev3w",
418 	}, {
419 		.id = TEGRA264_MEMORY_CLIENT_XUSB_DEV4R,
420 		.name = "xusb_dev4r",
421 	}, {
422 		.id = TEGRA264_MEMORY_CLIENT_XUSB_DEV4W,
423 		.name = "xusb_dev4w",
424 	}, {
425 		.id = TEGRA264_MEMORY_CLIENT_XUSB_DEV5R,
426 		.name = "xusb_dev5r",
427 	}, {
428 		.id = TEGRA264_MEMORY_CLIENT_XUSB_DEV5W,
429 		.name = "xusb_dev5w",
430 	}, {
431 		.id = TEGRA264_MEMORY_CLIENT_DCER,
432 		.name = "dcer",
433 	}, {
434 		.id = TEGRA264_MEMORY_CLIENT_DCEW,
435 		.name = "dcew",
436 	}, {
437 		.id = TEGRA264_MEMORY_CLIENT_HDAR,
438 		.name = "hdar",
439 		.bpmp_id = TEGRA264_BWMGR_HDA,
440 		.type = TEGRA_ICC_ISO_AUDIO,
441 	}, {
442 		.id = TEGRA264_MEMORY_CLIENT_HDAW,
443 		.name = "hdaw",
444 		.bpmp_id = TEGRA264_BWMGR_HDA,
445 		.type = TEGRA_ICC_ISO_AUDIO,
446 	}, {
447 		.id = TEGRA264_MEMORY_CLIENT_DISPNISOR,
448 		.name = "dispnisor",
449 	}, {
450 		.id = TEGRA264_MEMORY_CLIENT_DISPNISOW,
451 		.name = "dispnisow",
452 	}, {
453 		.id = TEGRA264_MEMORY_CLIENT_XUSB_DEV1W,
454 		.name = "xusb_dev1w",
455 	}, {
456 		.id = TEGRA264_MEMORY_CLIENT_XUSB_DEV2R,
457 		.name = "xusb_dev2r",
458 	}, {
459 		.id = TEGRA264_MEMORY_CLIENT_DISPR,
460 		.name = "dispr",
461 		.bpmp_id = TEGRA264_BWMGR_DISPLAY,
462 		.type = TEGRA_ICC_ISO_DISPLAY,
463 	}, {
464 		.id = TEGRA264_MEMORY_CLIENT_MSSSEQR,
465 		.name = "mssseqr",
466 	}, {
467 		.id = TEGRA264_MEMORY_CLIENT_MSSSEQW,
468 		.name = "mssseqw",
469 	}, {
470 		.id = TEGRA264_MEMORY_CLIENT_SMMU3PTWR,
471 		.name = "smmu3ptwr",
472 	}, {
473 		.id = TEGRA264_MEMORY_CLIENT_SMMU3CTWR,
474 		.name = "smmu3ctwr",
475 	}, {
476 		.id = TEGRA264_MEMORY_CLIENT_SMMU3CMDQVR,
477 		.name = "smmu3cmdqvr",
478 	}, {
479 		.id = TEGRA264_MEMORY_CLIENT_SMMU3CMDQVW,
480 		.name = "smmu3cmdqvw",
481 	}, {
482 		.id = TEGRA264_MEMORY_CLIENT_SMMU3EVNTQW,
483 		.name = "smmu3evntqw",
484 	}, {
485 		.id = TEGRA264_MEMORY_CLIENT_SMMU3CMDQR,
486 		.name = "smmu3cmdqr",
487 	}, {
488 		.id = TEGRA264_MEMORY_CLIENT_SMMU4PTWR,
489 		.name = "smmu4ptwr",
490 	}, {
491 		.id = TEGRA264_MEMORY_CLIENT_SMMU4CTWR,
492 		.name = "smmu4ctwr",
493 	}, {
494 		.id = TEGRA264_MEMORY_CLIENT_SMMU4CMDQVR,
495 		.name = "smmu4cmdqvr",
496 	}, {
497 		.id = TEGRA264_MEMORY_CLIENT_SMMU4CMDQVW,
498 		.name = "smmu4cmdqvw",
499 	}, {
500 		.id = TEGRA264_MEMORY_CLIENT_SMMU4EVNTQW,
501 		.name = "smmu4evntqw",
502 	}, {
503 		.id = TEGRA264_MEMORY_CLIENT_SMMU4CMDQR,
504 		.name = "smmu4cmdqr",
505 	}, {
506 		.id = TEGRA264_MEMORY_CLIENT_MGBE0R,
507 		.name = "mgbe0r",
508 		.bpmp_id = TEGRA264_BWMGR_EQOS,
509 		.type = TEGRA_ICC_NISO,
510 	}, {
511 		.id = TEGRA264_MEMORY_CLIENT_MGBE0W,
512 		.name = "mgbe0w",
513 		.bpmp_id = TEGRA264_BWMGR_EQOS,
514 		.type = TEGRA_ICC_NISO,
515 	}, {
516 		.id = TEGRA264_MEMORY_CLIENT_MGBE1R,
517 		.name = "mgbe1r",
518 		.bpmp_id = TEGRA264_BWMGR_EQOS,
519 		.type = TEGRA_ICC_NISO,
520 	}, {
521 		.id = TEGRA264_MEMORY_CLIENT_MGBE1W,
522 		.name = "mgbe1w",
523 		.bpmp_id = TEGRA264_BWMGR_EQOS,
524 		.type = TEGRA_ICC_NISO,
525 	}, {
526 		.id = TEGRA264_MEMORY_CLIENT_VI1W,
527 		.name = "vi1w",
528 	}, {
529 		.id = TEGRA264_MEMORY_CLIENT_VIFALCON1R,
530 		.name = "vifalcon1r",
531 	}, {
532 		.id = TEGRA264_MEMORY_CLIENT_VIFALCON1W,
533 		.name = "vifalcon1w",
534 	}, {
535 		.id = TEGRA264_MEMORY_CLIENT_ISPFALCON1R,
536 		.name = "ispfalcon1r",
537 	}, {
538 		.id = TEGRA264_MEMORY_CLIENT_ISPFALCON1W,
539 		.name = "ispfalcon1w",
540 	}, {
541 		.id = TEGRA264_MEMORY_CLIENT_RCE1R,
542 		.name = "rce1r",
543 	}, {
544 		.id = TEGRA264_MEMORY_CLIENT_RCE1W,
545 		.name = "rce1w",
546 	}, {
547 		.id = TEGRA264_MEMORY_CLIENT_SEU2R,
548 		.name = "seu2r",
549 	}, {
550 		.id = TEGRA264_MEMORY_CLIENT_SEU2W,
551 		.name = "seu2w",
552 	}, {
553 		.id = TEGRA264_MEMORY_CLIENT_SEU3R,
554 		.name = "seu3r",
555 	}, {
556 		.id = TEGRA264_MEMORY_CLIENT_SEU3W,
557 		.name = "seu3w",
558 	}, {
559 		.id = TEGRA264_MEMORY_CLIENT_PVA0R,
560 		.name = "pva0r",
561 	}, {
562 		.id = TEGRA264_MEMORY_CLIENT_PVA0W,
563 		.name = "pva0w",
564 	}, {
565 		.id = TEGRA264_MEMORY_CLIENT_PVA1R,
566 		.name = "pva1r",
567 	}, {
568 		.id = TEGRA264_MEMORY_CLIENT_PVA1W,
569 		.name = "pva1w",
570 	}, {
571 		.id = TEGRA264_MEMORY_CLIENT_PVA2R,
572 		.name = "pva2r",
573 	}, {
574 		.id = TEGRA264_MEMORY_CLIENT_PVA2W,
575 		.name = "pva2w",
576 	}, {
577 		.id = TEGRA264_MEMORY_CLIENT_ISP3W,
578 		.name = "isp3w",
579 	}, {
580 		.id = TEGRA264_MEMORY_CLIENT_ISP2R,
581 		.name = "isp2r",
582 	}, {
583 		.id = TEGRA264_MEMORY_CLIENT_ISP2W,
584 		.name = "isp2w",
585 	}, {
586 		.id = TEGRA264_MEMORY_CLIENT_EQOSR,
587 		.name = "eqosr",
588 	}, {
589 		.id = TEGRA264_MEMORY_CLIENT_EQOSW,
590 		.name = "eqosw",
591 	}, {
592 		.id = TEGRA264_MEMORY_CLIENT_FSI0R,
593 		.name = "fsi0r",
594 	}, {
595 		.id = TEGRA264_MEMORY_CLIENT_FSI0W,
596 		.name = "fsi0w",
597 	}, {
598 		.id = TEGRA264_MEMORY_CLIENT_FSI1R,
599 		.name = "fsi1r",
600 	}, {
601 		.id = TEGRA264_MEMORY_CLIENT_FSI1W,
602 		.name = "fsi1w",
603 	}, {
604 		.id = TEGRA264_MEMORY_CLIENT_SDMMC0R,
605 		.name = "sdmmc0r",
606 		.bpmp_id = TEGRA264_BWMGR_SDMMC_1,
607 		.type = TEGRA_ICC_NISO,
608 	}, {
609 		.id = TEGRA264_MEMORY_CLIENT_SDMMC0W,
610 		.name = "sdmmc0w",
611 		.bpmp_id = TEGRA264_BWMGR_SDMMC_1,
612 		.type = TEGRA_ICC_NISO,
613 	}, {
614 		.id = TEGRA264_MEMORY_CLIENT_SBR,
615 		.name = "sbr",
616 	}, {
617 		.id = TEGRA264_MEMORY_CLIENT_SBW,
618 		.name = "sbw",
619 	}, {
620 		.id = TEGRA264_MEMORY_CLIENT_HSS_MIU0R,
621 		.name = "hss_miu0r",
622 	}, {
623 		.id = TEGRA264_MEMORY_CLIENT_HSS_MIU0W,
624 		.name = "hss_miu0w",
625 	}, {
626 		.id = TEGRA264_MEMORY_CLIENT_HSS_MIU1R,
627 		.name = "hss_miu1r",
628 	}, {
629 		.id = TEGRA264_MEMORY_CLIENT_HSS_MIU1W,
630 		.name = "hss_miu1w",
631 	}, {
632 		.id = TEGRA264_MEMORY_CLIENT_HSS_MIU2R,
633 		.name = "hss_miu2r",
634 	}, {
635 		.id = TEGRA264_MEMORY_CLIENT_HSS_MIU2W,
636 		.name = "hss_miu2w",
637 	}, {
638 		.id = TEGRA264_MEMORY_CLIENT_HSS_MIU3R,
639 		.name = "hss_miu3r",
640 	}, {
641 		.id = TEGRA264_MEMORY_CLIENT_HSS_MIU3W,
642 		.name = "hss_miu3w",
643 	}, {
644 		.id = TEGRA264_MEMORY_CLIENT_HSS_MIU4R,
645 		.name = "hss_miu4r",
646 	}, {
647 		.id = TEGRA264_MEMORY_CLIENT_HSS_MIU4W,
648 		.name = "hss_miu4w",
649 	}, {
650 		.id = TEGRA264_MEMORY_CLIENT_HSS_MIU5R,
651 		.name = "hss_miu5r",
652 	}, {
653 		.id = TEGRA264_MEMORY_CLIENT_HSS_MIU5W,
654 		.name = "hss_miu5w",
655 	}, {
656 		.id = TEGRA264_MEMORY_CLIENT_HSS_MIU6R,
657 		.name = "hss_miu6r",
658 	}, {
659 		.id = TEGRA264_MEMORY_CLIENT_HSS_MIU6W,
660 		.name = "hss_miu6w",
661 	}, {
662 		.id = TEGRA264_MEMORY_CLIENT_HSS_MIU7R,
663 		.name = "hss_miu7r",
664 	}, {
665 		.id = TEGRA264_MEMORY_CLIENT_HSS_MIU7W,
666 		.name = "hss_miu7w",
667 	}, {
668 		.id = TEGRA264_MEMORY_CLIENT_GMMUR2MC,
669 		.name = "gmmur2mc",
670 	}, {
671 		.id = TEGRA264_MEMORY_CLIENT_UCFELAR,
672 		.name = "ucfelar",
673 	}, {
674 		.id = TEGRA264_MEMORY_CLIENT_UCFELAW,
675 		.name = "ucfelaw",
676 	}, {
677 		.id = TEGRA264_MEMORY_CLIENT_SLCR,
678 		.name = "slcr",
679 	}, {
680 		.id = TEGRA264_MEMORY_CLIENT_SLCW,
681 		.name = "slcw",
682 	}, {
683 		.id = TEGRA264_MEMORY_CLIENT_REMOTER,
684 		.name = "remoter",
685 	}, {
686 		.id = TEGRA264_MEMORY_CLIENT_REMOTEW,
687 		.name = "remotew",
688 	},
689 };
690 
691 static const char *const tegra264_hub_error_names[32] = {
692 	[0] = "coalescer error",
693 	[1] = "SMMU BYPASS ALLOW error",
694 	[2] = "Illegal tbugrp_id error",
695 	[3] = "Malformed MSI request error",
696 	[4] = "Read response with poison bit error",
697 	[5] = "Restricted access violation error",
698 	[6] = "Reserved PA error",
699 };
700 
701 static const char *const tegra264_mc_error_names[4] = {
702 	[1] = "EMEM decode error",
703 	[2] = "TrustZone violation",
704 	[3] = "Carveout violation",
705 };
706 
707 static const char *const tegra264_rt_error_names[16] = {
708 	[1] = "DECERR_PARTIAL_POPULATED",
709 	[2] = "DECERR_SMMU_BYPASS",
710 	[3] = "DECERR_INVALID_MMIO",
711 	[4] = "DECERR_INVALID_GIC_MSI",
712 	[5] = "DECERR_ATOMIC_SYSRAM",
713 	[9] = "DECERR_REMOTE_REQ_PRE_BOOT",
714 	[10] = "DECERR_ISO_OVER_C2C",
715 	[11] = "DECERR_UNSUPPORTED_SBS_OPCODE",
716 	[12] = "DECERR_SBS_REQ_OVER_SISO_LL",
717 };
718 
719 /*
720  * MC instance aperture mapping for hubc registers
721  */
722 static const int mc_hubc_aperture_number[5] = {
723 	7, 8, 9, 10, 11
724 };
725 
726 /*
727  * tegra264_mc_icc_set() - Pass MC client info to the BPMP-FW
728  * @src: ICC node for Memory Controller's (MC) Client
729  * @dst: ICC node for Memory Controller (MC)
730  *
731  * Passing the current request info from the MC to the BPMP-FW where
732  * LA and PTSA registers are accessed and the final EMC freq is set
733  * based on client_id, type, latency and bandwidth.
734  * icc_set_bw() makes set_bw calls for both MC and EMC providers in
735  * sequence. Both the calls are protected by 'mutex_lock(&icc_lock)'.
736  * So, the data passed won't be updated by concurrent set calls from
737  * other clients.
738  */
739 static int tegra264_mc_icc_set(struct icc_node *src, struct icc_node *dst)
740 {
741 	struct tegra_mc *mc = icc_provider_to_tegra_mc(dst->provider);
742 	struct mrq_bwmgr_int_request bwmgr_req = { 0 };
743 	struct mrq_bwmgr_int_response bwmgr_resp = { 0 };
744 	const struct tegra_mc_client *pclient = src->data;
745 	struct tegra_bpmp_message msg;
746 	int ret;
747 
748 	/*
749 	 * Same Src and Dst node will happen during boot from icc_node_add().
750 	 * This can be used to pre-initialize and set bandwidth for all clients
751 	 * before their drivers are loaded. We are skipping this case as for us,
752 	 * the pre-initialization already happened in Bootloader(MB2) and BPMP-FW.
753 	 */
754 	if (src->id == dst->id)
755 		return 0;
756 
757 	if (!mc->bwmgr_mrq_supported)
758 		return 0;
759 
760 	if (!mc->bpmp) {
761 		dev_err(mc->dev, "BPMP reference NULL\n");
762 		return -ENOENT;
763 	}
764 
765 	/* Skip forwarding bw requests to BPMP from clients without bpmp_id/type. */
766 	if (pclient->type == TEGRA_ICC_NONE || !pclient->bpmp_id)
767 		return 0;
768 
769 	if (pclient->type == TEGRA_ICC_NISO)
770 		bwmgr_req.bwmgr_calc_set_req.niso_bw = src->avg_bw;
771 	else
772 		bwmgr_req.bwmgr_calc_set_req.iso_bw = src->avg_bw;
773 
774 	bwmgr_req.bwmgr_calc_set_req.client_id = pclient->bpmp_id;
775 
776 	bwmgr_req.cmd = CMD_BWMGR_INT_CALC_AND_SET;
777 	bwmgr_req.bwmgr_calc_set_req.mc_floor = src->peak_bw;
778 	bwmgr_req.bwmgr_calc_set_req.floor_unit = BWMGR_INT_UNIT_KBPS;
779 
780 	memset(&msg, 0, sizeof(msg));
781 	msg.mrq = MRQ_BWMGR_INT;
782 	msg.tx.data = &bwmgr_req;
783 	msg.tx.size = sizeof(bwmgr_req);
784 	msg.rx.data = &bwmgr_resp;
785 	msg.rx.size = sizeof(bwmgr_resp);
786 
787 	ret = tegra_bpmp_transfer(mc->bpmp, &msg);
788 	if (ret < 0) {
789 		dev_err(mc->dev, "BPMP transfer failed: %d\n", ret);
790 		goto error;
791 	}
792 	if (msg.rx.ret < 0) {
793 		pr_err("failed to set bandwidth for %u: %d\n",
794 		       bwmgr_req.bwmgr_calc_set_req.client_id, msg.rx.ret);
795 		ret = -EINVAL;
796 	}
797 
798 error:
799 	return ret;
800 }
801 
802 static int tegra264_mc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *peak)
803 {
804 	*avg = 0;
805 	*peak = 0;
806 
807 	return 0;
808 }
809 
810 static void mcf_log_fault(struct tegra_mc *mc, u32 channel, unsigned long mcf_ch_intstatus)
811 {
812 	unsigned int bit;
813 
814 	for_each_set_bit(bit, &mcf_ch_intstatus, 32) {
815 		const char *client = "unknown", *desc = "NA";
816 		u32 status_reg, status1_reg = 0, addr_reg, addr_hi_reg = 0, err_type_mask = 0;
817 		u32 value, client_id, i, addr_hi_shift = 0, addr_hi_mask = 0, status1;
818 		u32 mc_rw_bit = MC_ERR_STATUS_RW, mc_sec_bit = MC_ERR_STATUS_SECURITY;
819 		phys_addr_t addr = 0;
820 		u8 type;
821 
822 		switch (BIT(bit)) {
823 		case MC_INT_DECERR_EMEM:
824 		case MC_INT_SECURITY_VIOLATION:
825 			status_reg = mc->soc->regs->err_status;
826 			addr_reg = mc->soc->regs->err_add;
827 			addr_hi_reg = mc->soc->regs->err_add_hi;
828 			err_type_mask = mc->soc->mc_err_status_type_mask;
829 			break;
830 
831 		case MC_INT_DECERR_VPR:
832 			status_reg = mc->soc->regs->err_vpr_status;
833 			addr_reg = mc->soc->regs->err_vpr_add;
834 			addr_hi_shift = MC_ERR_STATUS_ADR_HI_SHIFT;
835 			addr_hi_mask = mc->soc->mc_addr_hi_mask;
836 			break;
837 
838 		case MC_INT_SECERR_SEC:
839 			status_reg = mc->soc->regs->err_sec_status;
840 			addr_reg = mc->soc->regs->err_sec_add;
841 			addr_hi_shift = MC_ERR_STATUS_ADR_HI_SHIFT;
842 			addr_hi_mask = mc->soc->mc_addr_hi_mask;
843 			break;
844 
845 		case MC_INT_DECERR_MTS:
846 			status_reg = mc->soc->regs->err_mts_status;
847 			addr_reg = mc->soc->regs->err_mts_add;
848 			addr_hi_shift = MC_ERR_STATUS_ADR_HI_SHIFT;
849 			addr_hi_mask = mc->soc->mc_addr_hi_mask;
850 			break;
851 
852 		case MC_INT_DECERR_GENERALIZED_CARVEOUT:
853 			status_reg = mc->soc->regs->err_gen_co_status;
854 			status1_reg = MC_ERR_GENERALIZED_CARVEOUT_STATUS_1_0;
855 			addr_reg = mc->soc->regs->err_gen_co_add;
856 			addr_hi_shift = MC_ERR_STATUS_GSC_ADR_HI_SHIFT;
857 			addr_hi_mask = MC_ERR_STATUS_GSC_ADR_HI_MASK;
858 			break;
859 
860 		case MC_INT_DECERR_ROUTE_SANITY:
861 		case MC_INT_DECERR_ROUTE_SANITY_GIC_MSI:
862 			status_reg = mc->soc->regs->err_route_status;
863 			addr_reg = mc->soc->regs->err_route_add;
864 			addr_hi_shift = MC_ERR_STATUS_RT_ADR_HI_SHIFT;
865 			addr_hi_mask = mc->soc->mc_addr_hi_mask;
866 			mc_sec_bit = MC_ERR_ROUTE_SANITY_SEC;
867 			mc_rw_bit = MC_ERR_ROUTE_SANITY_RW;
868 			err_type_mask = MC_ERR_STATUS_RT_TYPE_MASK;
869 			break;
870 
871 		default:
872 			dev_err_ratelimited(mc->dev, "Incorrect MC interrupt mask\n");
873 			return;
874 		}
875 
876 		value = mc_ch_readl(mc, channel, status_reg);
877 		if (addr_hi_reg) {
878 			addr = mc_ch_readl(mc, channel, addr_hi_reg);
879 		} else {
880 			if (!status1_reg) {
881 				addr = ((value >> addr_hi_shift) & addr_hi_mask);
882 			} else {
883 				status1 = mc_ch_readl(mc, channel, status1_reg);
884 				addr = ((status1 >> addr_hi_shift) & addr_hi_mask);
885 			}
886 		}
887 
888 		addr <<= 32;
889 		addr |= mc_ch_readl(mc, channel, addr_reg);
890 
891 		client_id = value & mc->soc->client_id_mask;
892 		for (i = 0; i < mc->soc->num_clients; i++) {
893 			if (mc->soc->clients[i].id == client_id) {
894 				client = mc->soc->clients[i].name;
895 				break;
896 			}
897 		}
898 
899 		if (err_type_mask == MC_ERR_STATUS_RT_TYPE_MASK) {
900 			type = (value & err_type_mask) >>
901 				MC_ERR_STATUS_RT_TYPE_SHIFT;
902 			desc = tegra264_rt_error_names[type];
903 		} else if (err_type_mask) {
904 			type = (value & err_type_mask) >>
905 					MC_ERR_STATUS_TYPE_SHIFT;
906 			desc = tegra264_mc_error_names[type];
907 		}
908 
909 		dev_err_ratelimited(mc->dev, "%s: %s %s @%pa: %s (%s)\n",
910 				    client, value & mc_sec_bit ? "secure" : "non-secure",
911 				    value & mc_rw_bit ? "write" : "read", &addr,
912 				    tegra_mc_status_names[bit] ?: "unknown", desc);
913 		if (status1_reg)
914 			dev_err_ratelimited(mc->dev, "gsc_apr_id=%u gsc_co_apr_id=%u\n",
915 					    ((status1 >> ERR_GENERALIZED_APERTURE_ID_SHIFT)
916 					    & ERR_GENERALIZED_APERTURE_ID_MASK),
917 					    ((status1 >> ERR_GENERALIZED_CARVEOUT_APERTURE_ID_SHIFT)
918 					    & ERR_GENERALIZED_CARVEOUT_APERTURE_ID_MASK));
919 	}
920 
921 	/* clear interrupts */
922 	mc_ch_writel(mc, channel, mcf_ch_intstatus, MCF_INTSTATUS_0);
923 }
924 
925 static irqreturn_t handle_mcf_irq(int irq, void *data)
926 {
927 	struct tegra_mc *mc = data;
928 	unsigned long common_intstat, intstatus;
929 	u32 slice;
930 
931 	/* Read MCF_COMMON_INTSTATUS0_0_0 from MCB block */
932 	common_intstat = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, MCF_COMMON_INTSTATUS0_0_0);
933 	if (common_intstat == 0) {
934 		dev_warn(mc->dev, "No interrupt in MCF\n");
935 		return IRQ_NONE;
936 	}
937 
938 	for_each_set_bit(slice, &common_intstat, 32) {
939 		/* Find out the slice number on which interrupt occurred */
940 		if (slice > 4) {
941 			dev_err(mc->dev, "Slice index out of bounds: %u\n", slice);
942 			return IRQ_NONE;
943 		}
944 
945 		intstatus = mc_ch_readl(mc, slice, MCF_INTSTATUS_0);
946 		if (intstatus != 0)
947 			mcf_log_fault(mc, slice, intstatus);
948 	}
949 
950 	return IRQ_HANDLED;
951 }
952 
953 static void hub_log_fault(struct tegra_mc *mc, u32 hub, unsigned long hub_intstat)
954 {
955 	unsigned int bit;
956 
957 	for_each_set_bit(bit, &hub_intstat, 32) {
958 		const char *client = "unknown";
959 		u32 client_id, status_reg, value, i;
960 		phys_addr_t addr = 0;
961 
962 		switch (BIT(bit)) {
963 		case MSS_HUB_COALESCER_ERR_INTMASK:
964 			status_reg = MSS_HUB_COALESCE_ERR_STATUS_0;
965 			addr = mc_ch_readl(mc, hub, MSS_HUB_COALESCE_ERR_ADR_HI_0);
966 			addr <<= 32;
967 			addr |= mc_ch_readl(mc, hub, MSS_HUB_COALESCE_ERR_ADR_0);
968 			break;
969 
970 		case MSS_HUB_SMMU_BYPASS_ALLOW_ERR_INTMASK:
971 			status_reg = MSS_HUB_SMMU_BYPASS_ALLOW_ERR_STATUS_0;
972 			break;
973 
974 		case MSS_HUB_ILLEGAL_TBUGRP_ID_INTMASK:
975 			status_reg = MSS_HUB_ILLEGAL_TBUGRP_ID_ERR_STATUS_0;
976 			break;
977 
978 		case MSS_HUB_MSI_ERR_INTMASK:
979 			status_reg = MSS_HUB_MSI_ERR_STATUS_0;
980 			break;
981 
982 		case MSS_HUB_POISON_RSP_INTMASK:
983 			status_reg = MSS_HUB_POISON_RSP_STATUS_0;
984 			break;
985 
986 		case MSS_HUB_RESTRICTED_ACCESS_ERR_INTMASK:
987 			status_reg = MSS_HUB_RESTRICTED_ACCESS_ERR_STATUS_0;
988 			break;
989 
990 		case MSS_HUB_RESERVED_PA_ERR_INTMASK:
991 			status_reg = MSS_HUB_RESERVED_PA_ERR_STATUS_0;
992 			break;
993 
994 		default:
995 			dev_err_ratelimited(mc->dev, "Incorrect HUB interrupt mask\n");
996 			return;
997 		}
998 
999 		value = mc_ch_readl(mc, hub, status_reg);
1000 
1001 		client_id = value & mc->soc->client_id_mask;
1002 		for (i = 0; i < mc->soc->num_clients; i++) {
1003 			if (mc->soc->clients[i].id == client_id) {
1004 				client = mc->soc->clients[i].name;
1005 				break;
1006 			}
1007 		}
1008 
1009 		dev_err_ratelimited(mc->dev, "%s: @%pa: %s status: 0x%x\n",
1010 				    client, &addr, tegra264_hub_error_names[bit] ?: "unknown",
1011 				    value);
1012 	}
1013 
1014 	/* clear interrupts */
1015 	mc_ch_writel(mc, hub, hub_intstat, MSS_HUB_INTRSTATUS_0);
1016 }
1017 
1018 static irqreturn_t handle_hub_irq(int irq, void *data, int mc_hubc_aperture_number)
1019 {
1020 	struct tegra_mc *mc = data;
1021 	u32 global_intstat;
1022 	unsigned long hub_interrupt, intstat, hub;
1023 
1024 	/* Read MSS_HUB_GLOBAL_INTSTATUS_0 from mc_hubc_aperture_number block */
1025 	global_intstat = mc_ch_readl(mc, mc_hubc_aperture_number, MSS_HUB_GLOBAL_INTSTATUS_0);
1026 	if (global_intstat == 0) {
1027 		dev_warn(mc->dev, "No interrupt in HUB/HUBC\n");
1028 		return IRQ_NONE;
1029 	}
1030 
1031 	/* Handle interrupt from hubc */
1032 	if (global_intstat & MSS_HUBC_INTR) {
1033 		/* Read MSS_HUB_HUBC_INTSTATUS_0 from block mc_hubc_aperture_number */
1034 		intstat = mc_ch_readl(mc, mc_hubc_aperture_number, MSS_HUB_HUBC_INTSTATUS_0);
1035 		if (intstat != 0) {
1036 			dev_err_ratelimited(mc->dev, "Scrubber operation status: 0x%lx\n",
1037 					    intstat);
1038 			/* Clear hubc interrupt */
1039 			mc_ch_writel(mc, mc_hubc_aperture_number, intstat,
1040 				     MSS_HUB_HUBC_INTSTATUS_0);
1041 		}
1042 	}
1043 
1044 	hub_interrupt = (global_intstat & MSS_HUB_GLOBAL_MASK) >> MSS_HUB_GLOBAL_SHIFT;
1045 	/* Handle interrupt from hub */
1046 	for_each_set_bit(hub, &hub_interrupt, 32) {
1047 		/* Read MSS_HUB_INTRSTATUS_0 from block MCi */
1048 		intstat = mc_ch_readl(mc, hub, MSS_HUB_INTRSTATUS_0);
1049 		if (intstat != 0)
1050 			hub_log_fault(mc, hub, intstat);
1051 	}
1052 
1053 	/* Clear global interrupt status register */
1054 	mc_ch_writel(mc, mc_hubc_aperture_number, global_intstat, MSS_HUB_GLOBAL_INTSTATUS_0);
1055 	return IRQ_HANDLED;
1056 }
1057 
1058 static irqreturn_t handle_disp_hub_irq(int irq, void *data)
1059 {
1060 	return handle_hub_irq(irq, data, mc_hubc_aperture_number[0]);
1061 }
1062 
1063 static irqreturn_t handle_system_hub_irq(int irq, void *data)
1064 {
1065 	return handle_hub_irq(irq, data, mc_hubc_aperture_number[1]);
1066 }
1067 
1068 static irqreturn_t handle_vision_hub_irq(int irq, void *data)
1069 {
1070 	return handle_hub_irq(irq, data, mc_hubc_aperture_number[2]);
1071 }
1072 
1073 static irqreturn_t handle_uphy_hub_irq(int irq, void *data)
1074 {
1075 	return handle_hub_irq(irq, data, mc_hubc_aperture_number[3]);
1076 }
1077 
1078 static irqreturn_t handle_top_hub_irq(int irq, void *data)
1079 {
1080 	return handle_hub_irq(irq, data, mc_hubc_aperture_number[4]);
1081 }
1082 
1083 static irqreturn_t handle_generic_irq(struct tegra_mc *mc, unsigned long intstat_reg)
1084 {
1085 	u32 intstat, i;
1086 
1087 	/* Iterate over all MC blocks to read INTSTATUS */
1088 	for (i = 0; i < mc->num_channels; i++) {
1089 		intstat = mc_ch_readl(mc, i, intstat_reg);
1090 		if (intstat) {
1091 			dev_err_ratelimited(mc->dev, "channel: %i status: 0x%x\n", i, intstat);
1092 			/* Clear interrupt */
1093 			mc_ch_writel(mc, i, intstat, intstat_reg);
1094 		}
1095 	}
1096 
1097 	return IRQ_HANDLED;
1098 }
1099 
1100 static irqreturn_t handle_sbs_irq(int irq, void *data)
1101 {
1102 	return handle_generic_irq((struct tegra_mc *)data, MSS_SBS_INTSTATUS_0);
1103 }
1104 
1105 static irqreturn_t handle_channel_irq(int irq, void *data)
1106 {
1107 	return handle_generic_irq((struct tegra_mc *)data, MC_CH_INTSTATUS_0);
1108 }
1109 
1110 static const irq_handler_t tegra264_mc_irq_handlers[8] = {
1111 	handle_mcf_irq, handle_disp_hub_irq, handle_vision_hub_irq,
1112 	handle_system_hub_irq, handle_uphy_hub_irq, handle_top_hub_irq,
1113 	handle_sbs_irq, handle_channel_irq
1114 };
1115 
1116 static const struct tegra_mc_icc_ops tegra264_mc_icc_ops = {
1117 	.xlate = tegra_mc_icc_xlate,
1118 	.aggregate = icc_std_aggregate,
1119 	.get_bw = tegra264_mc_icc_get_init_bw,
1120 	.set = tegra264_mc_icc_set,
1121 };
1122 
1123 static const struct tegra_mc_regs tegra264_mc_regs = {
1124 	.cfg_channel_enable = 0x8870,
1125 	.err_status = 0xbc00,
1126 	.err_add = 0xbc04,
1127 	.err_add_hi = 0xbc08,
1128 	.err_vpr_status = 0xbc20,
1129 	.err_vpr_add = 0xbc24,
1130 	.err_sec_status = 0xbc3c,
1131 	.err_sec_add = 0xbc40,
1132 	.err_mts_status = 0xbc5c,
1133 	.err_mts_add = 0xbc60,
1134 	.err_gen_co_status = 0xbc78,
1135 	.err_gen_co_add = 0xbc7c,
1136 	.err_route_status = 0xbc64,
1137 	.err_route_add = 0xbc68,
1138 };
1139 
1140 static const struct tegra_mc_intmask tegra264_mc_intmasks[] = {
1141 	{
1142 		.reg = MCF_INTMASK_0,
1143 		.mask = MC_INT_DECERR_ROUTE_SANITY_GIC_MSI | MC_INT_DECERR_ROUTE_SANITY |
1144 			MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
1145 			MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | MC_INT_SECURITY_VIOLATION |
1146 			MC_INT_DECERR_EMEM,
1147 	},
1148 	{
1149 		.reg = MCF_INTPRIORITY_0,
1150 		.mask = MC_INT_DECERR_ROUTE_SANITY_GIC_MSI | MC_INT_DECERR_ROUTE_SANITY |
1151 			MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
1152 			MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | MC_INT_SECURITY_VIOLATION |
1153 			MC_INT_DECERR_EMEM,
1154 	},
1155 	{
1156 		.reg = MSS_HUB_INTRMASK_0,
1157 		.mask = MSS_HUB_COALESCER_ERR_INTMASK | MSS_HUB_SMMU_BYPASS_ALLOW_ERR_INTMASK |
1158 			MSS_HUB_ILLEGAL_TBUGRP_ID_INTMASK | MSS_HUB_MSI_ERR_INTMASK |
1159 			MSS_HUB_POISON_RSP_INTMASK | MSS_HUB_RESTRICTED_ACCESS_ERR_INTMASK |
1160 			MSS_HUB_RESERVED_PA_ERR_INTMASK,
1161 	},
1162 	{
1163 		.reg = MSS_HUB_INTRPRIORITY_0,
1164 		.mask = MSS_HUB_COALESCER_ERR_INTMASK | MSS_HUB_SMMU_BYPASS_ALLOW_ERR_INTMASK |
1165 			MSS_HUB_ILLEGAL_TBUGRP_ID_INTMASK | MSS_HUB_MSI_ERR_INTMASK |
1166 			MSS_HUB_POISON_RSP_INTMASK | MSS_HUB_RESTRICTED_ACCESS_ERR_INTMASK |
1167 			MSS_HUB_RESERVED_PA_ERR_INTMASK,
1168 	},
1169 	{
1170 		.reg = MSS_HUB_HUBC_INTMASK_0,
1171 		.mask = MSS_HUB_HUBC_SCRUB_DONE_INTMASK,
1172 	},
1173 	{
1174 		.reg = MSS_HUB_HUBC_INTPRIORITY_0,
1175 		.mask = MSS_HUB_HUBC_SCRUB_DONE_INTMASK,
1176 	},
1177 	{
1178 		.reg = MSS_SBS_INTMASK_0,
1179 		.mask = MSS_SBS_FILL_FIFO_ISO_OVERFLOW_INTMASK |
1180 			MSS_SBS_FILL_FIFO_SISO_OVERFLOW_INTMASK |
1181 			MSS_SBS_FILL_FIFO_NISO_OVERFLOW_INTMASK,
1182 	},
1183 	{
1184 		.reg = MC_CH_INTMASK_0,
1185 		.mask = WCAM_ERR_INTMASK,
1186 	}
1187 };
1188 
1189 const struct tegra_mc_soc tegra264_mc_soc = {
1190 	.num_clients = ARRAY_SIZE(tegra264_mc_clients),
1191 	.clients = tegra264_mc_clients,
1192 	.num_address_bits = 40,
1193 	.num_channels = 16,
1194 	.client_id_mask = 0x1ff,
1195 	.intmasks = tegra264_mc_intmasks,
1196 	.num_intmasks = ARRAY_SIZE(tegra264_mc_intmasks),
1197 	.has_addr_hi_reg = true,
1198 	.ops = &tegra186_mc_ops,
1199 	.icc_ops = &tegra264_mc_icc_ops,
1200 	.ch_intmask = 0x0000ff00,
1201 	.global_intstatus_channel_shift = 8,
1202 	/*
1203 	 * Additionally, there are lite carveouts but those are not currently
1204 	 * supported.
1205 	 */
1206 	.num_carveouts = 32,
1207 	.mc_addr_hi_mask = 0xff,
1208 	.mc_err_status_type_mask = (0x3 << 28),
1209 	.regs = &tegra264_mc_regs,
1210 	.handle_irq = tegra264_mc_irq_handlers,
1211 	.num_interrupts = ARRAY_SIZE(tegra264_mc_irq_handlers),
1212 };
1213