1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2025-2026, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <dt-bindings/memory/nvidia,tegra264.h> 7 8 #include <linux/interconnect.h> 9 #include <linux/of_device.h> 10 #include <linux/tegra-icc.h> 11 12 #include <soc/tegra/bpmp.h> 13 #include <soc/tegra/mc.h> 14 15 #include "mc.h" 16 #include "tegra264-bwmgr.h" 17 18 /* 19 * MC Client entries are sorted in the increasing order of the 20 * override and security register offsets. 21 */ 22 static const struct tegra_mc_client tegra264_mc_clients[] = { 23 { 24 .id = TEGRA264_MEMORY_CLIENT_HDAR, 25 .name = "hdar", 26 .bpmp_id = TEGRA264_BWMGR_HDA, 27 .type = TEGRA_ICC_ISO_AUDIO, 28 }, { 29 .id = TEGRA264_MEMORY_CLIENT_HDAW, 30 .name = "hdaw", 31 .bpmp_id = TEGRA264_BWMGR_HDA, 32 .type = TEGRA_ICC_ISO_AUDIO, 33 }, { 34 .id = TEGRA264_MEMORY_CLIENT_MGBE0R, 35 .name = "mgbe0r", 36 .bpmp_id = TEGRA264_BWMGR_EQOS, 37 .type = TEGRA_ICC_NISO, 38 }, { 39 .id = TEGRA264_MEMORY_CLIENT_MGBE0W, 40 .name = "mgbe0w", 41 .bpmp_id = TEGRA264_BWMGR_EQOS, 42 .type = TEGRA_ICC_NISO, 43 }, { 44 .id = TEGRA264_MEMORY_CLIENT_MGBE1R, 45 .name = "mgbe1r", 46 .bpmp_id = TEGRA264_BWMGR_EQOS, 47 .type = TEGRA_ICC_NISO, 48 }, { 49 .id = TEGRA264_MEMORY_CLIENT_MGBE1W, 50 .name = "mgbe1w", 51 .bpmp_id = TEGRA264_BWMGR_EQOS, 52 .type = TEGRA_ICC_NISO, 53 }, { 54 .id = TEGRA264_MEMORY_CLIENT_SDMMC0R, 55 .name = "sdmmc0r", 56 .bpmp_id = TEGRA264_BWMGR_SDMMC_1, 57 .type = TEGRA_ICC_NISO, 58 }, { 59 .id = TEGRA264_MEMORY_CLIENT_SDMMC0W, 60 .name = "sdmmc0w", 61 .bpmp_id = TEGRA264_BWMGR_SDMMC_1, 62 .type = TEGRA_ICC_NISO, 63 }, { 64 .id = TEGRA264_MEMORY_CLIENT_VICR, 65 .name = "vicr", 66 .bpmp_id = TEGRA264_BWMGR_VIC, 67 .type = TEGRA_ICC_NISO, 68 }, { 69 .id = TEGRA264_MEMORY_CLIENT_VICW, 70 .name = "vicw", 71 .bpmp_id = TEGRA264_BWMGR_VIC, 72 .type = TEGRA_ICC_NISO, 73 }, { 74 .id = TEGRA264_MEMORY_CLIENT_APER, 75 .name = "aper", 76 .bpmp_id = TEGRA264_BWMGR_APE, 77 .type = TEGRA_ICC_ISO_AUDIO, 78 }, { 79 .id = TEGRA264_MEMORY_CLIENT_APEW, 80 .name = "apew", 81 .bpmp_id = TEGRA264_BWMGR_APE, 82 .type = TEGRA_ICC_ISO_AUDIO, 83 }, { 84 .id = TEGRA264_MEMORY_CLIENT_APEDMAR, 85 .name = "apedmar", 86 .bpmp_id = TEGRA264_BWMGR_APEDMA, 87 .type = TEGRA_ICC_ISO_AUDIO, 88 }, { 89 .id = TEGRA264_MEMORY_CLIENT_APEDMAW, 90 .name = "apedmaw", 91 .bpmp_id = TEGRA264_BWMGR_APEDMA, 92 .type = TEGRA_ICC_ISO_AUDIO, 93 }, { 94 .id = TEGRA264_MEMORY_CLIENT_VIFALCONR, 95 .name = "vifalconr", 96 .bpmp_id = TEGRA264_BWMGR_VIFAL, 97 .type = TEGRA_ICC_ISO_VIFAL, 98 }, { 99 .id = TEGRA264_MEMORY_CLIENT_VIFALCONW, 100 .name = "vifalconw", 101 .bpmp_id = TEGRA264_BWMGR_VIFAL, 102 .type = TEGRA_ICC_ISO_VIFAL, 103 }, { 104 .id = TEGRA264_MEMORY_CLIENT_RCER, 105 .name = "rcer", 106 .bpmp_id = TEGRA264_BWMGR_RCE, 107 .type = TEGRA_ICC_NISO, 108 }, { 109 .id = TEGRA264_MEMORY_CLIENT_RCEW, 110 .name = "rcew", 111 .bpmp_id = TEGRA264_BWMGR_RCE, 112 .type = TEGRA_ICC_NISO, 113 }, { 114 .id = TEGRA264_MEMORY_CLIENT_PCIE0W, 115 .name = "pcie0w", 116 .bpmp_id = TEGRA264_BWMGR_PCIE_0, 117 .type = TEGRA_ICC_NISO, 118 }, { 119 .id = TEGRA264_MEMORY_CLIENT_PCIE1R, 120 .name = "pcie1r", 121 .bpmp_id = TEGRA264_BWMGR_PCIE_1, 122 .type = TEGRA_ICC_NISO, 123 }, { 124 .id = TEGRA264_MEMORY_CLIENT_PCIE1W, 125 .name = "pcie1w", 126 .bpmp_id = TEGRA264_BWMGR_PCIE_1, 127 .type = TEGRA_ICC_NISO, 128 }, { 129 .id = TEGRA264_MEMORY_CLIENT_PCIE2AR, 130 .name = "pcie2ar", 131 .bpmp_id = TEGRA264_BWMGR_PCIE_2, 132 .type = TEGRA_ICC_NISO, 133 }, { 134 .id = TEGRA264_MEMORY_CLIENT_PCIE2AW, 135 .name = "pcie2aw", 136 .bpmp_id = TEGRA264_BWMGR_PCIE_2, 137 .type = TEGRA_ICC_NISO, 138 }, { 139 .id = TEGRA264_MEMORY_CLIENT_PCIE3R, 140 .name = "pcie3r", 141 .bpmp_id = TEGRA264_BWMGR_PCIE_3, 142 .type = TEGRA_ICC_NISO, 143 }, { 144 .id = TEGRA264_MEMORY_CLIENT_PCIE3W, 145 .name = "pcie3w", 146 .bpmp_id = TEGRA264_BWMGR_PCIE_3, 147 .type = TEGRA_ICC_NISO, 148 }, { 149 .id = TEGRA264_MEMORY_CLIENT_PCIE4R, 150 .name = "pcie4r", 151 .bpmp_id = TEGRA264_BWMGR_PCIE_4, 152 .type = TEGRA_ICC_NISO, 153 }, { 154 .id = TEGRA264_MEMORY_CLIENT_PCIE4W, 155 .name = "pcie4w", 156 .bpmp_id = TEGRA264_BWMGR_PCIE_4, 157 .type = TEGRA_ICC_NISO, 158 }, { 159 .id = TEGRA264_MEMORY_CLIENT_PCIE5R, 160 .name = "pcie5r", 161 .bpmp_id = TEGRA264_BWMGR_PCIE_5, 162 .type = TEGRA_ICC_NISO, 163 }, { 164 .id = TEGRA264_MEMORY_CLIENT_PCIE5W, 165 .name = "pcie5w", 166 .bpmp_id = TEGRA264_BWMGR_PCIE_5, 167 .type = TEGRA_ICC_NISO, 168 }, { 169 .id = TEGRA264_MEMORY_CLIENT_GPUR02MC, 170 .name = "gpur02mc", 171 .bpmp_id = TEGRA264_BWMGR_GPU, 172 .type = TEGRA_ICC_NISO, 173 }, { 174 .id = TEGRA264_MEMORY_CLIENT_GPUW02MC, 175 .name = "gpuw02mc", 176 .bpmp_id = TEGRA264_BWMGR_GPU, 177 .type = TEGRA_ICC_NISO, 178 }, { 179 .id = TEGRA264_MEMORY_CLIENT_NVDECSRD2MC, 180 .name = "nvdecsrd2mc", 181 .bpmp_id = TEGRA264_BWMGR_NVDEC, 182 .type = TEGRA_ICC_NISO, 183 }, { 184 .id = TEGRA264_MEMORY_CLIENT_NVDECSWR2MC, 185 .name = "nvdecswr2mc", 186 .bpmp_id = TEGRA264_BWMGR_NVDEC, 187 .type = TEGRA_ICC_NISO, 188 }, 189 }; 190 191 static const char *const tegra264_hub_error_names[32] = { 192 [0] = "coalescer error", 193 [1] = "SMMU BYPASS ALLOW error", 194 [2] = "Illegal tbugrp_id error", 195 [3] = "Malformed MSI request error", 196 [4] = "Read response with poison bit error", 197 [5] = "Restricted access violation error", 198 [6] = "Reserved PA error", 199 }; 200 201 static const char *const tegra264_mc_error_names[4] = { 202 [1] = "EMEM decode error", 203 [2] = "TrustZone violation", 204 [3] = "Carveout violation", 205 }; 206 207 static const char *const tegra264_rt_error_names[16] = { 208 [1] = "DECERR_PARTIAL_POPULATED", 209 [2] = "DECERR_SMMU_BYPASS", 210 [3] = "DECERR_INVALID_MMIO", 211 [4] = "DECERR_INVALID_GIC_MSI", 212 [5] = "DECERR_ATOMIC_SYSRAM", 213 [9] = "DECERR_REMOTE_REQ_PRE_BOOT", 214 [10] = "DECERR_ISO_OVER_C2C", 215 [11] = "DECERR_UNSUPPORTED_SBS_OPCODE", 216 [12] = "DECERR_SBS_REQ_OVER_SISO_LL", 217 }; 218 219 /* 220 * MC instance aperture mapping for hubc registers 221 */ 222 static const int mc_hubc_aperture_number[5] = { 223 7, 8, 9, 10, 11 224 }; 225 226 /* 227 * tegra264_mc_icc_set() - Pass MC client info to the BPMP-FW 228 * @src: ICC node for Memory Controller's (MC) Client 229 * @dst: ICC node for Memory Controller (MC) 230 * 231 * Passing the current request info from the MC to the BPMP-FW where 232 * LA and PTSA registers are accessed and the final EMC freq is set 233 * based on client_id, type, latency and bandwidth. 234 * icc_set_bw() makes set_bw calls for both MC and EMC providers in 235 * sequence. Both the calls are protected by 'mutex_lock(&icc_lock)'. 236 * So, the data passed won't be updated by concurrent set calls from 237 * other clients. 238 */ 239 static int tegra264_mc_icc_set(struct icc_node *src, struct icc_node *dst) 240 { 241 struct tegra_mc *mc = icc_provider_to_tegra_mc(dst->provider); 242 struct mrq_bwmgr_int_request bwmgr_req = { 0 }; 243 struct mrq_bwmgr_int_response bwmgr_resp = { 0 }; 244 const struct tegra_mc_client *pclient = src->data; 245 struct tegra_bpmp_message msg; 246 int ret; 247 248 /* 249 * Same Src and Dst node will happen during boot from icc_node_add(). 250 * This can be used to pre-initialize and set bandwidth for all clients 251 * before their drivers are loaded. We are skipping this case as for us, 252 * the pre-initialization already happened in Bootloader(MB2) and BPMP-FW. 253 */ 254 if (src->id == dst->id) 255 return 0; 256 257 if (!mc->bwmgr_mrq_supported) 258 return 0; 259 260 if (!mc->bpmp) { 261 dev_err(mc->dev, "BPMP reference NULL\n"); 262 return -ENOENT; 263 } 264 265 /* Skip forwarding bw requests to BPMP from clients without bpmp_id/type. */ 266 if (pclient->type == TEGRA_ICC_NONE || !pclient->bpmp_id) 267 return 0; 268 269 if (pclient->type == TEGRA_ICC_NISO) 270 bwmgr_req.bwmgr_calc_set_req.niso_bw = src->avg_bw; 271 else 272 bwmgr_req.bwmgr_calc_set_req.iso_bw = src->avg_bw; 273 274 bwmgr_req.bwmgr_calc_set_req.client_id = pclient->bpmp_id; 275 276 bwmgr_req.cmd = CMD_BWMGR_INT_CALC_AND_SET; 277 bwmgr_req.bwmgr_calc_set_req.mc_floor = src->peak_bw; 278 bwmgr_req.bwmgr_calc_set_req.floor_unit = BWMGR_INT_UNIT_KBPS; 279 280 memset(&msg, 0, sizeof(msg)); 281 msg.mrq = MRQ_BWMGR_INT; 282 msg.tx.data = &bwmgr_req; 283 msg.tx.size = sizeof(bwmgr_req); 284 msg.rx.data = &bwmgr_resp; 285 msg.rx.size = sizeof(bwmgr_resp); 286 287 ret = tegra_bpmp_transfer(mc->bpmp, &msg); 288 if (ret < 0) { 289 dev_err(mc->dev, "BPMP transfer failed: %d\n", ret); 290 goto error; 291 } 292 if (msg.rx.ret < 0) { 293 pr_err("failed to set bandwidth for %u: %d\n", 294 bwmgr_req.bwmgr_calc_set_req.client_id, msg.rx.ret); 295 ret = -EINVAL; 296 } 297 298 error: 299 return ret; 300 } 301 302 static int tegra264_mc_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw, 303 u32 peak_bw, u32 *agg_avg, u32 *agg_peak) 304 { 305 struct icc_provider *p = node->provider; 306 struct tegra_mc *mc = icc_provider_to_tegra_mc(p); 307 308 if (!mc->bwmgr_mrq_supported) 309 return 0; 310 311 *agg_avg += avg_bw; 312 *agg_peak = max(*agg_peak, peak_bw); 313 314 return 0; 315 } 316 317 static int tegra264_mc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *peak) 318 { 319 *avg = 0; 320 *peak = 0; 321 322 return 0; 323 } 324 325 static void mcf_log_fault(struct tegra_mc *mc, u32 channel, unsigned long mcf_ch_intstatus) 326 { 327 unsigned int bit; 328 329 for_each_set_bit(bit, &mcf_ch_intstatus, 32) { 330 const char *client = "unknown", *desc = "NA"; 331 u32 status_reg, status1_reg = 0, addr_reg, addr_hi_reg = 0, err_type_mask = 0; 332 u32 value, client_id, i, addr_hi_shift = 0, addr_hi_mask = 0, status1; 333 u32 mc_rw_bit = MC_ERR_STATUS_RW, mc_sec_bit = MC_ERR_STATUS_SECURITY; 334 phys_addr_t addr = 0; 335 u8 type; 336 337 switch (BIT(bit)) { 338 case MC_INT_DECERR_EMEM: 339 case MC_INT_SECURITY_VIOLATION: 340 status_reg = mc->soc->regs->err_status; 341 addr_reg = mc->soc->regs->err_add; 342 addr_hi_reg = mc->soc->regs->err_add_hi; 343 err_type_mask = mc->soc->mc_err_status_type_mask; 344 break; 345 346 case MC_INT_DECERR_VPR: 347 status_reg = mc->soc->regs->err_vpr_status; 348 addr_reg = mc->soc->regs->err_vpr_add; 349 addr_hi_shift = MC_ERR_STATUS_ADR_HI_SHIFT; 350 addr_hi_mask = mc->soc->mc_addr_hi_mask; 351 break; 352 353 case MC_INT_SECERR_SEC: 354 status_reg = mc->soc->regs->err_sec_status; 355 addr_reg = mc->soc->regs->err_sec_add; 356 addr_hi_shift = MC_ERR_STATUS_ADR_HI_SHIFT; 357 addr_hi_mask = mc->soc->mc_addr_hi_mask; 358 break; 359 360 case MC_INT_DECERR_MTS: 361 status_reg = mc->soc->regs->err_mts_status; 362 addr_reg = mc->soc->regs->err_mts_add; 363 addr_hi_shift = MC_ERR_STATUS_ADR_HI_SHIFT; 364 addr_hi_mask = mc->soc->mc_addr_hi_mask; 365 break; 366 367 case MC_INT_DECERR_GENERALIZED_CARVEOUT: 368 status_reg = mc->soc->regs->err_gen_co_status; 369 status1_reg = MC_ERR_GENERALIZED_CARVEOUT_STATUS_1_0; 370 addr_reg = mc->soc->regs->err_gen_co_add; 371 addr_hi_shift = MC_ERR_STATUS_GSC_ADR_HI_SHIFT; 372 addr_hi_mask = MC_ERR_STATUS_GSC_ADR_HI_MASK; 373 break; 374 375 case MC_INT_DECERR_ROUTE_SANITY: 376 case MC_INT_DECERR_ROUTE_SANITY_GIC_MSI: 377 status_reg = mc->soc->regs->err_route_status; 378 addr_reg = mc->soc->regs->err_route_add; 379 addr_hi_shift = MC_ERR_STATUS_RT_ADR_HI_SHIFT; 380 addr_hi_mask = mc->soc->mc_addr_hi_mask; 381 mc_sec_bit = MC_ERR_ROUTE_SANITY_SEC; 382 mc_rw_bit = MC_ERR_ROUTE_SANITY_RW; 383 err_type_mask = MC_ERR_STATUS_RT_TYPE_MASK; 384 break; 385 386 default: 387 dev_err_ratelimited(mc->dev, "Incorrect MC interrupt mask\n"); 388 return; 389 } 390 391 value = mc_ch_readl(mc, channel, status_reg); 392 if (addr_hi_reg) { 393 addr = mc_ch_readl(mc, channel, addr_hi_reg); 394 } else { 395 if (!status1_reg) { 396 addr = ((value >> addr_hi_shift) & addr_hi_mask); 397 } else { 398 status1 = mc_ch_readl(mc, channel, status1_reg); 399 addr = ((status1 >> addr_hi_shift) & addr_hi_mask); 400 } 401 } 402 403 addr <<= 32; 404 addr |= mc_ch_readl(mc, channel, addr_reg); 405 406 client_id = value & mc->soc->client_id_mask; 407 for (i = 0; i < mc->soc->num_clients; i++) { 408 if (mc->soc->clients[i].id == client_id) { 409 client = mc->soc->clients[i].name; 410 break; 411 } 412 } 413 414 if (err_type_mask == MC_ERR_STATUS_RT_TYPE_MASK) { 415 type = (value & err_type_mask) >> 416 MC_ERR_STATUS_RT_TYPE_SHIFT; 417 desc = tegra264_rt_error_names[type]; 418 } else if (err_type_mask) { 419 type = (value & err_type_mask) >> 420 MC_ERR_STATUS_TYPE_SHIFT; 421 desc = tegra264_mc_error_names[type]; 422 } 423 424 dev_err_ratelimited(mc->dev, "%s: %s %s @%pa: %s (%s)\n", 425 client, value & mc_sec_bit ? "secure" : "non-secure", 426 value & mc_rw_bit ? "write" : "read", &addr, 427 tegra_mc_status_names[bit] ?: "unknown", desc); 428 if (status1_reg) 429 dev_err_ratelimited(mc->dev, "gsc_apr_id=%u gsc_co_apr_id=%u\n", 430 ((status1 >> ERR_GENERALIZED_APERTURE_ID_SHIFT) 431 & ERR_GENERALIZED_APERTURE_ID_MASK), 432 ((status1 >> ERR_GENERALIZED_CARVEOUT_APERTURE_ID_SHIFT) 433 & ERR_GENERALIZED_CARVEOUT_APERTURE_ID_MASK)); 434 } 435 436 /* clear interrupts */ 437 mc_ch_writel(mc, channel, mcf_ch_intstatus, MCF_INTSTATUS_0); 438 } 439 440 static irqreturn_t handle_mcf_irq(int irq, void *data) 441 { 442 struct tegra_mc *mc = data; 443 unsigned long common_intstat, intstatus; 444 u32 slice; 445 446 /* Read MCF_COMMON_INTSTATUS0_0_0 from MCB block */ 447 common_intstat = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, MCF_COMMON_INTSTATUS0_0_0); 448 if (common_intstat == 0) { 449 dev_warn(mc->dev, "No interrupt in MCF\n"); 450 return IRQ_NONE; 451 } 452 453 for_each_set_bit(slice, &common_intstat, 32) { 454 /* Find out the slice number on which interrupt occurred */ 455 if (slice > 4) { 456 dev_err(mc->dev, "Slice index out of bounds: %u\n", slice); 457 return IRQ_NONE; 458 } 459 460 intstatus = mc_ch_readl(mc, slice, MCF_INTSTATUS_0); 461 if (intstatus != 0) 462 mcf_log_fault(mc, slice, intstatus); 463 } 464 465 return IRQ_HANDLED; 466 } 467 468 static void hub_log_fault(struct tegra_mc *mc, u32 hub, unsigned long hub_intstat) 469 { 470 unsigned int bit; 471 472 for_each_set_bit(bit, &hub_intstat, 32) { 473 const char *client = "unknown"; 474 u32 client_id, status_reg, value, i; 475 phys_addr_t addr = 0; 476 477 switch (BIT(bit)) { 478 case MSS_HUB_COALESCER_ERR_INTMASK: 479 status_reg = MSS_HUB_COALESCE_ERR_STATUS_0; 480 addr = mc_ch_readl(mc, hub, MSS_HUB_COALESCE_ERR_ADR_HI_0); 481 addr <<= 32; 482 addr |= mc_ch_readl(mc, hub, MSS_HUB_COALESCE_ERR_ADR_0); 483 break; 484 485 case MSS_HUB_SMMU_BYPASS_ALLOW_ERR_INTMASK: 486 status_reg = MSS_HUB_SMMU_BYPASS_ALLOW_ERR_STATUS_0; 487 break; 488 489 case MSS_HUB_ILLEGAL_TBUGRP_ID_INTMASK: 490 status_reg = MSS_HUB_ILLEGAL_TBUGRP_ID_ERR_STATUS_0; 491 break; 492 493 case MSS_HUB_MSI_ERR_INTMASK: 494 status_reg = MSS_HUB_MSI_ERR_STATUS_0; 495 break; 496 497 case MSS_HUB_POISON_RSP_INTMASK: 498 status_reg = MSS_HUB_POISON_RSP_STATUS_0; 499 break; 500 501 case MSS_HUB_RESTRICTED_ACCESS_ERR_INTMASK: 502 status_reg = MSS_HUB_RESTRICTED_ACCESS_ERR_STATUS_0; 503 break; 504 505 case MSS_HUB_RESERVED_PA_ERR_INTMASK: 506 status_reg = MSS_HUB_RESERVED_PA_ERR_STATUS_0; 507 break; 508 509 default: 510 dev_err_ratelimited(mc->dev, "Incorrect HUB interrupt mask\n"); 511 return; 512 } 513 514 value = mc_ch_readl(mc, hub, status_reg); 515 516 client_id = value & mc->soc->client_id_mask; 517 for (i = 0; i < mc->soc->num_clients; i++) { 518 if (mc->soc->clients[i].id == client_id) { 519 client = mc->soc->clients[i].name; 520 break; 521 } 522 } 523 524 dev_err_ratelimited(mc->dev, "%s: @%pa: %s status: 0x%x\n", 525 client, &addr, tegra264_hub_error_names[bit] ?: "unknown", 526 value); 527 } 528 529 /* clear interrupts */ 530 mc_ch_writel(mc, hub, hub_intstat, MSS_HUB_INTRSTATUS_0); 531 } 532 533 static irqreturn_t handle_hub_irq(int irq, void *data, int mc_hubc_aperture_number) 534 { 535 struct tegra_mc *mc = data; 536 u32 global_intstat; 537 unsigned long hub_interrupt, intstat, hub; 538 539 /* Read MSS_HUB_GLOBAL_INTSTATUS_0 from mc_hubc_aperture_number block */ 540 global_intstat = mc_ch_readl(mc, mc_hubc_aperture_number, MSS_HUB_GLOBAL_INTSTATUS_0); 541 if (global_intstat == 0) { 542 dev_warn(mc->dev, "No interrupt in HUB/HUBC\n"); 543 return IRQ_NONE; 544 } 545 546 /* Handle interrupt from hubc */ 547 if (global_intstat & MSS_HUBC_INTR) { 548 /* Read MSS_HUB_HUBC_INTSTATUS_0 from block mc_hubc_aperture_number */ 549 intstat = mc_ch_readl(mc, mc_hubc_aperture_number, MSS_HUB_HUBC_INTSTATUS_0); 550 if (intstat != 0) { 551 dev_err_ratelimited(mc->dev, "Scrubber operation status: 0x%lx\n", 552 intstat); 553 /* Clear hubc interrupt */ 554 mc_ch_writel(mc, mc_hubc_aperture_number, intstat, 555 MSS_HUB_HUBC_INTSTATUS_0); 556 } 557 } 558 559 hub_interrupt = (global_intstat & MSS_HUB_GLOBAL_MASK) >> MSS_HUB_GLOBAL_SHIFT; 560 /* Handle interrupt from hub */ 561 for_each_set_bit(hub, &hub_interrupt, 32) { 562 /* Read MSS_HUB_INTRSTATUS_0 from block MCi */ 563 intstat = mc_ch_readl(mc, hub, MSS_HUB_INTRSTATUS_0); 564 if (intstat != 0) 565 hub_log_fault(mc, hub, intstat); 566 } 567 568 /* Clear global interrupt status register */ 569 mc_ch_writel(mc, mc_hubc_aperture_number, global_intstat, MSS_HUB_GLOBAL_INTSTATUS_0); 570 return IRQ_HANDLED; 571 } 572 573 static irqreturn_t handle_disp_hub_irq(int irq, void *data) 574 { 575 return handle_hub_irq(irq, data, mc_hubc_aperture_number[0]); 576 } 577 578 static irqreturn_t handle_system_hub_irq(int irq, void *data) 579 { 580 return handle_hub_irq(irq, data, mc_hubc_aperture_number[1]); 581 } 582 583 static irqreturn_t handle_vision_hub_irq(int irq, void *data) 584 { 585 return handle_hub_irq(irq, data, mc_hubc_aperture_number[2]); 586 } 587 588 static irqreturn_t handle_uphy_hub_irq(int irq, void *data) 589 { 590 return handle_hub_irq(irq, data, mc_hubc_aperture_number[3]); 591 } 592 593 static irqreturn_t handle_top_hub_irq(int irq, void *data) 594 { 595 return handle_hub_irq(irq, data, mc_hubc_aperture_number[4]); 596 } 597 598 static irqreturn_t handle_generic_irq(struct tegra_mc *mc, unsigned long intstat_reg) 599 { 600 u32 intstat, i; 601 602 /* Iterate over all MC blocks to read INTSTATUS */ 603 for (i = 0; i < mc->num_channels; i++) { 604 intstat = mc_ch_readl(mc, i, intstat_reg); 605 if (intstat) { 606 dev_err_ratelimited(mc->dev, "channel: %i status: 0x%x\n", i, intstat); 607 /* Clear interrupt */ 608 mc_ch_writel(mc, i, intstat, intstat_reg); 609 } 610 } 611 612 return IRQ_HANDLED; 613 } 614 615 static irqreturn_t handle_sbs_irq(int irq, void *data) 616 { 617 return handle_generic_irq((struct tegra_mc *)data, MSS_SBS_INTSTATUS_0); 618 } 619 620 static irqreturn_t handle_channel_irq(int irq, void *data) 621 { 622 return handle_generic_irq((struct tegra_mc *)data, MC_CH_INTSTATUS_0); 623 } 624 625 static const irq_handler_t tegra264_mc_irq_handlers[8] = { 626 handle_mcf_irq, handle_disp_hub_irq, handle_vision_hub_irq, 627 handle_system_hub_irq, handle_uphy_hub_irq, handle_top_hub_irq, 628 handle_sbs_irq, handle_channel_irq 629 }; 630 631 static const struct tegra_mc_icc_ops tegra264_mc_icc_ops = { 632 .xlate = tegra_mc_icc_xlate, 633 .aggregate = tegra264_mc_icc_aggregate, 634 .get_bw = tegra264_mc_icc_get_init_bw, 635 .set = tegra264_mc_icc_set, 636 }; 637 638 static const struct tegra_mc_regs tegra264_mc_regs = { 639 .cfg_channel_enable = 0x8870, 640 .err_status = 0xbc00, 641 .err_add = 0xbc04, 642 .err_add_hi = 0xbc08, 643 .err_vpr_status = 0xbc20, 644 .err_vpr_add = 0xbc24, 645 .err_sec_status = 0xbc3c, 646 .err_sec_add = 0xbc40, 647 .err_mts_status = 0xbc5c, 648 .err_mts_add = 0xbc60, 649 .err_gen_co_status = 0xbc78, 650 .err_gen_co_add = 0xbc7c, 651 .err_route_status = 0xbc64, 652 .err_route_add = 0xbc68, 653 }; 654 655 static const struct tegra_mc_intmask tegra264_mc_intmasks[] = { 656 { 657 .reg = MCF_INTMASK_0, 658 .mask = MC_INT_DECERR_ROUTE_SANITY_GIC_MSI | MC_INT_DECERR_ROUTE_SANITY | 659 MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | 660 MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | MC_INT_SECURITY_VIOLATION | 661 MC_INT_DECERR_EMEM, 662 }, 663 { 664 .reg = MCF_INTPRIORITY_0, 665 .mask = MC_INT_DECERR_ROUTE_SANITY_GIC_MSI | MC_INT_DECERR_ROUTE_SANITY | 666 MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | 667 MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | MC_INT_SECURITY_VIOLATION | 668 MC_INT_DECERR_EMEM, 669 }, 670 { 671 .reg = MSS_HUB_INTRMASK_0, 672 .mask = MSS_HUB_COALESCER_ERR_INTMASK | MSS_HUB_SMMU_BYPASS_ALLOW_ERR_INTMASK | 673 MSS_HUB_ILLEGAL_TBUGRP_ID_INTMASK | MSS_HUB_MSI_ERR_INTMASK | 674 MSS_HUB_POISON_RSP_INTMASK | MSS_HUB_RESTRICTED_ACCESS_ERR_INTMASK | 675 MSS_HUB_RESERVED_PA_ERR_INTMASK, 676 }, 677 { 678 .reg = MSS_HUB_INTRPRIORITY_0, 679 .mask = MSS_HUB_COALESCER_ERR_INTMASK | MSS_HUB_SMMU_BYPASS_ALLOW_ERR_INTMASK | 680 MSS_HUB_ILLEGAL_TBUGRP_ID_INTMASK | MSS_HUB_MSI_ERR_INTMASK | 681 MSS_HUB_POISON_RSP_INTMASK | MSS_HUB_RESTRICTED_ACCESS_ERR_INTMASK | 682 MSS_HUB_RESERVED_PA_ERR_INTMASK, 683 }, 684 { 685 .reg = MSS_HUB_HUBC_INTMASK_0, 686 .mask = MSS_HUB_HUBC_SCRUB_DONE_INTMASK, 687 }, 688 { 689 .reg = MSS_HUB_HUBC_INTPRIORITY_0, 690 .mask = MSS_HUB_HUBC_SCRUB_DONE_INTMASK, 691 }, 692 { 693 .reg = MSS_SBS_INTMASK_0, 694 .mask = MSS_SBS_FILL_FIFO_ISO_OVERFLOW_INTMASK | 695 MSS_SBS_FILL_FIFO_SISO_OVERFLOW_INTMASK | 696 MSS_SBS_FILL_FIFO_NISO_OVERFLOW_INTMASK, 697 }, 698 { 699 .reg = MC_CH_INTMASK_0, 700 .mask = WCAM_ERR_INTMASK, 701 } 702 }; 703 704 const struct tegra_mc_soc tegra264_mc_soc = { 705 .num_clients = ARRAY_SIZE(tegra264_mc_clients), 706 .clients = tegra264_mc_clients, 707 .num_address_bits = 40, 708 .num_channels = 16, 709 .client_id_mask = 0x1ff, 710 .intmasks = tegra264_mc_intmasks, 711 .num_intmasks = ARRAY_SIZE(tegra264_mc_intmasks), 712 .has_addr_hi_reg = true, 713 .ops = &tegra186_mc_ops, 714 .icc_ops = &tegra264_mc_icc_ops, 715 .ch_intmask = 0x0000ff00, 716 .global_intstatus_channel_shift = 8, 717 /* 718 * Additionally, there are lite carveouts but those are not currently 719 * supported. 720 */ 721 .num_carveouts = 32, 722 .mc_addr_hi_mask = 0xff, 723 .mc_err_status_type_mask = (0x3 << 28), 724 .regs = &tegra264_mc_regs, 725 .handle_irq = tegra264_mc_irq_handlers, 726 .num_interrupts = ARRAY_SIZE(tegra264_mc_irq_handlers), 727 }; 728