xref: /linux/drivers/memory/tegra/tegra234.c (revision c02ce1735b150cf7c3b43790b48e23dcd17c0d46) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2022-2023, NVIDIA CORPORATION.  All rights reserved.
4  */
5 
6 #include <soc/tegra/mc.h>
7 
8 #include <dt-bindings/memory/tegra234-mc.h>
9 #include <linux/interconnect.h>
10 #include <linux/tegra-icc.h>
11 
12 #include <soc/tegra/bpmp.h>
13 #include "mc.h"
14 
15 /*
16  * MC Client entries are sorted in the increasing order of the
17  * override and security register offsets.
18  */
19 static const struct tegra_mc_client tegra234_mc_clients[] = {
20 	{
21 		.id = TEGRA234_MEMORY_CLIENT_HDAR,
22 		.name = "hdar",
23 		.bpmp_id = TEGRA_ICC_BPMP_HDA,
24 		.type = TEGRA_ICC_ISO_AUDIO,
25 		.sid = TEGRA234_SID_HDA,
26 		.regs = {
27 			.sid = {
28 				.override = 0xa8,
29 				.security = 0xac,
30 			},
31 		},
32 	}, {
33 		.id = TEGRA234_MEMORY_CLIENT_NVENCSRD,
34 		.name = "nvencsrd",
35 		.bpmp_id = TEGRA_ICC_BPMP_NVENC,
36 		.type = TEGRA_ICC_NISO,
37 		.sid = TEGRA234_SID_NVENC,
38 		.regs = {
39 			.sid = {
40 				.override = 0xe0,
41 				.security = 0xe4,
42 			},
43 		},
44 	}, {
45 		.id = TEGRA234_MEMORY_CLIENT_PCIE6AR,
46 		.name = "pcie6ar",
47 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
48 		.type = TEGRA_ICC_NISO,
49 		.sid = TEGRA234_SID_PCIE6,
50 		.regs = {
51 			.sid = {
52 				.override = 0x140,
53 				.security = 0x144,
54 			},
55 		},
56 	}, {
57 		.id = TEGRA234_MEMORY_CLIENT_PCIE6AW,
58 		.name = "pcie6aw",
59 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
60 		.type = TEGRA_ICC_NISO,
61 		.sid = TEGRA234_SID_PCIE6,
62 		.regs = {
63 			.sid = {
64 				.override = 0x148,
65 				.security = 0x14c,
66 			},
67 		},
68 	}, {
69 		.id = TEGRA234_MEMORY_CLIENT_PCIE7AR,
70 		.name = "pcie7ar",
71 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
72 		.type = TEGRA_ICC_NISO,
73 		.sid = TEGRA234_SID_PCIE7,
74 		.regs = {
75 			.sid = {
76 				.override = 0x150,
77 				.security = 0x154,
78 			},
79 		},
80 	}, {
81 		.id = TEGRA234_MEMORY_CLIENT_NVENCSWR,
82 		.name = "nvencswr",
83 		.bpmp_id = TEGRA_ICC_BPMP_NVENC,
84 		.type = TEGRA_ICC_NISO,
85 		.sid = TEGRA234_SID_NVENC,
86 		.regs = {
87 			.sid = {
88 				.override = 0x158,
89 				.security = 0x15c,
90 			},
91 		},
92 	}, {
93 		.id = TEGRA234_MEMORY_CLIENT_DLA0RDB,
94 		.name = "dla0rdb",
95 		.bpmp_id = TEGRA_ICC_BPMP_DLA_0,
96 		.type = TEGRA_ICC_NISO,
97 		.sid = TEGRA234_SID_NVDLA0,
98 		.regs = {
99 			.sid = {
100 				.override = 0x160,
101 				.security = 0x164,
102 			},
103 		},
104 	}, {
105 		.id = TEGRA234_MEMORY_CLIENT_DLA0RDB1,
106 		.name = "dla0rdb1",
107 		.bpmp_id = TEGRA_ICC_BPMP_DLA_0,
108 		.type = TEGRA_ICC_NISO,
109 		.sid = TEGRA234_SID_NVDLA0,
110 		.regs = {
111 			.sid = {
112 				.override = 0x168,
113 				.security = 0x16c,
114 			},
115 		},
116 	}, {
117 		.id = TEGRA234_MEMORY_CLIENT_DLA0WRB,
118 		.name = "dla0wrb",
119 		.bpmp_id = TEGRA_ICC_BPMP_DLA_0,
120 		.type = TEGRA_ICC_NISO,
121 		.sid = TEGRA234_SID_NVDLA0,
122 		.regs = {
123 			.sid = {
124 				.override = 0x170,
125 				.security = 0x174,
126 			},
127 		},
128 	}, {
129 		.id = TEGRA234_MEMORY_CLIENT_DLA1RDB,
130 		.name = "dla1rdb",
131 		.bpmp_id = TEGRA_ICC_BPMP_DLA_1,
132 		.type = TEGRA_ICC_NISO,
133 		.sid = TEGRA234_SID_NVDLA1,
134 		.regs = {
135 			.sid = {
136 				.override = 0x178,
137 				.security = 0x17c,
138 			},
139 		},
140 	}, {
141 		.id = TEGRA234_MEMORY_CLIENT_PCIE7AW,
142 		.name = "pcie7aw",
143 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
144 		.type = TEGRA_ICC_NISO,
145 		.sid = TEGRA234_SID_PCIE7,
146 		.regs = {
147 			.sid = {
148 				.override = 0x180,
149 				.security = 0x184,
150 			},
151 		},
152 	}, {
153 		.id = TEGRA234_MEMORY_CLIENT_PCIE8AR,
154 		.name = "pcie8ar",
155 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
156 		.type = TEGRA_ICC_NISO,
157 		.sid = TEGRA234_SID_PCIE8,
158 		.regs = {
159 			.sid = {
160 				.override = 0x190,
161 				.security = 0x194,
162 			},
163 		},
164 	}, {
165 		.id = TEGRA234_MEMORY_CLIENT_HDAW,
166 		.name = "hdaw",
167 		.bpmp_id = TEGRA_ICC_BPMP_HDA,
168 		.type = TEGRA_ICC_ISO_AUDIO,
169 		.sid = TEGRA234_SID_HDA,
170 		.regs = {
171 			.sid = {
172 				.override = 0x1a8,
173 				.security = 0x1ac,
174 			},
175 		},
176 	}, {
177 		.id = TEGRA234_MEMORY_CLIENT_PCIE8AW,
178 		.name = "pcie8aw",
179 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
180 		.type = TEGRA_ICC_NISO,
181 		.sid = TEGRA234_SID_PCIE8,
182 		.regs = {
183 			.sid = {
184 				.override = 0x1d8,
185 				.security = 0x1dc,
186 			},
187 		},
188 	}, {
189 		.id = TEGRA234_MEMORY_CLIENT_PCIE9AR,
190 		.name = "pcie9ar",
191 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
192 		.type = TEGRA_ICC_NISO,
193 		.sid = TEGRA234_SID_PCIE9,
194 		.regs = {
195 			.sid = {
196 				.override = 0x1e0,
197 				.security = 0x1e4,
198 			},
199 		},
200 	}, {
201 		.id = TEGRA234_MEMORY_CLIENT_PCIE6AR1,
202 		.name = "pcie6ar1",
203 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
204 		.type = TEGRA_ICC_NISO,
205 		.sid = TEGRA234_SID_PCIE6,
206 		.regs = {
207 			.sid = {
208 				.override = 0x1e8,
209 				.security = 0x1ec,
210 			},
211 		},
212 	}, {
213 		.id = TEGRA234_MEMORY_CLIENT_PCIE9AW,
214 		.name = "pcie9aw",
215 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
216 		.type = TEGRA_ICC_NISO,
217 		.sid = TEGRA234_SID_PCIE9,
218 		.regs = {
219 			.sid = {
220 				.override = 0x1f0,
221 				.security = 0x1f4,
222 			},
223 		},
224 	}, {
225 		.id = TEGRA234_MEMORY_CLIENT_PCIE10AR,
226 		.name = "pcie10ar",
227 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
228 		.type = TEGRA_ICC_NISO,
229 		.sid = TEGRA234_SID_PCIE10,
230 		.regs = {
231 			.sid = {
232 				.override = 0x1f8,
233 				.security = 0x1fc,
234 			},
235 		},
236 	}, {
237 		.id = TEGRA234_MEMORY_CLIENT_PCIE10AW,
238 		.name = "pcie10aw",
239 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
240 		.type = TEGRA_ICC_NISO,
241 		.sid = TEGRA234_SID_PCIE10,
242 		.regs = {
243 			.sid = {
244 				.override = 0x200,
245 				.security = 0x204,
246 			},
247 		},
248 	}, {
249 		.id = TEGRA234_MEMORY_CLIENT_PCIE10AR1,
250 		.name = "pcie10ar1",
251 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
252 		.type = TEGRA_ICC_NISO,
253 		.sid = TEGRA234_SID_PCIE10,
254 		.regs = {
255 			.sid = {
256 				.override = 0x240,
257 				.security = 0x244,
258 			},
259 		},
260 	}, {
261 		.id = TEGRA234_MEMORY_CLIENT_PCIE7AR1,
262 		.name = "pcie7ar1",
263 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
264 		.type = TEGRA_ICC_NISO,
265 		.sid = TEGRA234_SID_PCIE7,
266 		.regs = {
267 			.sid = {
268 				.override = 0x248,
269 				.security = 0x24c,
270 			},
271 		},
272 	}, {
273 		.id = TEGRA234_MEMORY_CLIENT_MGBEARD,
274 		.name = "mgbeard",
275 		.bpmp_id = TEGRA_ICC_BPMP_EQOS,
276 		.type = TEGRA_ICC_NISO,
277 		.sid = TEGRA234_SID_MGBE,
278 		.regs = {
279 			.sid = {
280 				.override = 0x2c0,
281 				.security = 0x2c4,
282 			},
283 		},
284 	}, {
285 		.id = TEGRA234_MEMORY_CLIENT_MGBEBRD,
286 		.name = "mgbebrd",
287 		.bpmp_id = TEGRA_ICC_BPMP_EQOS,
288 		.type = TEGRA_ICC_NISO,
289 		.sid = TEGRA234_SID_MGBE_VF1,
290 		.regs = {
291 			.sid = {
292 				.override = 0x2c8,
293 				.security = 0x2cc,
294 			},
295 		},
296 	}, {
297 		.id = TEGRA234_MEMORY_CLIENT_MGBECRD,
298 		.name = "mgbecrd",
299 		.bpmp_id = TEGRA_ICC_BPMP_EQOS,
300 		.type = TEGRA_ICC_NISO,
301 		.sid = TEGRA234_SID_MGBE_VF2,
302 		.regs = {
303 			.sid = {
304 				.override = 0x2d0,
305 				.security = 0x2d4,
306 			},
307 		},
308 	}, {
309 		.id = TEGRA234_MEMORY_CLIENT_MGBEDRD,
310 		.name = "mgbedrd",
311 		.bpmp_id = TEGRA_ICC_BPMP_EQOS,
312 		.type = TEGRA_ICC_NISO,
313 		.sid = TEGRA234_SID_MGBE_VF3,
314 		.regs = {
315 			.sid = {
316 				.override = 0x2d8,
317 				.security = 0x2dc,
318 			},
319 		},
320 	}, {
321 		.id = TEGRA234_MEMORY_CLIENT_MGBEAWR,
322 		.bpmp_id = TEGRA_ICC_BPMP_EQOS,
323 		.type = TEGRA_ICC_NISO,
324 		.name = "mgbeawr",
325 		.sid = TEGRA234_SID_MGBE,
326 		.regs = {
327 			.sid = {
328 				.override = 0x2e0,
329 				.security = 0x2e4,
330 			},
331 		},
332 	}, {
333 		.id = TEGRA234_MEMORY_CLIENT_MGBEBWR,
334 		.name = "mgbebwr",
335 		.bpmp_id = TEGRA_ICC_BPMP_EQOS,
336 		.type = TEGRA_ICC_NISO,
337 		.sid = TEGRA234_SID_MGBE_VF1,
338 		.regs = {
339 			.sid = {
340 				.override = 0x2f8,
341 				.security = 0x2fc,
342 			},
343 		},
344 	}, {
345 		.id = TEGRA234_MEMORY_CLIENT_MGBECWR,
346 		.name = "mgbecwr",
347 		.bpmp_id = TEGRA_ICC_BPMP_EQOS,
348 		.type = TEGRA_ICC_NISO,
349 		.sid = TEGRA234_SID_MGBE_VF2,
350 		.regs = {
351 			.sid = {
352 				.override = 0x308,
353 				.security = 0x30c,
354 			},
355 		},
356 	}, {
357 		.id = TEGRA234_MEMORY_CLIENT_SDMMCRAB,
358 		.name = "sdmmcrab",
359 		.bpmp_id = TEGRA_ICC_BPMP_SDMMC_4,
360 		.type = TEGRA_ICC_NISO,
361 		.sid = TEGRA234_SID_SDMMC4,
362 		.regs = {
363 			.sid = {
364 				.override = 0x318,
365 				.security = 0x31c,
366 			},
367 		},
368 	}, {
369 		.id = TEGRA234_MEMORY_CLIENT_MGBEDWR,
370 		.name = "mgbedwr",
371 		.bpmp_id = TEGRA_ICC_BPMP_EQOS,
372 		.type = TEGRA_ICC_NISO,
373 		.sid = TEGRA234_SID_MGBE_VF3,
374 		.regs = {
375 			.sid = {
376 				.override = 0x328,
377 				.security = 0x32c,
378 			},
379 		},
380 	}, {
381 		.id = TEGRA234_MEMORY_CLIENT_SDMMCWAB,
382 		.name = "sdmmcwab",
383 		.bpmp_id = TEGRA_ICC_BPMP_SDMMC_4,
384 		.type = TEGRA_ICC_NISO,
385 		.sid = TEGRA234_SID_SDMMC4,
386 		.regs = {
387 			.sid = {
388 				.override = 0x338,
389 				.security = 0x33c,
390 			},
391 		},
392 	}, {
393 		.id = TEGRA234_MEMORY_CLIENT_VICSRD,
394 		.name = "vicsrd",
395 		.bpmp_id = TEGRA_ICC_BPMP_VIC,
396 		.type = TEGRA_ICC_NISO,
397 		.sid = TEGRA234_SID_VIC,
398 		.regs = {
399 			.sid = {
400 				.override = 0x360,
401 				.security = 0x364,
402 			},
403 		},
404 	}, {
405 		.id = TEGRA234_MEMORY_CLIENT_VICSWR,
406 		.name = "vicswr",
407 		.bpmp_id = TEGRA_ICC_BPMP_VIC,
408 		.type = TEGRA_ICC_NISO,
409 		.sid = TEGRA234_SID_VIC,
410 		.regs = {
411 			.sid = {
412 				.override = 0x368,
413 				.security = 0x36c,
414 			},
415 		},
416 	}, {
417 		.id = TEGRA234_MEMORY_CLIENT_DLA1RDB1,
418 		.name = "dla1rdb1",
419 		.bpmp_id = TEGRA_ICC_BPMP_DLA_1,
420 		.type = TEGRA_ICC_NISO,
421 		.sid = TEGRA234_SID_NVDLA1,
422 		.regs = {
423 			.sid = {
424 				.override = 0x370,
425 				.security = 0x374,
426 			},
427 		},
428 	}, {
429 		.id = TEGRA234_MEMORY_CLIENT_DLA1WRB,
430 		.name = "dla1wrb",
431 		.bpmp_id = TEGRA_ICC_BPMP_DLA_1,
432 		.type = TEGRA_ICC_NISO,
433 		.sid = TEGRA234_SID_NVDLA1,
434 		.regs = {
435 			.sid = {
436 				.override = 0x378,
437 				.security = 0x37c,
438 			},
439 		},
440 	}, {
441 		.id = TEGRA234_MEMORY_CLIENT_VI2W,
442 		.name = "vi2w",
443 		.bpmp_id = TEGRA_ICC_BPMP_VI2,
444 		.type = TEGRA_ICC_ISO_VI,
445 		.sid = TEGRA234_SID_ISO_VI2,
446 		.regs = {
447 			.sid = {
448 				.override = 0x380,
449 				.security = 0x384,
450 			},
451 		},
452 	}, {
453 		.id = TEGRA234_MEMORY_CLIENT_VI2FALR,
454 		.name = "vi2falr",
455 		.bpmp_id = TEGRA_ICC_BPMP_VI2FAL,
456 		.type = TEGRA_ICC_ISO_VIFAL,
457 		.sid = TEGRA234_SID_ISO_VI2FALC,
458 		.regs = {
459 			.sid = {
460 				.override = 0x388,
461 				.security = 0x38c,
462 			},
463 		},
464 	}, {
465 		.id = TEGRA234_MEMORY_CLIENT_VIW,
466 		.name = "viw",
467 		.bpmp_id = TEGRA_ICC_BPMP_VI,
468 		.type = TEGRA_ICC_ISO_VI,
469 		.sid = TEGRA234_SID_ISO_VI,
470 		.regs = {
471 			.sid = {
472 				.override = 0x390,
473 				.security = 0x394,
474 			},
475 		},
476 	}, {
477 		.id = TEGRA234_MEMORY_CLIENT_NVDECSRD,
478 		.name = "nvdecsrd",
479 		.bpmp_id = TEGRA_ICC_BPMP_NVDEC,
480 		.type = TEGRA_ICC_NISO,
481 		.sid = TEGRA234_SID_NVDEC,
482 		.regs = {
483 			.sid = {
484 				.override = 0x3c0,
485 				.security = 0x3c4,
486 			},
487 		},
488 	}, {
489 		.id = TEGRA234_MEMORY_CLIENT_NVDECSWR,
490 		.name = "nvdecswr",
491 		.bpmp_id = TEGRA_ICC_BPMP_NVDEC,
492 		.type = TEGRA_ICC_NISO,
493 		.sid = TEGRA234_SID_NVDEC,
494 		.regs = {
495 			.sid = {
496 				.override = 0x3c8,
497 				.security = 0x3cc,
498 			},
499 		},
500 	}, {
501 		.id = TEGRA234_MEMORY_CLIENT_APER,
502 		.name = "aper",
503 		.bpmp_id = TEGRA_ICC_BPMP_APE,
504 		.type = TEGRA_ICC_ISO_AUDIO,
505 		.sid = TEGRA234_SID_APE,
506 		.regs = {
507 			.sid = {
508 				.override = 0x3d0,
509 				.security = 0x3d4,
510 			},
511 		},
512 	}, {
513 		.id = TEGRA234_MEMORY_CLIENT_APEW,
514 		.name = "apew",
515 		.bpmp_id = TEGRA_ICC_BPMP_APE,
516 		.type = TEGRA_ICC_ISO_AUDIO,
517 		.sid = TEGRA234_SID_APE,
518 		.regs = {
519 			.sid = {
520 				.override = 0x3d8,
521 				.security = 0x3dc,
522 			},
523 		},
524 	}, {
525 		.id = TEGRA234_MEMORY_CLIENT_VI2FALW,
526 		.name = "vi2falw",
527 		.bpmp_id = TEGRA_ICC_BPMP_VI2FAL,
528 		.type = TEGRA_ICC_ISO_VIFAL,
529 		.sid = TEGRA234_SID_ISO_VI2FALC,
530 		.regs = {
531 			.sid = {
532 				.override = 0x3e0,
533 				.security = 0x3e4,
534 			},
535 		},
536 	}, {
537 		.id = TEGRA234_MEMORY_CLIENT_NVJPGSRD,
538 		.name = "nvjpgsrd",
539 		.bpmp_id = TEGRA_ICC_BPMP_NVJPG_0,
540 		.type = TEGRA_ICC_NISO,
541 		.sid = TEGRA234_SID_NVJPG,
542 		.regs = {
543 			.sid = {
544 				.override = 0x3f0,
545 				.security = 0x3f4,
546 			},
547 		},
548 	}, {
549 		.id = TEGRA234_MEMORY_CLIENT_NVJPGSWR,
550 		.name = "nvjpgswr",
551 		.bpmp_id = TEGRA_ICC_BPMP_NVJPG_0,
552 		.type = TEGRA_ICC_NISO,
553 		.sid = TEGRA234_SID_NVJPG,
554 		.regs = {
555 			.sid = {
556 				.override = 0x3f8,
557 				.security = 0x3fc,
558 			},
559 		},
560 	}, {
561 		.id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR,
562 		.name = "nvdisplayr",
563 		.bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
564 		.type = TEGRA_ICC_ISO_DISPLAY,
565 		.sid = TEGRA234_SID_ISO_NVDISPLAY,
566 		.regs = {
567 			.sid = {
568 				.override = 0x490,
569 				.security = 0x494,
570 			},
571 		},
572 	}, {
573 		.id = TEGRA234_MEMORY_CLIENT_BPMPR,
574 		.name = "bpmpr",
575 		.sid = TEGRA234_SID_BPMP,
576 		.regs = {
577 			.sid = {
578 				.override = 0x498,
579 				.security = 0x49c,
580 			},
581 		},
582 	}, {
583 		.id = TEGRA234_MEMORY_CLIENT_BPMPW,
584 		.name = "bpmpw",
585 		.sid = TEGRA234_SID_BPMP,
586 		.regs = {
587 			.sid = {
588 				.override = 0x4a0,
589 				.security = 0x4a4,
590 			},
591 		},
592 	}, {
593 		.id = TEGRA234_MEMORY_CLIENT_BPMPDMAR,
594 		.name = "bpmpdmar",
595 		.sid = TEGRA234_SID_BPMP,
596 		.regs = {
597 			.sid = {
598 				.override = 0x4a8,
599 				.security = 0x4ac,
600 			},
601 		},
602 	}, {
603 		.id = TEGRA234_MEMORY_CLIENT_BPMPDMAW,
604 		.name = "bpmpdmaw",
605 		.sid = TEGRA234_SID_BPMP,
606 		.regs = {
607 			.sid = {
608 				.override = 0x4b0,
609 				.security = 0x4b4,
610 			},
611 		},
612 	}, {
613 		.id = TEGRA234_MEMORY_CLIENT_APEDMAR,
614 		.name = "apedmar",
615 		.bpmp_id = TEGRA_ICC_BPMP_APEDMA,
616 		.type = TEGRA_ICC_ISO_AUDIO,
617 		.sid = TEGRA234_SID_APE,
618 		.regs = {
619 			.sid = {
620 				.override = 0x4f8,
621 				.security = 0x4fc,
622 			},
623 		},
624 	}, {
625 		.id = TEGRA234_MEMORY_CLIENT_APEDMAW,
626 		.name = "apedmaw",
627 		.bpmp_id = TEGRA_ICC_BPMP_APEDMA,
628 		.type = TEGRA_ICC_ISO_AUDIO,
629 		.sid = TEGRA234_SID_APE,
630 		.regs = {
631 			.sid = {
632 				.override = 0x500,
633 				.security = 0x504,
634 			},
635 		},
636 	}, {
637 		.id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1,
638 		.name = "nvdisplayr1",
639 		.bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
640 		.type = TEGRA_ICC_ISO_DISPLAY,
641 		.sid = TEGRA234_SID_ISO_NVDISPLAY,
642 		.regs = {
643 			.sid = {
644 				.override = 0x508,
645 				.security = 0x50c,
646 			},
647 		},
648 	}, {
649 		.id = TEGRA234_MEMORY_CLIENT_VIFALR,
650 		.name = "vifalr",
651 		.bpmp_id = TEGRA_ICC_BPMP_VIFAL,
652 		.type = TEGRA_ICC_ISO_VIFAL,
653 		.sid = TEGRA234_SID_ISO_VIFALC,
654 		.regs = {
655 			.sid = {
656 				.override = 0x5e0,
657 				.security = 0x5e4,
658 			},
659 		},
660 	}, {
661 		.id = TEGRA234_MEMORY_CLIENT_VIFALW,
662 		.name = "vifalw",
663 		.bpmp_id = TEGRA_ICC_BPMP_VIFAL,
664 		.type = TEGRA_ICC_ISO_VIFAL,
665 		.sid = TEGRA234_SID_ISO_VIFALC,
666 		.regs = {
667 			.sid = {
668 				.override = 0x5e8,
669 				.security = 0x5ec,
670 			},
671 		},
672 	}, {
673 		.id = TEGRA234_MEMORY_CLIENT_DLA0RDA,
674 		.name = "dla0rda",
675 		.bpmp_id = TEGRA_ICC_BPMP_DLA_0,
676 		.type = TEGRA_ICC_NISO,
677 		.sid = TEGRA234_SID_NVDLA0,
678 		.regs = {
679 			.sid = {
680 				.override = 0x5f0,
681 				.security = 0x5f4,
682 			},
683 		},
684 	}, {
685 		.id = TEGRA234_MEMORY_CLIENT_DLA0FALRDB,
686 		.name = "dla0falrdb",
687 		.bpmp_id = TEGRA_ICC_BPMP_DLA_0,
688 		.type = TEGRA_ICC_NISO,
689 		.sid = TEGRA234_SID_NVDLA0,
690 		.regs = {
691 			.sid = {
692 				.override = 0x5f8,
693 				.security = 0x5fc,
694 			},
695 		},
696 	}, {
697 		.id = TEGRA234_MEMORY_CLIENT_DLA0WRA,
698 		.name = "dla0wra",
699 		.bpmp_id = TEGRA_ICC_BPMP_DLA_0,
700 		.type = TEGRA_ICC_NISO,
701 		.sid = TEGRA234_SID_NVDLA0,
702 		.regs = {
703 			.sid = {
704 				.override = 0x600,
705 				.security = 0x604,
706 			},
707 		},
708 	}, {
709 		.id = TEGRA234_MEMORY_CLIENT_DLA0FALWRB,
710 		.name = "dla0falwrb",
711 		.bpmp_id = TEGRA_ICC_BPMP_DLA_0,
712 		.type = TEGRA_ICC_NISO,
713 		.sid = TEGRA234_SID_NVDLA0,
714 		.regs = {
715 			.sid = {
716 				.override = 0x608,
717 				.security = 0x60c,
718 			},
719 		},
720 	}, {
721 		.id = TEGRA234_MEMORY_CLIENT_DLA1RDA,
722 		.name = "dla1rda",
723 		.bpmp_id = TEGRA_ICC_BPMP_DLA_1,
724 		.type = TEGRA_ICC_NISO,
725 		.sid = TEGRA234_SID_NVDLA1,
726 		.regs = {
727 			.sid = {
728 				.override = 0x610,
729 				.security = 0x614,
730 			},
731 		},
732 	}, {
733 		.id = TEGRA234_MEMORY_CLIENT_DLA1FALRDB,
734 		.name = "dla1falrdb",
735 		.bpmp_id = TEGRA_ICC_BPMP_DLA_1,
736 		.type = TEGRA_ICC_NISO,
737 		.sid = TEGRA234_SID_NVDLA1,
738 		.regs = {
739 			.sid = {
740 				.override = 0x618,
741 				.security = 0x61c,
742 			},
743 		},
744 	}, {
745 		.id = TEGRA234_MEMORY_CLIENT_DLA1WRA,
746 		.name = "dla1wra",
747 		.bpmp_id = TEGRA_ICC_BPMP_DLA_1,
748 		.type = TEGRA_ICC_NISO,
749 		.sid = TEGRA234_SID_NVDLA1,
750 		.regs = {
751 			.sid = {
752 				.override = 0x620,
753 				.security = 0x624,
754 			},
755 		},
756 	}, {
757 		.id = TEGRA234_MEMORY_CLIENT_DLA1FALWRB,
758 		.name = "dla1falwrb",
759 		.bpmp_id = TEGRA_ICC_BPMP_DLA_1,
760 		.type = TEGRA_ICC_NISO,
761 		.sid = TEGRA234_SID_NVDLA1,
762 		.regs = {
763 			.sid = {
764 				.override = 0x628,
765 				.security = 0x62c,
766 			},
767 		},
768 	}, {
769 		.id = TEGRA234_MEMORY_CLIENT_RCER,
770 		.name = "rcer",
771 		.bpmp_id = TEGRA_ICC_BPMP_RCE,
772 		.type = TEGRA_ICC_NISO,
773 		.sid = TEGRA234_SID_RCE,
774 		.regs = {
775 			.sid = {
776 				.override = 0x690,
777 				.security = 0x694,
778 			},
779 		},
780 	}, {
781 		.id = TEGRA234_MEMORY_CLIENT_RCEW,
782 		.name = "rcew",
783 		.bpmp_id = TEGRA_ICC_BPMP_RCE,
784 		.type = TEGRA_ICC_NISO,
785 		.sid = TEGRA234_SID_RCE,
786 		.regs = {
787 			.sid = {
788 				.override = 0x698,
789 				.security = 0x69c,
790 			},
791 		},
792 	}, {
793 		.id = TEGRA234_MEMORY_CLIENT_PCIE0R,
794 		.name = "pcie0r",
795 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_0,
796 		.type = TEGRA_ICC_NISO,
797 		.sid = TEGRA234_SID_PCIE0,
798 		.regs = {
799 			.sid = {
800 				.override = 0x6c0,
801 				.security = 0x6c4,
802 			},
803 		},
804 	}, {
805 		.id = TEGRA234_MEMORY_CLIENT_PCIE0W,
806 		.name = "pcie0w",
807 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_0,
808 		.type = TEGRA_ICC_NISO,
809 		.sid = TEGRA234_SID_PCIE0,
810 		.regs = {
811 			.sid = {
812 				.override = 0x6c8,
813 				.security = 0x6cc,
814 			},
815 		},
816 	}, {
817 		.id = TEGRA234_MEMORY_CLIENT_PCIE1R,
818 		.name = "pcie1r",
819 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_1,
820 		.type = TEGRA_ICC_NISO,
821 		.sid = TEGRA234_SID_PCIE1,
822 		.regs = {
823 			.sid = {
824 				.override = 0x6d0,
825 				.security = 0x6d4,
826 			},
827 		},
828 	}, {
829 		.id = TEGRA234_MEMORY_CLIENT_PCIE1W,
830 		.name = "pcie1w",
831 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_1,
832 		.type = TEGRA_ICC_NISO,
833 		.sid = TEGRA234_SID_PCIE1,
834 		.regs = {
835 			.sid = {
836 				.override = 0x6d8,
837 				.security = 0x6dc,
838 			},
839 		},
840 	}, {
841 		.id = TEGRA234_MEMORY_CLIENT_PCIE2AR,
842 		.name = "pcie2ar",
843 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_2,
844 		.type = TEGRA_ICC_NISO,
845 		.sid = TEGRA234_SID_PCIE2,
846 		.regs = {
847 			.sid = {
848 				.override = 0x6e0,
849 				.security = 0x6e4,
850 			},
851 		},
852 	}, {
853 		.id = TEGRA234_MEMORY_CLIENT_PCIE2AW,
854 		.name = "pcie2aw",
855 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_2,
856 		.type = TEGRA_ICC_NISO,
857 		.sid = TEGRA234_SID_PCIE2,
858 		.regs = {
859 			.sid = {
860 				.override = 0x6e8,
861 				.security = 0x6ec,
862 			},
863 		},
864 	}, {
865 		.id = TEGRA234_MEMORY_CLIENT_PCIE3R,
866 		.name = "pcie3r",
867 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_3,
868 		.type = TEGRA_ICC_NISO,
869 		.sid = TEGRA234_SID_PCIE3,
870 		.regs = {
871 			.sid = {
872 				.override = 0x6f0,
873 				.security = 0x6f4,
874 			},
875 		},
876 	}, {
877 		.id = TEGRA234_MEMORY_CLIENT_PCIE3W,
878 		.name = "pcie3w",
879 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_3,
880 		.type = TEGRA_ICC_NISO,
881 		.sid = TEGRA234_SID_PCIE3,
882 		.regs = {
883 			.sid = {
884 				.override = 0x6f8,
885 				.security = 0x6fc,
886 			},
887 		},
888 	}, {
889 		.id = TEGRA234_MEMORY_CLIENT_PCIE4R,
890 		.name = "pcie4r",
891 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_4,
892 		.type = TEGRA_ICC_NISO,
893 		.sid = TEGRA234_SID_PCIE4,
894 		.regs = {
895 			.sid = {
896 				.override = 0x700,
897 				.security = 0x704,
898 			},
899 		},
900 	}, {
901 		.id = TEGRA234_MEMORY_CLIENT_PCIE4W,
902 		.name = "pcie4w",
903 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_4,
904 		.type = TEGRA_ICC_NISO,
905 		.sid = TEGRA234_SID_PCIE4,
906 		.regs = {
907 			.sid = {
908 				.override = 0x708,
909 				.security = 0x70c,
910 			},
911 		},
912 	}, {
913 		.id = TEGRA234_MEMORY_CLIENT_PCIE5R,
914 		.name = "pcie5r",
915 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_5,
916 		.type = TEGRA_ICC_NISO,
917 		.sid = TEGRA234_SID_PCIE5,
918 		.regs = {
919 			.sid = {
920 				.override = 0x710,
921 				.security = 0x714,
922 			},
923 		},
924 	}, {
925 		.id = TEGRA234_MEMORY_CLIENT_PCIE5W,
926 		.name = "pcie5w",
927 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_5,
928 		.type = TEGRA_ICC_NISO,
929 		.sid = TEGRA234_SID_PCIE5,
930 		.regs = {
931 			.sid = {
932 				.override = 0x718,
933 				.security = 0x71c,
934 			},
935 		},
936 	}, {
937 		.id = TEGRA234_MEMORY_CLIENT_DLA0RDA1,
938 		.name = "dla0rda1",
939 		.bpmp_id = TEGRA_ICC_BPMP_DLA_0,
940 		.type = TEGRA_ICC_NISO,
941 		.sid = TEGRA234_SID_NVDLA0,
942 		.regs = {
943 			.sid = {
944 				.override = 0x748,
945 				.security = 0x74c,
946 			},
947 		},
948 	}, {
949 		.id = TEGRA234_MEMORY_CLIENT_DLA1RDA1,
950 		.name = "dla1rda1",
951 		.sid = TEGRA234_SID_NVDLA1,
952 		.regs = {
953 			.sid = {
954 				.override = 0x750,
955 				.security = 0x754,
956 			},
957 		},
958 	}, {
959 		.id = TEGRA234_MEMORY_CLIENT_PCIE5R1,
960 		.name = "pcie5r1",
961 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_5,
962 		.type = TEGRA_ICC_NISO,
963 		.sid = TEGRA234_SID_PCIE5,
964 		.regs = {
965 			.sid = {
966 				.override = 0x778,
967 				.security = 0x77c,
968 			},
969 		},
970 	}, {
971 		.id = TEGRA234_MEMORY_CLIENT_NVJPG1SRD,
972 		.name = "nvjpg1srd",
973 		.bpmp_id = TEGRA_ICC_BPMP_NVJPG_1,
974 		.type = TEGRA_ICC_NISO,
975 		.sid = TEGRA234_SID_NVJPG1,
976 		.regs = {
977 			.sid = {
978 				.override = 0x918,
979 				.security = 0x91c,
980 			},
981 		},
982 	}, {
983 		.id = TEGRA234_MEMORY_CLIENT_NVJPG1SWR,
984 		.name = "nvjpg1swr",
985 		.bpmp_id = TEGRA_ICC_BPMP_NVJPG_1,
986 		.type = TEGRA_ICC_NISO,
987 		.sid = TEGRA234_SID_NVJPG1,
988 		.regs = {
989 			.sid = {
990 				.override = 0x920,
991 				.security = 0x924,
992 			},
993 		},
994 	}, {
995 		.id = TEGRA_ICC_MC_CPU_CLUSTER0,
996 		.name = "sw_cluster0",
997 		.bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER0,
998 		.type = TEGRA_ICC_NISO,
999 	}, {
1000 		.id = TEGRA_ICC_MC_CPU_CLUSTER1,
1001 		.name = "sw_cluster1",
1002 		.bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER1,
1003 		.type = TEGRA_ICC_NISO,
1004 	}, {
1005 		.id = TEGRA_ICC_MC_CPU_CLUSTER2,
1006 		.name = "sw_cluster2",
1007 		.bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER2,
1008 		.type = TEGRA_ICC_NISO,
1009 	}, {
1010 		.id = TEGRA234_MEMORY_CLIENT_NVL1R,
1011 		.name = "nvl1r",
1012 		.bpmp_id = TEGRA_ICC_BPMP_GPU,
1013 		.type = TEGRA_ICC_NISO,
1014 	}, {
1015 		.id = TEGRA234_MEMORY_CLIENT_NVL1W,
1016 		.name = "nvl1w",
1017 		.bpmp_id = TEGRA_ICC_BPMP_GPU,
1018 		.type = TEGRA_ICC_NISO,
1019 	},
1020 };
1021 
1022 /*
1023  * tegra234_mc_icc_set() - Pass MC client info to the BPMP-FW
1024  * @src: ICC node for Memory Controller's (MC) Client
1025  * @dst: ICC node for Memory Controller (MC)
1026  *
1027  * Passing the current request info from the MC to the BPMP-FW where
1028  * LA and PTSA registers are accessed and the final EMC freq is set
1029  * based on client_id, type, latency and bandwidth.
1030  * icc_set_bw() makes set_bw calls for both MC and EMC providers in
1031  * sequence. Both the calls are protected by 'mutex_lock(&icc_lock)'.
1032  * So, the data passed won't be updated by concurrent set calls from
1033  * other clients.
1034  */
1035 static int tegra234_mc_icc_set(struct icc_node *src, struct icc_node *dst)
1036 {
1037 	struct tegra_mc *mc = icc_provider_to_tegra_mc(dst->provider);
1038 	struct mrq_bwmgr_int_request bwmgr_req = { 0 };
1039 	struct mrq_bwmgr_int_response bwmgr_resp = { 0 };
1040 	const struct tegra_mc_client *pclient = src->data;
1041 	struct tegra_bpmp_message msg;
1042 	int ret;
1043 
1044 	/*
1045 	 * Same Src and Dst node will happen during boot from icc_node_add().
1046 	 * This can be used to pre-initialize and set bandwidth for all clients
1047 	 * before their drivers are loaded. We are skipping this case as for us,
1048 	 * the pre-initialization already happened in Bootloader(MB2) and BPMP-FW.
1049 	 */
1050 	if (src->id == dst->id)
1051 		return 0;
1052 
1053 	if (!mc->bwmgr_mrq_supported)
1054 		return 0;
1055 
1056 	if (!mc->bpmp) {
1057 		dev_err(mc->dev, "BPMP reference NULL\n");
1058 		return -ENOENT;
1059 	}
1060 
1061 	if (pclient->type == TEGRA_ICC_NISO)
1062 		bwmgr_req.bwmgr_calc_set_req.niso_bw = src->avg_bw;
1063 	else
1064 		bwmgr_req.bwmgr_calc_set_req.iso_bw = src->avg_bw;
1065 
1066 	bwmgr_req.bwmgr_calc_set_req.client_id = pclient->bpmp_id;
1067 
1068 	bwmgr_req.cmd = CMD_BWMGR_INT_CALC_AND_SET;
1069 	bwmgr_req.bwmgr_calc_set_req.mc_floor = src->peak_bw;
1070 	bwmgr_req.bwmgr_calc_set_req.floor_unit = BWMGR_INT_UNIT_KBPS;
1071 
1072 	memset(&msg, 0, sizeof(msg));
1073 	msg.mrq = MRQ_BWMGR_INT;
1074 	msg.tx.data = &bwmgr_req;
1075 	msg.tx.size = sizeof(bwmgr_req);
1076 	msg.rx.data = &bwmgr_resp;
1077 	msg.rx.size = sizeof(bwmgr_resp);
1078 
1079 	if (pclient->bpmp_id >= TEGRA_ICC_BPMP_CPU_CLUSTER0 &&
1080 	    pclient->bpmp_id <= TEGRA_ICC_BPMP_CPU_CLUSTER2)
1081 		msg.flags = TEGRA_BPMP_MESSAGE_RESET;
1082 
1083 	ret = tegra_bpmp_transfer(mc->bpmp, &msg);
1084 	if (ret < 0) {
1085 		dev_err(mc->dev, "BPMP transfer failed: %d\n", ret);
1086 		goto error;
1087 	}
1088 	if (msg.rx.ret < 0) {
1089 		pr_err("failed to set bandwidth for %u: %d\n",
1090 		       bwmgr_req.bwmgr_calc_set_req.client_id, msg.rx.ret);
1091 		ret = -EINVAL;
1092 	}
1093 
1094 error:
1095 	return ret;
1096 }
1097 
1098 static int tegra234_mc_icc_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
1099 				     u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
1100 {
1101 	struct icc_provider *p = node->provider;
1102 	struct tegra_mc *mc = icc_provider_to_tegra_mc(p);
1103 
1104 	if (!mc->bwmgr_mrq_supported)
1105 		return 0;
1106 
1107 	if (node->id == TEGRA_ICC_MC_CPU_CLUSTER0 ||
1108 	    node->id == TEGRA_ICC_MC_CPU_CLUSTER1 ||
1109 	    node->id == TEGRA_ICC_MC_CPU_CLUSTER2) {
1110 		if (mc)
1111 			peak_bw = peak_bw * mc->num_channels;
1112 	}
1113 
1114 	*agg_avg += avg_bw;
1115 	*agg_peak = max(*agg_peak, peak_bw);
1116 
1117 	return 0;
1118 }
1119 
1120 static int tegra234_mc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *peak)
1121 {
1122 	*avg = 0;
1123 	*peak = 0;
1124 
1125 	return 0;
1126 }
1127 
1128 static const struct tegra_mc_icc_ops tegra234_mc_icc_ops = {
1129 	.xlate = tegra_mc_icc_xlate,
1130 	.aggregate = tegra234_mc_icc_aggregate,
1131 	.get_bw = tegra234_mc_icc_get_init_bw,
1132 	.set = tegra234_mc_icc_set,
1133 };
1134 
1135 const struct tegra_mc_soc tegra234_mc_soc = {
1136 	.num_clients = ARRAY_SIZE(tegra234_mc_clients),
1137 	.clients = tegra234_mc_clients,
1138 	.num_address_bits = 40,
1139 	.num_channels = 16,
1140 	.client_id_mask = 0x1ff,
1141 	.intmask = MC_INT_DECERR_ROUTE_SANITY |
1142 		   MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
1143 		   MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1144 		   MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1145 	.has_addr_hi_reg = true,
1146 	.ops = &tegra186_mc_ops,
1147 	.icc_ops = &tegra234_mc_icc_ops,
1148 	.ch_intmask = 0x0000ff00,
1149 	.global_intstatus_channel_shift = 8,
1150 	/*
1151 	 * Additionally, there are lite carveouts but those are not currently
1152 	 * supported.
1153 	 */
1154 	.num_carveouts = 32,
1155 };
1156