1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #ifndef TEGRA210_EMC_H 7 #define TEGRA210_EMC_H 8 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/clk/tegra.h> 12 #include <linux/io.h> 13 #include <linux/platform_device.h> 14 15 #define DVFS_FGCG_HIGH_SPEED_THRESHOLD 1000 16 #define IOBRICK_DCC_THRESHOLD 2400 17 #define DVFS_FGCG_MID_SPEED_THRESHOLD 600 18 19 #define EMC_STATUS_UPDATE_TIMEOUT 1000 20 21 /* register definitions */ 22 #define EMC_INTSTATUS 0x0 23 #define EMC_INTSTATUS_CLKCHANGE_COMPLETE BIT(4) 24 #define EMC_DBG 0x8 25 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1) 26 #define EMC_CFG 0xc 27 #define EMC_TIMING_CONTROL 0x28 28 #define EMC_RC 0x2c 29 #define EMC_RFC 0x30 30 #define EMC_RAS 0x34 31 #define EMC_RP 0x38 32 #define EMC_R2W 0x3c 33 #define EMC_W2R 0x40 34 #define EMC_R2P 0x44 35 #define EMC_W2P 0x48 36 #define EMC_RD_RCD 0x4c 37 #define EMC_WR_RCD 0x50 38 #define EMC_RRD 0x54 39 #define EMC_REXT 0x58 40 #define EMC_WDV 0x5c 41 #define EMC_QUSE 0x60 42 #define EMC_QRST 0x64 43 #define EMC_QSAFE 0x68 44 #define EMC_RDV 0x6c 45 #define EMC_REFRESH 0x70 46 #define EMC_BURST_REFRESH_NUM 0x74 47 #define EMC_PDEX2WR 0x78 48 #define EMC_PDEX2RD 0x7c 49 #define EMC_PCHG2PDEN 0x80 50 #define EMC_ACT2PDEN 0x84 51 #define EMC_AR2PDEN 0x88 52 #define EMC_RW2PDEN 0x8c 53 #define EMC_TXSR 0x90 54 #define EMC_TCKE 0x94 55 #define EMC_TFAW 0x98 56 #define EMC_TRPAB 0x9c 57 #define EMC_TCLKSTABLE 0xa0 58 #define EMC_TCLKSTOP 0xa4 59 #define EMC_TREFBW 0xa8 60 #define EMC_TPPD 0xac 61 #define EMC_ODT_WRITE 0xb0 62 #define EMC_PDEX2MRR 0xb4 63 #define EMC_WEXT 0xb8 64 #define EMC_RFC_SLR 0xc0 65 #define EMC_MRS_WAIT_CNT2 0xc4 66 #define EMC_MRS_WAIT_CNT 0xc8 67 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 0 68 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK \ 69 (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT) 70 71 #define EMC_MRS 0xcc 72 #define EMC_EMRS 0xd0 73 #define EMC_EMRS_USE_EMRS_LONG_CNT BIT(26) 74 #define EMC_REF 0xd4 75 #define EMC_SELF_REF 0xe0 76 #define EMC_MRW 0xe8 77 #define EMC_MRW_MRW_OP_SHIFT 0 78 #define EMC_MRW_MRW_OP_MASK \ 79 (0xff << EMC_MRW_MRW_OP_SHIFT) 80 #define EMC_MRW_MRW_MA_SHIFT 16 81 #define EMC_MRW_USE_MRW_EXT_CNT 27 82 #define EMC_MRW_MRW_DEV_SELECTN_SHIFT 30 83 84 #define EMC_MRR 0xec 85 #define EMC_MRR_DEV_SEL_SHIFT 30 86 #define EMC_MRR_DEV_SEL_MASK 0x3 87 #define EMC_MRR_MA_SHIFT 16 88 #define EMC_MRR_MA_MASK 0xff 89 #define EMC_MRR_DATA_SHIFT 0 90 #define EMC_MRR_DATA_MASK 0xffff 91 92 #define EMC_FBIO_SPARE 0x100 93 #define EMC_FBIO_CFG5 0x104 94 #define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0 95 #define EMC_FBIO_CFG5_DRAM_TYPE_MASK \ 96 (0x3 << EMC_FBIO_CFG5_DRAM_TYPE_SHIFT) 97 #define EMC_FBIO_CFG5_CMD_TX_DIS BIT(8) 98 99 #define EMC_PDEX2CKE 0x118 100 #define EMC_CKE2PDEN 0x11c 101 #define EMC_MPC 0x128 102 #define EMC_R2R 0x144 103 #define EMC_EINPUT 0x14c 104 #define EMC_EINPUT_DURATION 0x150 105 #define EMC_PUTERM_EXTRA 0x154 106 #define EMC_TCKESR 0x158 107 #define EMC_TPD 0x15c 108 #define EMC_EMC_STATUS 0x2b4 109 #define EMC_EMC_STATUS_MRR_DIVLD BIT(20) 110 #define EMC_EMC_STATUS_TIMING_UPDATE_STALLED BIT(23) 111 #define EMC_CFG_DIG_DLL 0x2bc 112 #define EMC_CFG_DIG_DLL_CFG_DLL_EN BIT(0) 113 #define EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_UNTIL_LOCK BIT(1) 114 #define EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_TRAFFIC BIT(3) 115 #define EMC_CFG_DIG_DLL_CFG_DLL_STALL_RW_UNTIL_LOCK BIT(4) 116 #define EMC_CFG_DIG_DLL_CFG_DLL_MODE_SHIFT 6 117 #define EMC_CFG_DIG_DLL_CFG_DLL_MODE_MASK \ 118 (0x3 << EMC_CFG_DIG_DLL_CFG_DLL_MODE_SHIFT) 119 #define EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_SHIFT 8 120 #define EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_MASK \ 121 (0x7 << EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_SHIFT) 122 123 #define EMC_CFG_DIG_DLL_PERIOD 0x2c0 124 #define EMC_DIG_DLL_STATUS 0x2c4 125 #define EMC_DIG_DLL_STATUS_DLL_LOCK BIT(15) 126 #define EMC_DIG_DLL_STATUS_DLL_PRIV_UPDATED BIT(17) 127 #define EMC_DIG_DLL_STATUS_DLL_OUT_SHIFT 0 128 #define EMC_DIG_DLL_STATUS_DLL_OUT_MASK \ 129 (0x7ff << EMC_DIG_DLL_STATUS_DLL_OUT_SHIFT) 130 131 #define EMC_CFG_DIG_DLL_1 0x2c8 132 #define EMC_RDV_MASK 0x2cc 133 #define EMC_WDV_MASK 0x2d0 134 #define EMC_RDV_EARLY_MASK 0x2d4 135 #define EMC_RDV_EARLY 0x2d8 136 #define EMC_ZCAL_INTERVAL 0x2e0 137 #define EMC_ZCAL_WAIT_CNT 0x2e4 138 #define EMC_FDPD_CTRL_DQ 0x310 139 #define EMC_FDPD_CTRL_CMD 0x314 140 #define EMC_PMACRO_CMD_BRICK_CTRL_FDPD 0x318 141 #define EMC_PMACRO_DATA_BRICK_CTRL_FDPD 0x31c 142 #define EMC_PMACRO_BRICK_CTRL_RFU1 0x330 143 #define EMC_PMACRO_BRICK_CTRL_RFU2 0x334 144 #define EMC_TR_TIMING_0 0x3b4 145 #define EMC_TR_CTRL_1 0x3bc 146 #define EMC_TR_RDV 0x3c4 147 #define EMC_PRE_REFRESH_REQ_CNT 0x3dc 148 #define EMC_DYN_SELF_REF_CONTROL 0x3e0 149 #define EMC_TXSRDLL 0x3e4 150 #define EMC_CCFIFO_ADDR 0x3e8 151 #define EMC_CCFIFO_ADDR_STALL_BY_1 (1 << 31) 152 #define EMC_CCFIFO_ADDR_STALL(x) (((x) & 0x7fff) << 16) 153 #define EMC_CCFIFO_ADDR_OFFSET(x) ((x) & 0xffff) 154 #define EMC_CCFIFO_DATA 0x3ec 155 #define EMC_TR_QPOP 0x3f4 156 #define EMC_TR_RDV_MASK 0x3f8 157 #define EMC_TR_QSAFE 0x3fc 158 #define EMC_TR_QRST 0x400 159 #define EMC_TR_DVFS 0x460 160 #define EMC_AUTO_CAL_CHANNEL 0x464 161 #define EMC_IBDLY 0x468 162 #define EMC_OBDLY 0x46c 163 #define EMC_TXDSRVTTGEN 0x480 164 #define EMC_WE_DURATION 0x48c 165 #define EMC_WS_DURATION 0x490 166 #define EMC_WEV 0x494 167 #define EMC_WSV 0x498 168 #define EMC_CFG_3 0x49c 169 #define EMC_MRW6 0x4a4 170 #define EMC_MRW7 0x4a8 171 #define EMC_MRW8 0x4ac 172 #define EMC_MRW10 0x4b4 173 #define EMC_MRW11 0x4b8 174 #define EMC_MRW12 0x4bc 175 #define EMC_MRW13 0x4c0 176 #define EMC_MRW14 0x4c4 177 #define EMC_MRW15 0x4d0 178 #define EMC_WDV_CHK 0x4e0 179 #define EMC_CFG_PIPE_2 0x554 180 #define EMC_CFG_PIPE_1 0x55c 181 #define EMC_CFG_PIPE 0x560 182 #define EMC_QPOP 0x564 183 #define EMC_QUSE_WIDTH 0x568 184 #define EMC_PUTERM_WIDTH 0x56c 185 #define EMC_REFCTRL2 0x580 186 #define EMC_FBIO_CFG7 0x584 187 #define EMC_FBIO_CFG7_CH0_ENABLE BIT(1) 188 #define EMC_FBIO_CFG7_CH1_ENABLE BIT(2) 189 #define EMC_DATA_BRLSHFT_0 0x588 190 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_SHIFT 21 191 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_MASK \ 192 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_SHIFT) 193 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_SHIFT 18 194 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_MASK \ 195 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_SHIFT) 196 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_SHIFT 15 197 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_MASK \ 198 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_SHIFT) 199 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_SHIFT 12 200 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_MASK \ 201 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_SHIFT) 202 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_SHIFT 9 203 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_MASK \ 204 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_SHIFT) 205 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_SHIFT 6 206 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_MASK \ 207 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_SHIFT) 208 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT 3 209 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_MASK \ 210 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT) 211 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT 0 212 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_MASK \ 213 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT) 214 215 #define EMC_DATA_BRLSHFT_1 0x58c 216 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_SHIFT 21 217 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_MASK \ 218 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_SHIFT) 219 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_SHIFT 18 220 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_MASK \ 221 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_SHIFT) 222 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_SHIFT 15 223 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_MASK \ 224 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_SHIFT) 225 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_SHIFT 12 226 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_MASK \ 227 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_SHIFT) 228 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_SHIFT 9 229 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_MASK \ 230 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_SHIFT) 231 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_SHIFT 6 232 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_MASK \ 233 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_SHIFT) 234 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT 3 235 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_MASK \ 236 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT) 237 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT 0 238 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_MASK \ 239 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT) 240 241 #define EMC_RFCPB 0x590 242 #define EMC_DQS_BRLSHFT_0 0x594 243 #define EMC_DQS_BRLSHFT_1 0x598 244 #define EMC_CMD_BRLSHFT_0 0x59c 245 #define EMC_CMD_BRLSHFT_1 0x5a0 246 #define EMC_CMD_BRLSHFT_2 0x5a4 247 #define EMC_CMD_BRLSHFT_3 0x5a8 248 #define EMC_QUSE_BRLSHFT_0 0x5ac 249 #define EMC_QUSE_BRLSHFT_1 0x5b8 250 #define EMC_QUSE_BRLSHFT_2 0x5bc 251 #define EMC_CCDMW 0x5c0 252 #define EMC_QUSE_BRLSHFT_3 0x5c4 253 #define EMC_DLL_CFG_0 0x5e4 254 #define EMC_DLL_CFG_1 0x5e8 255 #define EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_SHIFT 10 256 #define EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_MASK \ 257 (0x7ff << EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_SHIFT) 258 259 #define EMC_CONFIG_SAMPLE_DELAY 0x5f0 260 #define EMC_PMACRO_QUSE_DDLL_RANK0_0 0x600 261 #define EMC_PMACRO_QUSE_DDLL_RANK0_1 0x604 262 #define EMC_PMACRO_QUSE_DDLL_RANK0_2 0x608 263 #define EMC_PMACRO_QUSE_DDLL_RANK0_3 0x60c 264 #define EMC_PMACRO_QUSE_DDLL_RANK0_4 0x610 265 #define EMC_PMACRO_QUSE_DDLL_RANK0_5 0x614 266 #define EMC_PMACRO_QUSE_DDLL_RANK1_0 0x620 267 #define EMC_PMACRO_QUSE_DDLL_RANK1_1 0x624 268 #define EMC_PMACRO_QUSE_DDLL_RANK1_2 0x628 269 #define EMC_PMACRO_QUSE_DDLL_RANK1_3 0x62c 270 #define EMC_PMACRO_QUSE_DDLL_RANK1_4 0x630 271 #define EMC_PMACRO_QUSE_DDLL_RANK1_5 0x634 272 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 0x640 273 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_SHIFT \ 274 16 275 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_MASK \ 276 (0x3ff << \ 277 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_SHIFT) 278 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_SHIFT \ 279 0 280 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_MASK \ 281 (0x3ff << \ 282 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_SHIFT) 283 284 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 0x644 285 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_SHIFT \ 286 16 287 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_MASK \ 288 (0x3ff << \ 289 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_SHIFT) 290 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_SHIFT \ 291 0 292 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_MASK \ 293 (0x3ff << \ 294 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_SHIFT) 295 296 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 0x648 297 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_SHIFT \ 298 16 299 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_MASK \ 300 (0x3ff << \ 301 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_SHIFT) 302 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_SHIFT \ 303 0 304 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_MASK \ 305 (0x3ff << \ 306 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_SHIFT) 307 308 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3 0x64c 309 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_SHIFT \ 310 16 311 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_MASK \ 312 (0x3ff << \ 313 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_SHIFT) 314 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_SHIFT \ 315 0 316 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_MASK \ 317 (0x3ff << \ 318 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_SHIFT) 319 320 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4 0x650 321 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5 0x654 322 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0 0x660 323 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_SHIFT \ 324 16 325 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_MASK \ 326 (0x3ff << \ 327 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_SHIFT) 328 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_SHIFT \ 329 0 330 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_MASK \ 331 (0x3ff << \ 332 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_SHIFT) 333 334 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1 0x664 335 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_SHIFT \ 336 16 337 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_MASK \ 338 (0x3ff << \ 339 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_SHIFT) 340 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_SHIFT \ 341 0 342 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_MASK \ 343 (0x3ff << \ 344 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_SHIFT) 345 346 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2 0x668 347 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_SHIFT \ 348 16 349 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_MASK \ 350 (0x3ff << \ 351 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_SHIFT) 352 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_SHIFT \ 353 0 354 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_MASK \ 355 (0x3ff << \ 356 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_SHIFT) 357 358 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3 0x66c 359 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_SHIFT \ 360 16 361 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_MASK \ 362 (0x3ff << \ 363 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_SHIFT) 364 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_SHIFT \ 365 0 366 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_MASK \ 367 (0x3ff << \ 368 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_SHIFT) 369 370 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4 0x670 371 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5 0x674 372 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0 0x680 373 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1 0x684 374 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2 0x688 375 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3 0x68c 376 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4 0x690 377 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5 0x694 378 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0 0x6a0 379 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1 0x6a4 380 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2 0x6a8 381 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3 0x6ac 382 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4 0x6b0 383 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5 0x6b4 384 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0 0x6c0 385 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1 0x6c4 386 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2 0x6c8 387 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3 0x6cc 388 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0 0x6e0 389 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1 0x6e4 390 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2 0x6e8 391 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3 0x6ec 392 #define EMC_PMACRO_TX_PWRD_0 0x720 393 #define EMC_PMACRO_TX_PWRD_1 0x724 394 #define EMC_PMACRO_TX_PWRD_2 0x728 395 #define EMC_PMACRO_TX_PWRD_3 0x72c 396 #define EMC_PMACRO_TX_PWRD_4 0x730 397 #define EMC_PMACRO_TX_PWRD_5 0x734 398 #define EMC_PMACRO_TX_SEL_CLK_SRC_0 0x740 399 #define EMC_PMACRO_TX_SEL_CLK_SRC_1 0x744 400 #define EMC_PMACRO_TX_SEL_CLK_SRC_3 0x74c 401 #define EMC_PMACRO_TX_SEL_CLK_SRC_2 0x748 402 #define EMC_PMACRO_TX_SEL_CLK_SRC_4 0x750 403 #define EMC_PMACRO_TX_SEL_CLK_SRC_5 0x754 404 #define EMC_PMACRO_DDLL_BYPASS 0x760 405 #define EMC_PMACRO_DDLL_PWRD_0 0x770 406 #define EMC_PMACRO_DDLL_PWRD_1 0x774 407 #define EMC_PMACRO_DDLL_PWRD_2 0x778 408 #define EMC_PMACRO_CMD_CTRL_0 0x780 409 #define EMC_PMACRO_CMD_CTRL_1 0x784 410 #define EMC_PMACRO_CMD_CTRL_2 0x788 411 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0x800 412 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0x804 413 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0x808 414 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3 0x80c 415 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0x810 416 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0x814 417 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0x818 418 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3 0x81c 419 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0x820 420 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0x824 421 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0x828 422 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3 0x82c 423 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0x830 424 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0x834 425 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0x838 426 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3 0x83c 427 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0x840 428 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0x844 429 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0x848 430 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3 0x84c 431 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0x850 432 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0x854 433 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0x858 434 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3 0x85c 435 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0x860 436 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0x864 437 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0x868 438 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3 0x86c 439 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0x870 440 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0x874 441 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0x878 442 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3 0x87c 443 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0 0x880 444 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1 0x884 445 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2 0x888 446 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3 0x88c 447 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0 0x890 448 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1 0x894 449 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2 0x898 450 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3 0x89c 451 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0 0x8a0 452 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1 0x8a4 453 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2 0x8a8 454 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3 0x8ac 455 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0 0x8b0 456 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1 0x8b4 457 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2 0x8b8 458 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3 0x8bc 459 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0x900 460 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0x904 461 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0x908 462 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3 0x90c 463 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0x910 464 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0x914 465 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0x918 466 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3 0x91c 467 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0x920 468 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0x924 469 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0x928 470 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3 0x92c 471 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0x930 472 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0x934 473 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0x938 474 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3 0x93c 475 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0x940 476 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0x944 477 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0x948 478 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3 0x94c 479 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0x950 480 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0x954 481 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0x958 482 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3 0x95c 483 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0x960 484 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0x964 485 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0x968 486 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3 0x96c 487 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0x970 488 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0x974 489 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0x978 490 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3 0x97c 491 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0 0x980 492 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1 0x984 493 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2 0x988 494 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3 0x98c 495 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0 0x990 496 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1 0x994 497 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2 0x998 498 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3 0x99c 499 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0 0x9a0 500 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1 0x9a4 501 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2 0x9a8 502 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3 0x9ac 503 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0 0x9b0 504 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1 0x9b4 505 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2 0x9b8 506 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3 0x9bc 507 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0xa00 508 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0xa04 509 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0xa08 510 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0xa10 511 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0xa14 512 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0xa18 513 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0xa20 514 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0xa24 515 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0xa28 516 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0xa30 517 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0xa34 518 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0xa38 519 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0xa40 520 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0xa44 521 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0xa48 522 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0xa50 523 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0xa54 524 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0xa58 525 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0xa60 526 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0xa64 527 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0xa68 528 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0xa70 529 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0xa74 530 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0xa78 531 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0xb00 532 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0xb04 533 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0xb08 534 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0xb10 535 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0xb14 536 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0xb18 537 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0xb20 538 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0xb24 539 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0xb28 540 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0xb30 541 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0xb34 542 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0xb38 543 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0xb40 544 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0xb44 545 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0xb48 546 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0xb50 547 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0xb54 548 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0xb58 549 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0xb60 550 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0xb64 551 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0xb68 552 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0xb70 553 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0xb74 554 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0xb78 555 #define EMC_PMACRO_IB_VREF_DQ_0 0xbe0 556 #define EMC_PMACRO_IB_VREF_DQ_1 0xbe4 557 #define EMC_PMACRO_IB_VREF_DQS_0 0xbf0 558 #define EMC_PMACRO_IB_VREF_DQS_1 0xbf4 559 #define EMC_PMACRO_DDLL_LONG_CMD_0 0xc00 560 #define EMC_PMACRO_DDLL_LONG_CMD_1 0xc04 561 #define EMC_PMACRO_DDLL_LONG_CMD_2 0xc08 562 #define EMC_PMACRO_DDLL_LONG_CMD_3 0xc0c 563 #define EMC_PMACRO_DDLL_LONG_CMD_4 0xc10 564 #define EMC_PMACRO_DDLL_LONG_CMD_5 0xc14 565 #define EMC_PMACRO_DDLL_SHORT_CMD_0 0xc20 566 #define EMC_PMACRO_DDLL_SHORT_CMD_1 0xc24 567 #define EMC_PMACRO_DDLL_SHORT_CMD_2 0xc28 568 #define EMC_PMACRO_VTTGEN_CTRL_0 0xc34 569 #define EMC_PMACRO_VTTGEN_CTRL_1 0xc38 570 #define EMC_PMACRO_BG_BIAS_CTRL_0 0xc3c 571 #define EMC_PMACRO_PAD_CFG_CTRL 0xc40 572 #define EMC_PMACRO_ZCTRL 0xc44 573 #define EMC_PMACRO_CMD_PAD_RX_CTRL 0xc50 574 #define EMC_PMACRO_DATA_PAD_RX_CTRL 0xc54 575 #define EMC_PMACRO_CMD_RX_TERM_MODE 0xc58 576 #define EMC_PMACRO_DATA_RX_TERM_MODE 0xc5c 577 #define EMC_PMACRO_CMD_PAD_TX_CTRL 0xc60 578 #define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_E_DCC BIT(1) 579 #define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSP_TX_E_DCC BIT(9) 580 #define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSN_TX_E_DCC BIT(16) 581 #define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_CMD_TX_E_DCC BIT(24) 582 #define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_DRVFORCEON BIT(26) 583 584 #define EMC_PMACRO_DATA_PAD_TX_CTRL 0xc64 585 #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_TX_E_DCC BIT(1) 586 #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSP_TX_E_DCC BIT(9) 587 #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSN_TX_E_DCC BIT(16) 588 #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_CMD_TX_E_DCC BIT(24) 589 590 #define EMC_PMACRO_COMMON_PAD_TX_CTRL 0xc68 591 #define EMC_PMACRO_AUTOCAL_CFG_COMMON 0xc78 592 #define EMC_PMACRO_VTTGEN_CTRL_2 0xcf0 593 #define EMC_PMACRO_IB_RXRT 0xcf4 594 #define EMC_TRAINING_CTRL 0xe04 595 #define EMC_TRAINING_QUSE_CORS_CTRL 0xe0c 596 #define EMC_TRAINING_QUSE_FINE_CTRL 0xe10 597 #define EMC_TRAINING_QUSE_CTRL_MISC 0xe14 598 #define EMC_TRAINING_WRITE_FINE_CTRL 0xe18 599 #define EMC_TRAINING_WRITE_CTRL_MISC 0xe1c 600 #define EMC_TRAINING_WRITE_VREF_CTRL 0xe20 601 #define EMC_TRAINING_READ_FINE_CTRL 0xe24 602 #define EMC_TRAINING_READ_CTRL_MISC 0xe28 603 #define EMC_TRAINING_READ_VREF_CTRL 0xe2c 604 #define EMC_TRAINING_CA_FINE_CTRL 0xe30 605 #define EMC_TRAINING_CA_CTRL_MISC 0xe34 606 #define EMC_TRAINING_CA_CTRL_MISC1 0xe38 607 #define EMC_TRAINING_CA_VREF_CTRL 0xe3c 608 #define EMC_TRAINING_SETTLE 0xe44 609 #define EMC_TRAINING_MPC 0xe5c 610 #define EMC_TRAINING_VREF_SETTLE 0xe6c 611 #define EMC_TRAINING_QUSE_VREF_CTRL 0xed0 612 #define EMC_TRAINING_OPT_DQS_IB_VREF_RANK0 0xed4 613 #define EMC_TRAINING_OPT_DQS_IB_VREF_RANK1 0xed8 614 615 #define EMC_COPY_TABLE_PARAM_PERIODIC_FIELDS BIT(0) 616 #define EMC_COPY_TABLE_PARAM_TRIM_REGS BIT(1) 617 618 enum burst_regs_list { 619 EMC_REFRESH_INDEX = 41, 620 EMC_PRE_REFRESH_REQ_CNT_INDEX = 43, 621 EMC_FBIO_CFG5_INDEX = 65, 622 EMC_DLL_CFG_0_INDEX = 144, 623 EMC_DYN_SELF_REF_CONTROL_INDEX = 150, 624 EMC_PMACRO_CMD_PAD_TX_CTRL_INDEX = 161, 625 EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX, 626 EMC_PMACRO_COMMON_PAD_TX_CTRL_INDEX, 627 EMC_PMACRO_BRICK_CTRL_RFU1_INDEX = 167, 628 }; 629 630 enum trim_regs_list { 631 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_INDEX = 60, 632 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_INDEX, 633 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_INDEX, 634 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_INDEX, 635 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_INDEX, 636 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_INDEX, 637 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_INDEX, 638 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_INDEX, 639 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_INDEX, 640 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_INDEX, 641 }; 642 643 enum burst_mc_regs_list { 644 MC_EMEM_ARB_MISC0_INDEX = 20, 645 }; 646 647 enum { 648 T_RP, 649 T_FC_LPDDR4, 650 T_RFC, 651 T_PDEX, 652 RL, 653 }; 654 655 enum { 656 AUTO_PD = 0, 657 MAN_SR = 2, 658 }; 659 660 enum { 661 ASSEMBLY = 0, 662 ACTIVE, 663 }; 664 665 enum { 666 C0D0U0, 667 C0D0U1, 668 C0D1U0, 669 C0D1U1, 670 C1D0U0, 671 C1D0U1, 672 C1D1U0, 673 C1D1U1, 674 DRAM_CLKTREE_NUM, 675 }; 676 677 #define VREF_REGS_PER_CHANNEL_SIZE 4 678 #define DRAM_TIMINGS_NUM 5 679 #define BURST_REGS_PER_CHANNEL_SIZE 8 680 #define TRIM_REGS_PER_CHANNEL_SIZE 10 681 #define PTFV_ARRAY_SIZE 12 682 #define SAVE_RESTORE_MOD_REGS_SIZE 12 683 #define TRAINING_MOD_REGS_SIZE 20 684 #define BURST_UP_DOWN_REGS_SIZE 24 685 #define BURST_MC_REGS_SIZE 33 686 #define TRIM_REGS_SIZE 138 687 #define BURST_REGS_SIZE 221 688 689 struct tegra210_emc_per_channel_regs { 690 u16 bank; 691 u16 offset; 692 }; 693 694 struct tegra210_emc_table_register_offsets { 695 u16 burst[BURST_REGS_SIZE]; 696 u16 trim[TRIM_REGS_SIZE]; 697 u16 burst_mc[BURST_MC_REGS_SIZE]; 698 u16 la_scale[BURST_UP_DOWN_REGS_SIZE]; 699 struct tegra210_emc_per_channel_regs burst_per_channel[BURST_REGS_PER_CHANNEL_SIZE]; 700 struct tegra210_emc_per_channel_regs trim_per_channel[TRIM_REGS_PER_CHANNEL_SIZE]; 701 struct tegra210_emc_per_channel_regs vref_per_channel[VREF_REGS_PER_CHANNEL_SIZE]; 702 }; 703 704 struct tegra210_emc_timing { 705 u32 revision; 706 const char dvfs_ver[60]; 707 u32 rate; 708 u32 min_volt; 709 u32 gpu_min_volt; 710 const char clock_src[32]; 711 u32 clk_src_emc; 712 u32 needs_training; 713 u32 training_pattern; 714 u32 trained; 715 716 u32 periodic_training; 717 u32 trained_dram_clktree[DRAM_CLKTREE_NUM]; 718 u32 current_dram_clktree[DRAM_CLKTREE_NUM]; 719 u32 run_clocks; 720 u32 tree_margin; 721 722 u32 num_burst; 723 u32 num_burst_per_ch; 724 u32 num_trim; 725 u32 num_trim_per_ch; 726 u32 num_mc_regs; 727 u32 num_up_down; 728 u32 vref_num; 729 u32 training_mod_num; 730 u32 dram_timing_num; 731 732 u32 ptfv_list[PTFV_ARRAY_SIZE]; 733 734 u32 burst_regs[BURST_REGS_SIZE]; 735 u32 burst_reg_per_ch[BURST_REGS_PER_CHANNEL_SIZE]; 736 u32 shadow_regs_ca_train[BURST_REGS_SIZE]; 737 u32 shadow_regs_quse_train[BURST_REGS_SIZE]; 738 u32 shadow_regs_rdwr_train[BURST_REGS_SIZE]; 739 740 u32 trim_regs[TRIM_REGS_SIZE]; 741 u32 trim_perch_regs[TRIM_REGS_PER_CHANNEL_SIZE]; 742 743 u32 vref_perch_regs[VREF_REGS_PER_CHANNEL_SIZE]; 744 745 u32 dram_timings[DRAM_TIMINGS_NUM]; 746 u32 training_mod_regs[TRAINING_MOD_REGS_SIZE]; 747 u32 save_restore_mod_regs[SAVE_RESTORE_MOD_REGS_SIZE]; 748 u32 burst_mc_regs[BURST_MC_REGS_SIZE]; 749 u32 la_scale_regs[BURST_UP_DOWN_REGS_SIZE]; 750 751 u32 min_mrs_wait; 752 u32 emc_mrw; 753 u32 emc_mrw2; 754 u32 emc_mrw3; 755 u32 emc_mrw4; 756 u32 emc_mrw9; 757 u32 emc_mrs; 758 u32 emc_emrs; 759 u32 emc_emrs2; 760 u32 emc_auto_cal_config; 761 u32 emc_auto_cal_config2; 762 u32 emc_auto_cal_config3; 763 u32 emc_auto_cal_config4; 764 u32 emc_auto_cal_config5; 765 u32 emc_auto_cal_config6; 766 u32 emc_auto_cal_config7; 767 u32 emc_auto_cal_config8; 768 u32 emc_cfg_2; 769 u32 emc_sel_dpd_ctrl; 770 u32 emc_fdpd_ctrl_cmd_no_ramp; 771 u32 dll_clk_src; 772 u32 clk_out_enb_x_0_clk_enb_emc_dll; 773 u32 latency; 774 }; 775 776 #define DRAM_TYPE_DDR3 0 777 #define DRAM_TYPE_LPDDR4 1 778 #define DRAM_TYPE_LPDDR2 2 779 #define DRAM_TYPE_DDR2 3 780 781 struct tegra210_emc { 782 struct tegra_mc *mc; 783 struct device *dev; 784 struct clk *clk; 785 786 struct tegra210_emc_timing *timings; 787 unsigned int num_timings; 788 789 const struct tegra210_emc_table_register_offsets *offsets; 790 791 const struct tegra210_emc_sequence *sequence; 792 spinlock_t lock; 793 794 void __iomem *regs, *channel[2]; 795 unsigned int num_channels; 796 unsigned int num_devices; 797 unsigned int dram_type; 798 799 struct tegra210_emc_timing *last; 800 struct tegra210_emc_timing *next; 801 802 unsigned int training_interval; 803 struct timer_list training; 804 805 ktime_t clkchange_time; 806 int clkchange_delay; 807 808 unsigned long resume_rate; 809 810 struct { 811 struct dentry *root; 812 unsigned long min_rate; 813 unsigned long max_rate; 814 } debugfs; 815 816 struct tegra210_clk_emc_provider provider; 817 }; 818 819 struct tegra210_emc_sequence { 820 u8 revision; 821 void (*set_clock)(struct tegra210_emc *emc, u32 clksrc); 822 u32 (*periodic_compensation)(struct tegra210_emc *emc); 823 }; 824 825 static inline void emc_writel(struct tegra210_emc *emc, u32 value, 826 unsigned int offset) 827 { 828 writel_relaxed(value, emc->regs + offset); 829 } 830 831 static inline u32 emc_readl(struct tegra210_emc *emc, unsigned int offset) 832 { 833 return readl_relaxed(emc->regs + offset); 834 } 835 836 static inline void emc_channel_writel(struct tegra210_emc *emc, 837 unsigned int channel, 838 u32 value, unsigned int offset) 839 { 840 writel_relaxed(value, emc->channel[channel] + offset); 841 } 842 843 static inline u32 emc_channel_readl(struct tegra210_emc *emc, 844 unsigned int channel, unsigned int offset) 845 { 846 return readl_relaxed(emc->channel[channel] + offset); 847 } 848 849 static inline void ccfifo_writel(struct tegra210_emc *emc, u32 value, 850 unsigned int offset, u32 delay) 851 { 852 writel_relaxed(value, emc->regs + EMC_CCFIFO_DATA); 853 854 value = EMC_CCFIFO_ADDR_STALL_BY_1 | EMC_CCFIFO_ADDR_STALL(delay) | 855 EMC_CCFIFO_ADDR_OFFSET(offset); 856 writel_relaxed(value, emc->regs + EMC_CCFIFO_ADDR); 857 } 858 859 static inline u32 div_o3(u32 a, u32 b) 860 { 861 u32 result = a / b; 862 863 if ((b * result) < a) 864 return result + 1; 865 866 return result; 867 } 868 869 u32 tegra210_emc_mrr_read(struct tegra210_emc *emc, unsigned int chip, 870 unsigned int address); 871 void tegra210_emc_do_clock_change(struct tegra210_emc *emc, u32 clksrc); 872 void tegra210_emc_set_shadow_bypass(struct tegra210_emc *emc, int set); 873 void tegra210_emc_timing_update(struct tegra210_emc *emc); 874 u32 tegra210_emc_get_dll_state(struct tegra210_emc_timing *next); 875 struct tegra210_emc_timing *tegra210_emc_find_timing(struct tegra210_emc *emc, 876 unsigned long rate); 877 int tegra210_emc_wait_for_update(struct tegra210_emc *emc, unsigned int channel, 878 unsigned int offset, u32 bit_mask, bool state); 879 unsigned long tegra210_emc_actual_osc_clocks(u32 in); 880 u32 tegra210_emc_compensate(struct tegra210_emc_timing *next, u32 offset); 881 void tegra210_emc_dll_disable(struct tegra210_emc *emc); 882 void tegra210_emc_dll_enable(struct tegra210_emc *emc); 883 u32 tegra210_emc_dll_prelock(struct tegra210_emc *emc, u32 clksrc); 884 u32 tegra210_emc_dvfs_power_ramp_down(struct tegra210_emc *emc, u32 clk, 885 bool flip_backward); 886 u32 tegra210_emc_dvfs_power_ramp_up(struct tegra210_emc *emc, u32 clk, 887 bool flip_backward); 888 void tegra210_emc_reset_dram_clktree_values(struct tegra210_emc_timing *timing); 889 void tegra210_emc_start_periodic_compensation(struct tegra210_emc *emc); 890 891 #endif 892